TWI626712B - Semiconductor devices and methods for forming the isolation structure in the semiconductor device - Google Patents

Abstract

The present disclosure provides a method of fabricating an isolation structure in a semiconductor device, including forming a patterned dielectric structure on a first region and a second region of a substrate, forming a first isolation structure in a first region of the substrate and forming a second region The isolation structure is in the second region of the substrate, wherein the sidewall of the first isolation structure and the surface of the lower surface of the patterned dielectric structure of the first region have a first curvature, and the sidewall of the second isolation structure and the second region The surface of the lower surface of the patterned dielectric structure has a first curvature, forming a cover layer on the substrate of the first region and the second region, performing an etching process, completely removing the cover layer of the second region, and the second region An oxidation process is performed to form a first oxide region under the patterned dielectric structure of the second region and a sidewall of the second isolation structure, and the first oxide region has a second curvature adjacent to a surface of the substrate.

Description

Method for manufacturing isolation structure of semiconductor device and semiconductor device

The present invention relates to a semiconductor device, and more particularly to a method of fabricating an isolation structure for a semiconductor device.

The high voltage semiconductor device technology is suitable for the field of high voltage and high power integrated circuits. Conventional high-voltage semiconductor devices, such as vertically diffused metal oxide semiconductor (VDMOS) transistors and horizontally diffused metal oxide semiconductor (LDMOS) transistors, are mainly used in component applications above 18V. The advantages of high-voltage device technology are cost-effective and easy to be compatible with other processes, and have been widely used in display driver IC components, power supplies, power management, communications, automotive electronics or industrial control.

Although currently existing semiconductor devices and their formation methods are sufficient for their intended use, they have not been fully compliant in all respects, and there is still a need for effort.

Some embodiments of the present disclosure relate to a method of fabricating an isolation structure in a semiconductor device, including forming a patterned dielectric structure on a first region and a second region of a substrate to form a first isolation structure in a first region of the substrate Inner and formation The second isolation structure is in the second region of the substrate, wherein the sidewall of the first isolation structure and the surface of the lower surface of the patterned dielectric structure of the first region have a first curvature, and the sidewall of the second isolation structure and the second The surface of the lower surface of the patterned dielectric structure of the region has a first curvature, the cover layer is formed on the substrate of the first region and the second region, an etching process is performed, the cover layer of the second region is completely removed, and The two regions perform an oxidation process to form a first oxide region under the patterned dielectric structure of the second region and a sidewall of the second isolation structure, and the first oxide region has a second curvature adjacent to a surface of the substrate.

Further embodiments of the present disclosure relate to a semiconductor device including a substrate having a first region and a second region, a gate oxide layer disposed on the first region and the second region of the substrate, and the first isolation structure disposed on the substrate a region and a second isolation structure are disposed in the second region of the substrate, wherein a surface of the lower surface of the gate oxide layer and the sidewall of the first isolation structure has a first curvature, and the first oxide region is disposed in the second region The gate oxide layer and the sidewall of the second isolation structure, wherein the first oxide region has a second curvature different from the first curvature adjacent to the surface of the substrate, and the gate electrode layer is disposed on the gate oxide layer.

10, 20‧‧‧ semiconductor devices

100‧‧‧Base

100A‧‧‧First District

100B‧‧‧Second District

100C‧‧‧ Third District

100D‧‧‧Fourth District

110‧‧‧Second dielectric layer

120‧‧‧First dielectric layer

130A‧‧‧First isolation structure

130B‧‧‧Second isolation structure

130C‧‧‧The third isolation structure

130D‧‧‧fourth isolation structure

140‧‧‧ Coverage

140C‧‧‧First Residency

140D‧‧‧Second Remaining Department

150‧‧‧ gate oxide layer

160‧‧‧gate electrode layer

170B‧‧‧First Oxide Zone

170C‧‧‧Second oxide zone

170D‧‧‧ Third Oxide Zone

190‧‧‧Isolation components

200‧‧‧Oxidation process

L1, L2‧‧‧ length

The best mode of understanding of the various aspects of the present disclosure is to read the following detailed description of the specification and the accompanying drawings. It should be noted that the various components of the present disclosure have not been drawn to the dimensions of industry standard work. In fact, the dimensions of the various components can be arbitrarily enlarged or reduced for clarity of description.

1A-1F shows the difference in forming a semiconductor device in accordance with some embodiments Schematic diagram of the stage.

2A-2F are schematic cross-sectional views showing different stages of forming a semiconductor device, in accordance with certain embodiments.

Figure 3A shows an enlarged schematic view of region B of Figure 2D, in accordance with some embodiments.

Figure 3B shows an enlarged schematic view of region C of Figure 2D, in accordance with some embodiments.

Figure 3C shows an enlarged schematic view of region D of Figure 2D, in accordance with some embodiments.

Some embodiments of the present disclosure, as described below, and FIGS. 1A-1F show cross-sectional schematic views of different stages of forming a semiconductor device 10, in accordance with certain embodiments. Additional processes may be provided before, during, and/or after the stages described in Figures 1A-1F. Some of the described stages may be replaced or removed in different embodiments. The semiconductor device 10 can add additional components. Some of the elements described below may be replaced or removed in different embodiments.

As shown in FIG. 1A, a substrate 100 is provided. Substrate 100 includes a semiconductor wafer (eg, a germanium wafer) or a portion of a semiconductor wafer. In some embodiments, substrate 100 is formed from an elemental semiconductor material, a single crystal, polycrystalline or amorphous structure comprising tantalum or niobium.

In other embodiments, the substrate 100 is composed of a compound semiconductor such as silicon carbide, gallium phosphide, gallium phosphide, indium phosphide, indium arsenide (indium). Arsenide). The substrate 100 also contains an alloy semiconductor such as germanium. (SiGe) or phosphorus gallium arsenide (GaAsP) or a combination thereof. The substrate 100 further includes a multilayer semiconductor, a semiconductor on insulator (SOI), or a combination thereof.

As shown in FIG. 1A, the substrate 100 includes a first region 100A and a second region 100B. In some embodiments, the first region 100A is a low voltage region and the second region 100B is a high voltage region.

The substrate 100 includes a patterned isolation structure 190. As shown in FIG. 1A, the patterned isolation structure 190 includes a first dielectric layer 120 and a second dielectric layer 110 formed under the first dielectric layer 120. The second dielectric layer 110 and the first dielectric layer 120 may be formed by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an oxidation process, or other suitable processes. In some embodiments, the first dielectric layer 120 is formed by depositing a layer of dielectric material (not shown), patterning it through a lithography process, and then performing an etch process removal portion of the dielectric material layer. In some embodiments, the etching process includes dry etching, wet etching, or other etching methods (eg, reactive ion etching). The etching process can also be a pure chemical etching, a pure physical etching, or a combination thereof.

The materials of the second dielectric layer 110 and the first dielectric layer 120 include yttrium oxide, tantalum nitride, yttrium oxynitride, fluorine-doped silicate glass (FSG), low dielectric constant dielectric materials, and the like. Material or a combination thereof. The materials of the first dielectric layer 120 and the second dielectric layer 110 may be the same or different. In some embodiments, the second dielectric layer 110 is made of tantalum oxide and the first dielectric layer 120 is made of tantalum nitride.

After the second dielectric layer 110 and the first dielectric layer 120 are formed, an etching process is performed, and the second dielectric layer 110 and the first dielectric layer 120 are used as a mask. The portion of the substrate 100 that is not covered by the second dielectric layer 110 and the first dielectric layer 120 is removed to form a trench. A dielectric material is then deposited in the trench, and then the excess dielectric material is removed to form a first isolation structure 130A and a second isolation structure 130B. The deposited dielectric material can be formed by a chemical vapor deposition process, a physical vapor deposition process, or other suitable process. In some embodiments, a CMP process is performed to remove excess dielectric material. The material of the first isolation structure 130A is the same as that of the second isolation structure 130B. The materials of the first isolation structure 130A and the second isolation structure 130B include hafnium oxide, tantalum nitride, hafnium oxynitride, fluorocarbon glass, a low dielectric constant dielectric material, and other suitable materials or a combination thereof. In some embodiments, the first isolation structure 130A and the second isolation structure 130B are made of hafnium oxide. As shown in FIG. 1A, the first isolation structure 130A is formed in the first region 100A of the substrate 100, and the second isolation structure 130B is formed in the second region 100B of the substrate 100.

In some embodiments, as shown in FIG. 1B, after the first isolation structure 130A and the second isolation structure 130B are formed, the cover layer 140 is deposited on the first region 100A and the second region 100B of the substrate 100, and the cover layer 140 The first isolation structure 130A and the first isolation structure 130B are covered. The cover layer 140 can be formed by a chemical vapor deposition process, a physical vapor deposition process, or other suitable process. The material of the cap layer 140 comprises hafnium oxide, tantalum nitride, hafnium oxynitride, fluorocarbon glass, a low dielectric constant dielectric material, other suitable materials, or a combination thereof. In some embodiments, the cap layer 140 is made of tantalum nitride.

In some implementations, the thickness of the cover layer 140 is between about 100-500 Å. If the cap layer 140 is not thick enough, it may not be able to prevent oxygen from reacting with the substrate 100 to form an oxide region in the subsequent oxidation process in the patterned dielectric junction. Structure 190. On the other hand, if the cover layer 140 is too thick, it may become difficult to remove the cover layer 140 in a subsequent process.

In some embodiments, as shown in FIG. 1C, after the cap layer 140 is formed, the cap layer 140 of the second region 100B is removed to expose the first dielectric layer 120 and the second isolation structure 130B of the second region. The surface, the cover layer 140 of the first zone 100A is not removed. In some embodiments, the cap layer 140 of the second region 100B is removed by performing a lithography process and an anisotropic etching process.

In some embodiments, as shown in FIG. 1D, after the cap layer 140 of the second region 100B is removed, the second isolation structure 130B is subjected to an oxidation process 200. In some embodiments, the oxidation process 200 can be carried out by introducing oxygen into the environment at a temperature of about 600-1000 °C. As shown in FIG. 1D, oxygen penetrates the second isolation structure 130B and is transferred to the interface of the substrate 100, the second isolation structure 130B and the second dielectric layer 110, and then oxygen reacts with the substrate 100 to form a first oxide region. 170B. More specifically, the first oxide region 170B is formed under the second dielectric layer 110 of the second region 100B and on the sidewall of the second isolation structure 130B. Since the first region 100A of the substrate 100 is covered by the cap layer 140, oxygen cannot be transferred to the substrate 100, the interface of the first isolation structure 130A and the second dielectric layer 110 through the cap layer 140. More specifically, oxygen cannot react with the substrate 100 of the first zone 100A. Thus, after the oxidation process 200 is performed, the second region 100B generates the first oxide region 170B, however the first region 100A does not generate additional oxide regions.

The first oxide region 170B has an insulating property, and thus the first oxide region 170B and the second isolation structure 130B may be regarded together as the second region 100B. Isolation component. The profile of the isolation elements of the second region 100B is altered by the generation of the first oxide region 170B.

As shown in FIG. 1D, the interface between the first isolation structure 130A, the substrate 100, and the second dielectric layer 110 has a first curvature, that is, the lower surface of the patterned dielectric structure 190 of the first region is isolated from the first The surface of the sidewall of structure 130A has a first curvature; the first oxide region 170B has a second curvature adjacent to the surface of substrate 100. After the oxidation process 200 is performed, since the first oxide region 170B is formed at the boundary between the second isolation structure 130B, the substrate 100, and the second dielectric layer 110, the interface becomes more rounded, and thus the second curvature is smaller than the first curvature. .

In some embodiments, as shown in FIG. 1E, after the oxidation process 200 is performed, the cap layer 140 and the first dielectric layer 120 are removed. In some embodiments, an anisotropic etch process is performed to remove the cap layer 140 and the first dielectric layer 120.

In some embodiments, as shown in FIG. 1F, after the cap layer 140 and the first dielectric layer 120 are removed, the second dielectric layer 110 is removed, and the gate oxide layer 150 is formed on the first isolation structure 130A and The opposite sides of the second isolation structure 130B. The second dielectric layer 110 can be removed by dry etching, wet etching, or other etching methods. After the gate oxide layer 150 is formed, the gate electrode layer 160 is formed on the gate oxide layer 150 to complete the semiconductor device 10. The material of the gate electrode layer 160 comprises a polysilicon layer or other suitable material.

In this embodiment, since the isolation element of the second region 100B (for example, the high voltage region) of the semiconductor device 10 has a small second curvature, the gate oxide thinning ratio becomes more Preferably, the gate oxide integrity of the gate oxide layer 150 is improved. GOI) enables various electrical properties of the second region 100B (eg, high voltage region) of the semiconductor device 10 to be improved.

However, if the curvature of the surface of the first region 100A (eg, the low voltage region) of the semiconductor device 10 (eg, the first isolation structure 130A) abuts the surface of the substrate 100 (eg, the first curvature) becomes small, the first The saturated drain current (Idsat) of a region 100A (eg, a low voltage region). In an embodiment of the present disclosure, a capping layer 140 is deposited on the first region 100A (eg, a low voltage region) of the semiconductor device 10 prior to performing the oxidation process 200, thereby preventing oxygen from reacting with the substrate 100 to form oxides, thereby The contour of the isolation element of the first zone 100A does not change. Therefore, after the first isolation structure 130A is covered by the cover layer 140, the subsequent oxidation process 200 may cause the isolation elements of the second region 100B (eg, the second isolation structure 130B and the first oxide 170B region) to abut the surface of the substrate 100. The curvature (e.g., the second curvature) becomes smaller, and the curvature of the spacer element of the first region 100A is not affected. As a result, the gate oxide integrity of the high voltage region of the semiconductor device 10 can be improved without affecting the electrical properties of the low voltage region of the semiconductor device 10.

Further embodiments of the present disclosure are described below, and FIGS. 2A-2F show cross-sectional schematic views of different stages of forming semiconductor device 20, in accordance with certain embodiments. Additional processes may be provided before, during, and/or after the stages described in Figures 2A-2F. Some of the described stages may be replaced or removed in different embodiments. The semiconductor device 20 can add additional components. Some of the elements described below may be replaced or removed in different embodiments.

In some embodiments, as shown in FIG. 2A, the substrate 100 includes a first region 100A, a second region 100B, a third region 100C, and a fourth region 100D. in In some embodiments, the first region 100A is a low voltage region, and the second region 100B, the third region 100C, and the fourth region 100D are high voltage regions.

As shown in FIG. 2A, the substrate 100 further includes a third isolation structure 130C and a fourth isolation structure 130D. The processes and materials for forming the third isolation structure 130C and the fourth isolation structure 130D may be similar or identical to the processes and materials for forming the first isolation structure 130A and the second isolation structure 130B, and are not repeated herein. As shown in FIG. 2A, a third isolation structure 130C is formed in the third region 100C of the substrate 100, and a fourth isolation structure 130D is formed in the fourth region 100D of the substrate 100.

As shown in FIG. 2B, after the first isolation structure 130A, the second isolation structure 130B, the third isolation structure 100C, and the fourth isolation structure 100D are formed, the cover layer 140 is deposited on the first region 100A and the second region 100B of the substrate 100. The third region 100C and the fourth region 100D cover the first isolation structure 130A, the second isolation structure 130B, the third isolation structure 130C, and the fourth isolation structure 130D. In some implementations, the thickness of the cover layer 140 is between about 100-500 Å. If the cap layer 140 is not thick enough, it may not be able to prevent oxygen from reacting with the substrate 100 to form oxides under the patterned dielectric structure 190 during subsequent oxidation processes. On the other hand, if the cover layer 140 is too thick, it may become difficult to remove the cover layer 140 in a subsequent process.

In some embodiments, as shown in FIG. 2C, after the cap layer 140 is formed, the entire cap layer 140 of the second region 100B of the substrate 100 is removed to expose the upper surface of the first dielectric layer 120 and the second isolation structure 130B. . In addition, a portion of the third region 100C and a portion of the cap layer 140 of the fourth region 100D are removed. As shown in FIG. 2C, after removing a portion of the cover layer 140 of the third region 100C, the shape is After the first remaining portion 140C removes a portion of the cover layer 140 of the fourth region 100D, the second remaining portion 140D is formed.

In some embodiments, as shown in FIG. 2C, the length L1 of the first remaining portion 140C extending in the horizontal direction is greater than the length L2 of the second remaining portion 140D extending in the horizontal direction. The first remaining portion 140C is formed over the first dielectric layer 120 of the third region 100C, and the first remaining portion 140C extends from the upper surface of the first dielectric layer 120 to the upper surface of the third isolation structure 130C. The second remaining portion 140D is formed over the first dielectric layer 120 of the fourth region 100D, and the first dielectric layer 120 of the fourth region 100D is not completely covered by the second remaining portion 140D, that is, a portion of the fourth portion The second dielectric layer 120 of the region 100D is exposed.

In some embodiments, a cover layer 140 having a different layout may be left for the first region 100A, the second region 100B, the third region 100C, and the fourth region 100D, using a patterned mask having four layouts. Covering layer 140, and simultaneously removing the cover layer 140 of the second region 100B by an anisotropic etching process, and forming the first remaining portion 140C in the third region 100C and the second remaining The remaining portion 140D is on the fourth region 100D, and the cover layer of the first region 100A is completely retained.

As shown in FIG. 2C, after the etching process is performed on the cap layer 140, the first dielectric layer 120 of the third region 100C and the fourth region 100D respectively have different lengths of the capping layer 140, wherein the covering of the first region 100A The layer 140 is not removed at all, the cover layer 140 of the second region 100B is completely removed, the cover layer 140 of the third region 100C forms the first remaining portion 140C, and the first remaining portion 140C is formed by the first dielectric layer 120 The upper surface extends to the upper surface of the third isolation structure 130C, And the cover layer 140 of the fourth region 100D forms the second remaining portion 140D, and the first dielectric layer 120 of the fourth region 100D is not completely covered by the second remaining portion 140D.

In some embodiments, as shown in FIG. 2D, an oxidation process 200 is performed on the second isolation structure 130B, the third isolation structure 130C, and the fourth isolation structure 130D. The oxidation process 200 can be carried out by introducing oxygen into the environment at a temperature of about 800-1200 °C. As shown in FIG. 2D, oxygen reacts with the substrate 100 of the second region 100B, the third region 100C, and the fourth region 100D to form a first oxide region, a second oxide region, and a third oxide region, respectively (first The oxide region, the second oxide region, and the third oxide region are shown in Figures 3A-3C).

Referring to Figures 3A-3C, Figures 3A-3C show enlarged views of regions B, C, and D, respectively, of Figure 2D, in accordance with certain embodiments. As shown in FIGS. 3A-3C, the first oxide region 170B is formed under the second dielectric layer 110 of the second region 100B and the sidewall of the second isolation structure 130B, and the second oxide region 170C is formed in the third region. On the sidewalls of the second dielectric layer 110 of 100C and the third isolation structure 130C, a third oxide region 170D is formed under the second dielectric layer 110 of the fourth region 100D and the sidewalls of the fourth isolation structure 130D. Since the first oxide region 170B, the second oxide region 170C, and the third oxide region 170D have insulating properties, generation by the first oxide region 170B, the second oxide region 170C, and the third oxide region 170D , substantially changing the isolation elements of the second region 100B (the second isolation structure 130B and the first oxide region 170B), the isolation elements of the third region 100C (the third isolation structure 130C and the second oxide region 170C), and The outline of the isolation elements (fourth isolation structure 130D and third oxide region 170D) of the fourth region 100D.

In addition, as shown in FIGS. 3A-3C, the second oxide region 170C formed on the sidewall of the third isolation structure 130C and under the second dielectric layer 110 has a third curvature adjacent to the surface of the substrate 100; The third oxide region 170D on the sidewall of the isolation structure 130D and under the second dielectric layer 110 has a fourth curvature adjacent to the surface of the substrate 100. Since the length L1 of the first remaining portion 140C is larger than the length L2 of the second remaining portion 140D, it is difficult for oxygen to react with the substrate 100 of the third region 100C. The above reason causes the third curvature to be greater than the fourth curvature. That is, the surface of the fourth oxide region 170D adjacent to the substrate 100 is rounded adjacent to the surface of the third oxidized region 170C adjacent to the substrate 100.

As described above, since the cap layer 140 of the first region 100A is not removed, the first region 100A does not generate an additional oxide region.

Since the first dielectric layer 120 of the first region 100A, the third region 100C, and the fourth region 100D respectively have different lengths of the capping layer 140, after the oxidation process 200 is performed, the isolation component of the first region 100A (for example, the first The isolation structure 130A), the isolation elements of the second region 100B (eg, the second isolation structure 130B and the first oxide region 170B), the isolation elements of the third region 100C (eg, the third isolation structure 130C and the second oxide region 170C) The outlines of the isolation elements of the fourth region 100D, such as the fourth isolation structure 130D and the third oxide region 170D, are different. Wherein the first curvature is greater than the third curvature, the third curvature is greater than the fourth curvature, and the fourth curvature is greater than the second curvature.

Further, as shown in FIGS. 3A-3C, the area of the first oxide region 170B is larger than the area of the third oxide region 170D, and the area of the third oxide region 170D is larger than the area of the second oxide region 170B.

In some embodiments, as shown in FIG. 2E, after the oxidation process 200 is performed, the cap layer 140, the first remaining portion 140C, the second remaining portion 140D, and the first dielectric layer 120 are removed. In some embodiments, an anisotropic etch process is performed to remove the cap layer 140, the first remaining portion 140C, the second remaining portion 140D, and the first dielectric layer 120.

In some embodiments, as shown in FIG. 2F, after the cap layer 140, the first remaining portion 140C, the second remaining portion 140D, and the first dielectric layer 120 are removed, the second dielectric layer 110 is removed. The gate oxide layer 150 is formed on opposite sides of the first isolation structure 130A, the second isolation structure 130B, the third isolation structure 130C, and the fourth isolation structure 130D. The second dielectric layer 110 can be removed by dry etching, wet etching, or other etching methods. After the gate oxide layer 150 is formed, the gate electrode layer 160 is formed on the gate oxide layer 150 to complete the semiconductor device 20.

In this embodiment, since the contours of the respective isolation elements of the second region 100B, the third region 100C, and the fourth region 100D (eg, the high voltage region) are changed, respectively, they have a first curvature smaller than that of the first region 100A. The second curvature, the third curvature, and the fourth curvature. Therefore, the gate oxide thinning ratio of the semiconductor device 200 becomes better, thereby improving the gate oxide integrity (GOI) of the gate oxide layer 150 of the semiconductor device 200. . At the same time, by leaving a different length of the cover layer 140 (for example, the first remaining portion 140C or the second remaining portion 140D) on the first dielectric layer 120, under the second dielectric layer 110 and the second isolation An oxide region having a different curvature is formed on sidewalls of the structure 130B, the third isolation structure 130C, and the fourth isolation structure 130D such that the first region 100A, the second region 100B, the third region 100C, and the fourth region 100D are separated The elements have different curvatures. Therefore, the electrical properties of the high voltage region can be improved without affecting the gate saturation current in the low voltage region.

Although the curvature of the isolation structure described herein is defined by the sidewalls of the isolation structure and the lower surface of the patterned dielectric structure 190, the disclosure is not intended to be limited thereto. The curvature may also be defined by the surface of the interface between the other material layers and the isolation structure, or by the contour of the isolation element.

The features of many embodiments are described above to enable those skilled in the art to clearly understand the following description. Those skilled in the art can understand that the disclosure of the present invention can be utilized as a basis for designing or modifying other processes and structures to achieve the same objectives and/or advantages over the above-described embodiments. It is also to be understood by those skilled in the art that <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt;

Claims (18)

A method of fabricating an isolation structure for a semiconductor device includes: forming a patterned dielectric structure on a first region and a second region of a substrate; forming a first isolation structure in the first region of the substrate and Forming a second isolation structure in the second region of the substrate, wherein a sidewall of the first isolation structure and a surface of the lower surface of the patterned dielectric structure of the first region have a first curvature, and a surface of the second isolation structure and a surface of the lower surface of the patterned dielectric structure of the second region have the first curvature; forming a cover layer on the substrate of the first region and the second region Performing an etching process to completely remove the cap layer of the second region; and when the second isolation structure is exposed, performing an oxidation process on the second region to form a first oxide region in the second region The patterned dielectric structure and the sidewall of the second isolation structure, and the surface of the first oxide region adjacent to the substrate has a second curvature different from the first curvature, and the first oxidation The object area has an arc wheel , And in direct contact with the second isolation structure. The method of fabricating an isolation structure for a semiconductor device according to claim 1, wherein the first curvature is greater than the second curvature. The method of fabricating an isolation structure for a semiconductor device according to claim 1, wherein the first region is a low voltage region and the second region is a high voltage region. The method of fabricating an isolation structure for a semiconductor device according to claim 1, wherein the patterned dielectric structure comprises a first dielectric layer and a second dielectric layer formed under the first dielectric layer And the first dielectric layer is made of tantalum nitride, and the second dielectric layer is made of tantalum oxide. The method for fabricating the isolation structure of the semiconductor device of claim 1, further comprising: forming the patterned dielectric structure on a third region and a fourth region of the substrate; forming a third isolation structure The third region of the substrate and a fourth isolation structure are in the fourth region of the substrate, wherein a sidewall of the third isolation structure and a lower surface of the patterned dielectric structure of the third region are formed The surface has the first curvature, and a sidewall of the fourth isolation structure and a surface of the lower surface of the patterned dielectric structure of the fourth region have the first curvature; and the third isolation structure, the The fourth isolation structure performs the oxidation process to form a second oxide region under the patterned dielectric structure of the third region and the sidewall of the third isolation structure to form a third oxide region The patterned dielectric structure of the four regions and the sidewall of the fourth isolation structure, and the second oxide region has a third curvature to the third region, the third oxide region having a fourth curvature In the fourth district. The method of fabricating the isolation structure of the semiconductor device of claim 5, further comprising: forming the cap layer on the substrate of the third region and the fourth region; Removing a portion of the cover layer located in the third region and the fourth region such that the cover layer of the third region has a first remaining portion over the patterned dielectric structure, the fourth region The cover layer has a second remaining portion above the patterned dielectric structure, wherein a length of the first remaining portion is greater than a length of the second remaining portion. The method of fabricating an isolation structure for a semiconductor device according to claim 5, wherein the third region and the fourth region are high voltage regions. The method of fabricating an isolation structure for a semiconductor device according to claim 6, wherein the first remaining portion extends from an upper surface of the patterned dielectric structure of the third region to the third isolation structure An upper surface, a portion of the patterned dielectric structure of the fourth region is not completely covered by the second remaining portion. The method of fabricating an isolation structure for a semiconductor device according to claim 8, wherein the first curvature is greater than the third curvature, the third curvature is greater than the fourth curvature, and the fourth curvature is greater than the second curvature. The method for fabricating the isolation structure of the semiconductor device of claim 9, further comprising: after performing the oxidation process, removing the cover layer of the first region and the first region and the second region Patterned dielectric structure. The method of fabricating an isolation structure for a semiconductor device according to claim 1, wherein the etching process comprises an anisotropic etching process. The method of manufacturing an isolation structure for a semiconductor device according to claim 1, wherein the cover layer is made of tantalum nitride. The method of fabricating an isolation structure for a semiconductor device according to claim 1, wherein the cover layer has a thickness of between about 100 and 500 Å. A semiconductor device comprising: a substrate having a first region and a second region; a gate oxide layer disposed on the first region and the second region of the substrate; a first isolation structure disposed on the substrate The first region of the substrate and a second isolation structure are disposed in the second region of the substrate, wherein a surface of the lower surface of the gate oxide layer and a sidewall of the first isolation structure have a first curvature a first oxide region disposed under the gate oxide layer of the second region and the sidewall of the second isolation structure, wherein the first oxide region has a different surface than the surface of the substrate a second curvature of the first curvature, and the first oxide region has an arcuate profile and is in direct contact with the second isolation structure; and a gate electrode layer is disposed on the gate oxide layer. The semiconductor device of claim 14, wherein the first region is a low voltage region and the second region is a high voltage region. The semiconductor device of claim 14, wherein the first curvature is greater than the second curvature. The semiconductor device of claim 14, further comprising: a third isolation structure disposed in a third region of the substrate; and a fourth isolation structure disposed in a fourth region of the substrate; a second oxide region disposed under the gate oxide layer of the third region and the sidewall of the third isolation structure, wherein the second oxide region has a third curvature adjacent to a surface of the substrate; And a third oxide region disposed under the gate oxide layer of the fourth region and the sidewall of the fourth isolation structure, wherein the third oxide region has a fourth curvature adjacent to a surface of the substrate Where the first curvature is greater than the third curvature, the third curvature is greater than the fourth curvature and the fourth curvature is greater than the second curvature. The semiconductor device of claim 17, wherein an area of the first oxide region is larger than an area of the third oxide region, and the area of the third oxide region is greater than the second oxide An area of the district.