TWI626633B - A single stage gate drive circuit with multiplex outputs - Google Patents

Abstract

The invention is a multi-output single-stage gate drive circuit. The single-stage gate drive circuit has a first scanning circuit and a second scanning circuit. The first scanning circuit includes a setting unit and a driving unit. The setting unit receives A start signal generates a control signal. The driving unit receives the control signal and a first clock signal, and the control signal and the first clock signal cause the driving unit to generate a first scanning signal. The driving unit drives the first scanning signal to a first level according to the first clock signal, and the driving unit drives the first scanning signal to a second level according to the first clock signal. The second scanning circuit receives the first scanning signal and a second clock signal, and the second scanning circuit generates a second scanning signal according to the first scanning signal and the second clock signal.

Description

Single-stage gate drive circuit with multi-output design

The invention relates to a single-stage gate drive circuit, in particular to a single-stage gate drive circuit with multi-output design.

According to the press, the thin film transistor display has become the mainstream of display technology products, especially in mobile phones. It has the characteristics of lightness and portability, and amorphous silicon thin film transistors use amorphous silicon thin film The display produced by the crystal can reduce the production cost and can be produced on a large-area glass substrate at a low temperature to increase the production rate.

As the concept of system-integrated glass panels has been proposed, many products have recently integrated the gate scanning circuit in the display drive circuit on the glass, which is the GOA (Gate-Driver-on-Array) circuit. The GOA circuit has many advantages. In addition to reducing the area of the display frame, it is also possible to reduce the use of gate scan drive circuit ICs.

In view of the requirement of the narrow bezel of the display, the present invention proposes a technique for reducing the area requirement of the single-stage gate drive circuit.

One of the purposes of the present invention is to provide a single-stage gate drive circuit which can be upgraded Scan line charge and discharge speed.

One of the objectives of the present invention is to provide a single-stage gate drive circuit that utilizes a multi-output design to achieve a reduction in layout area.

To achieve the above objective, the present invention provides a single-stage gate driving circuit with multiple scanning circuits and a multi-output design, wherein a first scanning circuit includes a setting unit and a driving unit, and the setting unit receives a start signal to generate A control signal. The driving unit is coupled to the setting unit and receives the control signal and a first clock signal. The control signal and the first clock signal enable the driving unit to generate a first scanning signal. The driving unit drives the first scan signal to a first level according to the first clock signal, and the driving unit drives the first scan signal to a second level according to the first clock signal, and the first level is higher than the second level Level. A second scanning circuit is coupled to the first scanning circuit and receives the first scanning signal and a second clock signal. The second scanning circuit generates a second scanning signal according to the first scanning signal and the second clock signal.

1‧‧‧ First single-stage gate drive circuit

2‧‧‧ Second single-stage gate drive circuit

3‧‧‧The third single-stage gate drive circuit

10‧‧‧Setting unit

11‧‧‧Drive unit

12‧‧‧ Setting unit

13‧‧‧Drive unit

14‧‧‧Control unit

15‧‧‧Anti-noise unit

16‧‧‧Protection unit

A‧‧‧Control signal

B‧‧‧Control signal

C‧‧‧Control signal

C1‧‧‧Capacitor

C2‧‧‧Capacitor

CLK1‧‧‧First clock signal

CLK2‧‧‧second clock signal

CLK3‧‧‧third clock signal

CLK4‧‧‧Fourth clock signal

D‧‧‧Control signal

E‧‧‧Control signal

F‧‧‧Control signal

M1‧‧‧First setting element

M2‧‧‧Second setting element

M3‧‧‧Drive element

M4‧‧‧Setting element

M5‧‧‧Drive element

M6‧‧‧transistor

M7‧‧‧transistor

M8‧‧‧transistor

M9‧‧‧ First transistor

M10‧‧‧second transistor

M11‧‧‧The third transistor

M12‧‧‧The fourth transistor

M13‧‧‧transistor

REF‧‧‧Reference level

S0‧‧‧Start signal

S1‧‧‧ First scan signal

S2‧‧‧Second scan signal

S3‧‧‧ Third scan signal

S4‧‧‧ Fourth scan signal

S5‧‧‧ fifth scan signal

S6‧‧‧Sixth scan signal

S7‧‧‧Seventh scan signal

T1‧‧‧The first section

T2‧‧‧Second interval

T3‧‧‧The third section

T4‧‧‧ fourth section

T5‧‧‧ fifth section

T6‧‧‧ sixth section

T7‧‧‧ seventh section

T8‧‧‧Eighth

T9‧‧‧The ninth interval

T10‧‧‧ Tenth

T11‧‧‧Eleventh section

VDD‧‧‧First power supply

VSS‧‧‧Second power supply

The first picture: it is a diagram of an embodiment of the series connection of the multi-level gate drive circuit of the invention; the second picture: it is an implementation of the single-level gate drive circuit of the multi-output design of the invention The circuit diagram of the example; the third diagram: it is the timing diagram of the single-stage gate drive circuit of the multi-output design of the invention; the fourth diagram: it is the gate drive of the first-stage multi-output design under the second diagram of the invention Circuit diagram of the circuit;

In order for your review committee to go further on the features of the present invention and the effects achieved Understand and recognize, we will use the embodiments and detailed descriptions as follows: Please refer to the first figure, which is an illustration of an embodiment of the series connection of the multi-level gate drive circuit of the present invention. As shown in the figure, the multi-level gate drive circuits 1, 2, and 3 are connected in series, and each level of the gate drive circuits 1, 2, and 3 respectively outputs two scanning signals S1 to S6. The first gate driving circuit 1 of the present invention receives a start signal S0, a first clock signal CLK1 and a second clock signal CLK2 to generate a first scan signal S1 and a second scan signal S2, the first scan signal S1 and the second scanning signal S2 control a plurality of pixels through a plurality of scanning lines, wherein the second scanning signal S2 is also a starting signal of a second single-stage gate drive circuit 2 and the output of the second single-stage gate drive circuit 2 is the same The scanning signal S4 is also the starting signal of the third single-stage gate drive circuit 3. In other words, if the single-stage gate drive circuit 1 is not the first stage, the single-stage gate drive circuit 1 will also receive the scan signal of the previous-stage gate drive circuit as the start signal S0.

Please refer to the second figure, which is a circuit diagram of an embodiment of the single-stage gate drive circuit 1 of the multi-output design of the present invention. As shown in the figure, the first single-stage gate driving circuit 1 has two scanning circuits, a first scanning circuit includes a setting unit 10 and a driving unit 11, and a second scanning circuit includes a setting unit 12 and a driving unit 13. The setting unit 10 receives the start signal S0 and a first power supply VDD to generate a control signal A. The driving unit 11 is coupled to the setting unit 10 and receives the control signal A and the first clock signal CLK1. The control signal A controls the driving unit 11 according to The first clock signal CLK1 generates the first scan signal S1. In other words, the control signal A and the first clock signal CLK1 cause the drive unit 11 to generate the first scan signal S1. The setting unit 12 of the second scanning circuit may include a setting element M4 coupled to the driving unit 11 of the first scanning circuit, and receives the first scanning signal S1 and the first power supply VDD to generate a control signal B. The driving unit 13 is coupled to the setting unit 12, and receives the control signal B and the second clock signal CLK2, and the control signal B controls the driving The moving unit 13 generates the second scanning signal S2 according to the second clock signal CLK2. In other words, the control signal B and the second clock signal CLK2 cause the driving unit 13 to generate the second scanning signal S2. In this way, the first single-stage gate driving circuit 1 of the present invention outputs the first scanning signal S1 and the second scanning signal S2, and a single-stage gate driving circuit designed for a multiple output.

Referring back to the first and second figures, the setting unit 10 of the first scanning circuit includes a first setting element M1 and a second setting element M2. The first setting element M1 has an input terminal, a control terminal and an output terminal The input terminal receives the first power supply VDD, the control terminal receives the start signal S0, the output terminal is coupled to the driving unit 11, and the first setting element M1 generates the control signal A according to the start signal S0 and the first power supply VDD. The second setting element M2 has an input terminal, a control terminal, and an output terminal. The input terminal receives a second power supply VSS, and the control terminal receives a third scanning signal S3 output by a second single-stage gate drive circuit 2 to output The terminal is coupled to the driving unit 11, and the second setting element M2 sets the control signal A according to the third scanning signal S3 and the second power VSS. In other words, the third scanning signal S3 sets the control signal A to the level of the second power VSS. If the level of the second power supply VSS is a ground potential, the third scan signal S3 sets the control signal A to the ground potential, so that the third scan signal S3 discharges the control signal A and decreases to the ground potential, so the drive unit 11 does not The first scan signal S1 will be generated.

Furthermore, the driving unit 11 of the first scanning circuit includes a driving element M3 and a capacitor C1. The driving element M3 has an input terminal, a control terminal and an output terminal. The input terminal receives the first clock signal CLK1 and the control terminal is coupled Connected to the setting unit 10, the output terminal is coupled to the setting unit 12 of the second scanning circuit, and the driving element M3 generates the first scanning signal S1 according to the first clock signal CLK1 and the control signal A. In this way, the output end of the driving unit 11 of the first scanning circuit outputs the first scanning signal S1, and the first scanning signal S1 is coupled to the setting unit 12 of the second scanning circuit, so that the second scanning circuit generates the second scanning signal S2.

Referring to the second figure, the first scanning circuit further includes a capacitor C1, which is coupled between the control terminal and the output terminal of the driving element M3. Therefore, when the control signal A does not control the driving element M3 to turn on, the level of the first end of one of the capacitors C1 is the level of the control signal A. When the control signal A controls the driving element M3 to turn on, the second end of one of the second ends of the capacitor C1 The level is the level of the first clock signal CLK1, and the level of the first end of the capacitor C1 is changed to the level of the control signal A plus the level of the first clock signal CLK1. As such, when the first clock signal CLK1 is at a high level, the first end of the capacitor C1 is the level of the control signal A plus the level of the first clock signal CLK1; that is, the capacitor C1 is based on the control signal A and the The clock signal CLK1 raises the level of the first scan signal S1.

Following the above, when the first clock signal CLK1 is at a low level (eg, a ground potential), the first end of the capacitor C1 is the level of the control signal A. In other words, the control end of the driving element M3 will generate the first scan signal S1 according to the first clock signal CLK1 raising or lowering the level, or it can be said that the single-stage gate driving circuit 1 of the present invention uses the driving units 11, 13 It can complete the charging and discharging of the scanning line, and greatly reduce the circuit area and increase the charging speed of the scanning line.

In addition, as shown in the second figure, the control signal A of the first scanning circuit only needs to control the driving element M3 without controlling the driving element M5, and the control signal B of the second scanning circuit only needs to control the driving element M5 without controlling other driving Components, so the output load of the single-stage gate drive circuit 1 of the present invention is low, so that the output capability of the single-stage gate drive circuit 1 is better. Furthermore, the driving unit 13 of the second scanning circuit also includes a driving element M5 and a capacitor C2. The capacitor C2 is coupled between the control end and the output end of the driving element M5.

Referring back to the second figure, the single-stage gate drive circuit 1 of the present invention has an anti-noise circuit. The anti-noise circuit is coupled to the first scanning circuit and the second scanning circuit, and receives the first time The pulse signal CLK1 reduces the noise of the first scanning circuit 1 and the noise of the second scanning circuit, where the noise occurs refers to the noise of the control terminals and output terminals of the driving elements M3, M5. The anti-noise circuit includes a control unit 14, an anti-noise unit 15 and a protection unit 16. The control unit 14 receives the first power supply VDD, the first clock signal CLK1 and the control signal A.

Following the above, the control unit 14 includes a plurality of transistors M6 ~ M8, the first power supply VDD controls the transistor M7 to be in an on state, the first clock signal CLK1 controls the transistor M6 to be in an on or off state, and similarly, the control signal A controls the electric The crystal M8 is turned on or off. When the control signal A controls the transistor M8 to turn on, the control signal C is the reference level REF, so the anti-noise circuit does not enable anti-noise operation. In other words, the control signal A controls the anti-noise circuit does not enable anti-noise operation. When the control signal A controls the transistor M8 to turn off, if the first clock signal CLK1 controls the transistor M6 to turn on, the control signal C is the level of the first power supply VDD, so the anti-noise circuit enables anti-noise work, in other words, The first power supply VDD and the first clock signal CLK1 control the anti-noise circuit to enable anti-noise operation.

Referring to the second figure, the anti-noise unit 15 includes a first transistor M9, a second transistor M10, a third transistor M11 and a fourth transistor M12. The first transistor M9 has an input terminal, a The control end and an output end, the input end is coupled to the driving unit 11 of the first scanning circuit, the control end is coupled to the control unit 14, the output end is coupled to a reference level REF, and the first transistor M9 drives the first scanning circuit The level of one control terminal of the unit 11 is stable at the reference level REF. The second transistor M10 has an input terminal, a control terminal and an output terminal. The input terminal is coupled to the driving unit 11 of the first scanning circuit, the control terminal is coupled to the control unit 14, the output terminal is coupled to the reference level REF, the second The transistor M10 stabilizes the level of the output end of the driving unit 11 of the first scanning circuit to the reference level REF.

Following the above, the third transistor M11 has an input terminal, a control terminal and an output terminal, the input terminal is coupled to a driving unit 13 of the second scanning circuit, the control terminal is coupled to the control unit 14, and the output terminal is coupled to the reference level REF, the third transistor M11 stabilizes the level of the control terminal of the driving unit 13 of the second scanning circuit to the reference level REF. The fourth transistor M12 has an input terminal, a control terminal and an output terminal. The input terminal is coupled to the driving unit 13 of the second scanning circuit, the control terminal is coupled to the control unit 14, and the output terminal is coupled to the reference level REF. The transistor M12 stabilizes the level of the output end of the driving unit 13 of the second scanning circuit to the reference level REF. In other words, when the control signal C controls the control terminals and the output terminals of the drive units 11, 13 to be the reference level REF, the potentials of the control terminals and the output terminals of the drive units 11, 13 can be stabilized to avoid the influence of noise. It will not be affected by signal coupling.

Referring to the second figure, the protection unit 16 may be a transistor M13. The transistor M13 has an input terminal, a control terminal and an output terminal. In the crystal M11 and the fourth transistor M12, the control terminal receives a third clock signal CLK3, and the output terminal is coupled to the reference level REF. When the first clock signal CLK1 and the second clock signal CLK2 are not a reference level (for example: ground potential), the first clock signal CLK1 and the second clock signal CLK2 will have coupling noise to the scanning line, Therefore, the third clock signal CLK3 controls the transistor M13 to be turned off, so that the control signal C is maintained at a high level, and the outputs of the first scanning circuit and the second scanning circuit are maintained at the reference level REF, thereby reducing the coupling noise to the scanning line. Impact.

Following the above, on the contrary, when the first clock signal CLK1 and the second clock signal CLK2 are a reference level REF, the first clock signal CLK1 and the second clock signal CLK2 will not have coupling noise to the scanning line, Therefore, the third clock signal CLK3 controls the discharge of the transistor M13, so that the control signal C changes to the reference level REF. In other words, the protection unit of the present invention 16 According to the third clock signal CLK3, periodically maintain the control terminals of the first transistor M9, the second transistor M10, the third transistor M11, and the fourth transistor M12 at the reference level REF to avoid coupling noise News.

Based on the above, the first scanning circuit and the second scanning circuit of the present invention share an anti-noise circuit, thereby reducing the layout area of the anti-noise circuit. Furthermore, the anti-noise circuit of the present invention resets the control terminals and output terminals of the driving units 11, 13 to maintain the reference level REF, so that the single-stage gate driving circuits 1, 2, 3 can reduce the reset The arrangement of components can also reduce the layout area. In other words, the anti-noise circuit of the present invention achieves both anti-noise and reset functions. Therefore, the present invention reduces the layout area of the gate drive circuit to achieve a narrow border.

Please refer to the third figure, which is a timing diagram of the single-stage gate driving circuit of the multi-output design of the present invention. This timing diagram is a timing diagram of the single-stage gate driving circuit of the present invention, that is, the first single-stage gate driving circuit 1, the second single-stage gate driving circuit 2 and the third single-stage gate of the first figure The operation mode and timing of the driving circuit 3 can refer to the third figure.

In the first interval T1, the start signal S0 is at a high level, and the first setting element M1 and the transistor M8 are in an on state; thus, the level of the control signal A is charged to the level of the first power supply VDD, and because the The first clock signal CLK1 and the second clock signal CLK2 are the reference level REF, there will be no coupling noise, so the control signal C is discharged through the transistor M8 and becomes the reference level REF; the anti-noise circuit is not enabled at this time. And the first scan signal S1 and the first clock signal CLK1 are also the reference level REF. In the second interval T2, the first clock signal CLK1 changes to a high level, and the level of the control signal A is raised to the level of the first power supply VDD plus the first clock signal CLK1 by charging the capacitor C1 Level, at this time the first scan signal S1 can also be raised to a high level, the first scan signal S1 will be The scanning line is charged to a high level; furthermore, the first scanning signal S1 will control the transistor M5 of the second scanning circuit to turn on, so the level of the control signal B will raise the level of the first power supply VDD; at this time the first scanning circuit Working with the second scanning circuit, so the anti-noise circuit does not enable anti-noise work.

In the third interval T3, the first clock signal CLK1 is reduced to the reference level REF, the level of the control signal A is reduced to the level of the first power supply VDD, and the first scan signal S1 is reduced to the reference level REF; The two-clock signal CLK2 is changed from the reference level REF to a high level, so the level of the control signal B is the level of the first power supply VDD plus the level of the second clock signal CLK2; at this time, the second scan signal S2 It can also be raised to a high level and charge the scanning line; in the same way, the second scanning signal S2 will control the setting unit of the next-stage gate driving circuit. In the fourth interval T4, the second clock signal CLK2 is reduced to the reference level REF, the level of the control signal B is also reduced to the level of the first power supply VDD, and the second scan signal S2 is also reduced to the reference level REF; Furthermore, since the third clock signal CLK3 is at a high level, the third scan signal S3 of the second single-stage gate drive circuit 2 (first image) is raised to a high level, and the third scan signal S3 controls the The second setting element M2 of a scanning circuit reduces the level of the control signal A from the level of the first power supply VDD to the level of the second power supply VSS (for example: reference level REF).

In the fifth interval T5, the level of the control signal B in the first single-stage gate drive circuit 1 is maintained at the level of the first power supply VDD, and the fourth clock signal CLK4 controls the second single-stage gate drive The circuit 2 generates a fourth scan signal S4. In the sixth interval T6, at this time, the first clock signal CLK1 is periodically high again, and controls the transistor M6 of the control unit 14 to be turned on, so that the level of the control signal C is the level of the first power supply VDD; Moreover, since the first single-stage gate drive circuit 1 is currently not working, in order to avoid coupling noise of the first clock signal CLK1 to the scanning line, the discharge mechanism is not used to reduce the control in this interval The level of the signal C, and the control signal C controls the anti-noise unit 15 to enable anti-noise operation, so that the control terminals and output terminals of the drive units 11, 13 can be the reference level REF, and the first clock signal CLK1 is reduced Coupling noise.

In the seventh interval T7, the first clock signal CLK1 is at a low level (for example: the reference level REF), the transistor M6 is in the off state, and the second clock signal CLK2 is periodically at a high level, but The level of the control signal C is not reduced by discharging, so the anti-noise unit 15 is still performing anti-noise work, and the second clock signal CLK2 does not have coupling noise to the scanning line. In the eighth interval T8, the third clock signal CLK3 controls the transistor M13 to turn on, and reduces the level of the control signal C to the reference level REF, the anti-noise unit 15 stops performing anti-noise work; furthermore, therefore In the interval, the first clock signal CLK1 and the second clock signal CLK2 are at a low level, so there will be no coupling noise, and there is no need to enable anti-noise work. Subsequent ninth interval T9 to eleventh interval T11 are as described in the aforementioned fifth interval T5 to seventh interval T7, and will not be repeated here.

It can be known from the above description that the plural single-stage gate drive circuits 1, 2, 3 of the display, during operation, the third clock signal CLK3 simultaneously controls the first single-stage of the single-stage gate drive circuits 1, 2, 3 The gate drive circuit 1 is discharged and the second single-stage gate drive circuit 2 is charged. The first clock signal CLK1 simultaneously controls the second single-stage gate drive circuit 2 of the single-stage gate drive circuits 1, 2, 3 to discharge and Three single-stage gate drive circuits 3 are charged.

Please refer to the fourth diagram, which is a circuit diagram of a gate driving circuit with a multi-output design under the third diagram of the present invention. As shown in the figure, it is the second single-stage gate drive circuit 2. The fourth figure shows what is different from the second figure is that the signal received when the gate drive circuit 2 of the fourth figure operates is the previous stage gate The second scan signal S2 of the pole drive circuit 1, the fifth scan signal S5, the third clock signal CLK3, the fourth clock signal CLK4 and the first clock signal CLK1 of the subsequent stage, but the operation mode and the second diagram Gate shown The drive circuit 1 is the same. Furthermore, for the difference, please refer to the first figure, it can be clearly seen the difference between the signal received by the second single-stage gate drive circuit 2 and the first single-stage gate drive circuit 1 during operation.

In summary, the present invention provides a single-stage gate driving circuit with multiple scanning circuits and a multi-output design, wherein a first scanning circuit includes a setting unit and a driving unit, and the setting unit receives a start signal to generate A control signal. The driving unit is coupled to the setting unit and receives the control signal and a first clock signal. The control signal and the first clock signal enable the driving unit to generate a first scanning signal. The driving unit drives the first scan signal to a first level according to the first clock signal, and the driving unit drives the first scan signal to a second level according to the first clock signal, and the first level is higher than the second level Level. A second scanning circuit is coupled to the first scanning circuit and receives the first scanning signal and a second clock signal. The second scanning circuit generates a second scanning signal according to the first scanning signal and the second clock signal.

Claims (8)

A single-stage gate drive circuit with a multi-output design. The single-stage gate drive circuit has a plurality of scanning circuits, including: a first scanning circuit, including: a setting unit, receiving a start signal, and generating a control signal A drive unit, coupled to the setting unit, receives the control signal and a first clock signal, the control signal and the first clock signal cause the drive unit to generate a first scan signal, the drive unit is based on the first A clock signal drives the first scan signal to a first level, the drive unit drives the first scan signal to a second level according to the first clock signal, and the first level is higher than the first level Second level; a second scanning circuit, coupled to the first scanning circuit, receiving the first scanning signal and a second clock signal, the second scanning circuit according to the first scanning signal and the second clock The signal generates a second scanning signal; and an anti-noise circuit, coupled to the first scanning circuit and the second scanning circuit, receives the first clock signal, reduces the noise of the first scanning circuit and the second scanning Noise, wherein the anti-noise circuit includes a control unit that receives a first power supply, the first clock signal, and the control signal, the control signal controls the anti-noise circuit without anti-noise enabled Operation, the first power supply and the first clock signal control the anti-noise circuit to enable anti-noise operation; wherein, the single-stage gate drive circuit outputs the first scanning signal and the second scanning signal to a plurality of pixels, Control these pixels. The single-stage gate drive circuit with multi-output design as described in item 1 of the patent scope, wherein the setting unit includes: a first setting element having an input terminal, a control terminal and an output terminal, the input terminal receiving The first power supply, the control terminal receives the start signal, the output terminal is coupled to the driving unit, the first setting element generates the control signal according to the start signal and the first power supply; and a second setting element, It has an input terminal, a control terminal and an output terminal, the input terminal receives a second power supply, the control terminal receives a third scanning signal, the output terminal is coupled to the driving unit, the second setting element is based on the third The scanning signal and the second power supply set the control signal. The single-stage gate drive circuit with multi-output design as described in item 1 of the patent scope, wherein the drive unit includes: a drive element having an input terminal, a control terminal and an output terminal, the input terminal receiving the first A clock signal, the control terminal is coupled to the setting unit, the output terminal is coupled to the second scanning circuit, the driving element generates the first scanning signal according to the first clock signal and the control signal; and a capacitor , Coupled between the control end and the output end of the driving element, and raising the level of the first scanning signal according to the control signal and the first clock signal. A single-stage gate drive circuit with multi-output design as described in item 1 of the patent scope, wherein the anti-noise circuit includes an anti-noise unit, and the anti-noise unit includes: a first transistor with an input Terminal, a control terminal and an output terminal, the input terminal is coupled to the driving unit of the first scanning circuit, the control terminal is coupled to the control unit, the output terminal is coupled to a reference level, the first transistor enables The level of a control terminal of the driving unit of the first scanning circuit is stable at the reference level; a second transistor has an input terminal, a control terminal and an output terminal, the input terminal is coupled to the first scan In the driving unit of the circuit, the control terminal is coupled to the control unit, the output terminal is coupled to the reference level, and the second transistor stabilizes the level of one output terminal of the driving unit of the first scanning circuit to the reference Level; a third transistor with an input terminal, a control terminal and an output terminal, the input terminal is coupled to a driving unit of the second scanning circuit, the control terminal is coupled to the control unit, the output terminal is coupled Connected to the reference level, the first Three transistors stabilize the level of a control terminal of the driving unit of the second scanning circuit at the reference level; and a fourth transistor having an input terminal, a control terminal and an output terminal, the input terminal being coupled The driving unit connected to the second scanning circuit, the control terminal is coupled to the control unit, the output terminal is coupled to the reference level, and the fourth transistor enables the output terminal of the driving unit of the second scanning circuit to The position is stable at this reference level. The single-stage gate drive circuit with multi-output design as described in item 4 of the patent application scope, wherein the anti-noise circuit includes: a protection unit having an input terminal, a control terminal and an output terminal, the input terminal being coupled Connected to the first transistor, the second transistor, the third transistor and the fourth transistor, the control terminal receives a third clock signal, the output terminal is coupled to the reference level, the protection unit is based on The third clock signal periodically maintains the control terminals of the first transistor, the second transistor, the third transistor, and the fourth transistor at the reference level. A single-stage gate drive circuit with a multi-output design as described in item 1 of the patent scope, wherein a control terminal of the drive unit of the first scan circuit is electrically connected to the control unit through a setting unit of the second scan circuit A control terminal of a driving unit of one of the second scanning circuits. The single-stage gate drive circuit of the multi-output design as described in item 1 of the patent application scope, wherein the single-stage gate drive circuit of the multi-output design is a unidirectional scan. The single-stage gate drive circuit of the multi-output design as described in item 1 of the patent scope, in which a display has a plurality of single-stage gate drive circuits, and a third clock signal controls the single-stage gate drive circuits simultaneously A first single-stage gate drive circuit discharges and a second single-stage gate drive circuit charges, and the first clock signal simultaneously controls the second single-stage gate drive circuits of the single-stage gate drive circuits to discharge and A third single-stage gate drive circuit is charged.