TWI625712B - Gate driver - Google Patents

Abstract

A gate driver includes a multi-stage first shift register circuit, a multi-stage second shift register circuit, and a multi-stage gate drive signal generating circuit. Each of the first shift register circuits is configured to output a first sub-gate drive signal, and each of the second shift register circuits is configured to output a second sub-gate drive signal according to the control signal, each gate The pole drive signal generating circuit is electrically coupled to the at least one first shift register circuit and the at least one second shift register circuit, and each gate drive signal generating circuit is configured to receive the first sub gate The driving signal and the second sub-gate driving signal output a gate driving signal at an output end, and the gate driving signal includes a plurality of pulses.

Description

Gate driver

The invention relates to a gate driver applied to a display device, in particular to a gate driver capable of outputting a signal having a multi-pulse gate drive.

Display devices such as liquid crystal displays have been widely used in daily life. However, as the user's requirements for viewing experience have increased, display devices have also increased in resolution and volume requirements in recent years. In order to avoid the increase in the resolution of the display device and increase the size and cost of the display device, a display device capable of receiving display data in a wireless communication manner has recently been proposed. Such a display device is often required to be equipped with a gate drive having a plurality of pulses. The signal is used to drive the pixels. However, in order to generate a gate drive signal having a plurality of pulses, it is conventional to operate with additional external control signals, which will greatly increase the cost and complexity of the circuit layout.

In order to solve the above drawbacks, the present invention provides a gate driver embodiment. The gate driver includes a multi-stage first shift register circuit, a multi-stage second shift register circuit, and a multi-stage gate drive signal generating circuit. . Each of the first shift register circuits is configured to output a first sub-gate drive signal, and each of the second shift register circuits is configured to output a second sub-gate drive signal according to the control signal, each gate The pole driving signal generating circuit is electrically coupled to the at least one first shift register circuit and the at least one second shift register circuit, and each gate driving signal generating circuit is used The gate driving signal is outputted to an output terminal according to the received first sub-gate driving signal and the second sub-gate driving signal, and the gate driving signal includes a plurality of pulses.

In one embodiment, each gate driving signal generating circuit includes a first transistor and a second transistor, the first transistor has a first end, a second end, and a control end, and the first transistor receives the first end The nth first sub-gate driving signal, the control end of the first transistor receives the n-1th level control signal, and the second end of the first transistor is electrically coupled to the output end. The second transistor has a first end, a second end, and a control end, the first end of the second transistor receives the nth stage second sub-gate drive signal, and the control end of the second transistor receives the n-th stage control The second end of the second transistor M16 is electrically coupled to the second end of the first transistor, and the output terminal is configured to output an nth-level gate driving signal, where n is a positive integer greater than zero.

Therefore, the gate driver embodiment of the present invention generates the gate driving signal by the internal control signal such as the control signal of the second shift register circuit, so the gate driver embodiment of the present invention does not require additional control signals and is stable. The voltage control signal can obtain the required gate driving signal, so the invention can effectively reduce the circuit layout cost and complexity. In addition, the gate driver embodiment of the present invention can also be applied to a conventional display device having a data driver and achieve the effect of pre-charging the gate driver, thereby further enhancing the flexibility of the application of the present invention.

The above and other objects, features, and advantages of the present invention will become more apparent from the description of the appended claims.

100‧‧‧ display device

110‧‧‧ pixel unit

120‧‧‧gate driver

DL‧‧‧ data line

G _o , G _o (1), G _o (2), G _o (3), G _o (4)... G _o (n-1), G _o (n) ‧ ‧ gate drive signal

121‧‧‧First shift register circuit

122‧‧‧Second shift register circuit

123‧‧‧Gate drive signal generation circuit

g, g(n-2), g(n-1), g(n), g(n+1)‧‧‧ first sub-level drive signal

G, G(n-1), G(n), G(n+1)‧‧‧ second sub-gate drive signal

1211, 1221‧‧‧ control signal generation circuit

1212, 1222‧‧‧ Pull-down control signal generation circuit

1213, 1223‧‧‧ pull-down circuit

1214, 1224‧‧‧ drive circuit

1215, 1225‧‧‧ main pull-down circuit

P _G (n), P _g (n), P _G (n-2), P _G (n-1) ‧‧‧ pull-down control signals

Q(n), q(n), Q(n-2), Q(n-1)‧‧‧ control signals

VGL‧‧‧ low voltage level

M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, M14, M15, M16, M17, M18, M19, M20, M21‧‧

U2D‧‧‧ first external signal

D2U‧‧‧ second external signal

C1, C3‧‧‧ capacitor

XCK1, XCK2, CK1, CK2‧‧‧ clock signal

C2, C4‧‧‧ parasitic capacitance

P1‧‧‧ first pulse

P2‧‧‧ second pulse

P3‧‧‧ third pulse

Time ₁ ‧‧‧First time

Time ₂ ‧‧‧Second time

Time ₁₁ , Time ₁₂ , Time ₁₃ ‧‧‧

1 is a schematic view of an embodiment of a display device.

2 is a schematic view of an embodiment of a gate driver of the present invention.

3A is a schematic diagram of an embodiment of a first shift register circuit of the present invention.

FIG. 3B is a schematic diagram of an embodiment of a second shift register circuit of the present invention.

4A is a schematic diagram of an embodiment of a gate driving signal generating circuit of the present invention.

4B is a schematic diagram of an embodiment of a gate driving signal of the present invention.

4C is a schematic view showing another embodiment of the gate driving signal of the present invention.

4D is a schematic view showing another embodiment of the gate driving signal generating circuit of the present invention.

FIG. 5 is a schematic diagram of an embodiment of a signal timing according to the present invention.

Please refer to FIG. 1. FIG. 1 is a schematic diagram of an embodiment of a display device. The display device 100 is, for example, a liquid crystal display device, but is not limited thereto. The display device 100 includes at least a plurality of pixel units 110 and a gate driver 120. Each of the pixel units 110 is electrically coupled to the gate driver 120 and the plurality of data lines DL. The gate driver 120 is for outputting a plurality of gate drive signals G _o (1), G _o (2), G _o (3), G _o (4) ... G _o (n-1), G _o (n), where n is a positive integer greater than zero, and the gate drive signal G _o is a pixel unit 110 for enabling electrical coupling. The data line DL is used for wireless transmission or receiving a plurality of display materials through a data driver (not shown), and the data line DL transmits the received display data to the electrically coupled pixel unit 110. each pixel unit 110 is thus displayed data gate drive signals G _o to actuation of one of the DL reception is enabled through the data line is electrically coupled to the display device 100 by the pixel unit 110 may therefore display the desired Picture.

Please refer to FIG. 2. FIG. 2 is a schematic diagram of an embodiment of a gate driver 120 of the present invention. The gate driver 120 includes a plurality of stages of first shift register circuits 121 and a plurality of stages of second shift register circuits 122. And a plurality of stages of the gate drive signal generating circuit 123, the first shift register circuit 121 of each stage is for outputting the first sub-gate drive signal g of the current stage, and the second shift register of each stage The circuit 122 is for outputting the second sub-gate driving signal G of the current stage. The gate driving signal generating circuit 123 of each stage is for outputting the gate driving signal G _{o of the current stage} . The first shift will be further explained below. The bit register circuit 121, the second shift register circuit 122, and the gate drive signal generating circuit 123 are electrically coupled to each other and the operation method of the gate driver 120.

Please refer to FIG. 3A. FIG. 3A is a schematic diagram of an embodiment of the first shift register circuit 121. FIG. 3A is only one embodiment of the first shift register circuit 121, but is not limited thereto. FIG. 3A is an example in which the first shift register circuit 121 outputs the nth first sub-gate drive signal g(n) as an example. The first shift register circuit 121 includes a control signal generating circuit 1211, a pull-down control signal generating circuit 1212, a pull-down circuit 1213, a driving circuit 1214, and a main pull-down circuit 1215. The control signal generating circuit 1211 is for outputting the nth stage control signal q(n), the pull-down control signal generating circuit 1212 is for outputting the nth stage pull-down control signal P _g (n), and the pull-down circuit 1213 is for receiving the nth stage. Pulling down the control signal P _g (n), and determining whether to stabilize the nth control signal q(n) and the nth first sub-gate drive signal g(n) according to the n-th pull-down control signal P _g (n) The disable voltage level is, for example, a low voltage level VGL, and the low voltage level is, for example, a logic low level, but is not limited thereto. The driving circuit 1214 is configured to receive the nth stage control signal q(n) and output the nth stage first sub-gate driving signal g(n) according to the nth stage control signal q(n), the main pull-down circuit 1215 and the driving circuit 1214. Electrically coupled and receiving the nth first sub-gate driving signal g(n), the main pull-down circuit 1215 is configured to be in the period of the nth first sub-gate driving signal g(n) disabled The n-th first sub-gate drive signal g(n) is maintained at a disable voltage level, such as a low voltage level VGL.

The control signal generating circuit 1211 includes a transistor M4 and a transistor M1. The transistor M4 has a first end, a second end, and a control end. The first end of the transistor M4 receives the first external signal U2D, and the control end of the transistor M4 is used. The first sub-gate driving signal g(n-1) of the n-1th stage is received, wherein, in this embodiment, the first external signal U2D is, for example, a high voltage level, and the high voltage level is, for example, a logic high level. . The transistor M1 has a first end, a second end, and a control end. The first end of the transistor M1 receives the second external signal D2U, and the control end of the transistor M1 receives the n+1th first sub-gate driving signal. G(n+1), the second end of the transistor M1 is electrically coupled to the second end of the transistor M4 And used to output the nth level control signal q(n). In this embodiment, the second external signal U2D is, for example, a low voltage level VGL.

The pull-down control signal generating circuit 1212 includes a first capacitor C1 and a transistor M2. The capacitor C1 has a first end and a second end. The first end of the capacitor C1 is for receiving the clock signal XCK1, and the second end of the capacitor C1 is for outputting. The nth stage pulls down the control signal P _g (n). The transistor M2 has a first end, a second end and a control end. The first end of the transistor M2 is electrically coupled to the second end of the capacitor C1 and receives the nth stage pull-down control signal P _g (n), the transistor M2 The control terminal receives the nth stage control signal q(n), the second end of the transistor M2 is used to receive the low voltage level VGL, and the transistor M2 is used to determine whether the first stage will be based on the nth stage control signal q(n) The n-stage pull-down control signal P _g (n) is maintained at the low voltage level VGL.

The pull-down circuit 1213 includes a transistor M3 and a transistor M6. The transistor M3 has a first end, a second end, and a control end. The first end of the transistor M3 receives the n-th control signal q(n), the transistor M3. The control terminal receives the nth stage pull-down control signal P _g (n), the second end of the transistor M3 is used to receive the low voltage level VGL, and the transistor M3 is used to pull down the control signal P _g (n) according to the nth stage It is decided whether to maintain the nth control signal q(n) at the low voltage level VGL. The transistor M6 has a first end, a second end and a control end. The first end of the transistor M6 is for receiving the nth first sub-gate driving signal g(n), and the control end of the transistor M6 receives the nth stage. Pulling down the control signal P _g (n), the second end of the transistor M6 is for receiving the low voltage level VGL, and the transistor M6 is for determining whether the nth level is based on the nth stage pulldown control signal P _g (n) A sub-gate drive signal g(n) is maintained at a low voltage level VGL.

The driving circuit 1214 includes a transistor M7 having a first end, a second end, and a control end. The first end of the transistor M7 is for receiving the clock signal XCK1, and the control end of the transistor M7 is for receiving the nth stage. Control signal q(n), the second end of the transistor M7 is used to output the nth first sub-gate driving signal g(n), and further, the parasitic capacitance C2 is formed at the first end and the second end of the transistor M7 between. The main pull-down circuit 1215 includes a transistor M5 having a first end, a second end, and a control end. The first end of the transistor M5 is configured to receive the nth first sub-gate drive signal g(n). The control terminal of the transistor M5 is configured to receive the clock signal CK1, and the timing of the clock signal CK1 and the clock signal XCK1 is opposite. The second end of the transistor M5 is for receiving the low voltage level VGL, and the transistor M5 is used for Whether the nth first sub-gate driving signal g(n) is maintained at the low voltage level VGL is determined according to the clock signal CK1.

Please refer to FIG. 3B. FIG. 3B is a schematic diagram of an embodiment of the second shift register circuit 122. The second shift register circuit 122 is used to output the nth second sub-gate drive signal G ( n) is explained as an example. The second shift register circuit 122 includes a control signal generating circuit 1221, a pull-down control signal generating circuit 1222, a pull-down circuit 1223, a driving circuit 1224, and a main pull-down circuit 1225. The control signal generating circuit 1221 is for outputting the nth stage control signal Q(n), the pull-down control signal generating circuit 1222 is for outputting the nth stage pull-down control signal P _G (n), and the pull-down circuit 1223 is for receiving the nth stage. Pulling down the control signal P _G (n), and determining whether to stabilize the nth control signal Q(n) and the nth second sub-gate drive signal G(n) according to the n-th pull-down control signal P _G (n) The banned voltage level is, for example, the aforementioned low voltage level VGL, but is not limited thereto. The driving circuit 1224 is configured to receive the nth stage control signal Q(n) and output the nth stage second sub-gate driving signal G(n) according to the nth stage control signal Q(n), the main pull-down circuit 1225 and the driving circuit 1224. Electrically coupled and receiving the nth second sub-gate driving signal G(n), the main pull-down circuit 1225 is configured to be in the period of the nth second sub-gate driving signal G(n) disabled The n-th second sub-gate drive signal G(n) is maintained at a disable voltage level, such as a low voltage level VGL.

The control signal generating circuit 1221 includes a transistor M11 and a transistor M8. The transistor M11 has a first end, a second end, and a control end. The first end of the transistor M11 receives the first external signal U2D, and the control of the transistor M11. The terminal is configured to receive the second sub-gate driving signal G(n-1) of the n-1th stage. The transistor M8 has a first end, a second end and a control end, the first end of the transistor M8 receives the second external signal D2U, and the control end of the transistor M8 is used to receive the n+1th second sub-gate The second driving end of the transistor M1 is electrically coupled to the second end of the transistor M4 and is used to output the nth stage control signal Q(n).

The pull-down control signal generating circuit 1222 includes a capacitor C3 and a transistor M9. The capacitor C3 has a first end and a second end. The first end of the capacitor C3 is used to receive the clock signal XCK2, and the second end of the capacitor C3 is used to output the nth. The level pull-down control signal P _G (n). The transistor M9 has a first end, a second end, and a control end. The first end of the transistor M9 is electrically coupled to the second end of the first capacitor and receives the nth stage pull-down control signal P _G (n), the transistor The control terminal of the M9 receives the nth stage control signal Q(n), the second end of the transistor M9 is used to receive the low voltage level VGL, and the transistor M9 is used to determine whether to be based on the nth stage control signal Q(n). The nth pulldown control signal P _G (n) is maintained at the low voltage level VGL.

The pull-down circuit 1223 includes a transistor M10 and a transistor M13. The transistor M10 has a first end, a second end, and a control end. The first end of the transistor M10 receives the n-th control signal Q(n), the transistor M10. The control terminal receives the nth stage pull-down control signal P _G (n), the second end of the transistor M10 is used to receive the low voltage level VGL, and the transistor M10 is used to pull down the control signal P _G (n) according to the nth stage. It is determined whether to maintain the nth control signal Q(n) at the low voltage level VGL. The transistor M13 has a first end, a second end and a control end. The first end of the transistor M13 is for receiving the nth second sub-gate driving signal G(n), and the control end of the transistor M13 receives the nth stage. Pulling down the control signal P _G (n), the second end of the transistor M13 is for receiving the low voltage level VGL, and the transistor M13 is for determining whether the nth stage is based on the nth stage pulldown control signal P _G (n) The second sub-gate drive signal G(n) is maintained at a low voltage level VGL.

The driving circuit 1224 includes a transistor M14 having a first end, a second end, and a control end. The first end of the transistor M14 is configured to receive the clock signal XCK2, and the control end of the transistor M14 is configured to receive the nth stage. Control signal Q(n), the second end of the transistor M14 is used to output the nth second sub-gate driving signal G(n), and further, the parasitic capacitance C4 is formed at the first end and the second end of the transistor M14. between. The main pull-down circuit 1225 includes a transistor M12 having a first end, The second end and the control end, the first end of the transistor M12 is used to receive the nth second sub-gate driving signal G(n), and the control end of the transistor M12 is used to receive the clock signal CK2, the clock signal CK2 Contrary to the timing of the clock signal XCK2, the second end of the transistor M12 is used to receive the low voltage level VGL, and the transistor M5 is used to determine whether to drive the nth second sub-gate driving signal according to the clock signal CK2. G(n) is maintained at a low voltage level VGL. The foregoing is only one of the embodiments of the second shift register circuit 122, but is not limited thereto.

Referring to FIG. 4A, FIG. 4A is a schematic diagram of an embodiment of a gate driving signal generating circuit 123 of the present invention. FIG. 4A is a gate driving signal generating circuit 123 for outputting an nth gate driving signal G _O (n). Give an example for explanation. The gate driving signal generating circuit 123 includes a transistor M15 and a transistor M16. The transistor M15 has a first end, a second end, and a control end. The first end of the transistor M15 receives the nth stage first shift register circuit. The nth first sub-gate driving signal g(n) of the output of the nth stage, the control end of the transistor M15 receives the n-1th control signal Q(n) generated by the n-1th second shift temporary storage circuit 122. -1), the second end of the transistor M15 is the output terminal of the gate drive signal generating circuit 123. The transistor M16 has a first end, a second end, and a control end, and the first end of the transistor M16 receives the nth second sub-gate driving signal G(n) outputted by the nth second second shift register circuit 122. The control terminal of the transistor M16 is configured to receive the nth stage control signal Q(n) generated by the nth stage second shift register circuit 122, and the second end of the transistor M16 and the second end of the transistor M15 are electrically The output is used to output the nth gate drive signal G _O (n). Therefore, in this embodiment, the nth gate driving signal G _O (n) includes the first pulse P1 generated by the nth first sub-gate driving signal g(n) and the second sub-stage by the nth stage The second pulse P2 generated by the gate driving signal G(n), the enabling period of the first pulse P1 is shorter than the enabling period of the second pulse P2, the enabling start time of the first pulse P1 and the enabling start time The enable start time of the second pulse P2 and the disable start time are as shown in FIG. 4B.

In other embodiments, the gate driving signal generating circuit 123 further includes a transistor M20 according to the design of the pixel unit 110. As shown in FIG. 4A, the transistor M20 has a first end, a second end, and a control end. The first end of the crystal M20 is configured to receive the n-2th first sub-gate driving signal g(n-2) outputted by the n-2th first shift register circuit 122, and the control end of the transistor M20 The second-stage control signal Q(n-2) is outputted from the second-stage second shift register circuit 123 of the n-2th stage. The second end of the transistor M20 is electrically coupled to the output end. Therefore, in this embodiment, the nth gate driving signal G _O (n) further includes a third pulse P3 generated by the n-2th first sub-gate driving signal g(n-2), and the third pulse The enabling period of P3 is shorter than the enabling period of the second pulse P2, the enabling start time of the third pulse P3 and the enabling start time are earlier than the enabling start times of the first pulse P1 and the second pulse P2 and The start time is disabled, as shown in Figure 4C.

In order to enable the nth gate driving signal G _O (n) to be stably maintained at the forbidden voltage level during the disabled period, in some embodiments, the gate driving signal generating circuit 123 may further include a transistor M17. The transistor M18 and the transistor M19, the transistor M17, the transistor M18, and the transistor M19 are used to stabilize the nth gate driving signal G _O (n) to the low voltage level VGL. As shown in FIG. 4A, the transistor M17 has a first end, a second end, and a control end. The first end of the transistor M17 is electrically coupled to the output end, and the control end of the transistor M17 is used to receive the nth stage and the second end. The nth stage pull-down control signal P _G (n) generated by the shift register circuit 122. The transistor M18 has a first end, a second end, and a control end. The first end of the transistor M18 is electrically coupled to the second end of the transistor M17, and the control end of the transistor M18 is used to receive the n-2th stage. The n-2 stage pull-down control signal P _G (n-2) generated by the second shift register circuit 122, and the second end of the transistor M18 is used to receive the low voltage level VGL. The transistor M19 has a first end, a second end and a control end. The first end of the transistor M19 is electrically coupled to the output end, and the control end of the transistor M19 is used to receive the n-1th stage second shift temporary storage. The n-1th stage pull-down control signal P _G (n-1) generated by the circuit 122 is used by the second end of the transistor M19 to receive the low voltage level VGL.

Please refer to FIG. 4D. FIG. 4D is a schematic diagram of another embodiment of the gate driving signal generating circuit 123. The difference between this embodiment and FIG. 4A is that the gate driving signal generating circuit 123 further includes a transistor M21 and a transistor M21. Having a first end, a second end, and a control end, the transistor M21 The first end is electrically coupled to the control end of the transistor M15, the control end of the transistor M21 is electrically coupled to the first end of the transistor M20, and the second end of the transistor M21 is electrically connected to the low voltage level VGL. Coupling. Therefore, when the second end of the transistor M20 is boosted to the enable voltage level due to the n-2th first sub-gate drive signal g(n-2), the control terminal of the transistor M15 is replaced by the transistor M21. Stabilized at the low voltage level VGL, the transistor M15 can be stably kept off, which can avoid the voltage of the second end of the transistor M20 being borrowed because the transistor M15 is enabled by the n-1th control signal Q(n-1) The case where the transistor M15 leaks.

The operation of the embodiment of the gate driving signal generating circuit 123 will be described below with reference to FIGS. 4A and 5. In the first time period Time ₁ , the gate driving signal generating circuit 123 is configured to output the nth gate driving signal G _O (n) including the first pulse P1, the second pulse P2, and the third pulse P3. The first time period Time ₁ further includes a time period Time ₁₁ , a time period Time _{12 ,} and a time period Time ₁₃ , and the time period ₁₁ , the n-2th level control signal Q(n-2) and the n-2th stage first sub-gate driving signal g(n-2) enables the voltage level, so the transistor M20 is turned on and the nth-level first sub-gate drive signal g(n-2) is output to the output terminal, which is the third pulse P3 described above. The n-2th control signal Q(n-2) is represented as the next two levels of the nth level control signal Q(n). Then, in the period Time ₁₂ , the n-1th control signal Q(n-1) and the nth first sub-gate driving signal g(n) are enabled voltage levels, and the transistor M15 is turned on and will be nth. The first sub-gate drive signal g(n) is output to the output terminal, which is the first pulse P1 described above. Then, in the time period Time ₁₃ , the nth control signal Q(n) is the enable voltage level and the nth second sub-gate drive signal G(n) is the enable voltage level, and the transistor M16 is turned on and The nth second sub-gate driving signal G(n) is outputted to the output end, which is the second pulse P2 described above. At the same time, in the first time period Time ₁ , the enable period of the n-2th pull-down control signal P _G (n-2) and the n-th pull-down control signal P _G (n) does not overlap, and the n-2th pull-down control The enable period of the signal P _G (n-2) overlaps with the enable period of the second sub-gate drive signal G(n) of the nth stage, and the n-1th pull-down control signal P _G (n-1) is forbidden. The disable period of the n-2th pull-down control signal P _G (n-2), the n-1th pull-down control signal P _G (n-1), and the n-th pull-down control signal P _G (n) The overlap, that is, the n-th pull-down control signal P _G (n) and the n-2-th pull-down control signal P _G (n-2) are not simultaneously enabled, and the n-1th pull-down control signal P _G ( n-1) remains disabled, so transistor M17, transistor M18 and transistor M19 are turned off in _a first holding period Time. In the second time period Time ₂ , the nth gate driving signal G _O (n) needs to be kept at the forbidden voltage level, so the enabling period of the n-2th pulldown control signal P _G (n-2) The enable period of the n-th pull-down control signal P _G (n) overlaps and does not overlap with the enable period of the n-1th pull-down control signal P _G (n-1). Therefore, the transistor M17 and the transistor M18 are simultaneously enabled, and the enabling time of the transistor M17 and the transistor M18 and the transistor M19 does not overlap, and the transistor M17 and the transistor M18 and the transistor M19 are enabled by staggering. The transistor M17, the transistor M18, and the transistor M19 maintain the nth gate drive signal G _O (n) at the disable voltage level.

According to the above embodiment, the gate driving signal generating circuit 123 of the present invention generates the gate driving signal G _{O by the} internal control signal such as the control signal P and the control signal Q being pulled down by the second shift register circuit 122. The gate driving signal generating circuit 123 of the present invention can obtain the required gate driving signal G _O without additional control signals and voltage stabilizing control signals, so that the present invention can effectively reduce the circuit layout cost and complexity. In addition, the gate driver 120 of the present invention can also be applied to a conventional display device having a data driver and achieve the effect of pre-charging the gate driver 120, thereby further enhancing the flexibility of the application of the present invention.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Any one skilled in the art can make some modifications and retouchings without departing from the spirit and scope of the present invention. The scope is subject to the definition of the patent application scope.

Claims (10)

A gate driver includes: a multi-stage first shift register circuit, each of the first shift register circuits for outputting a first sub-gate drive signal; and a multi-level second shift register The second shift register circuit is configured to output a second sub-gate driving signal according to a control signal; and a multi-level gate driving signal generating circuit, each of the gate driving signal generating circuits and The first shift register circuit and the at least one second shift register circuit are electrically coupled to each other, and each of the gate drive signal generating circuits is configured to receive the first sub-gate drive signal according to the first And the second sub-gate driving signal outputs a gate driving signal at an output end, and the gate driving signal includes a plurality of pulses. The gate driver of claim 1, wherein the gate driving signal generating circuit comprises: a first transistor having a first end, a second end, and a control end, the first transistor The first end receives an nth stage first sub-gate driving signal, and the control end of the first transistor receives an n-1th level control signal, the second end of the first transistor and the output The second transistor has a first end, a second end, and a control end, and the first end of the second transistor receives an nth second sub-gate drive signal The second end of the second transistor is electrically coupled to the second end of the first transistor, and the output end is electrically coupled to the second end of the second transistor. To output an nth gate drive signal, where n is a positive integer greater than zero. The gate driver of claim 2, wherein, in a first period, the nth gate driving signal comprises a first pulse of the nth first subgate driving signal and the nth a second pulse of the second sub-gate driving signal, the enabling period of the first pulse being shorter than the enabling period of the second pulse, the enabling start time of the first pulse and the inactivation start time being early The activation start time of the second pulse and the disable start time. The gate driver of claim 3, wherein the gate driving signal generating circuit is electrically coupled to the at least two first shift register circuits, and the gate driving signal generating circuit further comprises a third transistor having a first end, a second end, and a control end, wherein the first end of the third transistor is configured to receive an nth-level first sub-gate drive signal, the first The control terminal of the tri-crystal is configured to receive an n-th level control signal, and the second end of the third transistor is electrically coupled to the output end. The gate driver of claim 4, wherein, in the first period, the nth gate driving signal further comprises a third pulse, and the third pulse is shorter than the second pulse During the enabling period, the enable start time and the disable start time of the third pulse are earlier than the first pulse and the enable start time of the second pulse and the disable start time. The gate driver according to claim 4, wherein the gate driving signal generating circuit further comprises: a fourth transistor having a first end, a second end, and a control end, the fourth transistor The first end is electrically coupled to the control end of the first transistor, and the control end of the fourth transistor is electrically coupled to the first end of the third transistor, the fourth transistor The second end is electrically coupled to a low voltage level. The gate driver of claim 3, wherein each of the second shift register circuits generates a pull-down control signal, and each of the gate drive signal generating circuits is configured to be used according to the first sub-gate The pole drive signal, the second sub-gate drive signal, and the multi-level pull-down control signal output the gate drive signal at the output end. The gate driver of claim 7, wherein the gate driving signal generating circuit comprises: a third transistor having a first end, a second end, and a control end, the third transistor The first end is electrically coupled to the output end, the control end of the third transistor is configured to receive an nth stage pulldown control signal; and the fourth transistor has a first end and a second end And a control terminal, the first end of the fourth transistor is electrically coupled to the second end of the third transistor, and the control end of the fourth transistor is configured to receive an n-2th pulldown Controlling a signal, the second end of the fourth transistor is configured to receive a low voltage level; and a fifth transistor having a first end, a second end, and a control end, the fifth transistor The first end is electrically coupled to the output end, the control end of the fifth transistor is configured to receive an n-1th stage pull-down control signal, and the second end of the fifth transistor is configured to receive the low Voltage level. The gate driver of claim 8 does not overlap during the first period of time, the n-2th pulldown control signal and the enable period of the nth pulldown control signal, the n-2th pulldown The enable period of the control signal overlaps with the enable period of the nth second sub-gate drive signal, the n-1th pull-down control signal is disabled, and the n-2th pull-down control signal, the nth The -1 level pull-down control signal and the disable period of the n-th pull-down control signal partially overlap, and during a second period, the enable period of the n-2th pull-down control signal and the nth The enable period of the level pull-down control signal overlaps and does not overlap with the enable period of the n-1th stage pull-down control signal. The gate driver of claim 8, wherein each of the second shift register circuits comprises: a control signal generating circuit for outputting the nth stage control signal; and a pull control signal generating circuit For outputting the nth stage pull-down control signal; a pull-down circuit for receiving the n-th pull-down control signal; a driving circuit for receiving the nth-level control signal, the driving circuit is controlled according to the n-th stage The signal outputs the nth second sub-gate driving signal; and a main pull-down circuit electrically coupled to the driving circuit and receiving the nth second sub-gate driving signal.