TWI622143B - Electronic package and its manufacturing method - Google Patents

Abstract

An electronic package and a manufacturing method thereof include forming a stacked structure with a plurality of packaging units, and forming at least one conductive pillar electrically connected to each of the packaging units in the stacked structure, so as to reach the jumper line and shorten the conductive pillar through the conductive pillar. The purpose of conducting the path of the wiring can reduce the number of wiring layers and wiring length required for wiring.

Description

Electronic package and manufacturing method thereof

The invention relates to a packaging technology, in particular to a stacked electronic package and a manufacturing method thereof.

Due to the vigorous development of the electronics industry, most of the electronic products are constantly moving towards the goals of miniaturization, light weight and high speed. Many of these electronic products need to integrate multiple chips to achieve miniaturization or high speed. aims.

There are many known types of multi-chip package structures. In order to achieve a small surface bonding area, the common multi-chip module package (MCM) generally places multiple chips side by side on a carrier. After molding and leveling, a redistribution circuit layer is formed. In addition, there are three-dimensional forms in which a plurality of wafers are stacked.

FIG. 1 is a schematic cross-sectional view of a conventional semiconductor package 1. As shown in FIG. 1, the semiconductor package 1 includes a circuit board 10, a semiconductor wafer 11, an RF chip 12, and a control chip 13 stacked on the circuit board 10, and the semiconductor wafer 11, the RF chip 12, and The control chip 13 is electrically connected to the circuit board 10 with a plurality of bonding wires 14, and is packaged with a packaging gel 16 The semiconductor wafer 11, the radio frequency wafer 12 and the control wafer 13 are covered.

However, in the conventional semiconductor package 1, due to the manufacturing process limitation of the bonding wires 14, it is difficult to reduce the overall height of the semiconductor package 1, so the semiconductor package 1 cannot meet the miniaturization requirements.

Therefore, how to overcome the problems of the above-mentioned conventional technologies has become an urgent problem to be solved.

In view of the lack of the above-mentioned conventional technologies, the present invention provides an electronic package comprising: a stacked structure with a plurality of packaging units, wherein each of the packaging units includes a packaging gel, an electronic component buried in the packaging gel, and A fan-out line redistribution structure provided on the packaging colloid and electrically connected to the electronic component, and the fan-out line redistribution structure includes at least one insulation portion and a circuit layer combined with the insulation portion; and at least one conductive The pillars are the redistribution structure of the fan-out line and the packaging gel that run through the plurality of packaging units at the same time, so that the conductive pillar is at least electrically connected to the two circuit layers, and the peripheral surface of the conductive pillar directly contacts the fan-out of the plurality of packaging units. Type circuit redistribution structure and packaging gel.

The invention further provides a method for manufacturing an electronic package, comprising: forming a stacked structure with a plurality of packaging units, wherein each of the packaging units includes a packaging colloid, an electronic component buried in the packaging colloid, and the package A fan-out circuit redistribution structure electrically connected to the electronic component on the colloid, and the fan-out circuit redistribution structure includes at least one insulating portion and a circuit layer combined with the insulating portion; forming at least one communicating with the plurality of packages Perforations of the stacked structure of the units; and forming a conductive material in the perforations for electrical conduction Pillars, and the conductive pillars run through the fan-out circuit redistribution structure and packaging gel of the plurality of packaging units at the same time, so that the conductive pillars are electrically connected to at least two of the circuit layers, and the peripheral surface of the conductive pillars directly contact the plurality of packaging units Fan-out circuit redistribution structure and encapsulation gel.

In the aforementioned electronic package and its manufacturing method, at least two of the packaging units have different thicknesses.

In the aforementioned electronic package and its manufacturing method, the sizes of the electronic components of at least two of the packaging units are different.

In the aforementioned electronic package and its manufacturing method, the electrical conductor (or the perforation) sequentially penetrates the fan-out circuit redistribution structure and the packaging gel of the packaging units.

In the aforementioned electronic package and its manufacturing method, the conductive pillar (or perforation) is tapered.

In the aforementioned method for manufacturing an electronic package, the manufacturing process of the packaging unit includes: placing an electronic component on a carrier, wherein the electronic component has an opposite active surface and a non-active surface, and the active component is used to connect the carrier Forming a packaging gel on the carrier and covering the electronic component; removing the carrier to expose the active surface of the electronic component; and forming an electrical connection to the electronic component on the active surface of the packaging gel and the electronic component Fan-out line redistribution structure.

In the aforementioned method for manufacturing an electronic package, the process of forming the stacked structure with the plurality of packaging units includes: placing another electronic component on the fan-out line redistribution structure, wherein the other electronic component has a relative effect Surface and non-acting surface, and the non-acting surface is connected to the fan-out line to re-bundle Forming another packaging colloid on the fan-out circuit redistribution structure and covering the other electronic component; and forming an electrical connection to the other packaging colloid on the active surface of the other electronic component Another redistribution circuit structure of electronic components.

As can be seen from the above, the electronic package and its manufacturing method of the present invention mainly pass through the packaging units through the perforations, so that a single conductive pillar can be selectively electrically connected to a circuit of a redistribution circuit of each packaging unit. Therefore, the electronic package of the present invention can not only achieve the purpose of a jumper line, but also shorten the path of the conductive line, and can effectively reduce the number of wiring layers and wiring length required for wiring.

In addition, compared with the wiring method of the conventional technology, the electronic package of the present invention has an extension length of the conductive pillars equal to the sum of the stacking heights of the packaging units, so it is not necessary to consider the arc height of the conventional bonding wire, which is effective. Reduce overall height.

1‧‧‧ semiconductor package

10‧‧‧Circuit board

11‧‧‧Semiconductor wafer

12‧‧‧RF chip

13‧‧‧control chip

14‧‧‧ Welding Wire

16‧‧‧ encapsulated colloid

2‧‧‧electronic package

2a‧‧‧Package Unit

20‧‧‧carrying parts

200‧‧‧ Adhesive layer

21‧‧‧Electronic components

21a‧‧‧active surface

21b‧‧‧ non-active surface

210‧‧‧ electrode pad

22‧‧‧ encapsulated colloid

22a‧‧‧ 第一 表面

22b‧‧‧Second surface

23‧‧‧ Redistribution structure of fan-out line

230‧‧‧Insulation Department

231‧‧‧line layer

24,34,34’‧‧‧ conductive post

24c, 34c ‧‧‧ weekly

240,340,340’‧‧‧perforation

25‧‧‧ conductive element

9‧‧‧ support plate

S‧‧‧ cutting path

Figure 1 is a schematic sectional view of a conventional semiconductor package; Figures 2A to 2G are schematic sectional views of a method for manufacturing an electronic package of the present invention; Figures 3A and 3B are parts of other embodiments corresponding to Figure 2F 4A and 4B are partial top views of different embodiments corresponding to FIG. 2F.

The following describes the embodiment of the present invention by using specific embodiments. Formula, those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

It should be noted that the structures, proportions, sizes, etc. shown in the drawings in this specification are only used to match the content disclosed in the specification for the understanding and reading of those skilled in the art, and are not intended to limit the implementation of the present invention. The limited conditions are not technically significant. Any modification of the structure, change of the proportional relationship, or adjustment of the size should still fall within the scope of this invention without affecting the effects and goals that can be achieved by the present invention. The technical content disclosed by the invention can be covered. At the same time, the terms such as "upper", "first", "second", and "one" cited in this specification are only for the convenience of description, and are not intended to limit the scope of the present invention. Changes or adjustments in their relative relationships shall be considered to be the scope of the present invention without substantial changes in the technical content.

2A to 2G are schematic cross-sectional views of a method for manufacturing the electronic package 2 according to the present invention.

As shown in FIG. 2A, a carrier 20 is provided, and a plurality of electronic components 21 are placed on the carrier 20.

In this embodiment, the carrier 20 is a circular plate body made of semiconductor material such as glass, and an adhesive layer 200 or a release layer is formed on the substrate by coating, so that the electronic components 21 are disposed on the adhesive layer. Layer 200 or release layer.

Furthermore, the electronic component 21 is an active component, a passive component, or a combination thereof, and the active component is, for example, a semiconductor wafer, and the passive component is, for example, a resistor, a capacitor, and an inductor. In this embodiment, the electronic component 21 is, for example, a semiconductor wafer, and has an opposite active surface 21a and a non-active surface. 21b, the active surface 21a has a plurality of electrode pads 210, and the electronic component 21 is disposed on the adhesive layer 200 or the release layer with its active surface 21a.

As shown in FIG. 2B, a packaging gel 22 is formed on the adhesive layer 200 or the release layer of the carrier 20 to cover the electronic component 21.

In this embodiment, the encapsulating gel 22 has a first surface 22a and a second surface 22b opposite to each other, and the encapsulating gel 22 is bonded to the adhesive layer 200 or the release layer of the carrier 20 by its first surface 22a.

Furthermore, the encapsulating gel 22 is made of epoxy resin or other suitable materials, which can be formed by lamination or molding.

In addition, a leveling process can be performed according to requirements, so that the non-active surface 21 b of the electronic component 21 is exposed on the second surface 22 b of the packaging gel 22. For example, the leveling process uses a grinding method to remove the material of the packaging colloid 22, and may remove a portion of the material of the non-active surface 21b of the electronic component 21 as required.

As shown in FIG. 2C, the carrier 20 and the adhesive layer 200 or the release layer are removed to expose the first surface 22 a of the packaging gel 22 and the active surface 21 a of the electronic component 21.

In this embodiment, the first surface 22 a of the packaging gel 22 is flush with the active surface 21 a of the electronic component 21, and the second surface 22 b of the packaging gel 22 is flush with the non-active surface 21 b of the electronic component 21.

As shown in FIG. 2D, a fan out circuit redistribution structure (RDL) 23 is formed on the first surface 22a of the encapsulant 22 by a redistribution layer (RDL) process. On the active surface 21a of the electronic component 21, the fan-out circuit redistribution structure 23 is electrically connected to the electrode pad 210 of the electronic component 21 to form a packaging unit 2a.

In this embodiment, the layout of the general circuit redistribution structure (RDL) is defined as two types of fan-in and fan-out with respect to the chip. Specifically, the wiring for reducing the chip circuit specifications (line width / space) is a fan-in type, and the wiring for enlarging the chip circuit specifications (line width / space) is a fan-out type.

Furthermore, the fan-out line redistribution structure 23 includes at least one insulating portion 230 and at least one circuit layer 231 combined with the insulating portion 230. For example, the material forming the circuit layer 231 is copper, and the material forming the insulating portion 230 is, for example, polybenzoxazole (PBO), polyimide (PI), or prepreg. (Prepreg, PP for short) and other dielectric materials.

As shown in FIG. 2E, the aforementioned packaging unit 2a is placed on a support plate 9, and with reference to the aforementioned process, another electronic component is formed on the fan-out line redistribution structure 23, another packaging gel is formed, and Another fan-out circuit redistribution structure finally forms a stacked structure with a plurality of packaging units 2a on the support plate 9, and then forms a plurality of through holes 240 communicating with the packaging units 2a.

In this embodiment, the packaging units 2a are stacked on each other in the same placement direction. For example, the second surface 22b of the packaging gel 22 of each of the packaging units 2a faces downward, and the fan-out line redistribution structure 23 faces upward.

In addition, the thickness of at least two of the packaging units 2a is different, and the sizes of the electronic components 21 of the at least two of the packaging units 2a are different. However, the thicknesses of the packaging units 2a may be the same or different according to requirements, and the number, function, size, and type of electronic components embedded in the packaging units 2a may also be the same or different according to requirements, and may be based on actual needs. Change settings.

In addition, the perforations 240 are drilled by etching, machine drilling, or laser from a predetermined position, and sequentially run through the fan-out circuit redistribution structure 23 and the packaging gel 22 of each packaging unit 2a without Will pass through the electronic component 21. It should be understood that, because there is no electrical function in the encapsulant 22 of the lowermost packaging unit 2a, the through holes 240 may be selectively extended (as shown in FIG. 2E) or not extended (not shown) to the lowermost package. The encapsulant 22 of the unit 2a.

As shown in FIG. 2F, a conductive material is formed in the through hole 240 as a conductive pillar 24, and a single conductive pillar 24 penetrates the fan-out circuit redistribution structure 23 and the packaging gel 22 of the plurality of packaging units 2a at the same time, so that the A single conductive pillar 24 is electrically connected to at least two of the circuit layers 231, and a peripheral surface 24c of the conductive pillar 24 directly contacts the fan-out circuit redistribution structure 23 and the packaging gel 22 of the plurality of packaging units.

In this embodiment, the material of the conductive post 24 is a conductive glue, such as a copper metal material or a solder material.

Furthermore, the conductive pillar 24 may not contact the circuit layer 231 (as shown in FIG. 4A) or contact the circuit layer 231 (as shown in FIG. 4B) according to requirements, for selection of the circuit layer 231 to be electrically connected. To achieve the purpose of jumper.

As shown in FIG. 2G, a singulation process is performed along the cutting path S shown in FIG. 2F, and the support plate 9 is removed to obtain a plurality of electronic packages 2, and a single electronic package 2 is a plurality of electronic packages. The components 21 are three-dimensionally stacked and integrated into a three-dimensional (3D) stacked type.

In this embodiment, a plurality of conductive elements 25 such as solder balls can be formed on the circuit layer 231 of the outermost packaging unit 2a for subsequent connection as a circuit Board, package structure or other electronic devices (not shown).

Furthermore, in other embodiments, as shown in FIGS. 3A and 3B, the conductive posts 34, 34 ', according to the design requirements and the choice of the conductive effect, the perforations 340, 340' can be tapered, so that the end of the hole is up. Big down and small (as shown in Figure 3A) or up small and big (as shown in Figure 3B).

Therefore, the manufacturing method of the present invention uses the through holes 240, 340, 340 'to penetrate different packaging units 2a at the same time, so that a single conductive pillar 24, 34, 34' can selectively electrically connect the fan-out line redistribution structure of the packaging unit 2a. The wiring layer 231 of 23, therefore, the electronic package 2 of the present invention can not only achieve the purpose of jumper wiring, but also shorten the path of the conduction line, and can effectively reduce the number of wiring layers and wiring length required for wiring.

Furthermore, compared to the wiring method of the conventional technology, the extension length of the conductive pillars 24, 34, 34 'of the electronic package 2 of the present invention is at most equal to the sum of the stack heights of the packaging units 2a, so it is not necessary to consider The arc height of the welding line effectively reduces the overall height.

The present invention also provides an electronic package 2 comprising: a plurality of packaging units 2a stacked in a plurality of phases, and at least one conductive post 24, 34, 34 'passing through each of the packaging units 2a.

The packaging unit 2a includes a packaging gel 22, at least one electronic component 21 embedded in the packaging gel 22, and a fan-out circuit weight provided on the packaging gel 23 and electrically connected to the electronic component 21. The layout structure 23 and the fan-out line redistribution structure 23 include at least one insulation portion 230 and a circuit layer 231 combined with the insulation portion 230.

The conductive pillars 24, 34, and 34 'all penetrate the plurality of packaging units at the same time. The fan-out circuit redistribution structure 23 of 2a and the encapsulation gel 22 make the conductive pillars 24, 34, 34 'electrically connect at least two of the circuit layers 231, and the peripheral surface 24c of the conductive pillars 24, 34, 34' 34c directly contacts the fan-out circuit redistribution structure 23 and the packaging gel 22 of the plurality of packaging units 2a.

In one embodiment, at least two of the packaging units 2a have different thicknesses.

In one embodiment, at least two of the electronic components 21 of the packaging unit 2a have different sizes.

In one embodiment, the conductive pillars 24, 34, 34 'sequentially extend through the fan-out line redistribution structure 23 and the packaging gel 22 of the packaging units 2a.

In one embodiment, the conductive pillars 34, 34 'are tapered.

In summary, the electronic package and its manufacturing method of the present invention extend through the conductive posts through each of the packaging units to electrically connect the fan-out circuit redistribution structure of each of the packaging units, so that the present invention can not only To achieve the purpose of jumper wiring, and can shorten the path of the conductive line, and can effectively reduce the number of wiring layers and wiring length required for wiring, Furthermore, since the extension length of the conductive pillars of the present invention is at most equal to the sum of the stacked heights of the packaging units, the electronic package of the present invention can effectively reduce its overall height.

The above embodiments are used to exemplify the principle of the present invention and its effects, but not to limit the present invention. Anyone skilled in the art can modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the rights of the present invention should be listed in the scope of patent application described later.

Claims (12)

An electronic package includes: a stacked structure of a plurality of packaging units, wherein each packaging unit includes a packaging gel, an electronic component buried in the packaging gel, and the packaging gel is electrically connected to the packaging gel. Fan-out line redistribution structure of electronic components, and the fan-out line redistribution structure includes at least one insulation portion and a circuit layer combining the insulation portion; and at least one conductive pillar, which is a fan that runs through the plurality of packaging units at the same time. The redistribution structure of the outgoing line and the encapsulating gel make the conductive pillar be electrically connected to at least two of the circuit layers, and the peripheral surface of the conductive column directly contacts the redistribution structure and the encapsulating gel of the fan-out circuit of the plurality of packaging units. The electronic package according to item 1 of the scope of patent application, wherein at least two of the packaging units have different thicknesses. The electronic package according to item 1 of the scope of patent application, wherein the dimensions of the electronic components of at least two of the packaging units are different. The electronic package according to item 1 of the scope of the patent application, wherein the conductive pillars sequentially extend through the fan-out circuit redistribution structure and the packaging gel of the packaging units. The electronic package as described in item 1 of the patent application scope, wherein the conductive pillar is tapered. An electronic package manufacturing method includes forming a stacked structure with a plurality of packaging units, wherein each packaging unit includes a packaging colloid, an electronic component embedded in the packaging colloid, and an electrical component disposed on the packaging colloid and electrically Fan for sexually connecting the electronic component An outgoing line redistribution structure, and the fan-out line redistribution structure includes at least one insulation portion and a circuit layer combining the insulation portion; forming at least one perforation communicating with the stacked structure of the plurality of packaging units; and forming a conductive material A conductive pillar is used in the perforation, and the conductive pillar penetrates the fan-out circuit redistribution structure and packaging gel of the plurality of packaging units at the same time, so that the conductive pillar is electrically connected to at least two of the circuit layers, and the periphery of the conductive pillar The surface directly contacts the fan-out circuit redistribution structure of the plurality of packaging units and the packaging gel. According to the method for manufacturing an electronic package described in item 6 of the scope of patent application, wherein at least two of the packaging units have different thicknesses. According to the method for manufacturing an electronic package as described in item 6 of the scope of patent application, wherein the dimensions of the electronic components of at least two of the packaging units are different. According to the manufacturing method of the electronic package described in item 6 of the scope of the patent application, wherein the perforations are sequentially penetrated through the fan-out circuit redistribution structure and the encapsulating gel of the packaging units. According to the method for manufacturing an electronic package as described in item 6 of the scope of patent application, wherein the perforation is tapered. According to the method for manufacturing an electronic package described in item 6 of the scope of application for a patent, wherein the manufacturing process of the packaging unit includes: placing an electronic component on a carrier, wherein the electronic component has an opposite active surface and a non-active surface, And connecting the carrier with the active surface; forming a packaging gel on the carrier and covering the electronic component; Removing the carrier to expose the active surface of the electronic component; and forming a fan-out circuit redistribution structure electrically connecting the electronic component on the active surface of the packaging gel and the electronic component. According to the manufacturing method of the electronic package described in item 6 of the scope of the patent application, wherein the process of forming the stacked structure with the plurality of packaging units includes: placing another electronic component on the fan-out line redistribution structure, wherein The other electronic component has an opposite active surface and a non-active surface, and the fan-out circuit redistribution structure is connected with the non-action surface; another encapsulating gel is formed on the fan-out circuit redistribution structure and covers the other An electronic component; and another fan-out circuit redistribution structure electrically connected to the other electronic component on the active surface of the other packaging colloid and the other electronic component.