TWI620483B - Manufacturing method of circuit board - Google Patents

Abstract

A method of manufacturing a circuit board. The electronic component configured with the plurality of pads is placed in the receiving recess formed by the bonding of the substrate and the adhesive layer. A dielectric layer covering the pads, the electronic components, the adhesive layer, and the substrate is formed, and the dielectric layer is etched to expose the upper surface of the pads. Next, a composite material layer is formed to cover the pad and the dielectric layer, and the composite material layer sequentially includes a plateable dielectric layer, a conductive polymer layer, and a plating resist layer from bottom to top. Thereafter, a plurality of openings are formed in the composite layer to expose portions of the pads and portions of the dielectric layer. A metal layer connected to the conductive polymer layer is formed on the bottom of the opening and a portion of the sidewall formed of the plateable dielectric layer and the conductive polymer layer. A wiring layer is formed in the opening, and the conductive polymer layer and the plating resist are removed, and the upper surface of the wiring layer is aligned with the upper surface of the plateable dielectric layer.

Description

Circuit board manufacturing method

The present invention relates to a method of fabricating a circuit board, and more particularly to a method of fabricating a circuit board capable of increasing wiring density.

In recent years, with the rapid development of electronic technology, more humanized technology products have been introduced, and these technology products are designed to be light, thin, short and small. In the conventional circuit board manufacturing method, based on the lithography deviation factor, the annular ring limitation causes the width of the pad to be larger than the width of the via hole, thereby causing a problem that the area usage rate is lowered, so that the wiring density is affected. influences. 1 is a schematic structural view of a conventional circuit board. As shown in FIG. 1, the width of the pad 130 connected to the circuit layer 140 is larger than that of the via hole 120 connected to the conductive layer 110, and thus cannot be reduced. As a result, both area usage and wiring density are degraded, which is not conducive to the design of electronic products. Furthermore, the conventional circuit board structure may also have a problem of thin line peeling.

Based on the above, how to increase the area utilization rate, increase the wiring density, and improve the thin line peeling problem are the goals that those skilled in the art are eager to achieve.

The invention provides a method for manufacturing a circuit board, which can increase the area utilization rate and the wiring density of the circuit board, and at the same time improve the thin line stripping problem.

The invention provides a method for manufacturing a circuit board, comprising the following steps. First, a core layer is provided, wherein the core layer is included in the core dielectric layer and the conductive layer on the core dielectric layer, and then the first composite material layer is formed to cover the conductive layer and the core dielectric layer, and the first composite material layer is And sequentially comprising a first plateable dielectric layer, a first conductive polymer layer and a first plating resist. Thereafter, a plurality of first openings are formed in the first composite layer, each of the first openings corresponding to each of the conductive layers to expose a portion of the conductive layer. Next, a first metal layer is formed on the bottom of the first opening and a portion of the sidewall formed by the first plateable dielectric layer and the first conductive polymer layer, and the first metal layer is connected to the first conductive polymer layer. Then, a via hole is formed in the first opening, and the first conductive polymer layer and the first plating resist are removed, and the upper surface of the via hole is aligned with the upper surface of the first plateable dielectric layer. Next, a second composite material layer is formed to cover the via holes and the first plateable dielectric layer, and the second composite material layer sequentially includes a second plateable dielectric layer, a second conductive polymer layer, and a second Secondary coating. Thereafter, a plurality of second openings are formed in the second composite material layer to expose a portion of the via holes and a portion of the first plateable dielectric layer. Next, a second metal layer is formed on the bottom of the second opening and a portion of the sidewall formed by the second plateable dielectric layer and the second conductive polymer layer, and the second metal layer is connected to the second conductive polymer layer. Then, a wiring layer is formed in the second opening, and the second conductive polymer layer and the second plating resist are removed, and the upper surface of the wiring layer is aligned with the upper surface of the second switchable dielectric layer.

In an embodiment of the invention, the material of the first anti-plating layer and the second anti-plating layer comprises a hydrophobic polymer material, and the hydrophobic polymer material comprises a polymer material not containing a hydroxyl functional group or a carboxyl functional group.

In an embodiment of the invention, the hydrophobic polymer material comprises an epoxy resin, a polyamidamine, a liquid crystal polymer, a methacrylate type resin, a vinyl phenyl type resin, an allyl type resin, a polyacrylate. A resin, a polyether resin, a polyolefin resin, a polyamine resin, a polyoxyalkylene resin, or a combination thereof.

In an embodiment of the invention, the method of forming the first opening and the second opening comprises exposure development or laser drilling.

In an embodiment of the invention, the first composite material layer and the second composite material layer are formed by a lamination process, and the temperature of the lamination process is 60 ° C to 150 ° C.

The invention provides a method for manufacturing a circuit board, comprising the following steps. First, a substrate having a first surface and a second surface is provided, and a through hole penetrating the first surface and the second surface is formed. Thereafter, the adhesive layer is bonded to the second surface to form a receiving recess, and the electronic component configured with the plurality of pads is placed in the receiving recess. Next, a dielectric layer covering the pad, the electronic component, the adhesive layer and the first surface is formed, and the dielectric layer is etched to expose the upper surface of the pad. Then, a composite material layer is formed to cover the pad and the dielectric layer, and the composite material layer sequentially includes a plateable dielectric layer, a conductive polymer layer and a plating resist layer from bottom to top. Next, a plurality of openings are formed in the composite layer to expose portions of the pads and portions of the dielectric layer. A metal layer is formed on the bottom of the opening and a portion of the sidewall formed by the plateable dielectric layer and the conductive polymer layer, and the metal layer is connected to the conductive polymer layer. Finally, a wiring layer is formed in the opening, and the conductive polymer layer and the plating resist are removed, and the upper surface of the wiring layer is aligned with the upper surface of the plateable dielectric layer.

In an embodiment of the invention, the material of the plating resist comprises a hydrophobic polymer material, and the hydrophobic polymer material comprises a polymer material not containing a hydroxyl functional group or a carboxyl functional group.

In an embodiment of the invention, the hydrophobic polymer material comprises an epoxy resin, a polyamidamine, a liquid crystal polymer, a methacrylate type resin, a vinyl phenyl type resin, an allyl type resin, a polyacrylate. A resin, a polyether resin, a polyolefin resin, a polyamine resin, a polyoxyalkylene resin, or a combination thereof.

In an embodiment of the invention, the method of forming the opening comprises exposure development or laser drilling.

In an embodiment of the invention, the composite material layer is formed by a lamination process, and the temperature of the lamination process is from 60 ° C to 150 ° C.

Based on the above, the circuit board manufacturing method proposed by the present invention mainly uses a composite material layer including a plateable dielectric layer, a conductive polymer layer and an anti-plating layer, wherein the anti-plating layer of the surface layer is made of an anti-electroless plating material, and the inner layer The platable dielectric layer is made of a material that can be electrolessly plated for a selective electroless plating process. Then, by performing an electroplating process on the conductive polymer layer composed of a conductive material in the intermediate layer, a pad-less structure having a buried line can be fabricated, wherein the protruding pad structure is not provided and Reduce the width of the pads. Therefore, the circuit board manufacturing method of the present invention can improve the limitation of the annular gasket in the conventional circuit board manufacturing process, thereby improving the area utilization rate and increasing the wiring density, and further reducing the risk of thin line peeling.

The above described features and advantages of the invention will be apparent from the following description.

2A-2K are schematic cross-sectional views showing a method of fabricating a circuit board according to a first embodiment of the present invention.

First, referring to FIG. 2A, a core layer 200 is provided, wherein the core layer 200 includes a core dielectric layer 212 and a conductive layer 210 on the core dielectric layer 212. In more detail, the material of the core dielectric layer 212 is, for example, an epoxy resin, but is not limited thereto. The conductive layer 210 is, for example, a copper layer, and the conductive layer 210 is formed on the core dielectric layer 212, for example, by press bonding. In this embodiment, the core layer 200 may be a double panel structure or a single panel structure. For the sake of clarity and convenience of explanation, only the single-panel structure is illustrated in FIGS. 2A to 2K, but the invention is not limited thereto.

Next, referring to FIG. 2B, a composite material layer 220 is formed to cover the conductive layer 210 and the core dielectric layer 212. The composite material layer 220 sequentially includes a plateable dielectric layer 222, a conductive polymer layer 224, and a plating resist layer from bottom to top. 226. In more detail, the method of forming the composite material layer 220 is, for example, a lamination process having a lamination process temperature of about 60 ° C to 150 ° C. However, the present invention is not limited thereto, and the lamination process parameters may be adjusted according to the requirements of the dielectric material.

In the present embodiment, the plating resist 226 has anti-electroless plating properties, and the material thereof is, for example, a hydrophobic polymer material, and the hydrophobic polymer material may include a polymer material containing no hydroxyl functional group or carboxyl functional group. More specifically, the hydrophobic polymer material may include an epoxy resin, a polyamidamine, a liquid crystal polymer, a methacrylate type resin, a vinyl phenyl type resin, an allyl type resin, a polyacrylate type resin, A polyether type resin, a polyolefin type resin, a polyamine type resin, a polyoxyalkylene type resin, or a combination thereof. The thickness of the plating resist 226 is, for example, 5 μm to 10 μm, but the invention is not limited thereto.

In the present embodiment, the conductive polymer layer 224 has a conductive property, and is produced by, for example, uniformly doping a polymer having a conductive property (for example, bromine or iodine doped with polyacetylene) into the film layer. The thickness of the conductive polymer layer 224 is, for example, 3 μm to 5 μm, but the invention is not limited thereto. The plateable dielectric layer 222 has a property of being electrolessly plated, and the material thereof is, for example, a photo-imageable dielectric (PID). The thickness of the plateable dielectric layer 222 is, for example, 20 μm to 70 μm, but the invention is not limited thereto.

Thereafter, referring to FIG. 2C, a plurality of openings H1 are formed in the composite material layer 220, and each of the openings H1 corresponds to each of the conductive layers 210 to expose a portion of the conductive layer 210. In the present embodiment, the method of forming the plurality of openings H1 may include exposure development or laser drilling.

Then, referring to FIG. 2D, a metal layer 230 is formed on the bottom portion and a portion of the sidewall of the opening H1, and the first metal layer 230 is connected to the conductive polymer layer 224. In the present embodiment, the method of forming the metal layer 230 is, for example, a selective electroless plating process. As described above, since the plateable dielectric layer 222 has properties that can be electrolessly plated, and the plating resist 226 has anti-electroless plating properties, the metal layer 230 can be formed only in the opening by a selective electroless plating process. The bottom portion of the H1 and the side wall of the opening H1 composed of the plateable dielectric layer 222 and the conductive polymer layer 224 are not formed on the sidewall of the opening H1 formed by the plating resist 226.

Next, referring to FIG. 2E, a via hole 240 is formed in the opening H1. In the present embodiment, the method of forming the via holes 240 is, for example, an electroplating process. At this time, the upper surface of the via hole 240 is aligned with the upper surface of the conductive polymer layer 224.

Referring to FIG. 2E and FIG. 2F simultaneously, the conductive polymer layer 224 and the plating resist 226 are removed, and part of the via holes 240 are also removed. In the present embodiment, the method of removing the conductive polymer layer 224, the plating resist 226, and a portion of the via holes 240 is, for example, a film removing etching process. At this time, as shown in FIG. 2F, the upper surface of the via hole 240 is aligned with the upper surface of the plateable dielectric layer 222.

Then, referring to FIG. 2G, a composite material layer 250 is formed to cover the via holes 240 and the plateable dielectric layer 222. The composite material layer 250 sequentially includes a plateable dielectric layer 252, a conductive polymer layer 254, and an anti-resistant layer from bottom to top. Plating 256. In more detail, the method of forming the composite material layer 250 is, for example, a lamination process having a lamination process temperature of about 60 ° C to 150 ° C. However, the present invention is not limited thereto, and the lamination process parameters may be adjusted according to the requirements of the dielectric material.

It should be noted that the properties, materials and thicknesses of the plateable dielectric layer 252, the conductive polymer layer 254 and the plating resist 256 are respectively different from the plateable dielectric layer 222, the conductive polymer layer 224 and the anti-plating layer 226 described above. Similar, so I won't go into details here.

Next, referring to FIG. 2H, a plurality of openings H2 are formed in the composite material layer 250 to expose a portion of the via holes 240 and a portion of the plateable dielectric layer 222. In the present embodiment, the method of forming the plurality of openings H2 may include exposure development or laser drilling.

Then, referring to FIG. 2I, a metal layer 260 is formed on the bottom portion and a portion of the sidewall of the opening H2, and the metal layer 260 is connected to the conductive polymer layer 254. In the present embodiment, the method of forming the metal layer 260 is, for example, a selective electroless plating process. As described above, since the plateable dielectric layer 252 has properties that can be electrolessly plated, and the plating resist 256 has anti-electroless plating properties, the metal layer 260 can be formed only in the opening by a selective electroless plating process. The bottom portion of the H2 and the side wall of the opening H2 composed of the plateable dielectric layer 252 and the conductive polymer layer 254 are not formed on the sidewall of the opening H2 formed by the plating resist 256.

Next, referring to FIG. 2J, a wiring layer 270 is formed in the opening H2. In the present embodiment, the method of forming the wiring layer 270 is, for example, an electroplating process. At this time, the upper surface of the wiring layer 270 is aligned with the upper surface of the conductive polymer layer 254.

Referring to FIG. 2J and FIG. 2K simultaneously, the conductive polymer layer 254 and the plating resist 256 are removed, and part of the wiring layer 270 is also removed. In the present embodiment, the method of removing the conductive polymer layer 254, the plating resist 256, and the portion of the wiring layer 270 is, for example, a stripping etching process. At this time, as shown in FIG. 2K, the upper surface of the wiring layer 270 is aligned with the upper surface of the plateable dielectric layer 252. In this way, the production of the circuit board 20 can be completed. The circuit board 20 has a buried circuit structure in which the protruding pad structure is not provided and the width of the pad can be reduced. Therefore, the limitation of the annular gasket in the conventional circuit board process can be improved, thereby improving the area utilization rate. Increase the wiring density and reduce the risk of thin line stripping.

3A-3K are schematic cross-sectional views showing a method of fabricating a circuit board according to a second embodiment of the present invention. It should be noted that the second embodiment shown in FIG. 3A to FIG. 3K is similar to the first embodiment shown in FIG. 2A to FIG. 2K, and the difference between the two is that the embodiment shown in FIG. 3A to FIG. 3K is the present invention. The application of the circuit board in the application of embedded electronic components. Therefore, in the following embodiments, the description of the same technical content will be omitted, and the description of the omitted portions may refer to the foregoing embodiments, and the following embodiments will not be repeated.

First, referring to FIG. 3A and FIG. 3B simultaneously, a substrate 300 having a first surface 300A and a second surface 300B is provided, and a through hole 302 penetrating the first surface 300A and the second surface 300B is formed. In the present embodiment, the method of forming the through hole 302 is, for example, a laser drilling or a mechanical drilling. The material of the substrate 300 is, for example, a dielectric material, and the dielectric material may include resin fibers, but is not limited thereto.

Next, referring to FIG. 3C, the adhesive layer 310 is bonded to the second surface 300B of the substrate 300 to form a receiving recess 304 for inserting the embedded component in a subsequent process. In the present embodiment, the adhesive layer 310 is, for example, a polyimide tape, but not limited thereto, and other component adhesive layer materials capable of fixing the embedded component may be used.

Then, referring to FIG. 3D , the electronic component 320 configured with the plurality of pads 330 is placed on the adhesive layer 310 at the bottom of the receiving recess 304 to fix the electronic component 320 in the receiving recess 304 . The receiving recess 304 is sized to receive the electronic component 320. In this embodiment, the material of the pad 330 is, for example, a metal conductive material, and the electronic component 320 is, for example, a passive component such as a chip or a multi-layer ceramic capacitor (MLCC), but the present invention does not Limited.

Next, referring to FIG. 3E, a dielectric layer 340 covering the pad 330, the electronic component 320, the adhesive layer 310, and the first surface 300A is formed. In this embodiment, the material of the dielectric layer 340 may comprise a dielectric material as is known in the art.

Thereafter, referring to FIG. 3F, the dielectric layer 340 is etched to expose the upper surface of the pad 330. In the present embodiment, the method of etching the dielectric layer 340 is, for example, a dry etching method or a chemical etching method.

Next, referring to FIG. 3G, a composite material layer 350 is formed to cover the pad 330 and the dielectric layer 340. The composite material layer 350 sequentially includes a plateable dielectric layer 352, a conductive polymer layer 352, and a plating resist 356 from bottom to top. . In more detail, the method of forming the composite material layer 350 is, for example, a lamination process having a lamination process temperature of about 60 ° C to 150 ° C. However, the present invention is not limited thereto, and the lamination process parameters may be adjusted according to the requirements of the dielectric material.

It should be noted that the properties, materials, and thicknesses of the plateable dielectric layer 352, the conductive polymer layer 352, and the plating resist 356 are respectively different from the plateable dielectric layer 222 and the conductive polymer layer described in the first embodiment above. 224 is similar to the anti-plating layer 226, so it will not be described here.

Next, referring to FIG. 3H, a plurality of openings H3 are formed in the composite material layer 350 to expose the partial pads 330 and the portion of the dielectric layer 340. In the present embodiment, the method of forming the plurality of openings H3 may include exposure development or laser drilling.

Thereafter, referring to FIG. 3I, a metal layer 360 is formed on the bottom portion and a portion of the sidewall of the opening H3, and the metal layer 360 is connected to the conductive polymer layer 354. In the present embodiment, the method of forming the metal layer 360 is, for example, a selective electroless plating process. As described above, since the plateable dielectric layer 352 has properties that can be electrolessly plated, and the plating resist 356 has anti-electroless plating properties, the metal layer 360 can be formed only in the opening by a selective electroless plating process. The bottom portion of the H3 and the side wall of the opening H3 composed of the plateable dielectric layer 352 and the conductive polymer layer 354 are not formed on the sidewall of the opening H3 formed by the plating resist 356.

Next, referring to FIG. 3J, a wiring layer 370 is formed in the opening H3. In the present embodiment, the method of forming the wiring layer 370 is, for example, an electroplating process. At this time, the upper surface of the wiring layer 370 is aligned with the upper surface of the conductive polymer layer 354.

Referring to FIG. 3J and FIG. 3K simultaneously, the conductive polymer layer 354 and the plating resist 356 are removed, and part of the wiring layer 370 is also removed. In the present embodiment, the method of removing the conductive polymer layer 354, the plating resist 356, and the portion of the wiring layer 370 is, for example, a film removing etching process. At this time, as shown in FIG. 3K, the upper surface of the wiring layer 370 is aligned with the upper surface of the plateable dielectric layer 352, which has no protruding pad structure and can reduce the width of the pad, thereby improving the conventional line. Limitation of annular gaskets in the board process, which in turn increases area utilization and increases wiring density. In this way, the application method of the circuit board proposed by the present invention in the embedded component can be completed.

4 is a schematic view showing the structure of a circuit board produced by the method for fabricating a circuit board according to the present invention.

Referring to FIG. 1 and FIG. 4 simultaneously, as shown in FIG. 1 , the conduction holes 120 (blind holes) are first turned on between the layers, and there is a limitation of the annular gasket, so that the pads 130 cannot be reduced. As a result, both area usage and wiring density are degraded, which is not conducive to the design of electronic products. In contrast, as shown in FIG. 4, through the circuit board manufacturing method proposed by the present invention, the via hole 410 is connected to the circuit layer 420, and the component signal is fanned out through a pad-less technique, wherein There is no protruding pad structure and the pad width can be reduced, so that the area usage rate can be increased and the wiring density can be increased.

In summary, the circuit board manufacturing method proposed by the present invention mainly uses a composite material layer including a dielectric layer, a conductive polymer layer and an anti-plating layer in sequence, wherein the anti-plating layer of the surface layer is made of an anti-electroless plating material. The inner layer of the plateable dielectric layer is made of a material that can be electrolessly plated for a selective electroless plating process. Thereafter, the electroconductive polymer layer made of a conductive material in the intermediate layer is subjected to an electroplating process to fabricate a structure having no pads and a buried wiring. Moreover, the method of fabricating the circuit board of the present invention can also be applied to a buried component, which improves the problem that the pad cannot be reduced and the annular gasket is limited in the conventional conduction method. Therefore, the area utilization rate can be increased and the wiring density can be increased, and the risk of thin line peeling can be reduced.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

20: circuit boards 110, 210: conductive layers 120, 240, 410: vias 130, 330: pads 140, 270, 370, 420: circuit layer 200: core layer 212: core dielectric layers 220, 250, 350: Composite material layers 222, 252, 352: platable dielectric layers 224, 254, 354: conductive polymer layers 226, 256, 356: plating resists 230, 260, 360: metal layer 300: substrate 300A: first surface 300B: Second surface 302: through hole 304: receiving groove 310: adhesive layer 320: electronic component 340: dielectric layer H1, H2, H3: opening

1 is a schematic structural view of a conventional circuit board. 2A-2K are schematic cross-sectional views showing a method of fabricating a circuit board according to a first embodiment of the present invention. 3A-3K are schematic cross-sectional views showing a method of fabricating a circuit board according to a second embodiment of the present invention. 4 is a schematic view showing the structure of a circuit board produced by the method for fabricating a circuit board according to the present invention.

Claims (10)

A method of fabricating a circuit board, comprising: providing a core layer, the core layer comprising a core dielectric layer and a conductive layer on the core dielectric layer; forming a first composite material layer to cover the conductive layer and the a core dielectric layer, the first composite material layer sequentially includes a first plateable dielectric layer, a first conductive polymer layer and a first plating resist layer from bottom to top; formed in the first composite material layer a plurality of first openings, each of the first openings corresponding to each of the conductive layers to expose a portion of the conductive layer; at a bottom of the first opening and by the first plateable layer Forming a first metal layer on a portion of the sidewall formed by the electrical layer and the first conductive polymer layer, the first metal layer is connected to the first conductive polymer layer, and the first metal layer is not covered a portion of the sidewall formed by the first plating resist; forming a via hole in the first opening, and removing the first conductive polymer layer and the first plating resist, the upper surface of the via hole and Aligning upper surfaces of the first plateable dielectric layer; forming a second composite material And covering the via hole and the first plateable dielectric layer, the second composite material layer sequentially includes a second plateable dielectric layer, a second conductive polymer layer, and a second plating resist layer from bottom to top. Forming a plurality of second openings in the second composite material layer to expose a portion of the via holes and a portion of the first plateable dielectric layer; at a bottom of the second opening and by the Second plateable dielectric layer and second conductive Forming a second metal layer on a portion of the sidewall formed by the polymer layer, the second metal layer is connected to the second conductive polymer layer, and the second metal layer does not cover the second plating resist layer a portion of the sidewall; and forming a wiring layer in the second opening, and removing the second conductive polymer layer and the second plating resist, an upper surface of the wiring layer and the second plating The upper surface of the electrical layer is aligned. The method for fabricating a circuit board according to claim 1, wherein the material of the first plating resist and the second plating resist comprises a hydrophobic polymer material, and the hydrophobic polymer material comprises no hydroxyl group. A polymer material having a functional group or a carboxyl functional group. The method for fabricating a circuit board according to the second aspect of the invention, wherein the hydrophobic polymer material comprises an epoxy resin, a polyamidamide, a liquid crystal polymer, a methacrylate resin, or a vinyl phenyl resin. An allyl type resin, a polyacrylate type resin, a polyether type resin, a polyolefin type resin, a polyamine type resin, a polyoxyalkylene type resin, or a combination thereof. The method of fabricating a circuit board according to claim 1, wherein the method of forming the first opening and the second opening comprises exposure development or laser drilling. The method for fabricating a circuit board according to claim 1, wherein the first composite material layer and the second composite material layer are formed by a lamination process, and the temperature of the lamination process is 60 ° C to 150 °C. A method for manufacturing a circuit board, comprising: Providing a substrate having a first surface and a second surface, and forming a through hole penetrating the first surface and the second surface; bonding the adhesive layer to the second surface to form a receiving groove; An electronic component having a plurality of pads is disposed in the receiving recess; forming a dielectric layer covering the pad, the electronic component, the adhesive layer, and the first surface; etching the dielectric a layer to expose an upper surface of the pad; a composite material layer to cover the pad and the dielectric layer, the composite material layer including a plateable dielectric layer and a conductive polymer layer from bottom to top And a plating resist; forming a plurality of openings in the composite layer to expose a portion of the pads and a portion of the dielectric layer; at the bottom of the openings and by the platable dielectric layer a metal layer is formed on a portion of the sidewall of the conductive polymer layer, the metal layer is connected to the conductive polymer layer, and the metal layer does not cover a portion of the sidewall formed by the plating resist; Forming a wiring layer in the hole, and removing the conductive polymer layer and the anti-resistant layer Layer, the upper surface of the wiring layer and the dielectric layer may be coated on the surface of the alignment. The method for fabricating a circuit board according to claim 6, wherein the material of the plating resist comprises a hydrophobic polymer material, and the hydrophobic polymer material comprises a hydroxyl-free functional group or a carboxyl functional group. Polymer Materials. The method for fabricating a circuit board according to claim 7, wherein the hydrophobic polymer material comprises an epoxy resin, a polyamidamine, a liquid crystal polymer, A methacrylate type resin, a vinyl phenyl type resin, an allyl type resin, a polyacrylate type resin, a polyether type resin, a polyolefin type resin, a polyamine type resin, a polyoxyl type type resin, or a combination thereof. The method of fabricating a wiring board according to claim 6, wherein the method of forming the opening comprises exposure development or laser drilling. The method for fabricating a wiring board according to claim 6, wherein the composite material layer is formed by a lamination process, and the temperature of the lamination process is 60 ° C to 150 ° C.