TWI619249B - High electron mobility transistor structure and forming method thereof - Google Patents

Abstract

A high electron mobility transistor structure and its forming method, based on a semiconductor substrate A nano-belt is formed in the bottom epitaxial stack structure. The nano-belt is formed in the gate region of the epitaxial stack structure, and a gate metal layer is formed in the gate region to form a gate structure with a nano-belt structure design. Moreover, the present invention uses the change of the length and width of the plurality of pitches of the nano-belt to reduce the thermal effect of the high electron mobility transistor structure and increase the critical voltage.

Description

High electron mobility transistor structure and forming method

The invention relates to a high electron mobility transistor crystal structure and a formation method thereof, in particular to an enhancement-mode aluminum gallium nitride / gallium nitride high electron mobility transistor crystal structure and a formation method thereof.

"High electron mobility transistor (HEMT)", also known as "heterojunction field effect transistor (HFET)" or "modulated doped field effect transistor (MODFET)", generally uses two different energy A material with a width is used to form a junction. For example, a "heterojunction" replaces a "doped region" as a "channel".

In the aluminum gallium nitride / gallium nitride (AlGaN / GaN) system, the polarization effect of the aluminum gallium nitride / gallium nitride interface can be divided into two types, the first one is caused by the stress of the lattice mismatch The second type of piezoelectric polarization effect is spontaneous polarization due to the fact that the crystal lattice of Group III nitrides is not completely centrosymmetric. The channel of the "high electron mobility transistor" is mainly dominated by the piezoelectric polarization effect, and the stress produces the piezoelectric polarization effect, which in turn generates channels.

The energy band structure of the potential well, which bears the aforementioned polarization field effect and heterojunction, will produce a naturally conducting two-dimensional electron gas channel, so it is a depletion mode device. But in the circuit In order to simplify the complexity of circuit design and reduce unnecessary power consumption, the use of enhanced mode is an indispensable choice.

A change in the width of the "nano band" will cause the threshold voltage to change. This is because the change in the stress causes the threshold voltage to change. The smaller the width of the "nano band", the smaller the stress. If the stress is smaller and the piezoelectric polarization is smaller, the channel of the "high electron mobility transistor" can be smaller, which will increase the critical voltage and increase the thermal effect of the "high electron mobility transistor" structure. Therefore, the performance of the "high electron mobility transistor" structure is seriously affected.

Second, when the piezoelectric polarization effect becomes smaller, the carrier concentration will decrease (the channel becomes smaller), and in the conventional prior art, Kota Ohi et al. Published related papers in the "Japanese Journal of Applied Physics". The title of the paper is titled "Drain Current Stability and Controllability of Threshold Voltage and Subthreshold Current in a Multi-Mesa-Channel AlGaN / GaN High Electron Mobility Transistor", and Kota Ohi et al. Proposed to use the channel to change the "nano band" in the paper Width, according to the application principle of modulating the threshold voltage, when the threshold voltage of GaN HEMT transistor is to be adjusted, multi-mesa-channel is proposed, and the channel width is adjusted ( Modulation channel width) method to adjust the critical voltage of "GaN high electron mobility transistor". Although the method provided in this paper can shift the critical voltage of the device to the positive critical voltage and improve the thermal stability of the device, its disadvantage is that it greatly reduces the current density of the device.

According to the foregoing, the conventional prior art multi-channel gate 3D electric field coating can improve the "surface pinning effect" of semiconductor materials, but due to the "Sidewall effect on the channel" ) "The surface pinning effect of the device is not used properly, so the width of the device must be reduced to a width below 100 nanometers (nm) to produce such as" enhanced GaN high electron mobility transistor (E- mode GaN HEMT), because the width of the device is too small, it is very difficult to produce, and because the neutral region is not enough, the impedance of the device channel becomes larger and cannot be achieved Real practicality.

Therefore, in view of the aforementioned shortcomings of "high electron mobility transistors", in view of the future needs of the semiconductor industry, there is an urgent need to develop a "high electron mobility transistors" structure that can be actively applied to promote the development of integrated circuits .

Therefore, in order to increase the threshold voltage, the present invention provides a "high electron mobility transistor" structure and its forming method. The gate structure includes a "nano-belt" structure design, and changes the pitch length of the "nano-belt" structure or together Change the pitch width and use the vacancy on the side of the gate to adjust the critical voltage.

A "high electron mobility transistor" structure of the present invention includes: a semiconductor substrate, wherein the semiconductor substrate includes sapphire, silicon (Si), silicon carbide (SiC), gallium nitride (GaN), Zinc oxide (ZnO), gallium arsenide (GaAs), SOI (Silicon on Insulator) or other commercial semiconductor substrates for epitaxial use; a gallium nitride layer covering the semiconductor substrate; an aluminum gallium nitride layer Located on the gallium nitride layer, the aluminum gallium nitride layer is divided into a source region, a drain region, and a gate region between the source region and the drain region, the gate region has a plurality of A plurality of trenches, wherein each of the trenches exposes a portion of the gallium nitride layer, and the plurality of pitches between any two adjacent trenches have the same length and the same width, and any length of the pitch is greater than or equal to 0.8 micrometers (um); an ohmic metal layer covers the source region and the drain region of the aluminum gallium nitride layer; and a gate metal layer is located on the gate region of the aluminum gallium nitride layer, The gate metal layer covers at least a portion of each trench.

A method of "forming a high electron mobility transistor" structure of the present invention includes: providing an epitaxial stack structure including a semiconductor substrate, wherein the semiconductor substrate includes sapphire and silicon ( Si), silicon carbide (SiC), gallium nitride (GaN), zinc oxide (ZnO), gallium arsenide (GaAs), SOI (Silicon on Insulator) or other commercial semiconductor substrates for epitaxial use; Forming a gallium nitride layer covering the semiconductor substrate; forming an aluminum gallium nitride layer on the gallium nitride layer; forming a patterned mask layer on the epitaxial stack structure, wherein the patterned mask The layer covers part of the aluminum gallium nitride layer; a "nano band" is formed in the aluminum gallium nitride layer, wherein the "nano band" includes a plurality of trenches, and the patterned mask layer is used as a mask Removing part of the cover of the aluminum gallium nitride layer and the gallium nitride layer; forming an ohmic metal layer on the aluminum gallium nitride layer outside the "nano band"; and forming a gate metal layer on the "nanometer" Bring on.

One of the main objectives of the present invention is to use the gate side wall depletion method to modulate the threshold voltage (Vth) of the "high electron mobility transistor".

Another main object of the present invention is to reduce the thermal effect of the "high electron mobility transistor" structure by changing the length and width of a plurality of pitches of the "nano band", and at the same time have the effect of increasing the critical voltage.

The main feature of the present invention is that it has a three-dimensional (3D) three-dimensional (3D) strip structure, which can increase the surface state density of the side wall of the "high electron mobility transistor" device, thereby improving the semiconductor material. "Surface pinning effect". The main principle is that when the density of the "surface state" of the semiconductor is high, the "Fermi energy level" on the surface of the semiconductor will be fixed to the "surface state" of the semiconductor, and the phenomenon of "surface pinning" will occur. .

10‧‧‧High electron mobility transistor structure

12‧‧‧Semiconductor substrate

14‧‧‧GaN layer

16‧‧‧AlGaN layer

162‧‧‧Source

164‧‧‧Gate area

166‧‧‧ Jiji District

18‧‧‧Metal layer

182‧‧‧ohm metal layer

184‧‧‧Gate metal layer

20‧‧‧Groove

22‧‧‧spacing

40‧‧‧patterned mask layer

L‧‧‧Length

Lg‧‧‧Length

Lt‧‧‧Length

W‧‧‧Width

Wt‧‧‧Width

Fig. 1 is a schematic perspective side view of an embodiment of the "high electron mobility transistor" structure of the present invention.

FIG. 2 is a schematic flowchart of an embodiment of a method for forming a "high electron mobility transistor" of the present invention.

Figures 3A, 3B, 3C, and 3D are the "high electron migration" steps in the flow of Figure 2. Schematic diagram of the structure of the "Transfer Transistor" or "AlGaN / GaN High Electron Mobility Transistor" structure.

Figures 4A, 4B, 4C, and 4D are schematic top perspective views of the structure of the "high electron mobility transistor" according to the steps in the flow of Figure 2.

Figure 5 shows the normalized drain current (I _DS ) -gate voltage (V) curve characteristics of a transistor with a nano-band width of 100 nanometers according to the present invention.

FIG. 6 shows the normalized drain current (I _DS ) -gate voltage (V) curve characteristics of a transistor with a nano-band width of 300 nm according to the present invention.

FIG. 7 shows the normalized drain current (I _DS ) -gate voltage (V) curve characteristics of a transistor with a nano-band width of 500 according to the present invention.

FIG. 8 shows the normalized drain current (I _DS ) -gate voltage (V) curve characteristics of a transistor with a nanometer length of 0.8 μm according to the present invention.

Figure 9 shows the normalized drain current (I _DS ) -gate voltage (V) curve characteristics of a transistor with a nanometer length of 1 micrometer according to the present invention.

FIG. 10 shows the normalized drain current (I _DS ) -gate voltage (V) curve characteristics of a transistor with a nanometer length of 2 μm according to the present invention.

FIG. 11 shows the threshold voltages of the device of the present invention with different “NRs length” and “NRs width” in the foregoing FIGS. 5 to 10.

FIG. 12 is a trend diagram of the area of the “nano band” and the “device threshold voltage” of the present invention.

The pitch between trenches referred to below in the present invention can be basically regarded as a rectangle, and the length and width are measured on the surface of the aluminum gallium nitride layer. The groove referred to below in the present invention is basically It is a rectangular body with length, width and depth, but it is understandable that the groove may be displayed as a non-rectangular body under high magnification due to the influence of the manufacturing process, but this does not affect the distance between the grooves defined by the present invention.

Please refer to FIG. 1, the “high electron mobility transistor” structure 10 of the present invention has a semiconductor substrate 12, wherein the semiconductor substrate 12 includes sapphire, silicon (Si), silicon carbide (SiC), Gallium nitride (GaN), zinc oxide (ZnO), gallium arsenide (GaAs), SOI (Silicon on Insulator) or other commercial semiconductor substrates for epitaxial use 12, gallium nitride layer 14, aluminum gallium nitride layer 16 and a metal layer 18, in which the gallium nitride layer 14 is formed on the semiconductor substrate 12, the aluminum gallium nitride layer 16 is formed on the gallium nitride layer 14, and the metal layer 18 is formed on the aluminum gallium nitride layer 16.

First, for convenience of description, please still refer to FIG. 1, where the aluminum gallium nitride layer 16 covering the gallium nitride layer 14 is divided into a source region 162, a gate region 164, and a drain region 166, wherein The gate region 164 is located between the source region 162 and the drain region 166, and the ratio of each region on the aluminum gallium nitride layer 16 is not limited. The area size of each region in FIG. 1 is only an example and not a limitation. . Secondly, in the extending direction that can span the source region 162, the gate region 164 and the drain region 166 at the same time, it can be defined that the gate region 164 has a "length L" and the gate region 164 also has a "width W" ".

With continued reference to FIG. 1, a plurality of trenches 20 are formed in the gate region 164 and expose a portion of the gallium nitride layer 14, wherein the plurality of "trenches 20" are arranged in a row on the "width W" And maintain a "spacing 22" between each other. In the present invention, the plurality of "grooves 20" have the same "length Lt", and the "length Lt" is used as the "length Lt" of the "pitch 22", and the "pitch 22" has a "width Wt". Among them, it is worth noting that "Length Lt" is smaller than "Length L" and "Width Wt" is smaller than "Width W". Therefore, the plurality of "spacings 22" form a "nanoribbon structure" in the gate region 164, and the preferred range of distribution is that the "length Lt" is greater than or equal to 0.8 microns (um) and can be less than Is equal to 6 microns, "width Wt" is greater than or equal to 100 nanometers (nm) and less than or equal to 500 nanometers. Therefore, when the epitaxial structure of the "high electron mobility transistor structure 10" has the aforementioned "nano band" structure design, the heat dissipation problem of the semiconductor substrate structure can be improved and reduced The thermal effect maintains the performance of high current and high voltage operation. In the "aluminum gallium nitride / gallium nitride high electron mobility transistor", the length L of the source and drain elements does not Less than 3 microns (um), the main reason is due to "operating electric field decline" and "process technology" restrictions. In the general market, the "Length L" of the "RF GaN HEMT" device is 4 microns (28 volts) to 6 microns (50 volts). However, if it is an "aluminum gallium nitride / gallium nitride high electron mobility transistor" power device, there are currently 50 volt (V), 200 volt, and 650 volt specifications on the market, and if the withstand voltage should exceed 650 volts At this time, the component "length L" may have to reach several tens of microns.

With continued reference to FIG. 1, the metal layer 18 on the aluminum gallium nitride layer 16 is used as an electrode. In an embodiment, the metal layer 18 includes an ohmic metal layer 182 and a gate metal layer 184, wherein the ohmic metal layer 182 is a titanium aluminum nickel gold layer, and the gate metal layer 184 may be a nickel gold layer. Second, the ohmic metal layer 182 covers the source region 162 and the drain region 166 of the aluminum gallium nitride layer 16, and the gate metal layer 184 covers at least a portion of each trench 20 and the pitch 22. In the embodiment, the "length Lg" of the gate metal layer 184 is 2 micrometers (um). As shown in FIG. 1, the trench 20 and the pitch 22 of the present invention can be the entire gate metal layer The coverage of 184 may also be exposed because the "length Lt" of the trench 20 and the pitch 22 is greater than the "length Lg" of the gate metal layer 184, but the invention is not limited to any form.

Please refer to step 30 in FIG. 2 and cooperate with FIG. 3A and FIG. 4A. In step 30 in FIG. 2 is the step of “firstly provide an epitaxial stack structure”, and the epitaxial stack structure of the present invention may include The semiconductor substrate 12 in FIG. 1, wherein the semiconductor substrate includes sapphire, silicon (Si), silicon carbide (SiC), gallium nitride (GaN), zinc oxide (ZnO), gallium arsenide (GaAs) ), SOI (Silicon on Insulator) or other commercial semiconductor substrates for epitaxial use, and a gallium nitride layer (GaN layer) 14 is formed on the semiconductor substrate 12 and an aluminum gallium nitride layer (AlGaN layer) 16 It is formed on the gallium nitride layer (GaN layer) 14, wherein the thickness of the gallium nitride layer 14 can be 2 microns, the thickness of the aluminum gallium nitride layer 16 can be 21.8 nanometers, but the invention is not limited thereto, and the aforementioned structure Also shown in Figures 3A and 4A in.

Next, as shown in step 32 of FIG. 2 and in conjunction with FIGS. 3A and 4A, in step 32 of FIG. 2 is the step of “forming a patterned mask layer 40 on the epitaxial stack structure”. The patterned mask layer 40 of the invention may be a metal chromium layer (Cr layer) 40, and its pattern is the "nano band" structure design shown in FIG. 1, and a suitable manufacturing method may be selected for aluminum nitride The gate region of the gallium layer 16 defines a "nano-belt" pattern. This suitable manufacturing method can be selected from, but not limited to, for example, E-beam lithography. In addition, as shown in FIGS. 3A and 4A, the aforementioned patterned mask layer 40 can also form a thin patterned mask layer (GaN) 40, and the patterned mask layer ( The thickness of GaN) 40 is about 2 nm, but the invention is not limited thereto.

Next, as shown in step 34 of FIG. 2, and in conjunction with FIGS. 3B and 4B, in step 34 of FIG. 2, "a part of the aluminum gallium nitride layer 16 and the gallium nitride layer 14 are removed to form a plurality of "Trench" step, where the removal method includes reactive ion etching such as dry etching, using a patterned mask layer as an etching mask, and the etching depth is about 130 nm. After etching, move In addition to the patterned mask layer. Furthermore, the plurality of trenches expose the gallium nitride layer under the trenches. For the distance between the trenches, refer to the corresponding description in FIG. 1, but the present invention is not limited to the above dimensions.

Continuing to refer to step 36 of FIG. 2, and as shown in FIGS. 3C and 4C, in step 36 of FIG. 2 is the step of "forming an ohmic metal layer 182 on a portion of the aluminum gallium nitride layer 16", In the present invention, a titanium / aluminum / nickel / gold layer is formed as an ohmic metal layer 182 by using an electron gun (E-gun) deposition method or a thermal deposition method, wherein the thickness of titanium / aluminum / nickel / gold is 30 / 120/20/80 nm, but the invention is not limited to this. Second, the ohmic metal layer is formed on the source region and the drain region of the aluminum gallium nitride layer 16.

Next, referring to step 38 of FIG. 2, and in conjunction with FIGS. 3D and 4D, in step 38 of FIG. 2, a gate metal layer 184 is formed on the partially exposed aluminum gallium nitride layer 16 "Steps. In the present invention, the gate metal layer 184 is also formed by an E-gun deposition method or a thermal deposition method, which can be formed by a nickel / gold layer with a thickness of 20/80 nm, respectively. Secondly, The gate metal layer 184 is formed in the gate region between the source region and the drain region. The length Lg of the gate metal layer 184 is about 2 microns, as shown in FIG. 4D. Therefore, when the “length Lt” of the pitch 22 is greater than 2 μm, the gate metal layer 184 can only form a part covering each of the trenches 20. However, it is relatively understandable that, as shown in FIG. 4D, when the “length Lt” of the pitch 22 is smaller than the length Lg of the gate metal layer 184, the gate metal layer 184 can completely cover the trench 20 That is, the gate metal layer 184 can be completely formed to cover the exposed gallium nitride layer 14 to form the "high electron mobility transistor" or "aluminum gallium nitride / nitrogen" with the "nano band" of the present invention GaAs high electron mobility transistor "structure.

Figure 5 shows the normalized sink current (I _DS ) -gate voltage (V) curve characteristics of the transistor with a width of 100 nanometers (nm) in the "nano band" of the present invention, as shown in FIG. 5 The "width Wt" of the "nano band" is 100 nanometers (nm) transistors, the fixed drain bias (VDS) is 8 volts (V), and the drain current (IDS) is obtained for different gate biases ( VG), the gate bias is dependent on the "length Lt" of the "nano band" from 1 micrometer (μm) to 2 micrometers (μm), and the critical voltage of the device is from -0.14 volts to 0.79 volts The gate voltage when the drain current is 1mA / mm.

Figure 6 shows the normalized drain current (I _DS ) -gate voltage (V) curve characteristics of the transistor with a width of 300 nanometers (nm) in the "nano band" of the present invention, as shown in FIG. 6 The "width Wt" of the "nano band" is 300 nanometer transistors, the fixed drain bias (VDS) is 8 volts, and the relationship between the drain current and the different gate bias is changed. The gate bias is based on The "length Lt" of the "nano band" is from 1 micrometer to 6 micrometers, and the critical voltage of the device is from -2.12 volts to 0.46 volts. The value is the gate voltage when the drain current is 1 mA / mm.

Figure 7 shows the normalized drain current (I _DS ) -gate voltage (V) curve characteristics of the transistor with a width of 500 nanometers (nm) in the "nano band" of the present invention, as shown in FIG. 7 The "width Wt" of the "nano-belt" is a 500-nanometer transistor, the fixed drain bias (VDS) is 8 volts, and the relationship between the drain current and the different gate bias is changed. The gate bias is based on The "length Lt" of the "nano band" is from 1 micrometer to 6 micrometers, and the critical voltage of the device is from -2.52 volts to -1.62 volts. The value is the gate voltage when the drain current is 1 mA / mm.

Figure 8 shows the normalized drain current (I _DS ) -gate voltage (V) curve characteristics of the transistor with a length of 0.8 micrometers of the "nano band" of the present invention, as shown in FIG. 8 The "length Lt" of the band "is 0.8 micron transistor, the fixed drain bias (V _DS ) is 8 volts, and the relationship between the drain current (I _DS ) and different gate bias (V _G ). When the "width Wt" of the "nano band" is from 100 nm to 500 nm, the critical voltage of the device is from -0.41 volts to -2.62 volts, and the value is the gate voltage at the drain current of 1 mA / mm.

FIG. 9 shows the normalized drain current (I _DS ) -gate voltage (V) curve characteristics of the transistor with a length of 1 micron of the “nano band” of the present invention, as shown in FIG. 9 The "length Lt" of "band" is a 1 micron transistor, the fixed drain bias (V _DS ) is 8 volts, and the relationship between the drain current (I _DS ) and different gate bias (V _G ). When the "width Wt" of the "nano band" is from 100 nm to 500 nm, the critical voltage of the device is from -0.14 volts to -2.52 volts, which is the gate voltage at the drain current of 1 mA / mm.

Figure 10 shows the normalized drain current (I _DS ) -gate voltage (V) curve characteristics of a transistor with a "nanometer zone" length of 2 micrometers according to the present invention, as shown in FIG. 10 The "Lt" of the "band" is a 2 micron transistor, the fixed drain bias (V _DS ) is 8 volts, and the relationship between the drain current (I _DS ) and different gate bias (V _G ). When the "width Wt" of the "nano band" is from 100 nm to 500 nm, the critical voltage of the device is from 0.79 volts to -2.18 volts, and the value is the gate voltage at the drain current of 1 mA / mm.

As shown in Figure 11, as shown in Figures 5 to 10, the conditions of the device of the present invention at different "NRs length" and "NRs width" conditions Under the critical voltage. It can be seen from Figure 11 that when the width of the "nano band" is narrower and the length of the "nano band" is longer, the threshold voltage of the device will shift in the positive direction, so it can be speculated that the nano width is 100 nanometers Under the condition that the nanometer length is 4 microns (μm) and 6 microns (μm), the critical voltage of the device will also be greater than zero.

Still referring to FIG. 11, as the "side area (length * depth)" of the present invention becomes larger, it will increase the density of more surface states (Surface states), so the structure of the present invention can be used to control carriers ( carrier).

Refer to Figure 12 and also refer to Figure 11 "Area" plotted against "Critical Voltage". The horizontal axis shown in Figure 12 is the single-area "area" of the "nano zone" (NR area) ", the vertical axis is" critical voltage (Vth) ". The "area" of a single pitch is the product of "length Lt" and "width Wt", and "threshold voltage Vth" is the "gate voltage" of the "drain current" at 1 mA / mm. It can be seen from Figure 12 that when the "width Wt" is fixed, the larger the "length Lt" of the hole spacing, that is, the larger the area of the single spacing, the higher the "threshold voltage Vth". Therefore, when the epitaxial structure of the "high electron mobility transistor structure 10" of the present invention has the aforementioned "nano band" structure design, not only can the thermal effect of the device be reduced, but also the "critical voltage Vth" can be increased. In the case of a "width Wt" with a fixed pitch, if the "length Lt" of the pitch can be increased, the "threshold voltage Vth" can be increased.

According to the foregoing, the "high electron mobility transistor" structure of the present invention includes a gate structure with a "nano band" design, which can improve the heat dissipation effect of the semiconductor substrate structure, maintain better performance, and increase the threshold voltage. In addition, the present invention can reduce the thermal effect of the high electron mobility transistor structure by changing the length and width of the plurality of pitches of the "nano band", and at the same time has the effect of increasing the critical voltage. In addition, the present invention has a gate structure with a "nano band" design, so it can be obtained only by changing the pattern of the mask layer, without complicated process changes, and is beneficial to the formation of high electron mobility transistors.

According to the foregoing description, the main feature of the present invention is that it has a three-dimensional (3D) three-dimensional (ribbon) stripe structure, so the surface state of the side wall of the "GaN HEMT" device can be improved (surface state) density, which in turn improves the "surface pinning effect" of semiconductor materials.

The above are only the preferred embodiments of the present invention and are not intended to limit the rights of the present invention The scope is required, so any other equivalent changes or modifications made without departing from the spirit disclosed by the present invention should be included in the scope of the present invention.

10‧‧‧High electron mobility transistor structure

12‧‧‧Semiconductor substrate

14‧‧‧GaN layer

16‧‧‧AlGaN layer

162‧‧‧Source

164‧‧‧Gate area

166‧‧‧ Jiji District

18‧‧‧Metal layer

182‧‧‧ohm metal layer

184‧‧‧Gate metal layer

20‧‧‧Groove

22‧‧‧spacing

L‧‧‧Length

Lg‧‧‧Length

Lt‧‧‧Length

W‧‧‧Width

Wt‧‧‧Width

Claims (10)

A high electron mobility transistor structure includes: a semiconductor substrate; a gallium nitride layer is formed on the semiconductor substrate; an aluminum gallium nitride layer is formed on the gallium nitride layer, and the aluminum gallium nitride layer It is divided into a source region, a drain region, and a gate region between the source region and the drain region. The gate region has a plurality of trenches, wherein each of the trenches exposes a portion In the gallium nitride layer, the plurality of pitches between any two adjacent trenches have the same length and the same width, and the length of any one of the pitches is greater than or equal to 0.8 microns (um); an ohmic metal layer is formed on the nitrogen On the source region and the drain region of the aluminum gallium layer; and a gate metal layer formed on the gate region of the aluminum gallium nitride layer, the gate metal layer covering each of the trenches At least partly. The transistor structure as described in item 1 of the patent application scope, wherein the semiconductor substrate includes sapphire, silicon (Si), silicon carbide (SiC), gallium nitride (GaN), zinc oxide (ZnO), arsenic GaAs, SOI (Silicon on Insulator) or other commercial semiconductor substrates for epitaxial use. The transistor structure as described in item 1 of the patent application range, wherein the length of any one of the pitches is less than or equal to 6 microns, and the width of any one of the pitches is greater than or equal to 100 nanometers (nm) and less than or equal to 500 nanometers. The transistor structure as described in item 1 of the patent application range, wherein the plurality of trenches are arranged in a row. The transistor structure as described in item 1 of the patent application range, wherein the ohmic metal layer is a titanium / aluminum / nickel / gold layer, and the gate metal layer is a nickel / gold layer. A method for forming a high electron mobility transistor structure includes: providing an epitaxial stack structure including a semiconductor substrate and a nitrogen A gallium nitride layer is formed on the semiconductor substrate, and an aluminum gallium nitride layer is formed on the gallium nitride layer; a patterned mask layer is formed on the epitaxial stack structure, wherein the patterned mask layer Covering a part of the aluminum gallium nitride layer; forming a nano-belt in the aluminum gallium nitride layer, wherein the nano-belt includes a plurality of trenches, and the patterned mask layer is used as a mask to remove Part of the aluminum gallium nitride layer and the gallium nitride layer; forming an ohmic metal layer on the aluminum gallium nitride layer other than the nanometer band; and forming a gate metal layer on the nanometer band. The method for forming a transistor structure as described in Item 6 of the patent application range, wherein the step of forming the patterned mask layer includes forming the patterned mask layer by electron beam lithography. The method for forming a transistor structure as described in item 6 of the patent application scope, wherein the step of forming the nanoribbons includes removing part of the aluminum gallium nitride layer and the gallium nitride layer by reactive ion etching. The method for forming a transistor structure as described in item 6 of the patent application range, wherein the step of forming the ohmic metal layer includes an electron gun deposition method or a thermal deposition method to form a titanium / aluminum / nickel / gold layer. The method for forming a transistor structure as described in item 6 of the patent application range, wherein the step of forming the gate metal layer includes an electron gun deposition method or a thermal deposition method to form a nickel / gold layer.