TWI618229B - Flexible pixel array substrate and display panel - Google Patents

Abstract

A flexible pixel array substrate includes a flexible substrate, a plurality of signal lines, at least two thin film transistors, and a plurality of pixel electrodes. The flexible substrate has an active area and a peripheral area outside the active area. A plurality of signal lines are disposed on the flexible substrate. At least two thin film transistor arrays are arranged in the active area of the flexible substrate and electrically connected to the signal lines. Each of the thin film transistors includes a semiconductor pattern, a gate, a first inorganic insulating pattern between the gate and the semiconductor pattern, and a source and a drain electrically connected to the semiconductor pattern. The plurality of pixel electrodes are electrically connected to the at least two thin film transistors. In particular, the plurality of first inorganic insulating patterns of at least two thin film transistors are separated from each other. Further, a display panel including the above-described flexible pixel array substrate has also been proposed.

Description

Flexible pixel array substrate and display panel

The present invention relates to a pixel array substrate and a display panel, and more particularly to a flexible pixel array substrate and a flexible display panel.

With the development of display technology, display panels are increasingly used. For example, in the early days, display panels were mostly used as screens for electronic devices (eg, televisions, computers, mobile phones, etc.), while display panels applied to electronic devices were mostly hard display panels; in the near future, some people used display panels. In a wearable device (for example, a watch, a clothes, etc.), the display panel applied to the wearable device is mostly a flexible display panel.

Flexible display panels require considerable flexibility. In other words, when the flexible display panel is bent, components on the flexible substrate (eg, thin film transistors, data lines, scan lines, peripheral traces, etc.) need to be bent and maintain normal functions. However, in a conventional flexible display panel, the flexible pixel array substrate includes at least one layer of a substantially planar inorganic insulating layer. When the flexible display panel is bent, the relatively fragile inorganic insulating layer tends to be broken, and the surrounding film layer (for example, the first conductive layer, the second conductive layer, etc.) is cracked, thereby causing the flexible display panel. Invalid.

The invention provides a flexible pixel array substrate and a display panel, which are highly bendable.

A flexible pixel array substrate of the present invention comprises a flexible substrate, a plurality of signal lines, at least two thin film transistors, and a plurality of pixel electrodes. The flexible substrate has an active area and a peripheral area outside the active area. A plurality of signal lines are disposed on the flexible substrate. At least two thin film transistor arrays are arranged in the active area of the flexible substrate and electrically connected to the signal lines. Each of the thin film transistors includes a semiconductor pattern, a gate, a first inorganic insulating pattern between the gate and the semiconductor pattern, and a source and a drain electrically connected to the semiconductor pattern. The plurality of pixel electrodes are electrically connected to the at least two thin film transistors. In particular, the plurality of first inorganic insulating patterns of at least two thin film transistors are separated from each other.

Another flexible pixel array substrate of the present invention comprises a flexible substrate, a plurality of signal lines, a plurality of thin film transistors, a plurality of pixel electrodes, and a plurality of peripheral traces. The flexible substrate has an active area and a peripheral area outside the active area. A plurality of signal lines are disposed on the flexible substrate. The thin film transistor array is arranged on the active area of the flexible substrate and electrically connected to the signal line. The pixel electrode is electrically connected to the thin film transistor. The peripheral traces are disposed on the peripheral region of the flexible substrate and are electrically connected to the thin film transistor. The flexible substrate has two opposite first sides and a second side. The peripheral traces include n peripheral traces sequentially arranged in a direction in which the first side faces the second side. The first perimeter trace closest to the first side and the nth perimeter trace closest to the second side have non-linear portions. The peripheral trace between the first perimeter trace and the nth perimeter trace is linear.

In the above, in the flexible pixel array substrate and the display panel of the embodiment of the invention, the plurality of first inorganic insulating patterns of the plurality of thin film transistors are separated from each other. In other words, the first inorganic insulating layer which is relatively brittle and easily broken is broken into a plurality of small pieces (ie, a plurality of first inorganic insulating patterns). Therefore, when the flexible pixel array substrate is bent, each of the first inorganic insulating patterns having a small size is less likely to be cracked by the bending of the flexible pixel array substrate. Even if a certain first inorganic insulating pattern is cracked due to the bending of the flexible pixel array substrate, the crack of the one first inorganic insulating pattern does not easily extend to the other first inorganic insulating patterns, resulting in the periphery thereof. Components (eg bungee, source, partial perimeter traces, etc.) are damaged. Thereby, the flexible region of the active region of the flexible pixel array substrate can be improved.

On the other hand, in the flexible pixel array substrate and the display panel according to the embodiment of the present invention, the first and n peripheral traces closest to the opposite sides of the flexible substrate are designed to be non-linear. Moreover, the plurality of peripheral traces in the middle of the first and n peripheral traces are designed to be linear, which can save the layout space of all the peripheral traces and take into account the flexibility of the flexible pixel array substrate.

The above described features and advantages of the invention will be apparent from the following description.

1 is a top plan view of a flexible pixel array substrate according to an embodiment of the invention. 2A to 2G are schematic top views showing a manufacturing process of a flexible pixel array substrate according to an embodiment of the present invention. In particular, the region I of FIGS. 2A to 2G is a partial active region 110a corresponding to the flexible pixel array substrate 100 of FIG. 1, and the region II of FIGS. 2A to 2G is a flexible pixel array corresponding to FIG. A portion of the peripheral region 110b of the substrate 100. 3A to 3G are schematic cross-sectional views showing a manufacturing process of a flexible pixel array substrate according to an embodiment of the present invention. In particular, Figs. 3A to 3G are sectional lines A-A' and B-B' corresponding to Figs. 2A to 2G. Hereinafter, a manufacturing flow and a structure of the flexible pixel array substrate 100 according to an embodiment of the present invention will be described with reference to FIGS. 1, 2A to 2G, and 3A to 3G.

Referring to FIG. 1 , FIG. 2A and FIG. 3A , first, a flexible substrate 110 is provided. The flexible substrate 110 has an active area 110a and a peripheral area 110b outside the active area 110a. As shown in FIG. 1, in the embodiment, the flexible substrate 110 can selectively have a circular active area 110a and a neck-shaped peripheral area 110b connected below the circular active area 110a. However, the present invention is not limited thereto. In other embodiments, the appearance of the flexible substrate 110 can be differently designed according to actual needs. In this embodiment, the material of the flexible substrate 110 may be selected from organic polymers, such as: polyimide (PI), polyethylene naphthalate (PEN), polyethylene terephthalate. Polyethylene terephthalate (PET), polycarbonate (PC), polyether sulfone (PES), polyarylate, or other suitable materials, but the present invention does not limit.

Referring to FIGS. 2A and 3A , a plurality of inorganic buffer patterns 120 and a plurality of semiconductor patterns 130 are formed on the flexible substrate 110 . The plurality of inorganic buffer patterns 120 are disposed on the flexible substrate 110 and separated from each other. The plurality of semiconductor patterns 130 separated from each other are disposed on the plurality of inorganic buffer patterns 120, respectively. In detail, in the embodiment, an inorganic buffer layer (not shown) and a semiconductor layer (not shown) covering the inorganic buffer layer may be sequentially formed on the flexible substrate 110; The curtain patterning the plurality of inorganic buffer patterns 120 and the plurality of semiconductor patterns 130 stacked in phase. Each of the inorganic buffer patterns 120 and the corresponding one of the semiconductor patterns 130 are selectively spliced, but the present invention is not limited thereto. In other embodiments, each of the inorganic buffer patterns 120 may also selectively exceed a corresponding one of the semiconductor patterns. 130. The material of the inorganic buffer pattern 120 may be tantalum oxide, tantalum nitride, niobium oxynitride, other suitable materials, or a stacked layer of at least two materials, but the invention is not limited thereto. The semiconductor pattern 130 may be a single layer or a multilayer structure including an amorphous germanium, a polycrystalline germanium, a microcrystalline germanium, a single crystal germanium, an organic semiconductor material, an oxide semiconductor material (eg, indium zinc oxide, indium antimony zinc oxide, or Other suitable materials, or a combination thereof, or other suitable materials, or a dopant in the above materials, or a combination thereof, but the invention is not limited thereto.

Referring to FIG. 2B and FIG. 3B, next, a first inorganic insulating layer 140' is formed to cover the inorganic buffer pattern 120, the semiconductor pattern 130, and the partially flexible substrate 110. Then, a first conductive layer 150 is formed on the first inorganic insulating layer 140' (shown in Fig. 2B). The first conductive layer 150 may include a plurality of gates G and a plurality of scan lines SL. The scan line SL can also be called a signal line. Each gate G is located above a corresponding one of the semiconductor patterns 130 and is electrically connected to a corresponding one of the scan lines SL. In the present embodiment, the gate G and the scan line SL are made of a metal material, but the present invention is not limited thereto. According to other embodiments, other conductive materials may be used for the gate G and the scan line SL. For example: alloys, nitrides of metallic materials, oxides of metallic materials, oxynitrides of metallic materials, or stacked layers of metallic materials and other electrically conductive materials.

Referring to Fig. 2C and Fig. 3C, next, a second inorganic insulating layer 160' is formed to cover the gate G, the scanning line SL, and a portion of the first inorganic insulating layer 140'. Referring to FIG. 2C, FIG. 2D, FIG. 3C and FIG. 3D, the first inorganic insulating layer 140' and the second inorganic insulating layer 160' are patterned to form a plurality of first inorganic insulating patterns 140 and a plurality of second inorganic layers. Insulation pattern 160. As shown in FIG. 3D, each of the first inorganic insulating patterns 140 is located between the corresponding one of the gates G and the corresponding one of the semiconductor patterns 130. In other words, each of the first inorganic insulating patterns 140 covers a corresponding one of the semiconductor patterns 130. Each of the gates G is disposed on a corresponding one of the first inorganic insulating patterns 140. Each of the second inorganic insulating patterns 160 covers a corresponding one of the gates G and a corresponding one of the first inorganic insulating patterns 140. Each of the second inorganic insulating patterns 160 and the corresponding one of the first inorganic insulating patterns 140 has contact openings 160a, 140a, respectively. The interconnecting contact openings 140a, 160a expose both sides of a corresponding one of the semiconductor patterns 130. In particular, the plurality of first inorganic insulating patterns 140 on the plurality of semiconductor patterns 130 are separated from each other. The plurality of second inorganic insulating patterns 160 on the plurality of first inorganic insulating patterns 140 are separated from each other. In other words, the first inorganic insulating layer 140' whose material is brittle and easily broken has been patterned into a plurality of inorganic insulating patterns (ie, a plurality of first inorganic insulating patterns 140) which are disconnected from each other and are small in size, and the material is relatively brittle and easy. The broken second inorganic insulating layer 160' has been patterned into an inorganic insulating pattern (ie, a plurality of second inorganic insulating patterns 160) that are disconnected from each other and are in small pieces. There is a gap 140b between the plurality of first inorganic insulating patterns 140 (shown in FIG. 3D). There is a gap 160b between the plurality of second inorganic insulating patterns 160 (shown in FIG. 3D). In this embodiment, the material of the first inorganic insulating pattern 140 and the second inorganic insulating pattern 160 is, for example, tantalum oxide, tantalum nitride, hafnium oxynitride, other suitable materials, or a stacked layer of at least two materials described above, but The invention is not limited thereto.

Referring to FIG. 2E and FIG. 3E, a second conductive layer 170 (shown in FIG. 2E) is formed. The second conductive layer 170 includes a data line DL, a plurality of source electrodes S, a plurality of drain electrodes D, and a plurality of lower layer lead portions 172. The data line DL can also be called a signal line. Each source S is electrically connected to a corresponding one of the data lines DL. Each source S and each of the drains D are electrically connected to a corresponding one of the semiconductor patterns 130. In detail, in the embodiment, the source S and the drain D are disposed on the second inorganic insulating pattern 160 and filled in the contact openings 160a and 140a to pass through the second inorganic insulating pattern 160 and the first inorganic insulating pattern. 140, and electrically connected to the corresponding semiconductor pattern 130. In this embodiment, each of the inorganic buffer patterns 120, the corresponding one of the semiconductor patterns 130, the corresponding one of the first inorganic insulating patterns 140, the corresponding one of the second inorganic insulating patterns 160, the corresponding one of the source electrodes S, and the corresponding one The bungee D can be regarded as a thin film transistor T. The thin film transistor T is disposed on the active region 110a of the flexible substrate 110. The plurality of lower lead portions 172 are disposed in the peripheral region 110a of the flexible substrate 110. In the present embodiment, the lower wire portion 172 can be in direct contact with the flexible substrate 110. However, the present invention is not limited thereto, and in other embodiments, the lower wire portion 172 may be disposed on other suitable members, which will be exemplified in the following paragraphs in conjunction with other figures. The second conductive layer 170 (ie, the data line DL, the source S, the drain D, and the lower lead portion 172) is generally made of a metal material, but the present invention is not limited thereto. According to other embodiments, the second conductive layer 170 may also be used. Other conductive materials, such as alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, or stacked layers of metal materials and other conductive materials.

Referring to FIG. 2F and FIG. 3F, next, a first organic insulating layer 180 and a third conductive layer 190 (shown in FIG. 2F) are formed. As shown in FIG. 3F, the first organic insulating layer 180 covers the source S and the drain D of the thin film transistor T. The first organic insulating layer 180 fills the gap 140b between the plurality of first inorganic insulating patterns 140 of the plurality of thin film transistors T and the gap 160b between the plurality of second inorganic insulating patterns 160 of the plurality of thin film transistors T, It is in contact with the flexible substrate 110. The first organic insulating layer 180 covers the lower wiring portion 172 located in the peripheral region 110b and a portion of the peripheral region 110b of the flexible substrate 110. A portion of the first organic insulating layer 180 located in the peripheral region 110b has a plurality of contact openings 180a. Both ends of each lower layer wire portion 172 are exposed by the corresponding contact opening 180a.

Referring to FIG. 2F and FIG. 3F , the third conductive layer 190 is disposed on the first organic insulating layer 180 . The third conductive layer 190 includes an upper wire portion 192. In this embodiment, the third conductive layer 190 may selectively include the electrode 194 electrically connected to the drain D. However, the present invention is not limited thereto. In other embodiments, the electrode 194 may not be disposed, and the electrode may be disposed. 194 depends on actual needs. The upper wire portion 192 is located in the peripheral region 110b. The upper lead portion 192 is disposed on the first organic insulating layer 180 and filled in the contact opening 180a of the first organic insulating layer 180 to be electrically connected to the corresponding lower lead portion 172 to form the peripheral trace L. The peripheral trace L is electrically connected to the signal line. The signal line may refer to the data line DL, the scan line SL or other suitable wires for transmitting signals.

Referring to FIG. 2F and FIG. 3F, in the present embodiment, the plurality of lower lead portions 172 are separated from each other, and the plurality of upper lead portions 192 are separated from each other. The lower lead portion 172 and the upper lead portion 192 are alternately arranged and connected in series to the peripheral trace L. Each of the peripheral traces L is electrically connected to the corresponding thin film transistor T. For example, each of the peripheral traces L can be electrically connected to the source S of the plurality of thin film transistors T through a corresponding one of the data lines DL; or each of the peripheral traces L can pass through a corresponding one of the scan lines SL and The gates G of the plurality of thin film transistors T are electrically connected, but the invention is not limited thereto. The peripheral traces L may also refer to other signal lines electrically connected to the thin film transistor T. As shown in FIG. 2F, the lower lead portion 172 has a non-linear portion 172a. The upper lead portion 192 has a non-linear portion 192a. In the present embodiment, the non-linear portion 192a of the upper lead portion 192 overlaps with the non-linear portion 192a of the lower lead portion 172, and the non-linear portion 192a of the upper lead portion 192 fills the contact opening 180a of the first organic insulating layer 180, It is electrically connected to the non-linear portion 172a of the lower lead portion 172, but the invention is not limited thereto.

Referring to FIG. 2F, in the embodiment, the lower layer lead portion 172 and the upper layer lead portion 192 are selectively approximated to a semicircular pattern. However, the present invention is not limited thereto. In other embodiments, the lower wire portion 172 and the upper wire portion 192 may be selectively in other suitable patterns, such as a triangle, a trapezoid, a diamond, a circle, an ellipse, or the like. In this embodiment, each of the lower wire portions 172 may alternatively be a single pattern (eg, a pattern that approximates a semicircle), and each of the upper wire portions 192 may alternatively be a single pattern (eg, A pattern similar to a semicircle). However, the present invention is not limited thereto. In other embodiments, each of the lower wire portions 172 and/or each of the upper wire portions 192 may be combined by two or more repeating patterns, for example, two connected to each other are similar to A semicircular pattern, two trapezoids connected to each other, two diamonds connected to each other, two circles connected to each other, and two elliptical shapes connected to each other.

Referring to FIG. 2G and FIG. 3G, next, the second organic insulating layer 200 and the pixel electrode 210 are formed. The second organic insulating layer 200 covers the upper lead portion 192 of the peripheral trace L, the electrode 194, and a portion of the first organic insulating layer 180. The second organic insulating layer 200 has a contact opening 200a. The contact opening 200a exposes the drain D of the thin film transistor T. The pixel electrode 210 is electrically connected to the thin film transistor T. In detail, the pixel electrode 210 is disposed on the second organic insulating layer 200 to be electrically connected to the drain D of the thin film transistor T by filling the contact opening 200a of the second organic insulating layer 200. Thus, the flexible pixel array substrate 100 of the present embodiment is completed.

It is worth mentioning that, as shown in FIG. 3G, the plurality of first inorganic insulating patterns 140 of the plurality of thin film transistors T are separated from each other. In other words, the first inorganic insulating layer, which is relatively brittle and easily broken, has been broken into a plurality of small pieces (ie, a plurality of first inorganic insulating patterns 140). Therefore, when the flexible pixel array substrate 100 is bent, each of the first inorganic insulating patterns 140 having a small size is less likely to be cracked by the bending of the flexible pixel array substrate 100. Even if a certain first inorganic insulating pattern 140 is cracked due to the bending of the flexible pixel array substrate 100, the crack of the one first inorganic insulating pattern 140 does not easily extend to the other first inorganic insulating patterns 140, and The components surrounding it (for example: bungee D, source S, partial peripheral trace L, etc.) are damaged. Thereby, the degree of bendability of the active region 110a of the flexible pixel array substrate 100 can be improved. On the other hand, as shown in FIG. 3G, each of the peripheral traces L of the peripheral region 110b has a softer organic material (ie, the first organic insulating layer 180) interposed between the upper lead portion 192 and the lower lead portion 172. The inorganic material which is brittle and easily broken is not interposed. Therefore, when the flexible pixel array substrate 100 is bent, the upper lead portion 192 of the peripheral trace L is less likely to be broken by the weaker film layer. Thereby, the degree of bendability of the peripheral region 110b of the flexible pixel array substrate 100 can be improved.

4 illustrates a peripheral region of a flexible substrate and a plurality of peripheral traces thereon, in accordance with an embodiment of the present invention. Fig. 5 is a schematic cross-sectional view showing the peripheral traces taken along the line A-A', B-B' of Fig. 4. Referring to FIGS. 4 and 5, the peripheral region 110b of the flexible substrate 110 (eg, the neck-shaped peripheral region 110b of FIG. 1) has two opposite first side S1 and second side S2. The peripheral traces L, L' are electrically connected to the thin film transistor T. The peripheral traces L, L' include n peripheral traces L, L' sequentially arranged in the direction d in which the first side S1 points to the second side S2. n may be a positive integer greater than or equal to 3. The first peripheral trace L closest to the first side S1 and the nth peripheral trace L closest to the second side S2 each have non-linear portions 172a, 192a. The peripheral trace L' located between the first peripheral trace L and the nth peripheral trace L is linear.

Referring to Figures 4 and 5, in the present embodiment, each of the peripheral traces L, L' includes a lower lead portion 172 and an upper lead portion 192. The lower lead portion 172 is disposed on the flexible substrate 110. The first organic insulating layer 180 covers the lower wiring portion 172 and has a plurality of contact openings 180a exposing the lower wiring portion 172. The upper lead portion 192 is disposed on the first organic insulating layer 180 and filled in the contact opening 180a of the first organic insulating layer 180 to be electrically connected to the upper lead portion 192. The lower lead portion 172 of the first peripheral trace L closest to the first side S1 and the lower lead portion 172 of the nth peripheral trace L closest to the second side S2 have non-linear portions 172a, 192a. The upper lead portion 192 and the lower lead portion 172 of the peripheral trace L' located at the intermediate portion between the first peripheral trace L and the nth peripheral trace 1 may be linear. In other words, the intermediate peripheral trace L' can be formed by connecting the upper lead portion 192 and the lower lead portion 172 in series. However, the present invention is not limited thereto, and in the embodiment, the intermediate peripheral trace L' may also be a linear conductor composed of a single film layer (e.g., the aforementioned second conductive layer 170).

Referring to FIG. 4, in the present embodiment, the lower lead portion 172 of the first peripheral trace L closest to the first side S1 has two first contacts with the upper lead portion 192 of the first peripheral trace L. A contact point P1. Two vertical projections of the two first contact points P1 on the flexible substrate 110 are connected into a line l1. The vertical projection of the non-linear portion 172a of the lower lead portion 172 of the first peripheral trace L on the flexible substrate 110 is located between the line l1 and the first side S1. In short, the non-linear edge (eg, wavy edge) on the left side of the first perimeter trace L is closer to the first side S1 of the flexible substrate 110 than the straight edge on the right side. Similarly, the lower lead portion 172 of the nth peripheral trace L closest to the second side S2 has two second contact points P2 that are in contact with the upper lead portion 192 of the nth peripheral trace L. Two vertical projections of the two second contact points P2 on the flexible substrate 110 are connected into a line l2. The vertical projection of the non-linear portion 172a of the layer conductor portion 172 under the nth peripheral trace on the flexible substrate 110 is located between the line l2 and the second side S2. In short, the non-linear edge (for example, the wavy edge) on the right side of the nth peripheral trace L is closer to the second side S2 of the flexible substrate 110 than the straight edge on the left side thereof. The first and n peripheral traces L closest to the first and second sides S1 and S2 of the flexible substrate 110 are designed to be non-linear, and a plurality of peripheral portions of the first and n peripheral traces L are arranged. The trace L' is designed as a straight line, which saves the layout space of all the peripheral traces L and the degree of flexibility of the flexible pixel array substrate 100. However, the present invention is not limited thereto, and in other embodiments, all of the peripheral traces L, L' may be designed to be non-linear.

Referring to FIG. 4, in the present embodiment, the first peripheral trace L closest to the first side S1 of the flexible substrate 110 and the n-th periphery closest to the second side S2 of the flexible substrate 110 are taken. The line L has non-linear portions 172a, 192a. In other words, the first peripheral trace L and the nth peripheral trace L may be longer than the other peripheral traces L'. The maximum line width w1 of the non-linear portions 172a, 192a of the first peripheral trace L and the maximum line width w2 of the non-linear portions 172a, 192a of the n-th peripheral trace are larger than the middle of the first and n peripheral traces The maximum line width w3 of the surrounding trace L'. In other words, although the first peripheral trace L and the nth peripheral trace L have long lengths due to the non-linear portions 172a and 192a, the cross-sectional areas of the first and n peripheral traces are large, and the The resistance values of the first and n peripheral traces L of the periphery are close to the resistance values of the peripheral traces L' located in the middle, which contribute to the electrical properties of the flexible pixel array substrate 100.

In the foregoing embodiment, the peripheral trace L is formed by connecting the lower-layer lead portions 172 and the upper-layer lead portions 192 which are alternately arranged in series. Both the upper lead portion 192 and the lower lead portion 172 have non-linear portions 192a and 172a. However, the present invention is not limited thereto, and in other embodiments, the peripheral trace L may also be in other suitable states. The following description will be exemplified using Figs. 6 to 9 .

FIG. 6 is a top plan view of a peripheral trace according to an embodiment of the invention. Fig. 7 is a schematic cross-sectional view showing a peripheral trace taken along a line A-A' of Fig. 6. Referring to FIGS. 6 and 7, similarly to the peripheral trace L, the peripheral trace LA is also formed by connecting the lower lead portion 172A and the upper lead portion 192A in series. The lower lead portion 172A has a non-linear portion 172a. Different from the peripheral trace L, the upper lead portion 192A of the peripheral trace LA may be in a straight line. In the embodiment of FIG. 6 and FIG. 7, the lower lead portion 172A is approximately semicircular, but the present invention is not limited thereto. In the embodiment, the lower lead portion 172A may also have other suitable shapes, such as trapezoidal or rhombic. , round, oval, etc.

FIG. 8 is a top plan view of a peripheral trace according to another embodiment of the present invention. Fig. 9 is a schematic cross-sectional view showing a peripheral trace drawn along a line A-A' of Fig. 8. Referring to FIGS. 8 and 9, similarly to the peripheral trace L, the peripheral trace LB is also formed by connecting the lower lead portion 172B and the upper lead portion 192B in series. In detail, the non-linear portion 192a of the upper lead portion 192B is filled in the contact opening 180a of the first organic insulating layer 180 to be electrically connected to the non-linear portion 172a of the lower lead portion 172B. Unlike the peripheral trace L, the non-linear portion 172a of the upper lead portion 172B overlaps with the non-linear portion 192a of the lower lead portion 192B and may have the same pattern. Preferably, there are three or more contact points P3 between the lower lead portion 172B and the upper lead portion 192B. Thereby, if any of the lower wire portion 172B and the upper wire portion 192B is damaged, the signal can still be transmitted therethrough, and the function of the peripheral wire LB is maintained normal. In the embodiment of FIG. 8 and FIG. 9, the lower lead portion 172B and the upper lead portion 192B may have a plurality of circular shapes connected to each other, but the present invention is not limited thereto. In the embodiment, the lower lead portion 172B and the upper layer lead are used. The portion 192B may have other suitable shapes, for example, a plurality of trapezoids connected to each other, a plurality of rhombic shapes connected to each other, a plurality of semicircles connected to each other, a plurality of elliptical shapes connected to each other, and the like. The peripheral traces LA and LB described above may be used in place of the peripheral trace L of the flexible pixel array substrate 100 described above. A plurality of flexible pixel array substrates formed by replacing the peripheral traces L with the peripheral traces LA and LB are also within the scope of the present invention.

FIG. 10 is a top plan view of a flexible pixel array substrate according to another embodiment of the present invention. 11A to 11G are schematic top views showing a manufacturing process of a flexible pixel array substrate according to another embodiment of the present invention. In particular, the region I of FIGS. 11A to 11G is a partial active region 110a corresponding to the flexible pixel array substrate 100C of FIG. 10, and the region II of FIGS. 11A to 11G is a flexible pixel array corresponding to FIG. A portion of the peripheral region 110b of the substrate 100C. 12A to 12G are schematic cross-sectional views showing a manufacturing process of a flexible pixel array substrate according to another embodiment of the present invention. In particular, Figs. 12A to 12G correspond to the cross-sectional lines A-A' and B-B' of Figs. 11A to 11G. Hereinafter, a manufacturing flow and a structure of the flexible pixel array substrate 100C according to an embodiment of the present invention will be described with reference to FIGS. 10, 11A to 11G, and FIGS. 12A to 12G. The flexible pixel array substrate 100C of the present embodiment is similar to the aforementioned flexible pixel array substrate 100, and therefore the same or corresponding elements are denoted by the same or corresponding reference numerals. The difference between the flexible pixel array substrate 100C of the present embodiment and the flexible pixel array substrate 100 is that the third inorganic insulating pattern 142 is disposed under the peripheral trace LC of the flexible pixel array substrate 100C. The fourth inorganic insulating pattern 162. The following mainly explains the difference, and the same points are referred to the above description in accordance with the reference numerals in FIG. 10, FIG. 11A to FIG. 11G, and FIG. 12A to FIG. 12G, and the description thereof will not be repeated.

Referring to FIG. 10, FIG. 11A and FIG. 12A, first, a flexible substrate 110 is provided. The flexible substrate 110 has an active area 110a and a peripheral area 110b outside the active area 110a. Referring to FIGS. 11A and 12A , a plurality of inorganic buffer patterns 120 and a plurality of semiconductor patterns 130 are formed on the flexible substrate 110 . Referring to FIG. 11B and FIG. 12B, next, a first inorganic insulating layer 140' is formed to cover the inorganic buffer pattern 120, the semiconductor pattern 130, and the partially flexible substrate 110. Then, a first conductive layer 150 is formed on the first inorganic insulating layer 140'. The first conductive layer 150 may include a plurality of gates G and a plurality of scan lines SL. The scan line SL can also be called a signal line. Each gate G is located above a corresponding one of the semiconductor patterns 130 and is electrically connected to a corresponding one of the scan lines SL.

Referring to Fig. 11C and Fig. 12C, next, a second inorganic insulating layer 160' is formed to cover the gate G, the scanning line SL, and a portion of the first inorganic insulating layer 140'. Referring to FIG. 11C, FIG. 11D, FIG. 12C, and FIG. 12D, the first inorganic insulating layer 140' and the second inorganic insulating layer 160' are patterned to form a plurality of first inorganic insulating patterns 140 and a plurality of second inorganic layers. Insulation pattern 160. As shown in FIG. 12D, each of the first inorganic insulating patterns 140 is located between the corresponding one of the gates G and the corresponding one of the semiconductor patterns 130. Each of the first inorganic insulating patterns 140 covers a corresponding one of the semiconductor patterns 130. Each of the gates G is disposed on a corresponding one of the first inorganic insulating patterns 140. Each of the second inorganic insulating patterns 160 covers a corresponding one of the gates G and a corresponding one of the first inorganic insulating patterns 140. Each of the second inorganic insulating patterns 160 and the corresponding one of the first inorganic insulating patterns 140 has contact openings 160a, 140a, respectively. The communicating contact openings 140a, 160a expose opposite sides of a corresponding one of the semiconductor patterns 130. In particular, the plurality of first inorganic insulating patterns 140 on the plurality of semiconductor patterns 130 are separated from each other. The plurality of second inorganic insulating patterns 160 on the plurality of first inorganic insulating patterns 140 are separated from each other.

Referring to FIG. 11C, FIG. 11D, FIG. 12C and FIG. 12D, different from the flexible pixel array substrate 100, in the embodiment, the first inorganic insulating pattern 140 located in the active region 110a is patterned. When the inorganic insulating pattern 160 is used, the third inorganic insulating pattern 142 and the fourth inorganic insulating pattern 162 located in the peripheral region 110b are patterned at the same time. The first inorganic insulating pattern 140 and the third inorganic insulating pattern 142 belong to the same inorganic insulating layer. The second inorganic insulating pattern 160 and the fourth inorganic insulating pattern 162 belong to the same inorganic insulating layer. The plurality of third inorganic insulating patterns 142 are separated from each other and disposed on the peripheral region 110b of the flexible substrate 110. The plurality of fourth inorganic insulating patterns 162 are separated from each other and disposed on the peripheral region 110b of the flexible substrate 110. Each of the fourth inorganic insulating patterns 162 is stacked on a corresponding one of the third inorganic insulating patterns 142.

Referring to FIG. 11E and FIG. 12E, next, the second conductive layer 170 is formed. The second conductive layer 170 includes a data line (also referred to as a signal line) DL, a plurality of source electrodes S, a plurality of drain electrodes D, and a plurality of lower layer lead portions 172C. Each source S is electrically connected to a corresponding one of the data lines DL. Each source S and each of the drains D are electrically connected to a corresponding one of the semiconductor patterns 130. Each of the inorganic buffer patterns 120, the corresponding one of the semiconductor patterns 130, the corresponding one of the first inorganic insulating patterns 140, the corresponding one of the second inorganic insulating patterns 160, the corresponding one of the source electrodes S, and the corresponding one of the drain electrodes D can be regarded as one Thin film transistor T. The thin film transistor T is disposed on the active region 110a of the flexible substrate 110. The plurality of lower lead portions 172C are disposed in the peripheral region 110a of the flexible substrate 110. Different from the flexible pixel array substrate 100, in the present embodiment, the plurality of lower wiring portions 172C are respectively disposed on the plurality of fourth inorganic insulating patterns 162 separated from each other without being directly connected to the flexible substrate 110. contact.

Referring to FIG. 11F and FIG. 12F, next, the first organic insulating layer 180 and the third conductive layer 190 are formed. The first organic insulating layer 180 covers the peripheral region 110b of the flexible substrate 110 and the lower wiring portion 172C of the peripheral region 110b. The first organic insulating layer 180 has a plurality of contact openings 180a. Each lower layer wire portion 172C is exposed by a corresponding contact opening 180a. Referring to FIG. 12F , the third conductive layer 190 is disposed on the first organic insulating layer 180 . The third conductive layer 190 includes an upper wire portion 192. In the present embodiment, the third conductive layer 190 may selectively include the electrode 194 electrically connected to the drain D, but the invention is not limited thereto. The upper lead portion 192 is disposed on the first organic insulating layer 180 and filled in the contact opening 180a of the first organic insulating layer 180 to be electrically connected to the corresponding lower lead portion 172C to form the peripheral trace LC. The peripheral trace LC is electrically connected to the signal line. The signal line may refer to the data line DL, the scan line SL or other suitable wires for transmitting signals.

Referring to FIGS. 11G and 12G, next, the second organic insulating layer 200 and the pixel electrode 210 are formed. The second organic insulating layer 200 covers the upper wiring portion 192, the electrode 194, and a portion of the first organic insulating layer 180. The second organic insulating layer 200 has a contact opening 200a. The contact opening 200a exposes the drain D of the thin film transistor T. The pixel electrode 210 is electrically connected to the thin film transistor T. Thus, the flexible pixel array substrate 100C of the present embodiment is completed. The flexible pixel array substrate 100C has similar functions and advantages as the flexible pixel array substrate 100, and will not be repeated here.

FIG. 13 is a top plan view of a flexible pixel array substrate according to still another embodiment of the present invention. 14A to 14G are schematic top views showing a manufacturing process of a flexible pixel array substrate according to still another embodiment of the present invention. In particular, the region I of FIGS. 14A to 14G is a partial active region 110a corresponding to the flexible pixel array substrate 100D of FIG. 13, and the region II of FIGS. 14A to 14G is a flexible pixel array corresponding to FIG. A portion of the peripheral region 110b of the substrate 100D. 15A to 15G are schematic cross-sectional views showing a manufacturing process of a flexible pixel array substrate according to still another embodiment of the present invention. In particular, Figs. 15A to 15G correspond to the cross-sectional lines A-A' and B-B' of Figs. 14A to 14G. Hereinafter, a manufacturing flow and a structure of the flexible pixel array substrate 100D according to still another embodiment of the present invention will be described with reference to FIGS. 13, 14A to 14G, and FIGS. 15A to 15G. The flexible pixel array substrate 100D of the present embodiment is similar to the aforementioned flexible pixel array substrate 100, and thus the same or corresponding elements are denoted by the same or corresponding reference numerals. The difference between the flexible pixel array substrate 100D of the present embodiment and the flexible pixel array substrate 100 is that an inorganic buffer pattern 122 is disposed under the peripheral trace LD of the flexible pixel array substrate 100D. The following mainly explains the difference, and the same points are referred to the above description in accordance with the reference numerals in FIG. 13, FIG. 14A to FIG. 14G, and FIGS. 15A to 15G, and the description thereof will not be repeated.

Referring to FIG. 13 , FIG. 14A and FIG. 15A , first, a flexible substrate 110 is provided. The flexible substrate 110 has an active area 110a and a peripheral area 110b outside the active area 110a. Next, an inorganic buffer layer BL is formed on the flexible substrate 110. The inorganic buffer layer BL has a plurality of buffer convex portions 120' and a buffer thinned portion 122. The thickness of the buffer convex portion 120' is larger than the thickness of the buffer thinned portion 122. Next, a plurality of semiconductor patterns 130 are formed on the plurality of buffer convex portions 120', respectively. Referring to Fig. 14B and Fig. 15B, next, a first inorganic insulating layer 140' is formed to cover the inorganic buffer layer BL and the semiconductor pattern 130. Then, a first conductive layer 150 is formed on the first inorganic insulating layer 140'. The first conductive layer 150 may include a plurality of gates G and a plurality of scan lines (also referred to as signal lines) SL. Each gate G is located above a corresponding one of the semiconductor patterns 130 and is electrically connected to a corresponding one of the scan lines SL.

Referring to Fig. 14C and Fig. 15C, next, a second inorganic insulating layer 160' is formed to cover the gate G, the scanning line SL, and a portion of the first inorganic insulating layer 140'. Referring to FIG. 14C, FIG. 14D, FIG. 15C, and FIG. 15D, the first inorganic insulating layer 140', the second inorganic insulating layer 160', and the inorganic buffer layer BL are patterned to form a plurality of first inorganic insulating patterns 140, A plurality of second inorganic insulating patterns 160 and a plurality of inorganic buffer patterns 120, 122. As shown in FIG. 15D, a plurality of semiconductor patterns 130 are respectively located on the plurality of inorganic buffer patterns 120. The plurality of inorganic buffer patterns 122 are disposed on the peripheral region 110b of the flexible substrate 110 and separated from each other. Each of the first inorganic insulating patterns 140 is located between the corresponding one of the gates G and the corresponding one of the semiconductor patterns 130. Each of the first inorganic insulating patterns 140 covers a corresponding one of the semiconductor patterns 130. Each of the gates G is disposed on a corresponding one of the first inorganic insulating patterns 140. Each of the second inorganic insulating patterns 160 covers a corresponding one of the gates G and a corresponding one of the first inorganic insulating patterns 140. Each of the second inorganic insulating patterns 160 and the corresponding one of the first inorganic insulating patterns 140 has contact openings 160a, 140a, respectively. The interconnecting contact openings 140a, 160a expose both sides of a corresponding one of the semiconductor patterns 130. In particular, the plurality of first inorganic insulating patterns 140 on the plurality of semiconductor patterns 130 are separated from each other. The plurality of second inorganic insulating patterns 160 on the plurality of first inorganic insulating patterns 140 are separated from each other.

Referring to FIG. 14E and FIG. 15E, next, the second conductive layer 170 is formed. The second conductive layer 170 includes a data line (also referred to as a signal line) DL, a plurality of source S, a plurality of drain electrodes D, and a plurality of lower layer lead portions 172D. Each source S is electrically connected to a corresponding one of the data lines DL. Each source S and each of the drains D are electrically connected to a corresponding one of the semiconductor patterns 130. Each of the inorganic buffer patterns 120, the corresponding one of the semiconductor patterns 130, the corresponding one of the first inorganic insulating patterns 140, the corresponding one of the second inorganic insulating patterns 160, the corresponding one of the source electrodes S, and the corresponding one of the drain electrodes D can be regarded as one Thin film transistor T. The thin film transistor T is disposed on the active region 110a of the flexible substrate 110. The plurality of lower lead portions 172D are disposed in the peripheral region 110a of the flexible substrate 110. Unlike the flexible pixel array substrate 100, in the present embodiment, the plurality of lower wiring portions 172D are respectively disposed on the plurality of inorganic buffer patterns 122 separated from each other without being in direct contact with the flexible substrate 110.

Referring to FIG. 14F and FIG. 15F, next, the first organic insulating layer 180 and the third conductive layer 190 are formed. The first organic insulating layer 180 covers the thin film transistor T, the peripheral region 110b of the flexible substrate 110, and the lower wiring portion 172D located in the peripheral region 110b. The first organic insulating layer 180 has a plurality of contact openings 180a. Each lower layer wire portion 172D is exposed by a corresponding contact opening 180a. Referring to FIG. 15F , the third conductive layer 190 is disposed on the first organic insulating layer 180 . The third conductive layer 190 includes an upper wire portion 192. In this embodiment, the third conductive layer 190 can selectively include an electrode 194 electrically connected to the drain D. The upper lead portion 192 is disposed on the first organic insulating layer 180 and filled in the contact opening 180a of the first organic insulating layer 180 to be electrically connected to the corresponding lower lead portion 172D to form the peripheral trace LD. The peripheral trace LD is electrically connected to the signal line. The signal line may refer to the data line DL, the scan line SL or other suitable wires for transmitting signals.

Referring to FIGS. 14G and 15G, next, the second organic insulating layer 200 and the pixel electrode 210 are formed. The second organic insulating layer 200 covers the upper wiring portion 192, the electrode 194, and a portion of the first organic insulating layer 180. The second organic insulating layer 200 has a contact opening 200a. The contact opening 200a exposes the drain D of the thin film transistor T. The pixel electrode 210 is electrically connected to the thin film transistor T. Thus, the flexible pixel array substrate 100D of the present embodiment is completed. The flexible pixel array substrate 100D has similar functions and advantages as the flexible pixel array substrate 100, and will not be repeated here.

Figure 16 is a cross-sectional view showing a display panel in accordance with an embodiment of the present invention. Referring to FIG. 16, the display panel 1000 includes any one of the flexible pixel array substrates 100, 100C, and 100D, and is disposed opposite to any of the flexible pixel array substrates 100, 100C, and 100D. The substrate 300 and the display medium 400 disposed between the flexible pixel array substrates 100, 100C, and 100D and the counter substrate 300. In the present embodiment, the display medium 400 is, for example, an organic electroluminescent layer. However, the invention is limited thereto, and in other embodiments, display medium 400 can also be liquid crystal or other suitable material. Since the display panel 1000 employs any of the flexible pixel array substrates 100, 100C, and 100D, the display panel 1000 also has the advantage of being bendable.

As described above, in the flexible pixel array substrate and the display panel of one embodiment of the present invention, the plurality of first inorganic insulating patterns of the plurality of thin film transistors are separated from each other. In other words, the first inorganic insulating layer which is relatively brittle and easily broken is broken into a plurality of small pieces (ie, a plurality of first inorganic insulating patterns). Therefore, when the flexible pixel array substrate is bent, each of the first inorganic insulating patterns having a small size is less likely to be cracked by the bending of the flexible pixel array substrate. Even if a certain first inorganic insulating pattern is cracked due to bending of the flexible pixel array substrate, cracks of the one first inorganic insulating pattern are not easily extended to other first inorganic insulating patterns, resulting in peripheral members. (eg bungee, source, partial perimeter, etc.) damaged. Thereby, the flexible region of the active region of the flexible pixel array substrate can be improved.

On the other hand, in the flexible pixel array substrate and the display panel according to the embodiment of the present invention, the first and n peripheral traces closest to the opposite sides of the flexible substrate are designed to be non-linear. Moreover, the plurality of peripheral traces in the middle of the first and n peripheral traces are designed to be linear, which can save the layout space of all the peripheral traces and take into account the flexibility of the flexible pixel array substrate.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100, 100C, 100D‧‧‧ flexible pixel array substrate
110‧‧‧Flexible substrate
110a‧‧‧active area
110b‧‧‧ surrounding area
120‧‧‧Inorganic buffer pattern
120'‧‧‧buffer convex
122‧‧‧Buffering and thinning department
130‧‧‧Semiconductor pattern
140‧‧‧First inorganic insulation pattern
140'‧‧‧First inorganic insulation
140a, 160a, 180a, 200a‧‧‧ contact openings
140b, 160b‧‧‧ gap
142‧‧‧ Third inorganic insulation pattern
150‧‧‧First conductive layer
160‧‧‧Second inorganic insulation pattern
160'‧‧‧Second inorganic insulation
162‧‧‧fourth inorganic insulation pattern
170‧‧‧Second conductive layer
172, 172A, 172B, 172C, 172D‧‧‧ lower wire section
172a, 192a‧‧‧ non-linear
180‧‧‧First organic insulation
190‧‧‧ third conductive layer
192, 192A, 192B‧‧‧ upper wire section
194‧‧‧electrode
200‧‧‧Second organic insulation
210‧‧‧ pixel electrodes
300‧‧‧ opposite substrate
400‧‧‧Display media
A-A', B-B'‧‧‧ cut line
BL‧‧‧Inorganic buffer layer
DL‧‧‧ data line
D‧‧‧汲
D‧‧‧ Direction
G‧‧‧ gate
L, L', LA, LB, LC, LD‧‧‧ peripheral wiring
11, l2‧‧‧ connection
P1‧‧‧ first touch point
P2‧‧‧ second touch point
P3‧‧‧ touch points
S‧‧‧ source
SL‧‧‧ scan line
S1‧‧‧ first side
S2‧‧‧ second side
T‧‧‧film transistor
W1, w2, w3‧‧‧ line width I, II‧‧‧ area

1 is a top plan view of a flexible pixel array substrate according to an embodiment of the invention. 2A to 2G are schematic top views showing a manufacturing process of a flexible pixel array substrate according to an embodiment of the present invention. 3A to 3G are schematic cross-sectional views showing a manufacturing process of a flexible pixel array substrate according to an embodiment of the present invention. 4 illustrates a peripheral region of a flexible substrate and a plurality of peripheral traces thereon, in accordance with an embodiment of the present invention. Fig. 5 is a schematic cross-sectional view showing the peripheral traces taken along the line A-A', B-B' of Fig. 4. FIG. 6 is a top plan view of a peripheral trace according to an embodiment of the invention. Fig. 7 is a schematic cross-sectional view showing a peripheral trace taken along a line A-A' of Fig. 6. FIG. 8 is a top plan view of a peripheral trace according to another embodiment of the present invention. Fig. 9 is a schematic cross-sectional view showing a peripheral trace drawn along a line A-A' of Fig. 8. FIG. 10 is a top plan view of a flexible pixel array substrate according to another embodiment of the present invention. 11A to 11G are schematic top views showing a manufacturing process of a flexible pixel array substrate according to another embodiment of the present invention. 12A to 12G are schematic cross-sectional views showing a manufacturing process of a flexible pixel array substrate according to another embodiment of the present invention. FIG. 13 is a top plan view of a flexible pixel array substrate according to still another embodiment of the present invention. 14A to 14G are schematic top views showing a manufacturing process of a flexible pixel array substrate according to still another embodiment of the present invention. 15A to 15G are schematic cross-sectional views showing a manufacturing process of a flexible pixel array substrate according to still another embodiment of the present invention. Figure 16 is a cross-sectional view showing a display panel in accordance with an embodiment of the present invention.

Claims (21)

A flexible pixel array substrate comprising: a flexible substrate having an active region and a peripheral region outside the active region; a plurality of signal lines disposed on the flexible substrate; at least two thin film transistors, an array Arranging in the active region of the flexible substrate and electrically connecting to the signal lines, each of the thin film transistors includes: a semiconductor pattern; a gate; a first inorganic insulating pattern, the gate and the semiconductor pattern a source and a drain electrically connected to the semiconductor pattern, wherein the plurality of first inorganic insulating patterns of the thin film transistors are separated from each other; a plurality of pixel electrodes, and the thin film transistors And a first organic insulating layer covering the plurality of sources and the plurality of drains of the thin film transistors, wherein the pixel electrodes are disposed on the first organic insulating layer, wherein the first organic insulating layer A layer fills a gap between the first inorganic insulating patterns of the thin film transistors to contact the flexible substrate. The flexible pixel array substrate of claim 1, wherein the semiconductor pattern is disposed on the flexible substrate, the first inorganic insulating pattern covers the semiconductor pattern, and the gate is disposed on the first inorganic Each of the thin film transistors further includes: a second inorganic insulating pattern covering the gate and the first inorganic insulating pattern, wherein the source and the drain are disposed on the second inorganic insulating pattern and are worn Pass the second The inorganic insulating pattern and the first inorganic insulating pattern are electrically connected to the semiconductor pattern, wherein the plurality of second inorganic insulating patterns of the thin film transistors are separated from each other. The flexible pixel array substrate of claim 2, wherein each of the thin film transistors further comprises an inorganic buffer pattern disposed on the flexible substrate, the semiconductor pattern being disposed on the inorganic buffer pattern Wherein the plurality of inorganic buffer patterns of the thin film transistors are separated from each other. The flexible pixel array substrate of claim 1, wherein the first organic insulating layer further covers the peripheral region of the flexible substrate, and the flexible pixel array substrate further comprises: a plurality of peripheral traces disposed on the peripheral region of the flexible substrate and electrically connected to the thin film transistors, each of the peripheral traces comprising: at least a lower layer of lead portions disposed on the flexible substrate The first organic insulating layer covers the lower conductive portion and has a plurality of contact openings exposing the lower conductive portion; and at least one upper conductive portion disposed on the first organic insulating layer and filled with the first organic insulating layer The contact openings are electrically connected to the lower wire portion. The flexible pixel array substrate of claim 4, wherein the at least one lower wire portion is a plurality of lower wire portions separated from each other, and the at least one upper wire portion is a plurality of upper wire portions separated from each other The lower wire portions are alternately arranged with the upper wire portions and connected in series to the peripheral wires. The flexible pixel array substrate of claim 4, wherein the lower wire portion has a non-linear portion. The flexible pixel array substrate of claim 6, wherein the upper wire portion has a non-linear portion. The flexible pixel array substrate according to claim 7, wherein the non-linear portion of the upper lead portion overlaps with the non-linear portion of the lower lead portion, and the non-linear portion of the upper lead portion is filled with the non-linear portion The contact openings of the first organic insulating layer are electrically connected to the non-linear portion of the lower lead portion. The flexible pixel array substrate of claim 4, wherein the flexible substrate has a first side and a second side, and the peripheral traces are included on the first side n peripheral traces sequentially arranged in the direction of the second side, wherein the first perimeter trace closest to the first side and the n-th perimeter closest to the second side Each of the lines has a non-linear portion, and the peripheral traces between the first peripheral trace and the n-th peripheral trace are linear. The flexible pixel array substrate of claim 9, wherein a maximum line width of the non-linear portion of the first peripheral trace and a maximum line width of the non-linear portion of the n-th peripheral trace are large And a maximum line width of the peripheral traces in a portion between the first peripheral trace and the n-th peripheral trace. The flexible pixel array substrate of claim 9, wherein the lower lead portion of the first peripheral trace has two first contacts with the upper lead portion of the first peripheral trace a contact point, a vertical projection of the non-linear portion of the lower lead portion of the first peripheral trace on the flexible substrate is located at the first a contact point between the two vertical projection lines on the flexible substrate and the first side; the lower lead portion of the nth peripheral trace has the upper lead portion of the n-th circumference And a second vertical contact point of the contact, the vertical projection of the non-linear portion of the lower-layer lead portion of the n-th peripheral trace on the flexible substrate is located at two vertical projections of the second contact points on the flexible substrate Between the line and the second side. The flexible pixel array substrate of claim 4, wherein the lower layer trace is in contact with the flexible substrate. The flexible pixel array substrate of claim 4, further comprising: a plurality of third inorganic insulating patterns separated from each other and disposed on the peripheral region of the flexible substrate; and a plurality of fourth inorganic The insulating patterns are separated from each other and disposed on the third inorganic insulating patterns, wherein the lower conductive portions of each of the peripheral traces are respectively disposed on the fourth inorganic insulating patterns. A flexible pixel array substrate comprising: a flexible substrate having an active region and a peripheral region outside the active region; a plurality of signal lines disposed on the flexible substrate; a plurality of thin film transistors arranged in an array The plurality of pixel electrodes are electrically connected to the thin film transistors; and a plurality of peripheral traces are disposed on the flexible substrate. The peripheral region is electrically connected to the thin film transistors, wherein The flexible substrate has two opposite first sides and a second side, and the peripheral traces include n peripheral traces sequentially arranged in a direction in which the first side faces the second side The first perimeter trace closest to the first side and the nth perimeter trace closest to the second side have non-linear portions, and the first perimeter trace and the The peripheral traces between the n-th perimeter traces are linear. The flexible pixel array substrate of claim 14, further comprising: a first organic insulating layer covering the thin film transistors and the peripheral region of the flexible substrate, wherein each of the peripheral regions The wire includes: at least one lower wire portion disposed on the flexible substrate, the first organic insulating layer covering the lower wire portion and having a plurality of contact openings exposing the lower wire portion; and at least one upper wire portion configured The contact openings of the first organic insulating layer are filled in the first organic insulating layer to be electrically connected to the upper conductive portions. The flexible pixel array substrate of claim 15, wherein the lower lead portion of the first peripheral trace closest to the first side and the nth closest to the second side The lower lead portions of the peripheral traces of the strips each have a non-linear portion, and the lower lead portions of the peripheral traces located at an intermediate portion between the first peripheral trace and the n-th peripheral trace are linear . The flexible pixel array substrate of claim 15, wherein a maximum line width of the first peripheral trace and the non-linear portion of the n-th peripheral trace is larger than the intermediate portion The maximum line width of the surrounding traces. The flexible pixel array substrate of claim 15, wherein the lower lead portion of the first peripheral trace has two first contacts with the upper lead portion of the first peripheral trace a contact point, a vertical projection of the non-linear portion of the lower wire portion of the first peripheral trace on the flexible substrate is located at a line connecting the two vertical projections of the first contact points on the flexible substrate and the Between the first side; the lower lead portion of the nth peripheral trace has two second contact points in contact with the upper lead portion of the nth peripheral trace, and the nth peripheral trace A vertical projection of the non-linear portion of the lower wire portion on the flexible substrate is between a line connecting the two vertical projections of the second contact points on the flexible substrate and the second side. The flexible pixel array substrate of claim 15, wherein the at least one lower wire portion is a plurality of lower wire portions separated from each other, and the at least one upper wire portion is a plurality of upper wire portions separated from each other The lower wire portions are alternately arranged with the upper wire portions and connected in series to the peripheral wires. The flexible pixel array substrate of claim 15, wherein the lower wire portion and the upper wire portion each have a non-linear portion, the non-linear portion of the upper wire portion and the non-linear portion of the lower wire portion The portions overlap, and the non-linear portion of the upper lead portion is filled in the contact openings of the first organic insulating layer to be electrically connected to the non-linear portion of the lower lead portion. A flexible display panel comprising: The flexible pixel array substrate according to any one of claims 1 to 20, wherein the pair of substrates are disposed opposite to the flexible pixel array substrate; and a display medium disposed on the substrate Between the flexible pixel array substrate and the opposite substrate.