TWI616977B - Semiconductor device and method of manufacturing same - Google Patents

Abstract

In a method of manufacturing a semiconductor device, a dielectric layer is formed on a substrate. A first pattern and a second pattern are formed in the first dielectric layer. The first pattern has a width greater than a width of the second pattern. A first metal layer is formed in the first pattern and the second pattern. A second metal layer is formed in the first pattern. A planarization operation is performed on the first metal layer and the second metal layer, so that the first pattern forms a first metal wiring and the second pattern forms a second metal wiring. A metal material of the first metal layer is different from a metal material of the second metal layer. The first metal wiring includes the first metal layer and the second metal layer, and the second metal wiring includes the first metal layer but does not include the second metal layer.

Description

Semiconductor device and manufacturing method thereof

The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor device having an air gap between metal wirings and a method for manufacturing the same.

As the semiconductor industry has introduced several generations of integrated circuits with better performance and more functions, it has adopted a multi-layer metal wiring structure structure that is placed above electronic devices such as transistors. . In order to comply with faster speeds and better reliability, advanced metal wiring formation methods have been developed.

In some embodiments, the present disclosure provides a method for manufacturing a semiconductor device, including: forming a dielectric layer on a substrate; forming a first pattern and a second pattern in the first dielectric layer; A pattern having a width greater than a width of the second pattern; forming a first metal layer in the first pattern and the second pattern; forming a second metal layer in the first pattern; and in the first A planarization operation is performed on a metal layer and the second metal layer, so that the first pattern forms a first metal wiring and the second pattern forms a second metal wiring, wherein one of the first metal layers The metal material is different from one of the second metal layers, and the first metal wiring includes the first metal layer and the A second metal layer, and the second metal wiring includes the first metal layer but does not include the second metal layer.

In other embodiments, the present disclosure provides a semiconductor device including: a first metal wiring and a second metal wiring formed in a same interlayer dielectric layer disposed on a substrate, the first metal wiring and The second metal wiring is disposed in the same wiring layer within the interlayer dielectric layer, wherein the first metal wiring includes at least one first metal layer made of a first metal material, but does not include the Any metal layer made of a second metal material; and the first metal material is different from the second metal material.

In other embodiments, the present disclosure provides a semiconductor device including: a first metal wiring and a second metal wiring formed in a same interlayer dielectric layer disposed on a substrate, the first metal wiring and The second metal wiring is disposed in the same wiring layer located in the interlayer dielectric layer, wherein the first metal wiring includes a layered structure having more than one conductive layer, and the second metal wiring includes one or more The layered structure of the conductive layers is different from the layered structure of the first metal wiring.

1‧‧‧ substrate

5‧‧‧ structure below

7A‧‧‧ conductive pattern below

7B‧‧‧ conductive pattern below

10‧‧‧ Interlayer dielectric layer

10A‧‧‧Interlayer dielectric layer

10B‧‧‧Interlayer dielectric layer

12‧‧‧ Etch stop layer

15A‧‧‧notch

15B‧‧‧ Notch

15C‧‧‧Notch

16A‧‧‧Interstitial hole

16B‧‧‧Interstitial hole

16C‧‧‧Interstitial hole

17A‧‧‧First mesoporous hole

17B‧‧‧Second mesoscopic hole

20‧‧‧ barrier layer

30‧‧‧ first metal layer

35‧‧‧Gap or hole

40‧‧‧Second metal layer

45‧‧‧Disc effect

A‧‧‧Metal wiring film

B‧‧‧ interlayer film

Wa‧‧‧Width

Wb‧‧‧Width

Wc‧‧‧Width

Wc’‧‧‧Width

Wd‧‧‧Width

Wd’‧‧‧Width

We‧‧‧ width

Ws‧‧‧Width

Da‧‧‧ Depth

Da’‧‧‧ depth

Db‧‧‧ Depth

Dc‧‧‧ Depth

Dc’‧‧‧ depth

Dd‧‧‧Disc

T1‧‧‧thickness

T2‧‧‧thickness

T3‧‧‧thickness

M1‧‧‧Metal wiring

M1A‧‧‧First metal wiring

M1B‧‧‧Second metal wiring

HT‧‧‧Heat treatment

VA‧‧‧ interposer plug

VB‧‧‧ interposer plug

Figures 1, 2A-2B, and 3-7 show an exemplary continuous process of fabricating a metal wiring structure for a semiconductor device according to one embodiment of the present disclosure; Figures 8-9 show another one according to the present disclosure. Example cross-sectional view of one example of a continuous process for making a metal wiring structure for a semiconductor device; FIGS. 10A-10B and 11-15 show a method for making a semiconductor device according to another embodiment of the present disclosure. An exemplary continuous process of a metal wiring structure; 16A-16B and 17-21 illustrate an exemplary continuous process of fabricating a metal wiring structure for a semiconductor device according to another embodiment of the present disclosure.

Many different embodiments or examples are provided for the following disclosure to implement different features of the present application. The following disclosure describes specific examples of each component and its arrangement to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if this disclosure describes a first feature formed on or above a second feature, it means that it may include an embodiment where the first feature is in direct contact with the second feature, or it may include additional The feature is an embodiment in which the feature is formed between the first feature and the second feature, and the first feature and the second feature may not be in direct contact. In addition, different examples of the following disclosures may reuse the same reference symbols and / or marks. These repetitions are for simplicity and clarity, and are not intended to limit the specific relationship between the different embodiments and / or structures discussed.

Furthermore, in order to conveniently describe the relationship between one element or feature in the drawing and another (plural) element or (plural) feature, spatially related terms such as "below", "below", "Lower", "upper", "upper" and similar terms. In addition to the orientation shown in the drawings, space-related terms are used to cover different orientations of the device in use or operation. The device may also be otherwise positioned (eg, rotated 90 degrees or at other orientations), and the description of the spatially related terms used may be interpreted accordingly. Furthermore, the description of "made of" can be interpreted as meaning "including" or "consisting of".

1-7 illustrate an exemplary continuous process for fabricating a metal wiring structure for a semiconductor device according to an embodiment of the present disclosure. On pages 1-7 In the figure, a continuous process of manufacturing one of several metal wiring film layers A (wiring layers) formed on a substrate is illustrated. Although the core structure of a semiconductor device, such as several transistors or other elements (such as contacts), is stored between the substrate and the metal wiring film layer, for simplicity, this is omitted in Figures 1-7. These are detailed drawings of the structures below. Metal wirings are a number of conductive patterns extending laterally within a metal wiring layer, and may be referred to as an interconnection or an interconnect metal layer.

As shown in FIG. 1, an interlayer dielectric layer 10 is formed on the lower structure 5 disposed on the substrate 1. An interlayer dielectric layer can be referred to as an inter-metal dielectric layer. The interlayer dielectric layer 10 is made of one or more film layers of low-k dielectric material. Low dielectric constant dielectric materials have a k value (dielectric constant value) below about 4.0. A portion of the low-k dielectric material has a k value below about 3.5 and may have a k value below about 2.5.

The material of the interlayer dielectric layer 10 may include compounds including silicon, oxygen, carbon, and / or hydrogen, such as SiCOH and SiCO. The interlayer dielectric layer 10 may use an organic material such as a polymer. In some embodiments, the interlayer dielectric layer 10 may be made of a carbon-containing material, an organo-silicate glass, a porogen-containing material, and / or a combination thereof. One or more layers. In some embodiments, the interlayer dielectric layer 10 may also include nitrogen. The interlayer dielectric layer 10 may be a porous film layer. In one embodiment, the density of the interlayer dielectric layer 10 may be less than about 3 grams / cubic centimeter, and in other embodiments may be less than about 2.5 grams / cubic centimeter. The interlayer dielectric layer 10 can be formed by using, for example, plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), atomic layer chemistry Vapor deposition (ALCVD), and / or spin-coating techniques. In the case of plasma enhanced chemical vapor deposition (PECVD), the thin film can be deposited at a substrate temperature between about 25 ° C. and about 400 ° C. and a pressure of less than 100 Torr.

In some embodiments, the interlayer dielectric layer 10 includes an inter-layer insulating film and a wiring inter-wire insulating film, so that the metal wiring can be mainly formed on the metal interlayer insulating layer ( inter-metal insulating film). The interlayer insulating layer may include a SiOC film, and the wiring interlayer insulating layer may include a TEOS (tetraethoxysilane) film.

As shown in FIGS. 2A and 2B, one or more first notches 15A and second notches 15B are formed in the interlayer dielectric layer 10 through a patterning operation including a lithography and etching process. FIG. 2A is an upper view (plan view), and FIG. 2B is a cross-sectional view taken along line X1-X1 in FIG. 2A.

In some embodiments, an etch stop layer 12 may be used, so that the bottoms of the notches 15A and 15B can be defined. In this case, the interlayer dielectric layer 10 may include an etch stop layer 12 disposed between the lower interlayer dielectric layer 10A and the upper interlayer dielectric layer 10B. The materials of the lower interlayer dielectric layer 10A and the upper interlayer dielectric layer 10B may be the same or different. If an etch stop layer is not used, the depth of the notch can be controlled by controlling the etching time or the etching rate of the notch etching. In the following description, the upper portion of the interlayer dielectric layer 10 will be referred to as the upper interlayer dielectric layer 10B and the lower portion of the interlayer dielectric layer 10 will be referred to as the lower interlayer dielectric layer 10A, regardless of the presence or absence of the etch stop layer 12 .

As shown in FIGS. 2A and 2B, the first recess 15A has a width Wa that is greater than a width Wb of one of the second recesses 15B. In one embodiment, the width Wa is greater than about 40 nanometers and less than about 100 microns, and width Wb is in the range of about 40 nanometers to about 5 nanometers. In other embodiments, the width Wa is greater than about 60 nm and the width Wb is in a range from about 30 nm to 10 nm. As shown in FIG. 2A, these notches 15A and 15B correspond to metal wirings, and generally have the shape of long extension wires. The width is defined as a direction perpendicular to one of the extending directions of the metal wiring (notch).

In other embodiments, the depth Da of the first notch 15A is in a range of about 40 nm to about 100 nm, and in other embodiments is about 50 nm to about 80 nm. Within a range. The depth Db of the second notch 15B is substantially the same as or slightly smaller than the depth Da.

The aspect ratio (depth / width) of the first notch 15A is less than about 1, and the aspect ratio of the second notch 15B is in a range of about 1 to about 10.

As shown in FIG. 3, a barrier layer 20 is formed in the notch and on the interlayer dielectric layer 10. The barrier layer 20 is made of a transition metal nitride such as tantalum nitride (TaN) or titanium nitride (TiN). In some embodiments, the thickness of the barrier layer 20 is in a range of about 1 nm to 3 nm, while in other embodiments, it is in a range of about 1.5 nm to 2.5 nm. The barrier layer may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or plating such as electrodeless plating.

Next, a first metal layer 30 is formed on the barrier layer 20. The first metal layer 30 is made of one or more of copper (Cu), cobalt (Co), aluminum (Al), ruthenium (Ru), and silver (Ag). The first metal layer 30 may be formed by atomic layer deposition, physical vapor deposition, or chemical vapor deposition. First metal on interlayer dielectric layer 10 The thickness T1 of the layer is about 50% or more and about 100% or less of the width Wb of the second notch 15B, and is less than about 40 nm.

As shown in FIG. 3, by this metal layer forming operation, the second recess 15B is substantially filled by the first metal layer 30, and at this time, the first recess 15A is not the first metal layer 30. Fill in all.

Next, as shown in FIG. 4, a second metal layer 40 is formed on the first metal layer 30. The second metal layer 40 is made of one or more of copper, cobalt, aluminum, ruthenium, and gold, and is made of a material different from that of the first metal layer 30. The second metal layer 40 may be formed by physical vapor deposition, chemical vapor deposition, or electroplating. The thickness T2 of the second metal layer on the upper surface of the interlayer dielectric layer 10 is about 50% or more of the width Wa of the first recess 15A and less than about 1000 nanometers. In some embodiments, T2 is in the range of about 150 nanometers to about 1000 nanometers.

The second metal layer 40 is made of a material different from that of the first metal layer 30. For example, when the first metal layer 30 is made of cobalt, the second metal layer 40 is made of copper, aluminum, or gold, and when the first metal layer 30 is made of copper, the second The metal layer 40 is made of cobalt, aluminum, or gold. In one embodiment, the first metal layer 30 is made of cobalt, and the second metal layer 30 is made of copper. Through the operation of forming these metal layers, the first recess 15A can be substantially filled by the first metal layer 30 and the second metal layer 40.

After the second metal layer 30 is formed, a planarization operation such as a chemical mechanical polishing (CMP) operation is performed. In this embodiment, the planarization operation includes three chemical mechanical polishing operations.

As shown in FIG. 5, the second metal layer 40 is partially removed by the first chemical mechanical polishing operation. In some embodiments, the The remaining thickness T3 of the second metal layer 40 on the upper surface is in a range of about 80 nm to 120 nm. The first chemical mechanical polishing operation is performed at a relatively high polishing removal rate.

As shown in FIG. 6, a second chemical mechanical polishing operation is performed to partially remove the second metal layer 40 and the first metal layer 30, and the chemical mechanical polishing is stopped on the upper surface of the interlayer dielectric layer 10. 20 barrier layers. The second chemical mechanical polishing operation is performed at a relatively low polishing removal rate.

Compared with the first metal layer 30, the first polishing slurry used in the first chemical mechanical polishing has a polishing removal rate selection ratio of about 2 or more for the second metal layer 40. Compared to the second metal layer 40, the second polishing slurry used in the second chemical mechanical polishing has a polishing removal rate selection ratio of about 2 or more. The polishing removal rate selection ratio of the polishing slurry can be controlled by adjusting the type of the polishing particles, the pH value, the type of the surfactant, the type of the resist, and the chelating agent and the accelerator.

In the second chemical mechanical polishing operation, after the first metal layer 30 is exposed, the polishing removal rate of the second metal layer 40 is less than that of the first metal layer 30. As such, even if the first recess 15A has a wider pattern width, the dishing effect 45 of the second metal layer 40 can be reduced. In one embodiment, the amount of dishing Dd measured from the top surface of the barrier layer 20 at the center of the notch 15A filled with metal is in a range of about 10 nm to about 20 nm. .

As shown in FIG. 7, after the second chemical mechanical polishing operation, a third chemical mechanical polishing operation is performed to remove the barrier layer 20 provided on the upper surface of the interlayer dielectric layer 10 and the expectation of obtaining these metal layers. Thickness and flatness. The third polishing slurry used in the third chemical mechanical polishing operation is for the second metal. The layer 40 and the first metal layer 30 have substantially the same polishing removal rate.

Through a third chemical mechanical polishing operation, a first metal wiring M1A and a second metal wiring M1B are formed in a metal film layer stage (same metal film layer stage) disposed in the same interlayer dielectric layer. The first metal wiring M1A includes the barrier layer 20, the first metal layer 30, and the second metal layer 40, and the second metal wiring M1B includes the barrier layer 20 and the first metal layer 30 but does not have the second metal layer 40. In other words, the first metal wiring M1A is different from the second metal M1B, and in particular, the number of conductive layers of the first metal wiring M1A is different from (greater than) the number of conductive layers of the second metal wiring M1B. After forming these metal wirings in a metal layer, a second interlayer dielectric layer is formed on the interlayer dielectric layer 10 and the metal wirings M1A and M1B. The metal wirings M1A and M2A extend laterally in a plan view and are used to electrically connect different components located at different horizontal portions.

As shown in FIG. 3, in the foregoing embodiment, the second recess 15B is substantially completely filled by the first metal layer 30. However, as shown in FIG. 8, in some embodiments, a seam or a void 35 is formed in the second recess 15B. The width Ws of the gap or hole 35 is in a range of about 1 nm to about 5 nm.

As shown in FIG. 8, when a gap and a hole are formed, a heat treatment HT may be performed to remove the gap and the hole. This heat treatment includes a rapid thermal tempering (RTA) operation or a heating operation in a furnace tube. In some embodiments, the rapid thermal tempering is performed in an inert gas (such as argon and or nitrogen) environment at about 200 ° C and about 500 ° C for about 1 minute to about 10 minutes. Furnace tube heating can be performed in an inert gas (such as argon and or nitrogen) environment at a temperature between about 200 ° C and about 500 ° C for about 10 minutes to about 30 minutes. By heat treatment, the first metal layer 30 The internal grains grow to fill the gaps and holes 35.

As shown in FIG. 9, in some embodiments, the heat treatment HT is performed after the second metal layer 40 is formed. This heat treatment HT may be performed between or after these planarization operations. After the first metal layer and the second metal layer are formed, two or more heat treatments may be performed respectively.

10A-15 illustrate an exemplary continuous process of fabricating a metal wiring structure for a semiconductor device according to another embodiment of the present disclosure.

In Figures 10A-15, one of the manufacturing and forming between two metal wiring film layers (levels) or between a metal wiring film layer and a lower structure on a substrate in a vertical direction is shown. Or a continuous process of interposer film layer B (interposer stage). The interposer is a conductive pattern extending vertically in the interposer layer and connecting the lower conductive pattern and an upper conductive pattern. The via is also referred to as a via plug or a contact plug. The same or similar structures, operations, processes, and / or materials described above with respect to Figs. 1-9 can be applied to the following embodiments, and details thereof are omitted for simplicity.

Similar to FIG. 1, an interlayer dielectric layer 10 is formed on the structure 5 disposed below the substrate 1. In this embodiment, an interlayer dielectric layer 10A is formed below the interlayer dielectric layer 10 in FIG. 2B.

As shown in FIGS. 10A and 10B, one or more first via holes 16A and one or more via holes 16B are formed by using a patterning operation including a lithography and etching process. FIG. 10A is an upper view (plan view), and FIG. 10B is a cross-sectional view along line X2-X2 in FIG. 10A.

As shown in FIGS. 10A and 10B, the first via hole 16A is formed in The lower conductive pattern 7A is formed, and the second via hole 16B is formed on the lower conductive pattern 7B. The conductive patterns 7A and 7B below the bottoms of the first via 16A and the second via 16B are exposed, respectively. The lower conductive patterns 7A and 7B may be a conductive pattern located in a lower core structure or a conductive pattern located in a lower metal wiring film layer.

As shown in FIGS. 10A and 10B, the first via hole 16A has a width Wc, which is larger than a width Wd of one of the second via holes 16B. In one embodiment, the width Wc is greater than about 40 nm and less than about 150 nm, and the width Wd is between about 40 nm and about 5 nm. In other embodiments, the width Wc is greater than about 60 nanometers and the width Wd is between about 30 nanometers and about 10 nanometers. As shown in FIG. 10A, the vias 16A and 16B are substantially circular in a plan view. This width is defined as the diameter of a circle. When the size of the first via hole is sufficiently large, the shape of the first via hole is a rounded circle. When the via hole in a design has a rectangle, the via hole forming the interlayer dielectric layer 10A has an oval shape or a rounded rectangular outer shape.

In some embodiments, the depth Dc of the first via hole 16A and the second via hole 16B is in a range from about 40 nm to about 100 nm, while in other embodiments, it is between about 50nm to about 80nm.

The aspect ratio (depth / width) of the first via hole 16A is less than about 1, and the aspect ratio of the second via hole 16B is in a range of about 1 to about 10.

As shown in FIG. 11, similar to FIG. 3, a barrier layer 20 is formed in these recesses and over the interlayer dielectric layer 10A. The barrier layer 20 is made of a transition metal nitride such as tantalum nitride or titanium nitride. In some embodiments, the thickness of the barrier layer 20 is in a range from about 1 nm to about 3 nm, while in other embodiments, Medium is in the range of about 1.5 nm to about 2.5 nm. The barrier layer may be formed by, for example, chemical vapor deposition, physical vapor deposition, atomic layer deposition, or electroplating such as electroless plating.

Next, as shown in FIG. 11, similar to FIG. 3, a first metal layer 30 is formed on the barrier layer 20. The first metal layer 30 may be made of one or more of copper, cobalt, ruthenium, aluminum, and silver. The first metal layer 30 can be made by atomic layer deposition, physical vapor deposition, or chemical vapor deposition. The thickness T1 of the first metal layer on the upper surface of the interlayer dielectric layer 10 is about 50% or more and 100% or less of the width Wd of the second via 16B, and less than about 40 nm .

As shown in FIG. 11, by this metal layer forming operation, the second via hole 16B is generally filled in by the first metal layer 30, and the first via hole 16A is not completely in the first metal layer. Fill in.

Next, as shown in FIG. 12, a second metal layer 40 is formed on the first metal layer 30. The second metal layer 40 is made of copper, cobalt, aluminum, and gold, and is made of a material different from that of the first metal layer 30. The second metal layer 40 may be formed by physical vapor deposition, chemical vapor deposition, or electroplating. The thickness T2 of the second metal layer on the upper surface of the interlayer dielectric layer 10A is about 50% or more of the width Wc of the first via hole 16C and less than about 600 nm. In some embodiments, T2 is in the range of about 100 nanometers to about 600 nanometers. In one embodiment, the first metal layer 30 is made of cobalt, and the second metal layer 40 is made of copper. Through these metal layer forming operations, the first via layer system is substantially completely filled by the first metal layer 30 and the second metal layer 40.

After the second metal layer 40 is formed, a planarization process such as a chemical mechanical polishing operation may be performed. In this embodiment, the planarization operation includes three Chemical mechanical grinding operation.

As shown in FIG. 13, the second metal layer 40 is partially removed by the first chemical mechanical polishing operation. In some embodiments, the remaining thickness T3 of the second metal layer 40 on the upper surface of the interlayer dielectric layer 10A is in a range of about 80 nm to about 120 nm. This first chemical mechanical polishing operation is performed at a relatively high polishing removal rate.

A second CMP operation is then performed to partially remove the second metal layer 40 and the first metal layer 30. As shown in FIG. 14, the chemical mechanical polishing is stopped at the barrier layer 20 located on the upper surface of the interlayer dielectric layer 10A. The second chemical mechanical polishing operation is performed at a relatively low polishing removal rate.

Compared with the first metal layer 30, the first polishing slurry used in the first chemical mechanical polishing has a polishing removal rate selection ratio of about 2 or more for the second metal layer 40. Compared to the second metal layer 40, the second polishing slurry used in the second chemical mechanical polishing has a polishing removal rate selection ratio of about 2 or more.

In the second chemical mechanical polishing operation, after the first metal layer 30 is exposed, the polishing removal rate of the second metal layer 40 is less than that of the first metal layer 30. As such, even if the first via hole 16A has a wider pattern width, the dishing effect 45 of the second metal layer 40 can be reduced. In one embodiment, the amount of dishing Dd measured from the top surface of the barrier layer 20 at the center of the notch 16A filled with metal is in a range of about 10 nm to about 20 nm. .

As shown in FIG. 15, after the second chemical mechanical polishing operation, a third chemical mechanical polishing operation is performed to remove the barrier layer 20 provided on the upper surface of the interlayer dielectric layer 10A to obtain a dielectric plug. Desired thickness and flatness. to The third polishing slurry used in the third chemical mechanical polishing operation has substantially the same polishing removal rate for the second metal layer 40 and the first metal layer 30.

Through a third chemical mechanical polishing operation, a first interposer plug VA and a second interposer plug VB are formed within a layer of interposer film. The first interposer plug VA includes the barrier layer 20, the first metal layer 30, and the second metal layer 40, and the second interposer plug VB includes the barrier layer 20 and the first metal layer 30 but no第二 金属 层 40。 The second metal layer 40. After the interposer plugs are formed in a interposer film layer, a second interlayer dielectric layer is formed on the interlayer dielectric layer 10A and the interposer plugs VA and VB. The interposer plugs VA and VB are used to connect an upper element and a lower element, respectively.

Similar to FIGS. 8 and 9, when a gap or a hole is formed in the first metal layer 30, a heat treatment may be performed to remove the gap and the hole.

16A-21 illustrate an exemplary continuous process of fabricating a metal wiring structure for a semiconductor device according to another embodiment of the present disclosure.

In FIGS. 16A-21, the fabrication of one of a plurality of metal wiring film layers A (wiring layers) and the formation of a plurality of interposer film layers B immediately below one of the plurality of metal wiring film layers are illustrated. One continuous process. Although there is a core structure such as a transistor or other element (such as a contact) that composes a semiconductor device (hereinafter referred to as a lower structure) between the substrate and these metal wiring layers, for the purpose of simplification, These lower structures are omitted in the figure. The same or similar structures, operations, processes, and or materials described above with respect to Figs. 1-15 may be applied to the following embodiments, and details thereof are omitted for simplicity.

Similar to FIG. 1, an interlayer dielectric layer 10 is formed on the structure 5 disposed below the substrate 1.

As shown in FIGS. 16A and 16B, by using a patterning operation including a lithography and etching process to form one or more recesses 15C within the interlayer dielectric layer 10B above the interlayer dielectric layer 10 and one or A plurality of first vias 17A and one or more second vias 17B are located in the lower interlayer dielectric layer 10A. FIG. 16A is a top view (plan view), and FIG. 16B is a cross-sectional view along a line X3-X3 in FIG. 16A.

As shown in FIGS. 16A and 16B, the first via hole 17A is formed on the lower conductive pattern 7A, and the second via hole 17B is formed on the lower conductive pattern 7B. The conductive patterns 7A and 7B below the bottoms of the first via 17A and the second via 17B are exposed, respectively. The lower conductive patterns 7A and 7B may be a conductive pattern located in a lower core structure or a conductive pattern located in a lower metal wiring film layer.

As shown in FIGS. 16A and 16B, the first via hole 17A has a width Wc 'which is larger than a width Wd' of one of the second via holes 17B. In one embodiment, the width Wc 'is greater than about 40 nm, and the width Wd' is between about 40 nm and about 5 nm. The ratio Wc '/ Wd' is less than about 25. In other embodiments, the width Wc 'is greater than about 60 nm, and the width Wd is between about 30 nm and about 10 nm. The notch 15C has a width We which is larger than the width Wd 'of the second via hole 17B. This width We may be equal to or larger than the width Wc 'of the first via hole 17A. Although the first via hole 17A and the second via hole 17B are formed in one of the notches 15C in FIGS. 16A and 16B, the first via hole 17A and the second via hole 17B may be formed in different notches. within.

In some embodiments, the depth Da ′ of the notch 15C is in a range of about 40 nm to about 100 nm, and in other embodiments is about 50 nm. It ranges from one nanometer to about 80 nanometers. In some embodiments, the depth Dc ′ of the first via hole 17A and the second via hole 17B is in a range from about 40 nanometers to about 100 nanometers, and in other embodiments, it is about about 100 nanometers. 50nm to about 80nm.

The aspect ratio (depth / width) of the notch 15C is less than about 1. The aspect ratio (depth / width) of the first via hole 17A is less than about 1, and the aspect ratio of the second via hole 17B is in a range of about 1 to about 10.

As shown in FIG. 17, the barrier layer 20 is formed on the notch 15C, the first via hole 17A and the second via hole 17B, and the interlayer dielectric layer 10B. The barrier layer 20 is made of a transition metal nitride such as tantalum nitride or titanium nitride. In some embodiments, the thickness of the barrier layer 20 is in a range of about 1 nm to about 3 nm, and in other embodiments is in a range of about 1.5 nm to about 2.5 nm. Inside. The barrier layer may be formed by, for example, chemical vapor deposition, physical vapor deposition, atomic layer deposition, or electroplating such as electroless plating.

Next, a first metal layer 30 is formed on the barrier layer 20. The first metal layer 30 may be made of one or more of copper, cobalt, ruthenium, aluminum, and silver. The first metal layer 30 can be made by atomic layer deposition, physical vapor deposition, or chemical vapor deposition. The thickness T1 of the first metal layer on the upper surface of the interlayer dielectric layer 10 is about 50% or more and 100% or less, and less than about 40 nanometers of the width Wd 'of the first interlayer hole 17B. Meter.

As shown in FIG. 17, by this metal layer forming operation, the second interlayer hole 17B is substantially filled by the first metal layer 30, and the recess 15C and the first interlayer hole 17A are not the first The metal layer 30 is completely filled.

Next, as shown in FIG. 18, a second metal layer 40 is formed on the first On the metal layer 30. The second metal layer 40 is made of copper, cobalt, aluminum, and gold, and is made of a material different from that of the first metal layer 30. The second metal layer 40 may be formed by physical vapor deposition, chemical vapor deposition, or electroplating. The thickness T2 of the second metal layer on the top surface of the interlayer dielectric layer 10B is about 50% or more of the width We of the notch 15C and less than about 1000 nm. In some embodiments, T2 is in the range of about 150 nanometers to about 1000 nanometers.

The second metal layer 40 is made of a material different from that of the first metal layer 30. For example, when the first metal layer 30 is made of cobalt and the second metal layer 40 is made of copper, aluminum, or gold, and when the first metal layer 30 is made of copper, the second The metal layer 40 is made of cobalt, aluminum, or gold. In one embodiment, the first metal layer 30 is made of cobalt, and the second metal layer 40 is made of copper. Through these metal layer forming operations, the recess 15C and the first via hole 17A are substantially filled by the first metal layer 30 and the second metal layer 40.

After the second metal layer 40 is formed, a planarization process such as a chemical mechanical polishing operation may be performed. In this embodiment, the planarization operation includes three chemical mechanical polishing operations.

As shown in FIG. 19, the second metal layer 40 is partially removed by the first chemical mechanical polishing operation. In some embodiments, the remaining thickness T3 of the second metal layer 40 on the upper surface of the interlayer dielectric layer 10B is in a range of about 80 nm to about 120 nm. This first chemical mechanical polishing operation is performed at a relatively high polishing removal rate.

As shown in FIG. 19, a second chemical mechanical polishing operation is then performed to partially remove the second metal layer 40 and the first metal layer 30. The chemical mechanical polishing is stopped at the resistance on the surface above the interlayer dielectric layer 10B 20 barriers. second Chemical mechanical polishing operations are performed at relatively low abrasive removal rates.

In the second chemical mechanical polishing operation, after the first metal layer 30 is exposed, the polishing removal rate of the second metal layer 40 is less than that of the first metal layer 30. As such, even if the notch 15C has a wider pattern width, the dishing effect 45 of the second metal layer 40 can be reduced. In one embodiment, the amount of dishing Dd measured from the top surface of the barrier layer 20 at the center of the notch 15C filled with metal is in a range of about 10 nm to about 20 nm. .

As shown in FIG. 21, after the second chemical mechanical polishing operation, a third chemical mechanical polishing operation is performed to remove the barrier layer 20 provided on the upper surface of the interlayer dielectric layer 10B to obtain a dielectric plug. Desirable thickness and flatness. The third polishing slurry used in the third chemical mechanical polishing has substantially the same polishing removal rate for the second metal layer 40 and the first metal layer 30.

Through the third chemical mechanical polishing operation, the metal wiring M1 is formed in a metal layer level, and a first interposer plug VA and a second interposer plug VB are located in this metal film layer. Below the layer is a via layer level. The metal wiring M1 and the first interposer plug VA include the barrier layer 20, the first metal layer 30 and the second metal layer 40, and the second interposer plug VB includes the barrier layer 20 and the first metal Layer 30 but no second metal layer 40. After the metal wirings are formed in a metal layer, a second interlayer dielectric layer is formed on the interlayer dielectric layer 10B, the metal wiring MA and the dielectric plugs VA and VB.

Similar to FIGS. 8 and 9, when a gap or hole is formed in the first metal layer 30, a heat treatment may be performed to remove the gap and hole.

The above-mentioned multiple embodiments are not mutually exclusive, but can be combined with different Examples. Furthermore, the number of patterns (eg, notches, vias, etc.) is not limited to the number shown in the drawing.

The foregoing embodiments and examples provide a number of advantages over today's technology. For example, in this disclosure, due to the use of two different metal layers and two different planarization techniques (chemical mechanical polishing), the dishing effect in a wider pattern can be reduced. Furthermore, the reduction effect can reduce the total loss of the film during chemical mechanical polishing and reduce the polishing time. Furthermore, the contour of the pattern can be improved, thereby improving the manufacturing yield.

It can be understood that not all advantages discussed herein are necessary, and specific advantages are not required in all embodiments and examples, and different advantages may be provided in other embodiments or examples.

According to one object of the present disclosure, in a method for manufacturing a semiconductor device, a dielectric layer is formed on a substrate. A first pattern and a second pattern are formed in the first dielectric layer. The first pattern has a width greater than a width of the second pattern. A first metal layer is formed in the first pattern and the second pattern. A second metal layer is formed in the first pattern. A planarization operation is performed on the first metal layer and the second metal layer, so that the first pattern forms a first metal wiring and the second pattern forms a second metal wiring. A metal material of the first metal layer is different from a metal material of the second metal layer, and the first metal wiring includes the first metal layer and the second metal layer, and the second metal wiring includes the The first metal layer does not include the second metal layer.

According to another object of the present disclosure, a semiconductor device includes a first metal wiring and a second metal wiring formed in a same interlayer dielectric layer disposed on a substrate. The first metal wiring and the second metal wiring are disposed in place In the same wiring layer in the interlayer dielectric layer. The first metal layer includes at least a first metal layer made of a first metal material and a second metal layer made of a second metal material disposed on the first metal layer. The second metal wiring includes at least one first metal layer made of a first metal material, but does not include any metal layer made of the second metal material. The first metal material is different from the second metal material.

According to one object of the present disclosure, a semiconductor device includes a first metal wiring and a second metal wiring formed in a same interlayer dielectric layer disposed on a substrate. The first metal wiring and the second metal wiring are disposed in the same wiring layer located in the interlayer dielectric layer. The first metal wiring includes a layered structure having more than one conductive layer, and the second metal wiring includes a layered structure having one or more conductive layers. The layered structure of the first metal wiring is different from the layered structure of the second metal wiring.

The foregoing text summarizes the features of many embodiments so that those having ordinary skill in the art can better understand the disclosure from various aspects. Those with ordinary knowledge in the technical field should understand that other processes and structures can be easily designed or modified based on this disclosure to achieve the same purpose and / or achieve the same as the embodiments and the like described herein. Advantages. Those of ordinary skill in the art should also understand that these equivalent structures do not depart from the spirit and scope of the invention disclosed herein. Without departing from the spirit and scope of the disclosure, various changes, substitutions, or modifications can be made to the disclosure.

Although the present invention has been disclosed above with several preferred embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make any changes without departing from the spirit and scope of the present invention. And retouching, Therefore, the protection scope of the present invention shall be determined by the scope of the appended patent application.

10‧‧‧ Interlayer dielectric layer

20‧‧‧ barrier layer

30‧‧‧ first metal layer

40‧‧‧Second metal layer

45‧‧‧Disc effect

Dd‧‧‧Disc

Claims (13)

A method for manufacturing a semiconductor device includes: forming a dielectric layer on a substrate; forming a first pattern and a second pattern in the first dielectric layer, the first pattern having one larger than the second pattern One of the widths; forming a first metal layer in the first pattern and the second pattern; forming a second metal layer in the first pattern; and on the first metal layer and the second metal layer A planarization operation is performed, so that the first pattern forms a first metal wiring and the second pattern forms a second metal wiring; wherein a metal material of one of the first metal layers is different from that of the second metal layer. A metal material; and the first metal wiring includes the first metal layer and the second metal layer, the second metal wiring includes the first metal layer but does not include the second metal layer, and the first metal The metal material of the layer includes at least one of cobalt and silver. According to the method for manufacturing a semiconductor device described in item 1 of the scope of patent application, before forming the first metal layer, the method further includes forming a third metal layer within the first pattern and the second pattern and the dielectric layer. One on the top surface. According to the method for manufacturing a semiconductor device described in item 1 of the scope of patent application, after the first metal layer is formed and before the second metal layer is formed, it further includes performing a heat treatment. According to the method for manufacturing a semiconductor device described in item 1 of the scope of patent application, after forming the second metal layer, it further includes performing a heat treatment. A semiconductor device includes a first metal wiring and a second metal wiring formed in the same interlayer dielectric layer provided on a substrate, and the first metal wiring and the second metal wiring are disposed between the layers. Within the same wiring layer in the dielectric layer; wherein the first metal wiring includes at least a first metal layer made of a first metal material and a second metal material disposed over the first metal layer At least one second metal layer made, the second metal wiring includes another first metal layer made of the first metal material, but does not include any metal layer made of the second metal material The first metal material is different from the second metal material, and the first metal material of the first metal layer includes at least one of cobalt and silver. The semiconductor device according to item 5 of the scope of patent application, wherein the first metal wiring further includes a barrier metal made of a third metal material disposed under the first metal layer of the first metal wiring. Layer; and the second metal wiring further includes a barrier metal layer made of a third metal material disposed under the first metal layer of the second metal wiring. The semiconductor device according to item 6 of the application, wherein the third metal material includes one of titanium nitride and tantalum nitride. A semiconductor device includes a first metal wiring and a second metal wiring formed in the same interlayer dielectric layer provided on a substrate, and the first metal wiring and the second metal wiring are disposed between the layers. Within the same wiring layer within the dielectric layer; wherein the first metal wiring includes a layered structure having more than one conductive layer, and the second metal wiring includes a layered junction having one or more conductive layers The layered structure of the first metal wiring is different from the layered structure of the second metal wiring, and at least one conductive layer or more than one conductive layer of the first metal wiring includes at least one of cobalt and silver. The semiconductor device according to item 8 of the scope of patent application, wherein the number of the conductive layers in the first metal wiring is greater than the number of the conductive layers in the second wiring layer. A method for manufacturing a semiconductor device includes: forming a dielectric layer on a substrate; forming a first pattern and a second pattern in the first dielectric layer, the first pattern having one larger than the second pattern One of the widths; forming a first metal layer in the first pattern in the second pattern; forming a second metal layer in the first pattern; and on the first metal layer and the second metal layer A planarization operation is performed, so that the first pattern forms a first metal wiring and the second pattern forms a second metal wiring; wherein a metal material of one of the first metal layers is different from that of the second metal layer. A metal material, the first metal wiring includes the first metal layer and the second metal layer, and the second metal wiring includes the first metal layer but does not include the second metal layer, and wherein the planarization The operations include: a first planarization operation, which has a higher abrasive removal rate for the second metal layer than an abrasive removal rate for the first metal layer; and A second planarization operation is performed after the first planarization operation, and the polishing removal rate of the second metal layer is smaller than that of the first metal layer. The method for manufacturing a semiconductor device according to item 10 of the scope of patent application, wherein the execution of the first planarization operation does not expose the first metal layer. The method for manufacturing a semiconductor device according to item 10 of the scope of patent application, further comprising: before forming the first metal layer, forming a third metal layer within the first pattern and the second pattern and within the first pattern A top surface of a dielectric layer; and the second planarization operation uses the third metal layer disposed on the upper surface of the dielectric layer as an etch stop layer. The method for manufacturing a semiconductor device according to item 12 of the application, wherein the planarization operation includes: performing a third planarization operation after the second planarization operation, and removing the third planarization operation. The third metal layer is disposed on the upper surface of the dielectric layer.