TWI616866B - Driving unit and driving array - Google Patents

Abstract

A driving unit includes a first switching unit, a shift register, and a second switching unit. The shift register has a temporary storage node and an output end, wherein the temporary storage node is configured to temporarily store the shift signal and the temporary storage node is coupled to the control end of the first switching unit. The second switching unit has an input end, an output end and a control end, wherein the input end of the second switch unit receives the first clock signal, the output end of the second switch unit is coupled to the input end of the first switch unit, and the second switch The control terminal of the unit receives a control signal to control whether the second switching unit conducts the first clock signal to the first switching unit.

Description

Drive unit and drive array

The present disclosure relates to a driving unit, and more particularly to a driving unit and a driving array for a display panel having a partial scanning function.

Currently, most of the display panels on the market are driven by the Full Scan method, that is, each time the display panel updates the frame, each scan line is sequentially scanned. However, this full-scan mode does not effectively save power when it comes to special power-saving screens. For example, when only some of the screens of the display panel have to be updated, the full scan mode will continue to update all the scan lines, and the scan lines of the screen portions that do not need to be updated will still be recharged and updated.

Therefore, a concept of Partial Scan is proposed in which only the scanning lines of the display panel having the portion to be updated are charged for updating, and the remaining portions are not charged to maintain the picture of the previous frame time. This can greatly reduce unnecessary power waste.

In order to implement a partial scanning mechanism, one of the techniques disclosed in this document A drive unit is proposed in the surgical aspect. The driving unit includes a first switching unit, a shift register, and a second switching unit. The first switching unit has an input end, an output end, and a control end. The shift register has a temporary storage node and an output end, wherein the temporary storage node is used for temporarily storing the shift signal. The temporary storage node is coupled to the control end of the first switching unit. The second switching unit has an input end, an output end and a control end, wherein the input end of the second switch unit receives the first clock signal, the output end of the second switch unit is coupled to the input end of the first switch unit, and the second switch The control terminal of the unit receives a control signal to control whether the second switching unit conducts the first clock signal to the first switching unit.

Another driving unit is proposed in another technical aspect of the disclosure. The driving unit includes a first switching unit, a shift register, a second switching unit, and a third switching unit. The first switching unit has an input end, an output end, and a control end. The shift register has an input end and a first output end, wherein the input end of the shift register is configured to receive the shift signal. The second switching unit has an input end, an output end and a control end, wherein the input end of the second switch unit receives the first clock signal, and the output end of the second switch unit is coupled to the control end of the first switch unit. The third switching unit has an input end, an output end and a control end, wherein the shift register is triggered according to the shift signal to send the first shift signal to the input end of the third switch unit via the first output end. The output end of the third switching unit is coupled to the control end of the second switching unit. The control terminal of the third switching unit receives a control signal to control whether the third switching unit is turned on to transmit the first shift signal to the control terminal of the second switching unit.

In another technical aspect of the disclosed document, a drive array is proposed. The drive array is used to drive the display panel. The drive array contains multiple drives Moving unit. The plurality of driving units are respectively used to drive a corresponding column of pixels in the display panel. Each of the driving units includes a first switching unit, a shift register, and a second switching unit. The first switching unit has an input end, an output end, and a control end, wherein the output end is coupled to the corresponding column pixel in the display panel. The shift register has a temporary storage node and an output terminal, wherein the temporary storage node is used for temporarily storing the shift signal. The temporary storage node is coupled to the control end of the first switching unit. The second switching unit has an input end, an output end and a control end, wherein the input end of the second switch unit receives the first clock signal, the output end of the second switch unit is coupled to the input end of the first switch unit, and the second switch The control terminal of the unit receives a control signal to control whether the second switching unit conducts the first clock signal to the first switching unit.

Through the disclosure of the drive unit and the drive array of the disclosed document, a novel partial scanning technique has been disclosed to enable the display panel to reduce power consumption.

100‧‧‧Drive array

110‧‧‧ display panel

C1‧‧‧ capacitor

CK1‧‧‧ first clock signal

CK2‧‧‧ second clock signal

CK3‧‧‧ third clock signal

CT1, CT3‧‧‧ first control circuit

CT2, CT4‧‧‧ second control circuit

Ctrl‧‧‧ control signal

D[N-1], D[N], D[N]'‧‧‧ drive units

D[N+1], D[N+2]‧‧‧ drive unit

ENA, ENB‧‧‧ periodic signals

G1~G6‧‧‧ control terminal

G[1]~G[10], G[N-2], G[N-1]‧‧‧ shift signals

G[N], G[N+1], G[N+2]‧‧‧ shift signals

G[K], H[N]‧‧‧ shift signals

I1~I6‧‧‧ input

M1~M20‧‧‧Switch unit

O1~O8‧‧‧ output

P1‧‧‧ temporary node

PH1, PH2‧‧‧ reference voltage input unit

PX[N-1], PX[N], PX[N+1], PX[N+2]‧‧‧ pixels

Q‧‧‧ node

S1~S2‧‧‧ voltage regulator

S1[3]~S1[7], S1[K], S1[N-1]‧‧‧ first scan signal

S1[N], S1[N+1], S1[N+2]‧‧‧ first scan signal

S2[3]~S2[7], S2[K], S2[N-1]‧‧‧ second scan signal

S2[N], S2[N+1], S2[N+2]‧‧‧ second scan signal

SR1, SR2‧‧‧ shift register

T1~T9‧‧‧

VGH‧‧‧reference voltage

VST, G[0]‧‧‧ start signal

XCtrl‧‧‧ voltage control signal

FIG. 1 is a schematic diagram of a driving array and a display panel according to an embodiment of the disclosure.

Figure 2 is a circuit diagram of a driving unit of one embodiment of the present disclosure.

Figure 3 is a timing waveform diagram of a driving unit of one embodiment of the present disclosure.

Figure 4 is a timing waveform diagram of a driving array of one embodiment of the present disclosure.

Figure 5 is a circuit diagram of a driving unit of one embodiment of the present disclosure.

The following detailed description of the embodiments of the present invention is intended to be illustrative of the invention, and is not intended to limit the invention, and the description of structural operation is not intended to limit the order of execution, any The means for re-combining the components, resulting in equal functionality, are within the scope of the present disclosure.

Moreover, the drawings are only for illustrative purposes and are not drawn in their true dimensions. By "electrical connection" or "electrical coupling" as used herein, it may mean that two or more elements are physically or indirectly electrically contacted.

The terms used in the entire specification and the scope of the patent application, unless otherwise specified, generally have the ordinary meaning of each term used in the field, the content disclosed herein, and the particular content. Certain terms used to describe the disclosure are discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art in the description of the disclosure.

Please refer to FIG. 1 . FIG. 1 is a schematic diagram of a driving array 100 and a display panel 110 according to an embodiment of the disclosure. In FIG. 1, the driving array 100 includes multi-level driving units, such as driving units D[N-1], D[N], D[N+1], D[N+2], etc., where N is greater than A positive integer equal to 2. For example, when N is 2, the driving unit D[N-1] is the first-level driving unit D[1], and the driving unit D[N] is the second-level driving unit. D[2], and so on.

The display panel 110 includes a plurality of columns of pixels, such as column pixels PX[N-1], PX[N], PX[N+1], PX[N+2], etc., wherein each column of pixels is driven by a corresponding one level. The unit is driven. For example, the driving unit D[N] is used to drive the corresponding column pixel PX[N], the driving unit D[N+1] is used to drive the corresponding column pixel PX[N+1], and so on. Each column of pixels is composed of a plurality of pixel electrodes, and is driven to emit light according to a scanning signal provided by a corresponding driving unit and a data signal provided by a data circuit (not shown). This is the basic principle of the display panel, and will not be further described herein.

It should be understood that the number of driving units in the driving array 100 and the number of columns of pixels in the display panel 110 can be adjusted according to actual applications, and the disclosure file is not limited. For example, when the resolution of the display panel 110 is 1024×768 pixels, the display panel 110 has 768 columns of pixels (PX[1]~PX[768]), or when the resolution of the display panel 110 is 1920× At 1080 pixels, the display panel 110 has 1080 columns of pixels (PX[1]~PX[1080]). In general, a single driving unit is used to drive a single column of pixels, that is, the number of driving units is equal to the number of columns of pixels. However, the present invention does not limit the number of driving units and the number of columns of pixels must be equal.

In the embodiment of FIG. 1 , the display panel 110 is an active-matrix organic light-emitting diode (AMOLED) panel. In an AMOLED panel, pixels typically require two (or more) scan signals to drive, so in this example, each drive unit in the array 100 is driven (eg, D[N-1], D[N], D[N+1], D[N+2], etc.) respectively generate a first scan signal and a second scan The signals are drawn to drive a respective column of pixels. Specifically, the first stage driving unit D[1] is configured to generate the first scan signal S1[1] and the second scan signal S2[1] to the column pixel PX[1], and the second stage driving unit D[2] For generating the first scan signal S1[2] and the second scan signal S2[2] to the column pixel PX[2], etc., and so on, the Nth stage driving unit D[N] is used to generate the first scan signal S1[N] and second scan signal S2[N] to column pixel PX[N]. It should be noted that the number of scan signals used to drive a column of pixels is adjusted according to the panel type. The present disclosure only uses two scan signals as an example to simplify the description. In practical applications, the number of scan signals driving a single column of pixels may be one. Or more than two.

According to the above example, the driving units of each level (for example, D[N-1], D[N], D[N+1], D[N+2]) share the control signal Ctrl and the voltage stabilization control signal XCtrl, and receive each. The shift signal generated by the driving unit of the previous stage, wherein the control signal Ctrl is inverted from the voltage stabilizing control signal XCtrl. For example, the second stage driving unit D[2] receives the shift signal G[1] generated by the first stage driving unit D[1], and the third stage driving unit D[3] receives the second stage driving unit D [ 2] the generated shift signal G[2], and so on, the Nth stage driving unit D[N] receives the shift signal G[N generated by the (N-1)th stage driving unit D[N-1] -1]. For the first stage driving unit D[1], the received shift signal is the start signal VST(G[0]) provided by the panel wafer (not shown).

In addition, as shown in FIG. 1, the (N-1)th driving unit D[N-1] further receives the third clock signal CK3, the first clock signal CK1, and the periodic signal ENB, and the Nth stage driving unit D [N] receiving the first clock signal CK1, the second clock signal CK2, and the periodic signal ENA, the (N+1)th stage drive The moving unit D[N+1] receives the second clock signal CK2, the third clock signal CK3, and the periodic signal ENB, and the (N+2)th stage driving unit D[N+2] receives the third clock signal CK3 The first clock signal CK1 and the periodic signal ENA are sequentially analogized to know that the (N+3)th stage driving unit D[N+3] receives the first clock signal CK1, the second clock signal CK2, and the periodic signal ENA, The (N+4)th stage driving unit D[N+4] receives the second clock signal CK2, the third clock signal CK3, the periodic signal ENB, and the like.

The pulse waveform of the second clock signal CK2 is substantially similar to the first clock signal CK1, and the time point (falling edge and rising edge) of the pulse of the second clock signal CK2 is one unit behind the first clock signal CK1. time. In an embodiment, if the first clock signal CK1 is delayed by one unit time, it is the second clock signal CK2. Similarly, the second clock signal CK2 is delayed by one unit time, that is, the third clock signal CK3, and the periodic signal ENA is delayed by one unit time, that is, another period signal ENB. In addition, the third clock signal CK3 is delayed by one unit time to return to the first clock signal CK1, and the periodic signal ENB is delayed by one unit time to return to the periodic signal ENA. In the above example, the relationship between the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, the periodic signal ENA, and the periodic signal ENB is merely an example, and the present invention is not limited thereto.

For example, when N is 2, the first-stage driving unit D[1] receives the third clock signal CK3, the first clock signal CK1, and the second period signal ENB; the second-stage driving The unit D[2] receives the first clock signal CK1, the second clock signal CK2 and the first period signal ENA; the third stage driving unit D[3] receives the second clock signal CK2 and the third clock signal CK3 And the second period signal ENB; and the fourth stage driving unit D[4] receives the third clock signal CK3, the first clock signal CK1, the first period signal ENA, and the like.

The first clock signal CK1, the second clock signal CK2, the control signal Ctrl, the voltage stabilization control signal XCtrl, the periodic signal ENA, and the enable signal VST are all generated by the panel wafer. Please refer to Figures 2~3 for the detailed actuation mechanism of each drive unit.

FIG. 2 is a detailed circuit diagram of the driving unit D[N]. In an embodiment, the driving unit D[N] includes a shift register SR1, a first control circuit CT1, a second control circuit CT2, and a reference voltage input unit PH1. The first control circuit CT1 is configured to output a first scan signal S1[N], and the second control circuit CT2 is configured to output a second scan signal S2[N]. It should be understood that the second control circuit CT2 is a selective circuit. When the column pixel PX[N] can be driven only by a single scan signal according to the panel type, the driving unit D[N] does not need to provide the second control circuit. CT2.

Specifically, the first control circuit CT1 controls whether the driving unit D[N] outputs the first scan signal S1[N] according to the control signal Ctrl. The first control circuit CT1 has a first switching unit M1, a second switching unit M2, and a voltage stabilizing element S1. The first switching unit M1 has an input terminal I1, an output terminal O1, and a control terminal G1. The output terminal O1 is coupled to the column of pixels PX[N] of the display panel 110. The second switching unit M2 has an input terminal I2, an output terminal O2 and a control terminal G2. The input terminal I2 receives the first clock signal CK1, the output terminal O2 is coupled to the input terminal I1 of the first switching unit M1, and the control terminal G2 receives The control signal Ctrl controls whether the second switching unit M2 conducts the first clock signal CK1 to the first switching unit M1.

The voltage stabilizing element S1 is connected to the input terminal I1 of the first switching unit M1 and receives the reference voltage VGH for providing stable stability when the potential of the input terminal I1 of the first switching unit M1 floats according to the voltage stabilizing control signal XCtrl. Reference voltage VGH. The reference voltage VGH is a constant voltage source. The voltage stabilizing element S1 is a selective element. In some cases, since the potential of the input terminal I1 of the first switching unit M1 is regarded as fixed and not floating, it is not necessary to provide the voltage stabilizing element S1.

Similar to the first control circuit, the second control circuit CT2 also controls whether the drive unit D[N] outputs the second scan signal S2[N] according to the control signal Ctrl. The second control circuit CT2 has a third switching unit M3, a fourth switching unit M4, and a voltage stabilizing element S2. The third switching unit M3 has an input terminal I3, an output terminal O3, and a control terminal G3. The output terminal O3 and the output terminal O1 are also coupled to the same column of pixels PX[N] of the display panel 110. The fourth switching unit M4 has an input terminal I4, an output terminal O4 and a control terminal G4. The input terminal I4 receives the periodic signal ENA, the output terminal O4 is coupled to the input terminal I3 of the third switching unit, and the control terminal G4 receives the control signal Ctrl. It is controlled whether the fourth switching unit M4 turns on the periodic signal ENA to the third switching unit M3. The voltage stabilizing element S2 is connected to the input terminal I3 of the third switching unit and receives the reference voltage VGH, and outputs the reference voltage VGH to the input terminal I3 of the third switching unit M3 according to the voltage stabilizing control signal XCtrl. The voltage stabilizing element S2 is a selective element similarly to the voltage stabilizing element S1.

The shift register SR1 has a temporary node P1, a switch unit M5, and a switch unit M6, wherein the switch unit M6 is configured to receive the shift signal G[N-1] output by the previous stage drive unit D[N-1], and With switch unit M5 The control terminal, the control terminal G1 of the first switching unit M1, and the control terminal G3 of the third switching unit are connected at the temporary storage node P1. The input end of the switch unit M6 is connected to the control terminal as a one-way switch. The M6 does not necessarily need to be a one-way switch, and may also be a three-terminal component. When the shift signal G[N-1] is generated, the switch unit M6 is turned on to temporarily store the shift signal G[N-1], and further turns on the switch unit M5, the first switch unit M1, and The third switching unit M3. The switch unit M5 receives the first clock signal CK1. Therefore, when the switch unit M5 is turned on, the first clock signal CK1 is triggered to be output through the output terminal O5 of the switch unit M5 as the shift of the next-stage driving unit D[N+1]. Bit signal G[N].

The reference voltage input unit PH1 has switching units M7 to M12 and a capacitor C1. The control end of the switch unit M8 and the output end of the switch unit M9 are electrically connected to the output end of the switch unit M6 of the shift register SR1 (ie, the temporary storage node P1), and the output end of the switch unit M10 and the switch unit M5. The output terminal O5 is electrically connected, the output end of the switch unit M11 is electrically connected to the output end O1 of the first switch unit M1, and the output end of the switch unit M12 is electrically connected to the output end O3 of the third switch unit M3.

The reference voltage input unit PH1 is configured to provide the reference voltage VGH to the shift register SR1, the first switching unit M1, and the third switching unit M3 according to the second clock signal CK2. The control end of the switch unit M7 is connected to the input end as a one-way switch and is configured to receive the second clock signal CK2. The output of the switching unit M7 is connected to the output of the switching unit M8 at the node Q. The control terminals of the switch units M9~M12 are all connected to the node Q to be controlled by the potential of the node Q to be turned on or off. One end of the capacitor C1 is also connected to the node Q. The input terminals of the switch units M8 to M12 and the other end of the capacitor C1 receive the reference voltage VGH. When the switch units M9~M12 are turned on, the reference voltage VGH is turned on to the temporary storage node P1, the output terminal O5, the output terminal O1, and the output terminal O3 through the switch units M9~M12, so that the temporary storage node P1, the output terminal O5, and the output terminal The potentials of O1 and the output terminal O3 are all changed to the potential of the reference voltage VGH.

In one embodiment, each of the above-mentioned switch units M1 M M12 and voltage stabilizing elements S1 and S2 is, for example, an NMOS (n-type MOSFET) switch or a PMOS (p-type MOSFET) switch. For convenience of description, each switch unit will be hereinafter described. M1~M12 are all examples of PMOS switches. The PMOS on relationship is turned on according to the low voltage level signal, and is turned off according to the high voltage level signal.

It should be understood that each driving unit (for example, D[N-1], D[N+1], D[N+2]) has the same circuit structure as the driving unit D[N] illustrated in FIG. . Wherein, in the circuit of the driving unit D[N-1], the switching unit M2 and the switching unit M5 receive the third clock signal CK3, and the switching unit M4 receives the periodic signal ENB; in the driving unit D[N+1] In the circuit, the switch unit M2 and the switch unit M5 receive the second clock signal CK2, and the switch unit M4 receives the periodic signal ENB; and in the circuit of the drive unit D[N+2], the switch unit M2 and the switch unit M5 Receiving the third clock signal CK3, the switching unit M4 receives the periodic signal ENA. Please also refer to Figures 2 and 3.

FIG. 3 is a timing waveform diagram of the driving array 100 of one embodiment of the disclosed document. In the timing waveform diagram of Fig. 3, during the period T1, The drive unit D[N-1] generates a shift signal G[N-1] to the drive unit D[N]. The shift signal G[N-1] is a pulse signal. Therefore, the switching unit M6 of the shift register SR1 of the driving unit D[N] is turned on during the period T1, so that the temporary node P1 temporarily stores the shift signal G. The potential of [N-1].

At the same time, the switching unit M5 of the driving unit D[N] and the first switching unit M1 of the first control circuit CT1 and the third switching unit M3 of the second control circuit CT2 are turned on according to the potential of the temporary node P1. Further, in the period T1, the potential of the temporary node P1 also causes the switching unit M8 of the reference voltage input unit PH1 to be turned on, and the reference voltage VGH enters the node Q of the driving unit D[N]. In this example, the reference voltage VGH is a high voltage level constant voltage source, so the potential of the node Q is boosted to the potential of the reference voltage VGH to turn off the PMOS switch units M9~M12. In addition, the reference voltage VGH can be coupled through the capacitor C1 to assist the potential of the node Q to be stabilized at a high voltage level.

Then, during the time period T2, the first clock signal CK1 and the periodic signal ENA are at a low voltage level and the second clock signal CK2 is at a high voltage level. Therefore, the switching unit M5 of the driving unit D[N] will be at this time. The electric power of the first clock signal CK1 is output at the output terminal O5 as a shift signal G[N]. Among them, as can be seen from FIG. 3, the waveform of the shift signal G[N] is delayed by one unit time from the waveform of the shift signal G[N-1].

In the period T2, the control signal Ctrl is switched from the high voltage level to the low voltage level, and the voltage stabilization control signal XCtrl is switched from the low voltage level to the high voltage level, so the second switching unit M2 of the driving unit D[N] Turning on, the voltage stabilizing element S1 is turned off, so that the first clock signal CK1 passes through the second switching unit M2 and the first switching unit M1 to output the first scanning signal at the output end O1. No. S1[N].

In the embodiment of FIG. 2, the first scan signal S1[N] generated by the second switch unit M2 and the first switch unit M1 is sent to the effective display area of the display panel 110 (Active Area, not shown in the figure And used to drive each pixel in the effective display area. Therefore, the second switching unit M2 and the first switching unit M1 employ a transistor element that has better driving capability and can provide a larger output current. In an embodiment, the second switch unit M2 and the first switch unit M1 use a transistor having a larger component size to achieve a larger output current, that is, the second switch unit M2 and the first switch unit M1. The component size is larger than the component size of the switch unit M5~M12 (as shown in Fig. 2). In another embodiment, the second switching unit M2 and the first switching unit M1 adopt a low temperature poly-silicon (LTPS) architecture transistor, and the second switching unit M2 and the first switching unit are implemented by using a low temperature polysilicon architecture. M1 can provide a large drive current. The present disclosure is not limited to the above manner, and the second switching unit M2 and the first switching unit M1 may adopt other transistor elements.

At the same time, the voltage stabilizing element S2 of the driving unit D[N] is also turned off according to the voltage stabilizing control signal XCtrl, and the fourth switching unit M4 is turned on according to the control signal Ctrl, so that the periodic signal ENA passes through the fourth switching unit M4 and the The three-switch unit M3 outputs a second scan signal S2[N] at the output terminal O3.

In the embodiment of FIG. 2, the second scan signal S2[N] generated by the fourth switch unit M4 and the third switch unit M3 is sent to the effective display area (not shown) of the display panel 110, and used. Drive effectively Each pixel in the area is shown. Therefore, the fourth switching unit M4 and the third switching unit M3 employ a transistor element which has a better driving capability and can provide a larger output current. Similar to the second switch unit M2 and the first switch unit M1, in an embodiment, the component sizes of the fourth switch unit M4 and the third switch unit M3 are larger than the component sizes of the switch units M5-M12 (as shown in FIG. 2). Show). In another embodiment, the fourth switching unit M4 and the third switching unit M3 employ a low temperature polysilicon (LTPS) architecture transistor. The present disclosure is not limited to the above manner, and the fourth switching unit M4 and the third switching unit M3 may employ other transistor elements.

In addition, at the time period T2, there is no input of the shift signal G[N-1], so the switching unit M8 of the driving unit D[N] is turned off, and the potential of the node Q is maintained at the high potential of the previous period (T1). And the reference voltage VGH is coupled through the capacitor C1 to assist the potential of the node Q to be stabilized at a high voltage level, so that the switching units M9 to M12 in the reference voltage input unit PH1 are kept turned off.

In the period T3, the first clock signal CK1 and the periodic signal ENA are at a high voltage level and the second clock signal CK2 is at a low voltage level. Therefore, the switching unit of the reference voltage input unit PH1 of the driving unit D[N] M7 is turned on, and the second clock signal CK2 is turned on to the node Q to further turn on the switch units M9 to M12. Since the switching unit M9 is turned on, the reference voltage VGH is turned on to the temporary node P1, and the switching unit M5, the first switching unit M1, and the third switching unit M3 are turned off. Since the switch units M10~M12 are turned on, the reference voltage VGH will be turned on to the output terminal O5, the output terminal O1, and the output terminal O3, so that the shift signal G[N], the first scan signal S1[N], and the second scan Signal S2[N] stops outputting.

See time period T4. At the time period T4, the previous stage driving unit D[N-1] outputs the shift signal G[N-1] to the driving unit D[N], so the switching unit M6 of the driving unit D[N] is turned on again, further making the switch The unit M5, the first switching unit M1 and the third switching unit M3 are also turned on again. Then, in the period T5, the first clock signal CK1 is at a low voltage level, so the switching unit M5 outputs the first clock signal CK1 as the shift signal G[N].

It should be noted that during the period T5, the control signal Ctrl is at the high voltage level and the voltage stabilization control signal XCtrl is at the low voltage level, so the second switching unit M2 and the fourth switching unit M4 of the driving unit D[N] are both Turning off, and the voltage stabilizing element S1 and the voltage stabilizing element S2 are turned on. When the voltage stabilizing element S1 and the voltage stabilizing element S2 are turned on, the reference voltage VGH passes through the first switching unit M1, and thus the potential of the output terminal O1 of the first switching unit M1 changes to the potential of the reference voltage VGH.

Next, in the period T6, the second clock signal CK2 is at a low voltage level, and the reference voltage input unit PH1 of the driving unit D[N] is actuated to stop the output of the shift signal G[N].

Same as the driving unit D[N], when the shift signal G[N] is generated during the period T2, the driving unit D[N+1] of the next stage is also activated, so as to be according to the second clock signal CK2 in the period T3. A shift signal G[N+1] and a first scan signal S1[N+1] are generated, and a second scan signal S2[N+1] is generated according to the periodic signal ENB. As can be seen from FIG. 3, the waveforms of the shift signal G[N+1], the first scan signal S1[N+1], and the second scan signal S2[N+1] are respectively behind the shift signal G[N ], the waveform of the first scan signal S1 [N] and the second scan signal S2 [N] is one unit time.

In the time period T5, the driving unit D[N+1] is also activated according to the shift signal G[N] generated by the previous stage, so that the shift signal G[N+1 is generated according to the second clock signal CK2 in the period T6. ]. Similarly, since the control signal Ctrl is at the high voltage level during the period T6 and the voltage stabilization control signal XCtrl is at the low voltage level, the driving unit D[N+1] cannot output the first scan signal S1[N+1] and The second scan signal S2[N+1] is as shown in FIG.

It can be seen from the above operation that during the time periods T2 and T3, since the control signal Ctrl is at the low voltage level, the driving units D[N], D[N+1] can generate the respective first scanning signals (S1[N], S1[N+1]) and the second scan signal (S2[N], S2[N+1]), and in the period T5, T6, since the control signal Ctrl is at the high voltage level, the driving unit D[ N] and D[N+1] cannot generate respective first scan signals (S1[N], S1[N+1]) and second scan signals (S2[N], S2[N+1]). Therefore, by adjusting the potential of the control signal Ctrl, it is possible to control whether the driving units of the respective stages drive the corresponding column pixels in the display panel 110.

Referring to FIG. 4, FIG. 4 is a timing waveform diagram of the driving array 100 according to an embodiment of the disclosed document. In Fig. 4, the timing waveform of the clock signal CK1/CK2/CK3 is displayed as a superimposed waveform of the first clock signal CK1, the second clock signal CK2, and the third clock signal CK3, and the timing of the periodic signal ENA/ENB. The waveform is shown as a superimposed waveform of the periodic signals ENA and ENB, and the timing waveform of the shift signal G[K] shows, for example, the shift of the respective output of the first stage driving unit D[1] to, for example, the tenth stage driving unit D[10]. The superimposed waveform of the signals G[1] to G[10], the timing waveform of the first scan signal S1[K] shows, for example, the first-stage driving unit D[1] to, for example, the tenth-level driving unit D[10] respectively superimposes the superimposed waveform of the first scan signal, and the timing waveform of the second scan signal S2[K] displays, for example, the first stage drive unit D[1] to, for example, the tenth stage drive unit D[10] Superimposed waveforms of the respective second scan signals output.

In the embodiment of FIG. 4, the mechanism of each of the driving units is controlled by the foregoing control signal Ctrl, so that the control portion driving unit generates the first scanning signal and the second scanning signal, and suppresses the remaining driving units from generating the first scanning signal. And a second scan signal. For example, in FIG. 4, it is assumed that between the time periods T7 and T9, the driving units D[1] to D[10] are sequentially operated to be based on the corresponding clock signals (the first clock signal CK1, the second time) The pulse signal CK2 or the third clock signal CK3) generates a shift signal G[1]~G[10]. In the period T7 and the period T9, the control signal Ctrl is at the high voltage level and the voltage stabilization control signal XCtrl is at the low voltage level, and in the period T8, the control signal Ctrl is at the low voltage level and the voltage stabilization control signal XCtrl is at the high voltage. Level.

In the period T7 and T9, although the drive units D[1]~D[2], D[8]~D[10] can still generate the shift signals G[1]~G[2], G[8]~ G[10], but because the control signal Ctrl is at a high voltage level, the second switching unit M2 of each of the driving units D[1]~D[2], D[8]~D[10] in the two periods is When the fourth switching unit M4 is turned off, the driving units D[1]~D[2], D[8]~D[10] cannot output the first scanning signals S1[1]~S1[2] and S1[8]. ~S1[10] and the second scan signals S2[1]~S2[2] and S2[8]~S2[10].

In the T8 period, the driving units D[3]~D[7] generate the shift signals G[3]~G[7], and during this period, because the control signal Ctrl is low. The second switching unit M2 and the fourth switching unit M4 of the driving units D[3]~D[7] are turned on, and the driving unit D[3] is respectively based on the second clock signal CK2 and the periodic signal ENB. The first scan signal S1[3] and the second scan signal S2[3] are generated, and the driving unit D[4] generates the first scan signal S1[4] and the second scan according to the third clock signal CK3 and the periodic signal ENA, respectively. The signal S2[4], the driving unit D[5] generates the first scanning signal S1[5] and the second scanning signal S2[5] according to the first clock signal CK1 and the periodic signal ENB, respectively, and the driving unit D[6] respectively The first scan signal S1[6] and the second scan signal S2[6] are generated according to the second clock signal CK2 and the periodic signal ENA, and the driving unit D[7] generates the first according to the third clock signal CK3 and the periodic signal ENB, respectively. A scan signal S1 [7] and a second scan signal S2 [7].

Thereby, the partial driving unit (for example, D[3]~D[7]) can be controlled to generate the first scanning signal (S1[3]~S1[7]) and the second scanning signal (S2[3] through the control signal Ctrl. ]~S2[7]), and some drive units (such as D[1]~D[2], D[8]~D[10]) do not output the first scan signal (S1[1]~S1[2] , S1[8]~S1[10]) and the second scan signal (S2[1]~S2[2], S2[8]~S2[10]). Therefore, the column pixels that need to be updated in the new frame can be updated (for example, the third column pixel PX[3] to the seventh column pixel PX[7] of the corresponding driving unit D[3]~D[7] are updated. The remaining column pixels may not be updated to maintain the picture of the previous frame, so that the power consumption of the display panel 110 can be minimized.

In the present disclosure, the circuit structure of the driving unit D[N] is not limited to the embodiment shown in FIG. Figure 5 is a diagram showing the circuit architecture of the driving unit D[N]' in accordance with another embodiment of the present disclosure. Drive in Figure 5 The cell D[N]' also has a shift register SR2, a first control circuit CT3, a second control circuit CT4, and a reference voltage input unit PH2. The shift register SR2, the first control circuit CT3, the second control circuit CT4, and the reference voltage input unit PH2 in the driving unit D[N]' in FIG. 5 have functions and operations substantially similar to those in the previous FIG. The shift register SR1 of the unit D[N] is similar to the first control circuit CT1, the second control circuit CT2, and the reference voltage input unit PH1.

In this example, the shift register SR2 has switching units M7 to M9. The switch unit M9 is a one-way switch for receiving the previous stage shift signal G[N-1], and the control ends of the switch units M7, M8 are connected to the output end of the switch unit M9 at the temporary storage node P1. The M9 does not necessarily need to be a one-way switch, and may be a three-terminal element as long as the shift signal G[N-1] of the previous stage can be transmitted during a specific period. The switching units M7 and M8 receive the first clock signal CK1 and the periodic signal ENA, respectively. When the switch unit M9 is turned on according to the shift signal G[N-1], the temporary storage node P1 receives the shift signal G[N-1] to turn on the switch units M7 and M8, and triggers the first clock signal CK1 to pass the switch. The unit M7 outputs a shift signal G[N] at the first output terminal O7, and the trigger period signal ENA is output as a shift signal H[N] through the switch unit M8 at the second output terminal O8.

The first control circuit CT3 controls whether or not the driving unit D[N]' outputs the first scan signal S1[N] in accordance with the control signal Ctrl. The first control circuit CT3 has a first switching unit M1, a second switching unit M2, a third switching unit M3, and a voltage stabilizing element S1. The first switching unit M1 has an input terminal I1, an output terminal O1, and a control terminal G1. The input terminal I1 receives the first clock signal CK1, The output terminal O1 is coupled to the column of pixels PX[N] of the display panel 110. The second switching unit M2 has an input terminal I2, an output terminal O2 and a control terminal G2. The input terminal I2 receives the first clock signal CK1, and the output terminal O2 is coupled to the control terminal G2 of the first switching unit.

The third switching unit M3 has an input terminal I3, an output terminal O3, and a control terminal G3. The input terminal I3 receives the shift signal G[N] outputted by the shift register SR2, the output terminal O3 is coupled to the control terminal G2 of the second switch unit M2, and the control terminal G3 receives the control signal Ctrl to control the third switch unit M3. Whether to be turned on to transmit the shift signal G[N] to the control terminal G2 of the second switching unit M2. The voltage stabilizing element S1 is connected to the control terminal G2 of the second switching unit M2 and receives the reference voltage VGH. The voltage stabilizing element S1 outputs the reference voltage VGH to the control terminal G2 of the second switching unit M2 according to the voltage stabilization control signal XCtrl.

Similar to the first control circuit CT3, the second control circuit CT4 also controls whether the drive unit D[N]' outputs the second scan signal S2[N] according to the control signal Ctrl. The second control circuit CT4 has a fourth switching unit M4, a fifth switching unit M5, a sixth switching unit M6, and a voltage stabilizing element S2. The fourth switching unit M4 has an input terminal I4, an output terminal O4, and a control terminal G4. The input terminal I4 receives the periodic signal ENA, and the output terminal O4 is coupled to the column pixel PX[N] of the display panel 110. The fifth switch unit M5 has an input terminal I5, an output terminal O5 and a control terminal G5. The input terminal I5 receives the periodic signal ENA, and the output terminal O5 is coupled to the control terminal G4 of the fourth switching unit.

The sixth switching unit M6 has an input terminal I6, an output terminal O6, and a control terminal G6. The input terminal I6 receives the shift signal H[N] outputted by the shift register SR2, and the output terminal O6 is coupled to the control terminal G5 of the fifth switch unit M5. The control terminal G6 receives the control signal Ctrl to control whether the sixth switching unit M6 is turned on to transmit the shift signal H[N] to the control terminal G5 of the fifth switching unit M5. The voltage stabilizing element S2 is connected to the control terminal G5 of the fifth switching unit M5 and receives the reference voltage VGH. The voltage stabilizing element S2 outputs the reference voltage VGH to the control terminal G5 of the fifth switching unit M5 according to the voltage stabilization control signal XCtrl.

The reference voltage input unit PH2 has switching units M10 to M20. The control end of the switch unit M11 and the output end of the switch unit M10 are electrically connected to the output end of the switch unit M9 of the shift register SR2 (ie, the temporary storage node P1), and the output end of the switch unit M13 and the switch unit M8. The output end (ie, the second output end O8) is electrically connected, and the output end of the switch unit M14 is electrically connected to the output end of the switch unit M7 (ie, the first output end O7), and the output end of the switch unit M15 and the first switch The control terminal G of the unit M1 is electrically connected, and the output terminals of the switch unit M16 and the switch unit M17 are electrically connected to the output end O1 of the first switch unit M1, and the output end of the switch unit M18 and the control end G4 of the fourth switch unit M4. The electrical connection is made, and the output ends of the switch unit M19 and the switch unit M20 are electrically connected to the output end O4 of the fourth switch unit M4.

The reference voltage input unit PH2 is configured to provide the reference voltage VGH to the shift register SR2, the first switching unit M1, and the fourth switching unit M4 according to the second clock signal CK2. The control end of the switch unit M10 is connected to the input end as a one-way switch and is configured to receive the second clock signal CK2. The M10 does not necessarily need to be a one-way switch, and may also be a three-terminal component. The output of the switching unit M10 is connected to the output of the switching unit M11 at the node Q. The control terminals of the switch units M12~M16 and M18~M19 are connected. To node Q, to be controlled by the potential of node Q to be turned on or off, and switch units M17, M20 are controlled by the regulation control signal XCtrl. The input terminals of the switch units M11 to M20 receive the reference voltage VGH. When the switch units M12~M20 are turned on, the reference voltage VGH is turned on to the temporary storage node P1, the output terminal O7, the output terminal O8, the output terminal O1, the control terminal G, the output terminal O, and the control terminal G4 through the switch units M12~M20. The potentials of each of the temporary node P1, the output terminal O7, the output terminal O8, the output terminal O1, the control terminal G, the output terminal O, and the control terminal G4 are all changed to the potential of the reference voltage VGH.

It should be understood that, in this example, each driving unit (for example, D[N-1], D[N+1], D[N+2]) has the same driving unit D as that shown in FIG. 5 [ N]' circuit architecture. Wherein, in the circuit of the driving unit D[N-1], the switching units M1, M2, M7 receive the third clock signal CK3, and the switching units M4, M5, M8 receive the periodic signal ENB; in the driving unit D[N In the circuit of +1], the switching units M1, M2, and M7 receive the second clock signal CK2, and the switching units M4, M5, and M8 receive the periodic signal ENB; and in the circuit of the driving unit D[N+2], The switching units M1, M2, and M7 receive the third clock signal CK3, and the switching units M4, M5, and M8 receive the periodic signal ENA.

In the above embodiment, each of the switching units M1 to M20 in the driving unit D[N]' of FIG. 5 is also described by taking a PMOS switch as an example, and the timing waveform of FIG. 3 is also applicable to the driving unit D of FIG. N]'. For example, in the period T1, the previous stage driving unit D[N-1] generates the shift signal G[N-1] to the driving unit D[N]', so that the switching unit M9 of the shift register SR2 is turned on. The temporary node P1 temporarily stores the potential of the shift signal G[N-1]. According to the temporary node The potential of P1, the switching units M7, M8 are simultaneously turned on, so that the shift signal G[N] and the shift signal H[N] are respectively generated according to the first clock signal CK1 and the periodic signal ENA in the period T2 (not shown) ).

In the time period T2, the control signal Ctrl is switched to the low voltage level, so the switch unit M3 and the switch unit M6 are turned on, so that the shift signals G[N], H[N] pass through the third switch unit M3 and the switch unit M6, respectively. And further turning on the second switching unit M2 and the fifth switching unit M5. At the same time, because the first clock signal CK1 is at a low voltage level, the first clock signal CK1 passes through the second switching unit M2 to the control terminal G1 of the first switching unit M1 to turn on the first switching unit M1. The first switching unit M1 conducts the first clock signal CK1 to the output terminal O1 to output the first scan signal S1[N].

In the embodiment of FIG. 5, the first scan signal S1[N] generated by the first switch unit M1 is sent to an effective display area (not shown) of the display panel 110, and is used to drive the effective display area. Each pixel, therefore, the first switching unit M1 employs a transistor element that has a better driving capability and can provide a larger output current. In one embodiment, the first switching unit M1 uses a transistor having a larger component size (as shown in FIG. 5), and the second switching unit M2 and the first switching unit M1 are compared to the embodiment in FIG. A transistor having a larger component size is used to generate the first scan signal S1[N]. In the embodiment of FIG. 5, only the first switch unit M1 adopts a transistor having a larger component size, which saves space for circuit layout. In another embodiment, the first switching unit M1 employs a low temperature polysilicon (LTPS) architecture transistor. The present disclosure is not limited to the above manner, and the first switching unit M1 may employ other transistor elements.

Similarly, at this time, the periodic signal ENA is also at a low voltage level, so the periodic signal ENA passes through the fifth switching unit M5 to the control terminal G4 of the fourth switching unit M4 to turn on the fourth switching unit M4. The fourth switching unit M4 turns on the periodic signal ENA to the output terminal O4 to output the second scan signal S2[N].

In the embodiment of FIG. 5, the second scan signal S2[N] generated by the fourth switch unit M4 is sent to the effective display area (not shown) of the display panel 110, and is used to drive the effective display area. Each pixel, therefore, the fourth switching unit M4 employs a transistor element that has a better driving capability and can provide a larger output current. In an embodiment, the fourth switch unit M4 uses a transistor having a larger component size (as shown in FIG. 5), and the fourth switch unit M4 and the third switch unit M3 are compared to the embodiment of FIG. A transistor having a larger component size is used to generate the second scan signal S2[N]. In the embodiment of FIG. 5, only the fourth switch unit M4 is a transistor having a larger component size, which saves space for circuit layout. In another embodiment, the fourth switching unit M4 employs a low temperature polysilicon (LTPS) architecture transistor. The present disclosure is not limited to the above manner, and the fourth switching unit M4 may employ other transistor elements.

Then, in the period T3, the first clock signal CK1 and the periodic signal ENA are at a high voltage level and the second clock signal CK2 is at a low voltage level. Therefore, the switching unit M10 is turned on in the reference voltage input unit PH2, so that the second The clock signal CK2 is turned on to the node Q to further turn on the switch units M12~M16, M18~M19. Since the switching unit M12 is turned on, the reference voltage VGH is turned on to the temporary node P1, and the switching units M7, M8 are turned off. and Since the switching units M13 to M14 are turned on, the reference voltage VGH is turned on to the first output terminal O7 and the second output terminal O8, so that the shift signals G[N], H[N] are stopped.

In addition, the switch units M15~M16, M18~M19 respectively conduct the reference voltage VGH to the control terminal G1 and the output terminal O1 of the first switching unit M1 and the control terminal G4 and the output terminal O4 of the fourth switching unit M4, the first switch The unit M1 and the fourth switching unit M4 are closed, and the first scan signal S1[N] and the second scan signal S2[N] are stopped.

It should be noted that, during the period T3, the voltage stabilization control signal XCtrl is at a low voltage level, so the switching unit M17 and the switching unit M20 are turned on to further provide the reference voltage VGH to the output terminal O1 and the output terminal O4, respectively. At the same time, the voltage stabilizing element S1 and the voltage stabilizing element S2 are also turned on according to the voltage stabilizing control signal XCtrl, so that the reference voltage VGH passes through the voltage stabilizing element S1 and the voltage stabilizing element S2 to turn off the second switching unit M2 and the fifth switching unit M5.

Next, please see time period T4. During the period T4, the previous stage shift signal G[N-1] is generated again, and the switching units M7~M9 of the driving unit D[N]' are turned on, and according to the first clock signal CK1 and the periodic signal ENA in the period T5, respectively. The shift signals G[N], H[N] are generated. Because the control signal Ctrl at the time period T5 is at the high voltage level and the voltage stabilization control signal XCtrl is at the low voltage level, the second switching unit M3 and the sixth switching unit M6 are turned off, and the voltage stabilizing elements S1 and S2 are turned on. The second switching unit M2 and the fifth switching unit M5 are also turned off due to the reference voltage VGH supplied from the voltage stabilizing elements S1, S2. At the same time, the switch units M17 and M18 are turned on according to the voltage stabilization control signal XCtrl, so that the potentials of the output terminal O1 and the output terminal O4 are pulled to the reference voltage. The potential of VGH, the first scan signal S1 [N] and the second scan signal S2 [N] cannot be output.

In the period T6, the second clock signal CK2 is at the low voltage level, and the reference voltage input unit PH2 of the driving unit D[N]' is actuated to stop the outputs of the shift signals G[N] and H[N].

As can be seen from the above, the driving unit D[N]' of FIG. 5 can also determine whether to output the first scan signal S1[N] and the second scan signal S2[N] to drive the corresponding column pixel PX according to the control signal Ctrl. N]. Therefore, the driving array 100 constituted by the driving unit D[N]' of Fig. 5 can also realize the partial scanning technique as shown in Fig. 4.

The partial scanning technique of the display panel can be realized by the driving unit and the driving array disclosed in the disclosure document, and because the scanning signal is blocked by the control circuit before being generated, the scanning signal is blocked after the scanning signal is generated. The traditional technology of entering panel pixels further reduces power consumption.

Although the embodiments of the present invention have been disclosed as above, it is not intended to limit the present invention, and any person skilled in the art can make some modifications and retouchings without departing from the spirit and scope of the present invention. The scope is defined as defined in the scope of the patent application.

Claims (12)

A driving unit comprises: a first switching unit having an input end, an output end and a control end; a shift register having a temporary storage node and an output end, wherein the temporary storage node is used for temporarily a shift signal is coupled to the control end of the first switch unit; and a second switch unit has an input end, an output end, and a control end, wherein the second switch unit The input end receives a first clock signal, the output end of the second switch unit is coupled to the input end of the first switch unit, and the control end of the second switch unit receives a control signal to control the first Whether the second switching unit turns on the first clock signal to the first switching unit. The driving unit of claim 1, wherein the control signal received by the second switching unit is fixed at a first level or switched between the first level and a second level, when the control signal is When the first level is fixed, the second switch unit is not turned on. When the control signal is switched from the first level to the second level, the second switch unit turns on the first clock signal to The first switching unit, the output end of the first switching unit outputs a first scan signal. The driving unit of claim 1, further comprising: a voltage stabilizing component connected to the input end of the first switching unit, receiving a reference voltage, and outputting the reference power according to a voltage stabilizing control signal Pressing to the input end of the first switching unit; wherein the regulated control signal is inverted from the control signal. The driving unit of claim 1, wherein the shift register is triggered according to the shift signal to send the first clock signal to the one of the other driving units via the output terminal of the shift register Shift register. The driving unit of claim 1, further comprising: a reference voltage input unit, connected to the temporary storage node of the shift register and the output end and the output end of the first switch unit, according to A second clock signal provides a reference voltage to the shift register and the first switch unit; wherein a time point at which the pulse of the second clock signal is triggered is one unit time behind the first clock signal. The driving unit of claim 1, further comprising: a third switching unit having an input end, an output end, and a control end, wherein the control end of the third switch unit is coupled to the temporary storage node; And a fourth switching unit having an input end, an output end, and a control end, wherein the input end of the fourth switch unit receives a periodic signal, and the output end of the fourth switch unit is coupled to the third The control terminal of the fourth switching unit receives the control signal to control whether the fourth switching unit turns on the periodic signal to the third switch The element outputs a second scan signal to the output end of the third switching unit. A driving unit comprising: a first switching unit having an input end, an output end and a control end, wherein the input end receives a first clock signal; and a shift register has a temporary a storage node and a first output terminal, wherein the temporary storage node is configured to temporarily store a shift signal; a second switch unit has an input end, an output end, and a control end, wherein the second switch unit The input end receives the first clock signal, the output end of the second switch unit is coupled to the control end of the first switch unit; and a third switch unit has an input end, an output end, and a control end The shift register is triggered according to the shift signal to send a first shift signal to the input end of the third switch unit via the first output end, and the output end of the third switch unit is coupled Connected to the control end of the second switch unit, the control end of the third switch unit receives a control signal to control whether the third switch unit is turned on to send the first shift signal to the second switch unit The control End. The driving unit of claim 7, wherein the control signal received by the third switching unit is fixed at a first level or switched between the first level and a second level, when the control signal is When the first level is fixed, the third switching unit is not turned on, and when the control signal is switched from the first level to the second level, the third switching unit sends the first shift signal to The control end of the second switch unit, the second switch The unit turns on the first clock signal to the control end of the first switch unit to turn on the first switch unit, and the output end of the first switch unit outputs a first scan signal. The driving unit of claim 7, further comprising: a voltage stabilizing component connected to the control terminal of the second switching unit and receiving a reference voltage, wherein the voltage stabilizing component outputs the reference voltage according to a voltage stabilizing control signal And to the control end of the second switching unit; wherein the voltage stabilization control signal and the control signal are inverted. The drive unit of claim 7, wherein the shift register further has a second output, the drive unit further comprising: a fourth switch unit having an input end, an output end, and a control end, The input end of the fourth switch unit receives a periodic signal; a fifth switch unit has an input end, an output end, and a control end, wherein the input end of the fifth switch unit receives the periodic signal, the first The output end of the fifth switch unit is coupled to the control end of the fourth switch unit; and a sixth switch unit having an input end, an output end, and a control end, wherein the shift register is based on the shift The signal is triggered to send a second shift signal to the input end of the sixth switch unit via the second output end, the output end of the sixth switch unit being coupled to the control end of the fifth switch unit, The control terminal of the sixth switch unit receives the control signal to control whether the sixth switch unit is turned on to send the second shift signal to the control end of the fifth switch unit; When the fifth switch unit is turned on, the fifth switch unit turns on the periodic clock signal to the control end of the fourth switch unit to turn on the fourth switch unit, and the output end of the fourth switch unit outputs a first Two scan signals. A driving array for driving a display panel, the driving array comprising: a plurality of driving units respectively for driving a corresponding column of pixels in the display panel, the driving units each comprising: a first switching unit having a An input end, an output end and a control end, the output end is coupled to the corresponding column of pixels in the display panel; a shift register has a temporary storage node and an output end, wherein the temporary storage node is used The temporary storage node is coupled to the control end of the first switch unit; and the second switch unit has an input end, an output end, and a control end, wherein the second switch The input end of the unit receives a first clock signal, the output end of the second switch unit is coupled to the input end of the first switch unit, and the control end of the second switch unit receives a control signal to control Whether the second switching unit turns on the first clock signal to the first switching unit. The driving array of claim 11, wherein the control signal received by the second switching unit of each of the plurality of driving units is fixed at a first level or at the first level and a second level between Switching, when the control signal corresponding to one of the plurality of driving units is fixed to the first level, the second switching unit of one of the driving units is not turned on, when one of the driving units When the corresponding control signal is switched from the first level to the second level, the second switching unit of one of the driving units turns on the first clock signal to the first switching unit, the first The output of the switching unit outputs a scan signal to the corresponding column of pixels in the display panel.