TWI616861B - Active matrix liquid crystal display device - Google Patents

Abstract

An active matrix liquid crystal display device includes a plurality of data lines and a plurality of scanning lines forming a matrix. A plurality of sub-pixel units are arranged in the first column of the matrix, and include a first sub-pixel unit and a second sub-pixel unit arranged in the first column. The first sub-pixel unit includes a first transistor and a second transistor, and a control terminal of the first transistor is electrically connected to the first scan line. The control terminal of the second transistor is electrically connected to the second scan line, and the first terminal of the first transistor is electrically connected to the first terminal of the second transistor. The second sub-pixel unit includes a third transistor. The control terminal of the third transistor is electrically connected to the first scan line, and the first terminal of the third transistor and the second terminal of the second transistor are electrically connected to the first data line.

Description

Active matrix liquid crystal display device

This application relates to a display device, and more particularly to a display device with a half source driving (HSD) pixel array.

With the rapid development of display devices, people will use large and small display devices, such as mobile phones and computers, at any time and at any occasion. While using the display device, each time the screen of the display device changes, it will cause different power consumption, and the power consumption directly affects people's more concerns about using the display device.

Various components of the display device are often integrated through precision design to ensure better display effects while reducing power consumption. A large number of scan driving circuits and data driving circuits are required in the display device to drive each pixel in the display device. Compared with the data driving circuit, the cost and power consumption of the scan driving circuit are lower. Therefore, the number of data lines can be reduced through reasonable design, so less data is used to drive the chip, thereby reducing the power consumption of the display device. the goal of.

For example, in the prior art, half-source-driven HSD (Half The left and right adjacent sub pixels of the Source Driving) pixel array share one data line, so that the number of data lines is halved compared to the number of data lines of a conventional display device. Adjacent sub-pixels of the same line are connected to different scan lines, and sub-pixels separated by one sub-pixel in the same line are connected to the same scan line, so that the number of scan lines is doubled compared to the number of scan lines of traditional display devices to reduce Shows the power consumption of the device.

However, the doubling of the number of scan lines reduces the aperture ratio of the display device, which affects the performance of the display device. Moreover, when the pixel array is driven by half source, two adjacent sub pixels are connected to the same data line, and one of the two adjacent sub pixels is carried out through the adjacent sub pixels. Charging results in a difference in the charging rate of each pixel, resulting in bright and dark lines.

Therefore, how to improve the aperture ratio and the bright and dark lines of the half-source-driven pixel array is one of the problems to be improved in this field.

One aspect of this case is to provide a display device including a plurality of data lines, a plurality of scanning lines, and a plurality of sub-pixel units. Multiple scan lines and multiple data lines form a matrix of N columns and M rows, where N and M are positive integers. A plurality of sub-pixel units are arranged in the first column of the matrix and include a first sub-pixel unit and a second sub-pixel unit. The first sub-pixel unit is arranged in a first column and includes a first transistor and a second transistor. The control terminal of the first transistor is electrically connected to a first scan line of the plurality of scan lines. The control terminal of the second transistor is electrically connected to the second scan line of the plurality of scan lines, and the first terminal of the first transistor is electrically connected. At the first end of the second transistor. The second sub-pixel unit is arranged in the first column and includes a third transistor and a fourth transistor. The control terminal of the third transistor is electrically connected to the first scan line, and the first terminal of the third transistor and the second terminal of the second transistor are electrically connected to the first data line of the plurality of data lines.

Therefore, according to the technical aspect of the present case, the embodiments of the present case provide a display device to effectively improve the problems of the aperture ratio of the half-source driven pixel array and the bright and dark lines.

100A, 100B‧‧‧ display panel

200‧‧‧scanning signal wave

SP1, SP2, SP3, SP4, SP5, SP6 ‧‧‧ sub pixel units

P1, P2, P3, P4, P5, P6 ‧‧‧ sub pixel electrodes

G1 ~ GM + 1‧‧‧scan line

D1 ~ DN + 1‧‧‧Data line

G11, G12, G21, G22 ‧‧‧ sub-scan lines

T1, T2, T3, T4, T5, T6, T7, T8, T9‧‧‧ transistors

C1, C2, C3, C4‧‧‧ cycles

VS1, VS2, VS3‧‧‧scan signal

In order to make the above and other objects, features, advantages, and embodiments of the present invention more comprehensible, the description of the drawings is as follows: FIG. 1 is a schematic diagram of a display panel according to some embodiments of the present invention; FIG. 2 is a waveform diagram of a scanning signal wave according to some embodiments of the present invention; and FIG. 3 is a schematic diagram of a display panel according to some embodiments of the present invention.

The following disclosure provides many different embodiments or illustrations to implement different features of the invention. The elements and configurations in the particular example are used in the following discussion to simplify the present disclosure. Any illustrations discussed are for illustrative purposes only and do not in any way limit the scope and meaning of the invention or its illustrations. In addition, the present disclosure may refer to numerical symbols and / or words repeatedly in different examples. For the sake of simplicity and explanation, these repetitions do not themselves specify the relationship between different embodiments and / or configurations in the following discussion.

The terms used throughout the specification and the scope of patent applications, unless otherwise specified, usually have the ordinary meaning of each term used in this field, in the content disclosed here, and in special content. Certain terms used to describe this disclosure are discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art on the description of this disclosure.

As used herein, "coupling" or "connection" can mean that two or more components make direct physical or electrical contact with each other, or indirectly make physical or electrical contact with each other, and "coupling" or " "Connected" may also mean that two or more elements operate or act on each other.

In this article, the terms first, second, third, etc. are used to describe various elements, components, regions, layers, and / or blocks that are understandable. However, these elements, components, regions, layers and / or blocks should not be limited by these terms. These terms are limited to identifying single elements, components, regions, layers, and / or blocks. Therefore, a first element, component, region, layer, and / or block in the following may also be referred to as a second element, component, region, layer, and / or block without departing from the intention of the present invention. As used herein, the term "and / or" includes any combination of one or more of the associated listed items. The "and / or" mentioned in this document refers to any, all or any combination of at least one of the listed elements.

See Figure 1. FIG. 1 is a schematic diagram of a display panel 100A according to some embodiments of the present invention. As shown in FIG. 1, the display panel 100A includes a plurality of data lines D1 to DN + 1 and a plurality of scanning lines. G1 ~ GM + 1 and multiple pixel units. The scanning lines G1 ~ GM + 1 are arranged in the direction of the column, and the data lines D1 ~ DN + 1 are arranged in the direction of the row. Multiple data lines D1 ~ DN + 1 and multiple scan lines G1 ~ GM + 1 form a matrix of M columns and N rows, where N and M are positive integers. Two adjacent sub-pixel units on the same column form a pixel unit. For example, the sub-pixel unit SP1 and the sub-pixel unit SP2 arranged in the same column form a pixel unit, and the sub-pixel unit SP3 and the sub-pixel unit SP4 arranged in the same column form a pixel unit, and the sub-pixels arranged in the same column The unit SP5 and the sub-pixel unit SP6 form a pixel unit, and the rest can be deduced by analogy. As shown in FIG. 1, the sub-pixel unit SP1, the sub-pixel unit SP2, the sub-pixel unit SP3, and the sub-pixel unit SP4 are arranged in the first column, that is, between the scanning line G1 and the scanning line G2. The pixel unit P5 and the sub-pixel unit P6 are arranged in a second column, that is, between the scanning line G2 and the scanning line G3.

As shown in FIG. 1, the sub-pixel unit SP1 includes a transistor T1 and a transistor T2. The control terminal of the transistor T1 is electrically connected to the scanning line G1. One end of the transistor T1 is electrically connected to one end of the transistor T2. The other end of the transistor T1 is electrically connected to the sub-pixel electrode P1. The control terminal of the transistor T2 is electrically connected to the scanning line G2, one end of the transistor T2 is electrically connected to one end of the transistor T1, and the other end of the transistor T2 is connected to the data line D1. The sub-pixel unit SP2 includes a transistor T3. The control terminal of the transistor T3 is electrically connected to the scanning line G1. One end of the transistor T3 is electrically connected to the data line D1. The other end of the transistor T3 is electrically connected to the sub-pixel unit P2. Sexual connection. In some embodiments, one end of the transistor T1 is one end directly connected to the transistor T2. In some embodiments, one end of the transistor T1 and one end of the transistor T2 are directly connected through a wire. The material of the wire, for example, may be metal, Alloy, or transparent conductive material. In some embodiments, when the data voltage transfer between the transistor T1 and the transistor T2 does not need to be conducted through the pixel electrode, the resistance and capacitance load on the transmission path can be reduced.

As shown in FIG. 1, in some embodiments, the display device 100A further includes a sub-scan line G11. The sub-scan line G11 is arranged in a row direction and is coupled to the control end of the scan line G1 and the transistor T1. between. The sub-scan line G11 extends substantially along the row direction from the scan line G1 and is coupled to the control terminal of the transistor T1.

As shown in FIG. 1, the sub-pixel unit SP3 includes a transistor T4 and a transistor T5. The control terminal of the transistor T4 is electrically connected to the scanning line G1. One end of the transistor T4 is electrically connected to one end of the transistor T5. The other end of the transistor T4 is electrically connected to the sub-pixel electrode P3. The control terminal of the transistor T5 is electrically connected to the scanning line G2, one end of the transistor T5 is electrically connected to one end of the transistor T4, and the other end of the transistor T5 is connected to the data line D2. The sub-pixel unit SP4 includes a transistor T6. The control terminal of the transistor T6 is electrically connected to the scanning line G1. One end of the transistor T6 is electrically connected to the data line D2. The other end of the transistor T6 is electrically connected to the sub-pixel unit P4. Sexual connection.

As shown in FIG. 1, in some embodiments, the display device 100A further includes a sub-scan line G12. The sub-scan line G12 is arranged in a row direction and is coupled to the control end of the scan line G1 and the transistor T4. between. The sub-scanning line G12 extends substantially along the row direction from the scanning line G1 and is coupled to the control terminal of the transistor T5.

As shown in FIG. 1, the sub-pixel unit SP5 includes a transistor T7 and a transistor T8, and a control terminal of the transistor T7 is electrically connected to the scanning line. G2, one end of the transistor T7 is electrically connected to one end of the transistor T8, and the other end of the transistor T7 is electrically connected to the sub-pixel electrode P5. The control terminal of the transistor T8 is electrically connected to the scanning line G3, one end of the transistor T8 is electrically connected to one end of the transistor T7, and the other end of the transistor T8 is connected to the data line D1. Sub-pixel unit SP6 includes transistor T9. The control terminal of transistor T9 is electrically connected to scan line G2. One end of transistor T9 is electrically connected to data line D1. The other end of transistor T9 is electrically connected to sub-pixel unit P6. Sexual connection.

As shown in FIG. 1, in some embodiments, the display device 100A further includes a sub-scan line G21, which is arranged in a row direction and coupled to the control end of the scan line G2 and the transistor T7. between. The sub-scanning line G21 extends substantially along the row direction from the scanning line G2 and is coupled to the control terminal of the transistor T8.

In some embodiments of the present case, the scanning lines G1 to GM + 1 are electrically connected to a scanning driver (not shown), and the data lines D1 to DN + 1 are electrically connected to a data driver (not shown). The scan driver outputs a scan signal to the scan lines G1 ~ GM + 1. The data driver outputs the data voltage to the data lines D1 ~ DN + 1.

See Figure 2. FIG. 2 is a waveform diagram of a scanning signal wave 200 according to some embodiments of the present invention. The scan signal VS1 is a scan signal input to the scan line G1, the scan signal VS2 is a scan signal input to the scan line G2, and the scan signal VS3 is a scan signal input to the scan line G3. As shown in Figure 2, the waveform of the scanning signal VS3 is the same as the waveform of the scanning signal VS2, but the pulse signal of the scanning signal VS3 is one cycle later than the pulse signal of the scanning signal VS2.

Please refer to Figure 1 and Figure 2 together. As shown in Figure 2, In the period C1, the scan signals VS1 and VS2 respectively input pulse signals to the scan lines G1 and G2. At this time, the transistor T1 and the transistor T2 are turned on, and the data voltage of the data line D1 is input to the sub-pixel electrode P1 through the transistor T1 and the transistor T2. At the same time, the data voltage of the data line D1 is also input to the sub-pixel electrode P2 through the transistor T3. In the period C1, the sub-pixel electrode P3 and the sub-pixel electrode P4 also receive the data voltage transmitted through the data line D2.

In the period C2, the scanning signals VS1 and VS3 respectively input pulse signals to the scanning lines G1 and G3. At this time, the transistor T3 is turned on, and the data voltage of the data line D1 is input to the sub-pixel electrode P2 through the transistor T3. The transistor T6 is also turned on, and the data voltage of the data line D2 is input to the sub-pixel electrode P4 through the transistor T6.

In the period C3, the scan signal VS2 inputs a pulse signal to the scan line G2. At this time, the transistor T9 is turned on, and the data voltage of the data line D1 is input to the sub-pixel electrode P6 through the transistor T9.

In the period C4, the scan signal VS2 and the scan signal VS3 respectively input a pulse signal to the scan line G2 and the scan line G3. At this time, the transistor T7 and the transistor T8 are turned on, and the data voltage of the data line D1 is input to the sub-pixel electrode P5 through the transistor T7 and the transistor T8.

Please refer to FIG. 3, which is a schematic diagram of a display panel 100B according to some embodiments of the present invention. In the display panel 100A of FIG. 1, the sub-pixel units of two adjacent columns are the same. In the display panel 100B of FIG. 3, the sub-pixel units of two adjacent columns are different. For example, in Figure 1, the sub-pixel unit SP1 arranged in the first column and the sub-pixel unit SP1 arranged in the second column The unit SP5 is the same, and the sub-pixel unit SP2 arranged in the first column is the same as the sub-pixel unit SP6 arranged in the second column. In FIG. 3, the sub-pixel unit SP1 arranged in the first column is different from the adjacent sub-pixel unit SP5 arranged in the second column, and the sub-pixel unit SP2 arranged in the first column and the sub-pixel unit SP2 arranged in the first column are different. Adjacent sub-pixel units SP6 of the two columns are different. The rest and so on. Moreover, in FIG. 3, the sub-pixel unit SP1 arranged in the first column is the same as the non-adjacent sub-pixel unit SP6 arranged in the second column, and the sub-pixel unit SP2 arranged in the first column is the same. The pixel units SP5 which are not adjacent to the children arranged in the second column are the same. And so on

The sub pixel units SP1 to SP4 in the display panel 100B of FIG. 3 are the same as the sub pixel units SP1 to SP4 of the display panel 100A in FIG.

As shown in FIG. 3, the sub-pixel unit SP5 includes a transistor T7. The control terminal of the transistor T7 is electrically connected to the scanning line G2. One end of the transistor T7 is electrically connected to the data line D1. One end is electrically connected to the sub-pixel electrode P5. The sub-pixel unit SP6 includes a transistor T8 and a transistor T9. The control terminal of the transistor T8 is electrically connected to the scanning line G3. One end of the transistor T8 is electrically connected to one end of the transistor T9. The other end of the transistor T8 is electrically connected. Connect to data line D1. The control terminal of the transistor T9 is electrically connected to the scanning line G2, one end of the transistor T9 is electrically connected to one end of the transistor T8, and the other end of the transistor T9 is connected to the sub-pixel electrode P6.

As shown in FIG. 3, in some embodiments, the display device 100B further includes a sub-scan line G22, which is arranged in the row direction and coupled to the control end of the scan line G2 and the transistor T9. between. Subscan The line G22 extends substantially along the row direction from the scanning line G2 and is coupled to the control terminal of the transistor T.

Please refer to Figure 2 and Figure 3 together. As shown in FIG. 2, in the period C1, the scan signals VS1 and VS2 respectively input pulse signals to the scan lines G1 and G2. At this time, the transistor T1 and the transistor T2 are turned on, and the data voltage of the data line D1 is input to the sub-pixel electrode P1 through the transistor T1 and the transistor T2.

In the period C2, the scanning signals VS1 and VS3 respectively input pulse signals to the scanning lines G1 and G3. At this time, the transistor T3 is turned on, and the data voltage of the data line D1 is input to the sub-pixel electrode P2 through the transistor T3.

In the period C3, the scan signal VS2 inputs a pulse signal to the scan line G2. At this time, the transistor T7 is turned on, and the data voltage of the data line D1 is input to the sub-pixel electrode P5 through the transistor T7.

In the period C4, the scan signal VS2 and the scan signal VS3 respectively input a pulse signal to the scan line G2 and the scan line G3. At this time, the transistor T8 and the transistor T9 are turned on, and the data voltage of the data line D1 is input to the sub-pixel electrode P6 through the transistor T8 and the transistor T9.

As described above, in the display panel 100A and the display panel 100B in the embodiment of the present invention, the sub-pixel electrodes in the sub-pixel units do not need to be charged through other sub-pixel units, thereby effectively improving the problem of bright and dark lines. In addition, in the display panel 100A and the display panel 100B in the embodiment of the present invention, the sub-scanning lines are arranged in a row direction, thereby increasing the aperture ratios of the display panel 100A and the display panel 100B.

It can be known from the implementation of the above-mentioned case that the embodiment of the present case provides a display device, and particularly relates to a half-source driving HSD (Half Source Driving) pixel array display device, thereby effectively improving the half-source driving pixel Array aperture ratio and light and dark lines.

In addition, the above-mentioned illustration includes sequential exemplary steps, but the steps need not be performed in the order shown. It is within the scope of this disclosure to perform these steps in different orders. Within the spirit and scope of the embodiments of the present disclosure, these steps may be added, replaced, changed, and / or omitted as appropriate.

Although this case has been disclosed as above in the form of implementation, it is not intended to limit the case. Any person skilled in this art can make various modifications and retouches without departing from the spirit and scope of the case. Therefore, the scope of protection of this case should be considered after The attached application patent shall prevail.

100A‧‧‧Display Panel

SP1, SP2, SP3, SP4, SP5, SP6 ‧‧‧ sub pixel units

P1, P2, P3, P4, P5, P6 ‧‧‧ sub pixel electrodes

G1 ~ GM + 1‧‧‧scan line

D1 ~ DN + 1‧‧‧Data line

G11, G12, G21 ‧‧‧ sub-scan lines

T1 ~ T9‧‧‧Transistors

Claims (9)

An active matrix liquid crystal display device includes: a plurality of data lines; a plurality of scan lines defining a matrix with the data lines; and a plurality of sub-pixel units arranged in a first column of the matrix, including: A first sub-pixel unit arranged in the first column includes: a first transistor, a control terminal of the first transistor is electrically connected to a first scan line among the scan lines; and a A second transistor, a control terminal of the second transistor is electrically connected to a second scan line of the scan lines, and a first terminal of the first transistor is electrically connected to the second transistor A first end of the second subpixel unit arranged in the first column, including: a third transistor, a control terminal of the third transistor is electrically connected to the first scan line, and the A first terminal of the third transistor and a second terminal of the second transistor are electrically connected to a first data line of the data lines; and a third sub-pixel unit is arranged on the first Column and adjacent to the second sub-pixel unit, wherein the third sub-pixel unit includes: A fourth transistor, a control terminal of the fourth transistor is electrically connected to the first scan line; and a fifth transistor, a control terminal of the fifth transistor is electrically connected to the second scan line, A first terminal of one of the fifth transistors is electrically connected to a first terminal of the fourth transistor. The active matrix liquid crystal display device according to claim 1, wherein a second terminal of the first transistor is electrically connected to a first sub-pixel electrode of one of the first sub-pixel units, and the first A second terminal of one of the three transistors is electrically connected to a second sub-pixel electrode of the second sub-pixel unit. The active matrix liquid crystal display device according to claim 1, wherein the scanning lines are arranged in a direction of the columns, the data lines are arranged in a direction of the rows, and the display device further includes A first sub-scan line, the first sub-scan line is disposed in the direction of the rows, and is coupled between the first scan line and the control terminal of the first transistor. The active matrix liquid crystal display device according to item 1 of the claim, further comprising a fourth sub-pixel unit arranged in the first column and adjacent to the third sub-pixel unit, wherein the fourth sub-pixel unit The pixel unit includes: a sixth transistor, a control terminal of the sixth transistor is electrically connected to the first scan line, and a first terminal of the sixth transistor and a first terminal of the fifth transistor The two terminals are electrically connected to a second data line of the data lines. The active matrix liquid crystal display device according to item 4 of the claim, further comprising a second sub-scan line, the second sub-scan line is arranged in the direction of the rows, and is coupled to the first scan line and Between the control terminals of the fourth transistor. The active matrix liquid crystal display device according to item 1 of the claim, further comprising a third sub-pixel unit arranged in a second column of the matrix, wherein the third sub-pixel unit includes: a fourth A crystal, a control terminal of the fourth transistor is electrically connected to the second scan line; and a fifth transistor, a control terminal of the fifth transistor is electrically connected to a third of the scan lines A scan line, and a first terminal of the fourth transistor is electrically connected to a first terminal of the fifth transistor. The active matrix liquid crystal display device according to claim 6, further comprising a sub-scan line arranged in the direction of the rows and coupled to the second scan line and the fourth electric line. Between the control terminals of the crystal. The active matrix liquid crystal display device according to claim 7, further comprising a fourth sub-pixel unit arranged in the second column of the matrix, wherein the fourth sub-pixel unit includes: a sixth A crystal, a control terminal of the sixth transistor is electrically connected to the second scan line, and a first terminal of the sixth transistor and a second terminal of the fifth transistor are electrically connected to the first Data line. The active matrix liquid crystal display device according to item 1 of the claim, further comprising a third sub-pixel unit arranged in a second column of the matrix, wherein the third sub-pixel unit includes: A fourth transistor, a control terminal of the fourth transistor is electrically connected to the second scan line.