TWI614873B - Self-balancing diode device - Google Patents

Abstract

The invention discloses a self-balancing diode device, which includes a substrate, a doped well region, at least one first conductivity type heavily doped fin and at least two second conductivity type heavily doped fins. The doped well region is disposed in the substrate, and the first conductive type heavily doped fin is disposed in the doped well region, is disposed along the first direction, and protrudes from the surface of the substrate. The second conductive type heavily doped fin is disposed in the doped well region and is disposed along the second direction, and the second direction intersects the first direction. The second conductivity type heavily doped fins are respectively located on opposite sides of the first conductivity type heavily doped fin, and protrude from the surface of the substrate. Each second conductivity type heavily doped fin is heavily doped with the first conductivity type. Miscellaneous fins are separated by a fixed distance.

Description

Self-balancing diode device

The invention relates to a diode device, and more particularly to a self-balancing diode device.

With the continuous improvement of integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.), the semiconductor industry has experienced rapid growth. The largest part of the improvement in the accumulation degree comes from the continuous shrinking of the minimum feature size, so that more components can be integrated in a specific area. However, smaller feature sizes may lead to more leakage current scenarios. As the demand for smaller electronic components increases, it is necessary to reduce the leakage current situation of semiconductor components.

With the evolution of semiconductor technology, FinFETs have become an effective solution for reducing leakage current in semiconductor devices. In a fin-type field-effect transistor, its active region includes a drain electrode, a channel region, and a source electrode protruding from the surface of a semiconductor substrate where the fin-type field-effect transistor is located. The active area of the fin-type field effect transistor is a fin-type (fin), and its cross section may be rectangular. In addition, the gate structure of the fin-type field-effect transistor is like an upside-down U, so it surrounds three sides of the active area. In this way, channel control for the gate structure can be enhanced. Therefore, the short channel effect of the conventional planar transistor can be reduced. Therefore, when the fin-type field effect transistor is turned off, its gate structure can better control the channel to reduce leakage current. Semiconductor devices including fin-type field-effect transistors are extremely sensitive to high voltage spikes such as ESD transients. Electrostatic discharge is a rapid discharge situation caused by the accumulation of electrostatic charges between two objects. Since a rapid discharge will cause a relatively large current, electrostatic discharge may destroy the semiconductor device. For example, US Patent Publication No. 200700745736 discloses a semiconductor device including a gate electrode, a first transistor and a second transistor, wherein the first transistor and the second transistor each have a first active Zone and a second active zone. The first active region is vertical to the gate electrode, and the direction of the second active region is inclined to the gate electrode. The first active area and the second active area can increase the mobility of electrons and electric motors. However, in this semiconductor device, no electrostatic discharge (ESD) protection device is installed, and this US patent does not mention ESD protection technology.

Therefore, the present invention proposes a self-balancing diode device in order to solve the problems mentioned above.

The main object of the present invention is to provide a self-balancing diode device, which is used to establish at least two diodes by using at least one first conductivity type heavily doped fin and at least two second conductivity type heavily doped fins. One conductive type heavily doped fin is disposed along the first direction, and the second conductive type heavily doped fin is disposed along the second direction intersecting the first direction, so that these diodes release a uniform electrostatic discharge (ESD) current to reduce Damage to semiconductor devices due to electrostatic discharge.

To achieve the above object, the present invention provides a self-balancing diode device, which includes a substrate, a doped well region, at least one first conductivity type heavily doped fin, and at least two second conductivity type heavily doped fins. And an insulating layer, the substrate is a semiconductor substrate, and the doped well region is a P-type doped well region or an N-type doped well region. The doped well region is disposed in the substrate, and the first conductive type heavily doped fin is disposed in the doped well region, is disposed along the first direction, and protrudes from the surface of the substrate. The second conductive type heavily doped fin is disposed in the doped well region and is disposed along the second direction, and the second direction intersects the first direction. The second conductive type heavily doped fins are located on different sides of the first conductive type heavily doped fin, respectively, and protrude from the surface of the substrate. For example, the second direction is perpendicular to the first direction. Each second conductive type heavily doped fin is separated from the first conductive type heavily doped fin by a fixed distance, and the doped well region, the first conductive type heavily doped fin and the second conductive type heavily doped fin form at least two or two. Polar body. The insulating layer is disposed on the surface of the substrate and is interposed between the first conductive type heavily doped fin and each second conductive type heavily doped fin. The first conductive type heavily doped fin is electrically connected to the first voltage terminal, the second conductive type heavily doped fin is electrically connected to the second voltage terminal, and the voltage of the first voltage terminal and the second voltage terminal is forward biased to the diode. To generate at least two uniform electrostatic discharge (ESD) currents through the diode. When the first conductive type heavily doped fin is an N type heavily doped fin, the second conductive type heavily doped fin is a P type heavily doped fin, and the first voltage terminal and the second voltage terminal are a low voltage terminal and a high voltage terminal, respectively. Voltage terminal. Alternatively, when the first conductive type heavily doped fin is a P type heavily doped fin, the second conductive type heavily doped fin is an N type heavily doped fin, and the first voltage terminal and the second voltage terminal are high voltage terminals, respectively. With low voltage side.

In the first embodiment, the number of the second conductivity type heavily doped fins is greater than two, and the insulating layer is between the adjacent second conductivity type heavily doped fins, and the numbers of the diodes and the electrostatic discharge current are both Greater than two. The plurality of first contact electrodes are disposed on the top and side walls of the first conductive type heavily doped fin and the insulating layer, and are disposed along the second direction, and are electrically connected to the first voltage terminal. Two second contact electrodes are respectively disposed on the top and side walls of the second conductive type heavily doped fin on the opposite two sides of the first conductive type heavily doped fin, and are disposed on the insulating layer, and the second contact electrode is along The first direction is arranged, and the second voltage terminal is electrically connected. The number of the first contact electrodes is equal to the number of the second conductive type heavily doped fins on each side of the first conductive type heavily doped fin.

Compared with the first embodiment, the second embodiment further includes a first heavily doped clamping fin, which is of the same conductivity type as the second conductivity type heavily doped fin. The first heavily doped clamping fin is located in the doped well region and is disposed along the second direction, is separated from the first conductive type heavily doped fin, and protrudes from the surface of the substrate. The first conductivity type heavily doped fin has a first end and a second end, and the first heavily doped clamp fin is adjacent to the first end and the two closest second conductivity type heavily doped fins. The insulating layer is between the first heavily doped clamping fin and its adjacent second conductively doped fin, and between the first heavily doped clamping fin and the first conductively doped fin, The second contact electrode is disposed on the top and the sidewall of the first heavily doped clamping fin.

Compared with the second embodiment, the third embodiment further includes a second heavily doped clamping fin, which belongs to the same conductivity type as the second conductivity type heavily doped fin. The second heavily doped clamping fin is located in the doped well region and is disposed along the second direction, is separated from the first conductive type heavily doped fin, and protrudes from the surface of the substrate. The second heavily doped clamping fin is adjacent to the second end of the second heavily doped clamping fin and is closest to the second conductive doped fin of the second conductivity type. The insulating layer is between the second heavily doped clamping fin and its adjacent second conductive type heavily doped fin, and between the second heavily doped clamping fin and the first conductivity type heavily doped fin, The second contact electrode is disposed on the top and the sidewall of the second heavily doped clamping fin.

In the fourth embodiment, the number of the first conductive type heavily doped fins is plural, the insulating layer is between the adjacent first conductive type heavily doped fins, and the numbers of the diodes and the electrostatic discharge current are both Greater than two. A first contact electrode is disposed on the top and side walls of the first conductive type heavily doped fin and the insulating layer, and is disposed along the second direction, and is electrically connected to the first voltage terminal. The plurality of second contact electrodes are uniformly disposed on the top and side walls of the second conductive type heavily doped fin on the opposite sides of the first conductive type heavily doped fin, and are disposed on the insulating layer and along the first direction. Set, and is electrically connected to the second voltage terminal. The number of the first conductive type heavily doped fins is equal to the number of the second contact electrodes on each side of the first conductive type heavily doped fin.

In order to make the reviewers of the Guigui have a better understanding and understanding of the structural features of the present invention and the effects achieved, I would like to refer to the preferred embodiment diagram and the detailed description, as described below:

The self-balancing diode device of the present invention is used as an electrostatic discharge protection structure required in an integrated circuit. In the electrostatic discharge protection process, an electrostatic discharge protection circuit is formed near the end of the integrated circuit, such as the output terminal and the input terminal, and the power supply terminal. The electrostatic discharge protection circuit provides a current discharge channel to reduce the damage of semiconductor devices caused by electrostatic discharge.

See Figures 1 and 2. The first embodiment of the self-balancing diode device of the present invention is described as follows. The first embodiment includes a substrate 10, a doped well region 12, at least one first conductivity type heavily doped fin 14, at least two second conductivity type heavily doped fins 16, an insulating layer 18, and a plurality of first contacts. The electrode 20 and two second contact electrodes 22. The doped well region 12, the first conductive type heavily doped fin 14 and the second conductive type heavily doped fin 16 form at least two diodes to release at least two uniform electrostatic discharge currents. In the first embodiment, the number of the first conductive type heavily doped fins 14 is one, and the number of the second conductive type heavily doped fins 16, the number of diodes, and the electrostatic discharge current are all greater than two.

The substrate 10 is a semiconductor substrate, and the doped well region 12 is a P-type doped well region or an N-type doped well region. The doped well region 12 is disposed in the substrate 10, and the first conductive type heavily doped fin 14 is disposed in the doped well region 12 and is disposed along the first direction and protrudes from the surface of the substrate 10. The second conductive type heavily doped fin 16 is disposed in the doped well region 12 and is disposed along the second direction, and the second direction intersects the first direction. The second conductive type heavily doped fins 16 are respectively located on two different sides of the first conductive type heavily doped fins 14 and protrude from the surface of the substrate 10. For example, the second direction is perpendicular to the first direction. Each of the second conductive type heavily doped fins 16 is spaced a fixed distance from the first conductive type heavily doped fins 14. The insulating layer 18 is disposed on the surface of the substrate 10 and is interposed between the first conductive type heavily doped fins 14 and each of the second conductive type heavily doped fins 16 and between adjacent second conductive type heavily doped fins 16. Miscellaneous fins 16. The first contact electrode 20 is disposed on the top and side walls of the first conductive type heavily doped fin 14 and the insulating layer 18, and is disposed along the second direction, and is electrically connected to the first voltage terminal V1. The first conductive type heavily doped fin 14 is electrically connected to the first voltage terminal V1 through the first contact electrode 20. The second contact electrode 22 is provided on the top and the side wall of the second conductive type heavily doped fin 16 on the opposite sides of the first conductive type heavily doped fin 14, respectively, and is disposed on the insulating layer 18, and the second The contact electrode 22 is disposed along the first direction and is electrically connected to the second voltage terminal V2. The second conductive type heavily doped fin 16 is electrically connected to the second voltage terminal V2 through the second contact electrode 22. The number of the first contact electrodes 20 is equal to the number of the second conductive type heavily doped fins 16 on each side of the first conductive type heavily doped fin 14.

The voltages at the first voltage terminal V1 and the second voltage terminal V2 forward bias the diodes to generate a uniform electrostatic discharge (ESD) current through the diodes, thereby reducing the damage to the semiconductor device caused by the electrostatic discharge. Therefore, when the first conductive type heavily doped fin 14 is an N type heavily doped fin, the second conductive type heavily doped fin 16 is a P type heavily doped fin, and the first voltage terminal V1 and the second voltage terminal V2 are respectively It is a low voltage terminal and a high voltage terminal. Alternatively, when the first conductive type heavily doped fin 14 is a P type heavily doped fin, the second conductive type heavily doped fin 16 is an N type heavily doped fin, and the first voltage terminal V1 and the second voltage terminal V2 are respectively It is a high voltage terminal and a low voltage terminal.

See Figures 3 and 4. The second embodiment of the self-balancing diode device of the present invention is described as follows. Compared with the first embodiment, the second embodiment further includes a first heavily doped clamp fin 24, which is of the same conductivity type as the second conductivity type heavily doped fin 16. The first heavily doped clamping fin 24 is located in the doped well region 12 and is disposed along the second direction. The first heavily doped clamping fin 24 is separated from the first conductive type heavily doped fin 14 and protrudes from the surface of the substrate 10. The first conductive type heavily doped fin 14 has a first end and a second end, and the first heavily doped clamping fin 24 is adjacent to the first end and the two closest second conductive type heavily doped fins 16. The insulating layer 18 is interposed between the first heavily doped clamp fin 24 and its adjacent second conductivity type heavily doped fin 16, and is interposed between the first heavily doped clamp fin 24 and the first conductivity type heavily doped Between the fins 14, a second contact electrode 22 is provided on the top and the sidewall of the first heavily doped clamp fin 24. The first heavily doped clamp fin 24 is electrically connected to the second voltage terminal V2 through the second contact electrode 22. In the second embodiment, the doped well region 12, the first conductivity type heavily doped fin 14, the second conductivity type heavily doped fin 16, and the first heavily doped clamp fin 24 form a plurality of diodes, so that Discharge a plurality of uniform electrostatic discharge currents to reduce damage to semiconductor devices caused by electrostatic discharge.

See Figures 5 and 6. The third embodiment of the self-balancing diode device of the present invention is described as follows. Compared with the second embodiment, the third embodiment further includes a second heavily doped clamping fin 26 which is of the same conductivity type as the second conductivity type heavily doped fin 16. The second heavily doped clamp 26 fin is located in the doped well region 12 and is disposed along the second direction, and is separated from the first conductive type heavily doped fin 14 and protrudes from the surface of the substrate 10. The second heavily-doped clamp fin 26 is adjacent to the second end and the two closest second-conductivity-type heavily-doped fins 16. The insulating layer 18 is interposed between the second heavily doped clamp fin 26 and its adjacent second conductivity type heavily doped fin 16, and is interposed between the second heavily doped clamp fin 26 and the first conductivity type heavily doped Between the fins 14, a second contact electrode 22 is provided on the top and the sidewall of the second heavily doped clamp fin 26. The second heavily doped clamp fin 26 is electrically connected to the second voltage terminal V2 through the second contact electrode 22. In the third embodiment, the doped well region 12, the first conductivity type heavily doped fin 14, the second conductivity type heavily doped fin 16, the first heavily doped clamp fin 24, and the second heavily doped clamp The fins 26 form a plurality of diodes to release a plurality of uniform electrostatic discharge currents, so as to reduce the damage of the semiconductor device caused by the electrostatic discharge.

See Figures 7 and 8. The fourth embodiment of the self-balancing diode device of the present invention is described as follows. The fourth embodiment includes a substrate 10, a doped well region 12, a plurality of first conductivity type heavily doped fins 14, two second conductivity type heavily doped fins 16, an insulating layer 18, and a first contact electrode 20. And a plurality of second contact electrodes 22. The doped well region 12, the first conductive type heavily doped fin 14 and the second conductive type heavily doped fin 16 form a plurality of diodes to release a plurality of uniform electrostatic discharge currents.

The substrate 10 is a semiconductor substrate, and the doped well region 12 is a P-type doped well region or an N-type doped well region. The doped well region 12 is disposed in the substrate 10, and the first conductive type heavily doped fin 14 is disposed in the doped well region 12 and is disposed along the first direction and protrudes from the surface of the substrate 10. The second conductive type heavily doped fin 16 is disposed in the doped well region 12 and is disposed along the second direction, and the second direction intersects the first direction. The second conductive type heavily doped fins 16 are respectively located on two different sides of the first conductive type heavily doped fins 14 and protrude from the surface of the substrate 10. For example, the second direction is perpendicular to the first direction. Each of the second conductive type heavily doped fins 16 is spaced a fixed distance from the first conductive type heavily doped fins 14. The insulating layer 18 is disposed on the surface of the substrate 10 and is interposed between each of the first conductive type heavily doped fins 14 and each of the second conductive type heavily doped fins 16 and between the adjacent first conductive type Between heavily doped fins 14. The first contact electrode 20 is disposed on the top and side walls of the first conductive type heavily doped fin 14 and the insulating layer 18, and is disposed along the second direction, and is electrically connected to the first voltage terminal V1. The first conductive type heavily doped fin 14 is electrically connected to the first voltage terminal V1 through the first contact electrode 20. The second contact electrode 22 is evenly disposed on the top and side walls of the second conductive type heavily doped fin 16 on the opposite sides of the first conductive type heavily doped fin 14, and is disposed on the insulating layer 18, and the second The contact electrode 22 is disposed along the first direction and is electrically connected to the second voltage terminal V2. The second conductive type heavily doped fin 16 is electrically connected to the second voltage terminal V2 through the second contact electrode 22. The number of the first conductive type heavily doped fins 14 is equal to the number of the second contact electrodes 22 on each side of the first conductive type heavily doped fin 14.

The voltage of the first voltage terminal V1 and the second voltage terminal V2 forwardly biases the diode to generate a uniform electrostatic discharge current through the diode, thereby reducing the damage of the semiconductor device caused by the electrostatic discharge. Therefore, when the first conductive type heavily doped fin 14 is an N type heavily doped fin, the second conductive type heavily doped fin 16 is a P type heavily doped fin, and the first voltage terminal V1 and the second voltage terminal V2 are respectively It is a low voltage terminal and a high voltage terminal. Alternatively, when the first conductive type heavily doped fin 14 is a P type heavily doped fin, the second conductive type heavily doped fin 16 is an N type heavily doped fin, and the first voltage terminal V1 and the second voltage terminal V2 are respectively It is a high voltage terminal and a low voltage terminal.

In summary, the present invention uses the first conductive type heavily doped fin and the second conductive type heavily doped fin to establish a uniform electrostatic discharge current, wherein the first conductive type heavily doped fin is disposed along the first direction, and the second conductive type The heavily doped fins are disposed along a second direction that intersects the first direction to reduce damage to the semiconductor device due to electrostatic discharge.

The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of implementation of the present invention. Therefore, all equivalent changes and modifications in accordance with the shape, structure, characteristics, and spirit described in the scope of the patent application for the present invention are provided. Shall be included in the scope of patent application of the present invention.

10‧‧‧ substrate
12‧‧‧ doped well area
14‧‧‧ The first conductive type heavily doped fin
16‧‧‧Second conductivity type heavily doped fin
18‧‧‧ Insulation
20‧‧‧First contact electrode
22‧‧‧Second contact electrode
24‧‧‧ First heavily doped clamp fin
26‧‧‧Second heavily doped clamp fin

FIG. 1 is a schematic circuit layout diagram of the first embodiment of the self-balancing diode device of the present invention. Fig. 2 is a cross-sectional view of the structure of the self-balancing diode device of the present invention taken along line A-A 'in Fig. 1. FIG. 3 is a schematic circuit layout diagram of the second embodiment of the self-balancing diode device of the present invention. Fig. 4 is a cross-sectional view of the structure of the self-balancing diode device of the present invention taken along line B-B 'of Fig. 3. FIG. 5 is a schematic circuit layout diagram of the third embodiment of the self-balancing diode device of the present invention. Fig. 6 is a cross-sectional view of the structure of the self-balancing diode device of the present invention taken along line C-C 'of Fig. 5. FIG. 7 is a schematic circuit layout diagram of the fourth embodiment of the self-balancing diode device of the present invention. Fig. 8 is a cross-sectional view of the structure of the self-balancing diode device of the present invention taken along line D-D 'of Fig. 7.

10‧‧‧ substrate

14‧‧‧ The first conductive type heavily doped fin

16‧‧‧Second conductivity type heavily doped fin

18‧‧‧ Insulation

20‧‧‧First contact electrode

22‧‧‧Second contact electrode

Claims (8)

A self-balancing diode device includes: a substrate; a doped well region provided in the substrate; at least one first conductivity type heavily doped fin provided in the doped well region and along the The first direction is provided and protrudes from the surface of the substrate; at least two second conductivity type heavily doped fins are provided in the doped well region and are arranged along the second direction, the second direction and the first direction The directions intersect, the second conductive type heavily doped fins are located on different sides of the first conductive type heavily doped fin, respectively, and protrude from the surface of the substrate, and each of the second conductive type heavily doped fins The doping fin is separated from the first conductive type heavily doped fin by a fixed distance, the doped well region, the first conductive type heavily doped fin, and the second conductive type heavily doped fin form at least a diode, The first conductive type heavily doped fins are electrically connected to the first voltage terminal, the second conductive type heavily doped fins are electrically connected to the second voltage terminal, and the voltages of the first voltage terminal and the second voltage terminal are forward. Bias the diodes to generate at least two uniform electrostatic discharge (ESD) currents through the diodes; an insulating layer, which is On the surface of the substrate, between the first conductive type heavily doped fin and each of the second conductive type heavily doped fins, the number of the second conductive type heavily doped fins is greater than two, and The insulating layer is between the adjacent second conductive type heavily doped fins, and the number of the diode and the electrostatic discharge current are greater than two; a plurality of first contact electrodes are provided on the first conductive The top and side walls of the heavily doped fin and the insulating layer are disposed along the second direction and are electrically connected to the first voltage terminal; and two second contact electrodes are respectively disposed on the different two sides. The tops and sidewalls of the second conductive type heavily doped fins are disposed on the insulating layer, and the second contact electrodes It is disposed along the first direction and is electrically connected to the second voltage terminal. The self-balancing diode device according to claim 1, wherein the doped well region is a P-type doped well region or an N-type doped well region. The self-balancing diode device according to claim 1, wherein when the first conductive type heavily doped fins are N type heavily doped fins, the second conductive type heavily doped fins are P type heavily doped Fins, and the first voltage terminal and the second voltage terminal are a low voltage terminal and a high voltage terminal, respectively; when the first conductivity type heavily doped fin is a P type heavily doped fin, the second conductivity type heavily doped The doping fin is an N-type heavily doped fin, and the first voltage terminal and the second voltage terminal are a high voltage terminal and a low voltage terminal, respectively. The self-balancing diode device according to claim 1, wherein the first direction is perpendicular to the second direction. The self-balancing diode device according to claim 1, wherein the number of the first contact electrodes is equal to the second conductively doped fin on each side of the first conductively doped fin. Of quantity. The self-balancing diode device according to claim 1, further comprising a first heavily doped clamp fin, which is of the same conductivity type as the second conductive doped fin, and the first heavily doped clamp The bit fins are located in the doped well region and are disposed along the second direction, and are separated from the first conductive type heavily doped fins, and are raised from the surface of the substrate, the first conductive type heavily doped The fin has a first end and a second end, the first heavily doped clamping fin is adjacent to the first end and the closest two of the second conductive type heavily doped fins, and the insulating layer is interposed between the first heavy Between the doped clamp fin and its adjacent second conductivity type heavily doped fin, and between the first heavily doped clamp fin and the first conductivity type heavily doped fin, the second The contact electrode is disposed on the top and the sidewall of the first heavily doped clamp fin. The self-balancing diode device according to claim 6, further comprising a second heavily doped clamp The fin is of the same conductivity type as the second conductivity type heavily doped fin, and the second heavily doped clamp fin is located in the doped well region and is disposed along the second direction and is in line with the first conductivity type The heavily doped fins are separated and protrude from the surface of the substrate. The second heavily doped clamping fin is adjacent to the second end and the closest two of the second conductive type heavily doped fins. A layer between the second heavily doped clamping fin and its adjacent second conductivity type heavily doped fin, and a layer between the second heavily doped clamping fin and the first conductivity type heavily doped fin In between, the second contact electrodes are disposed on the top and the sidewall of the second heavily doped clamp fin. The self-balancing diode device according to claim 1, wherein the substrate is a semiconductor substrate.