TWI612664B - Semiconductor device - Google Patents

Abstract

A semiconductor device comprising: a gate structure, a first doped region having a first conductivity type, a plurality of second doped regions having a second conductivity type, a third doped region having a first conductivity type, and having a A plurality of fourth doped regions of the second conductivity type. The gate structure is located on the substrate. The first doped region is located in the substrate on the first side of the gate structure. The second doped region is located in the first doped region. Each of the second doped regions is separated from each other. The third doped region is located in the substrate on the second side of the gate structure. The fourth doped region is located in the third doped region. Each of the fourth doped regions is separated from each other. The second doped region and the fourth doped region are alternately arranged.

Description

Semiconductor component

The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an ElectroStatic Discharge (ESD) protection capability.

Electrostatic discharge (ESD) is a phenomenon in which a charge is rapidly dissipated in a short time after being accumulated on a non-conductor or an ungrounded conductor. Electrostatic discharge can cause damage to circuits in integrated circuits. For example, a human body, a machine for packaging an integrated circuit, or a device for testing an integrated circuit are common charged bodies, and when the charged body is in contact with the wafer, it is possible to discharge the wafer. The instantaneous power of the electrostatic discharge can cause damage or failure of the integrated circuit in the wafer.

Because it is compatible with existing CMOS processes, extended Drain MOSFETs (EDMOSFETs), lateral double-diffused MOSFETs (LDMOSFETs), and reduced surface electric fields (Reduced Surface Field) , RESURF) is widely used in Power Semiconductor Devices. In the field of power semiconductor devices, MOS having a low on-state resistance is often used as a switch. However, current flows only through the MOS surface at low on-state resistance, which limits the ESD discharge path. In addition, MOS with a high breakdown voltage (BV) also has a higher Trigger Voltage, which leads to an increased risk of MOS damage. In the field of power semiconductor components, both of the above considerations are a great challenge in improving the performance of electrostatic discharge protection.

The present invention provides a semiconductor device having an electrostatic discharge protection capability, which can reduce the on-state resistance and improve the performance of electrostatic discharge protection.

The present invention provides a semiconductor device comprising: a gate structure, a first doped region having a first conductivity type, a plurality of second doped regions having a second conductivity type, and a third doped region having a first conductivity type And a plurality of fourth doped regions having a second conductivity type. The gate structure is located on the substrate. The first doped region is located in the substrate on the first side of the gate structure. The second doped region is located in the first doped region. Each of the second doped regions is separated from each other. The third doped region is located in the substrate on the second side of the gate structure. The fourth doped region is located in the third doped region. Each of the fourth doped regions is separated from each other. The second doped region and the fourth doped region are alternately arranged.

In an embodiment of the invention, the gate structure includes a first portion and a second portion. The first portion is adjacent to the first doped region. The first portion has a first gate dielectric layer on the substrate. The second portion is adjacent to the third doped region. The second portion has a second gate dielectric layer on the substrate. The conductor layer covers the first gate dielectric layer and the second gate dielectric layer. The thickness of the second gate dielectric layer is greater than the thickness of the first gate dielectric layer.

In an embodiment of the invention, the semiconductor component further includes a first well region having a first conductivity type located in the substrate. The third doped region and the fourth doped region are located in the first well region.

In an embodiment of the invention, the semiconductor component further includes a second well region having a second conductivity type located in the substrate. The first doped region and the second doped region are located in the second well region. The second well zone does not contact the first well zone.

In an embodiment of the invention, the semiconductor device further includes a fifth doped region having a first conductivity type located in the substrate. The third doped region and the fourth doped region are located in the fifth doped region. The fifth doped region extends further below the gate structure.

In an embodiment of the invention, the semiconductor component further includes a second well region having a second conductivity type located in the substrate. The fifth doped region is located in the second well region.

In an embodiment of the invention, the semiconductor device further includes a field region having a second conductivity type located in the substrate. The first doped region and the second doped region are located in the field region. The field region and the fifth doping region are in contact with each other.

In an embodiment of the invention, the semiconductor component further includes a second well region having a second conductivity type located in the substrate. The field is located in the second well area.

The present invention provides another semiconductor device comprising: a plurality of drain regions, a plurality of source regions, and a gate structure. The bungee zone is located in the base. The source region is located in the substrate. The bungee region and the source region are arranged in a checkerboard interval. The gate structure is located on the substrate between the drain region and the source region to surround the drain region and the source region. The gate structure includes a plurality of first portions and a plurality of second portions. Each of the first portions is adjacent to the corresponding source region and has a first gate dielectric layer on the substrate. Each of the second portions is adjacent to the corresponding drain region and has a second gate dielectric layer on the substrate. The conductor layer covers the first gate dielectric layer and the second gate dielectric layer. The thickness of the second gate dielectric layer is greater than the thickness of the first gate dielectric layer.

In an embodiment of the invention, each of the source regions includes a first doped region having a first conductivity type and a plurality of second doped regions having a second conductivity type. The first doped region is located in the substrate. The second doped region is located in the first doped region. The first doped region surrounds the second doped region. Each of the above-described drain regions includes a third doped region having a first conductivity type and a plurality of fourth doped regions having a second conductivity type. The third doped region is located in the substrate. The fourth doped region is located in the third doped region. The third doped region surrounds the fourth doped region.

Based on the above, the present invention can reduce the on-state resistance of the element by a thinner second gate dielectric layer. In addition, since the second doped region and the fourth doped region are alternately disposed, the present invention can parallel the second doped region, the first doped region, the substrate, the third doped region, and the fourth doped region to A BJT structure (i.e., a P/N/P and an N/P/N structure) is formed, thereby increasing the secondary breakdown current of the semiconductor device of the present embodiment. Therefore, the present invention can not only lower the on-state resistance of the power semiconductor element but also improve the performance of the electrostatic discharge protection of the semiconductor element of the present embodiment.

The above described features and advantages of the invention will be apparent from the following description.

In the following embodiments, when the first conductivity type is N type, the second conductivity type is P type; when the first conductivity type is P type, and the second conductivity type is N type. The P-type doping is, for example, boron; the N-type doping is, for example, phosphorus or arsenic. In the present embodiment, the first conductivity type is N-type and the second conductivity type is P-type as an example, but the invention is not limited thereto. In addition, the same or similar component symbols represent the same or similar components.

1 is a top plan view of a semiconductor device in accordance with an embodiment of the invention. 2A and 2B are cross-sectional views, respectively, of the A-A' line and the B-B' line of the semiconductor element in accordance with the first embodiment of the present invention.

First, referring to FIG. 1, in the above view, the present invention provides a semiconductor device 1 including a substrate 100, two gate structures 102a, 102b, two source regions 104a, 104b, and a drain region 106. The two gate structures 102a, 102b are located on the substrate 100. The drain region 106 is located in the substrate 100 between the two gate structures 102a, 102b. The source region 104a is located in the substrate 100 of the first side S1 of the gate structure 102a; and the source region 104b is located in the substrate 100 of the second side S4 of the gate structure 102b. Substrate 100 can be, for example, a semiconductor substrate having a first conductivity type, such as a P-type substrate. The material of the semiconductor substrate is, for example, at least one material selected from the group consisting of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, and InP. Substrate 100 can also be an undoped epitaxial (Non-EPI) layer, a doped epitaxial layer, a blanket insulating (SOI) substrate, or a combination thereof.

The semiconductor device 10 of the first embodiment of the present invention will be described in detail as an example. Referring to FIG. 1, FIG. 2A and FIG. 2B simultaneously, the gate structure 102a includes a first portion P _1a and a second portion P _2a . The first portion P _{1a is} adjacent to the source region 104a and has a first gate dielectric layer 108a on the substrate 100. The second portion P _{2a is} adjacent to the drain region 106 and has a second gate dielectric layer 110a on the substrate 100. The conductor layer 112a covers the first gate dielectric layer 108a and the second gate dielectric layer 110a. The thickness of the second gate dielectric layer 110a is greater than the thickness of the first gate dielectric layer 108a. In an embodiment, the first gate dielectric layer 108a may have a thickness between 5 nm and 30 nm. The thickness of the second gate dielectric layer 110a may be between 10 nm and 100 nm. The conductor layer 112a may have a thickness between 80 nm and 500 nm. The material of the first gate dielectric layer 108a and the second gate dielectric layer 110a may be, for example, hafnium oxide, tantalum nitride or a high dielectric constant material having a dielectric constant greater than 4, and the formation method thereof is, for example, thermal oxidation or Chemical vapor deposition. The material of the conductor layer 112a may be, for example, doped polysilicon, non-doped polysilicon or a combination thereof, and the formation method thereof is, for example, a chemical vapor deposition method.

Likewise, the other gate structure 102b includes a first portion P _1b and a second portion P _2b . The first portion P _{1b is} adjacent to the source region 104b and has the first gate dielectric layer 108b on the substrate 100. The second portion P _{2b is} adjacent to the drain region 106 and has a second gate dielectric layer 110b on the substrate 100. The conductor layer 112b covers the first gate dielectric layer 108b and the second gate dielectric layer 110b. The thickness of the second gate dielectric layer 110b is greater than the thickness of the first gate dielectric layer 108b. Since the thickness, material, and formation method of the first gate dielectric layer 108b, the second gate dielectric layer 110b, and the conductor layer 112b are the same as the first gate dielectric layer 108a, the second gate dielectric layer 110a, and the conductor layer 112a, This will not be repeated. In addition, the semiconductor device 10 of the first embodiment further includes a dielectric layer 110c disposed on the substrate 100 of the third doping region 118, covering the surface of the third doping region 118 to avoid subsequent doping processes, deposition processes, and The lithography process damages the surface of the substrate 100. However, in the subsequent process of forming the contact window, the dielectric layer 110c on the third doping region 118 will be removed to electrically connect the third doping region 118 with the contact window (not shown).

It is worth noting that the thickness of the second gate dielectric layer 110a, 110b is thinner than the thickness of the conventional field oxide layer (FOX) (ie, 200 nm to 700 nm), so the second gate dielectric is formed. The layers 110a, 110b do not consume excessive substrate 100 material, such that the interface between the second gate dielectric layers 110a, 110b and the substrate 100 is relatively flat. As a result, compared with the prior art, the current generated by the semiconductor device of the present embodiment flows through the fifth doping region 122 (shown in FIG. 2A) below the second gate dielectric layer 110a, 110b. The path is shorter, which in turn reduces its on-state resistance. In an embodiment, the on-state resistance of the semiconductor device 10 of the first embodiment can be reduced by 20% to 40% compared to the prior art.

Referring to FIG. 1 , FIG. 2A and FIG. 2B simultaneously, the source region 104 a includes a first doping region 114 a having a first conductivity type and a plurality of second doping regions 116 a having a second conductivity type. The first doped region 114a is located in the substrate 100. The second doping region 116a is located in the first doping region 114a. Each of the second doping regions 116a is separated from each other, and the first doping region 114a surrounds the periphery of each of the second doping regions 116a. Likewise, the other source region 104b includes a first doping region 114b having a first conductivity type and a plurality of second doping regions 116b having a second conductivity type. The first doped region 114b is located in the substrate 100. The second doping region 116b is located in the first doping region 114b. Each of the second doping regions 116b is separated from each other, and the first doping region 114b surrounds the periphery of each of the second doping regions 116b. In an embodiment, the dopants implanted in the first doping regions 114a, 114b may be, for example, phosphorus or arsenic, and the doping concentration may be, for example, 1 ́10 ¹⁷ /cm ³ to 8 ^{́10 20} /cm ^{3 .} . The dopant implanted in the second doped regions 116a, 116b may be, for example, boron, and the doping concentration may be, for example, 1 ́10 ¹⁷ /cm ³ to 8 ^{́10 20} /cm ³ .

The drain region 106 includes a third doped region 118 having a first conductivity type and a plurality of fourth doped regions 120 having a second conductivity type. The third doped region 118 is located in the substrate 100. The fourth doping region 120 is located in the third doping region 118. Each of the fourth doping regions 120 is separated from each other. The second doping regions 116a, 116b and the fourth doping region 120 are staggered with each other. In other words, as shown in FIG. 1, in the same A-A' line direction (or BB' line direction), the second doping regions 116a, 116b and the fourth doping region 120 do not appear on the same cross section. . Since the second doping regions 116a, 116b and the fourth doping region 120 are staggered with each other, the second doping region 116a / the first doping region 114a / the substrate 100 / the third doping region 118 / the fourth doping The distance of the P/N/P/N/P junction formed by the region 120 is long, and the secondary breakdown current (It ₂ ) of the semiconductor element of the present embodiment is further improved. The so-called secondary breakdown current represents the maximum current that the semiconductor component can withstand when it reaches the p/n junction. After this point, the semiconductor component will be permanently damaged and have a considerable leakage current, which cannot restore the original component. Characteristics. Therefore, the secondary breakdown current of the semiconductor element of the present embodiment is improved, that is, the performance of the electrostatic discharge protection of the semiconductor element of the present embodiment is improved. In an embodiment, the dopant implanted in the third doping region 118 may be, for example, phosphorus or arsenic, and the doping concentration may be, for example, 1 ́10 ¹⁷ /cm ³ to 8 ^{́10 20} /cm ³ . The dopant implanted in the fourth doping region 120 may be, for example, boron, and the doping concentration may be, for example, 1 ́10 ¹⁷ /cm ³ to 8 ^{́10 20} /cm ³ .

In addition, referring to FIG. 2A and FIG. 2B simultaneously, the semiconductor device 10 of the first embodiment further includes: a fifth doping region 122 having a first conductivity type, a second well region 124 having a second conductivity type, and having a second A conductive field region 126, a deep well region 128 having a first conductivity type, and a sixth doping region 130 having a first conductivity type.

The fifth doped region 122 is located in the substrate 100. The third doped region 118 and the fourth doped region 120 are located in the fifth doped region 122, and the fifth doped region 122 extends further below the gate structures 102a, 102b. In an embodiment, the dopant implanted in the fifth doping region 122 may be, for example, phosphorus or arsenic, and the doping concentration may be, for example, 1 ^{́10 15} /cm ³ to 5 ^{́10 18} /cm ³ . Since the fifth doping region 122 has a shallow doping depth and a high doping concentration, it can lower the on-state resistance of the device.

Field region 126 is located in substrate 100. The first doped regions 114a, 114b and the second doped regions 116a, 116b are both located in the field region 126, and the field region 126 and the fifth doped region 122 are in contact with each other. The second well region 124 is located in the substrate 100. The fifth doped region 122 and the field region 126 are both located in the second well region 124. The second well region 124 extends from below the field region 126 to below the fifth doped region 122. The second well zone 124 is located in the deep well zone 128. In one embodiment, the dopant implanted in the second well region 124 can be, for example, boron, and the doping concentration can be, for example, 2 ^{́10 14} /cm ³ to 1 ́10 ¹⁷ /cm ³ . The dopant implanted in field 126 can be, for example, boron, and the doping concentration can be, for example, from 1 ́10 ¹⁶ /cm ³ to 5 ^{́10 18} /cm ³ . In this embodiment, the characteristics of the component channel can be adjusted by the concentration of the field region 126, thereby reducing the trigger voltage (Trigger Voltage) to improve the performance of the device for electrostatic discharge protection.

The deep well zone 128 is located in the substrate 100. The sixth doped region 130a is located in the substrate 100 on one side of the first doped region 104a and extends below the gate structure 102a. Likewise, the sixth doped region 130b is located in the substrate 100 on one side of the first doped region 104b and extends below the gate structure 102b. In one embodiment, the dopant implanted in the deep well region 128 can be, for example, phosphorus or arsenic, and the doping concentration can be, for example, 5 ́10 ¹³ /cm ³ to 8 ^{́10 16} /cm ³ . The dopant implanted in the sixth doping region 130a, 130b may be, for example, phosphorus or arsenic, and the doping concentration may be, for example, 1 ^{́10 15} /cm ³ to 5 ^{́10 17} /cm ³ .

In addition, the semiconductor device 10 of the first embodiment further includes two isolation structures 200 disposed in the substrate 100 on both sides of the two source regions 104a, 104b, thereby electrically isolating other components. The material of the isolation structure 200 may be, for example, doped or undoped yttrium oxide, low stress tantalum nitride, ytterbium oxynitride or a combination thereof, which may be formed by, for example, local area thermal oxidation (LOCOS) or shallow trenches. Separation method (STI).

In summary, the present invention can reduce the on-state resistance of the device by a thinner second gate dielectric layer. In addition, since the second doped region and the fourth doped region are alternately disposed, the present invention can parallel the second doped region, the first doped region, the substrate, the third doped region, and the fourth doped region to A BJT structure (i.e., a P/N/P and an N/P/N structure) is formed, thereby increasing the secondary breakdown current of the semiconductor device of the present embodiment. Therefore, the present invention can not only lower the on-state resistance of the power semiconductor element but also improve the performance of the electrostatic discharge protection of the semiconductor element of the present embodiment.

3A and 3B are cross-sectional views, respectively, of the A-A' line and the B-B' line of the semiconductor device in accordance with the second embodiment of the present invention.

Referring to FIG. 3A and FIG. 3B, the semiconductor device 10 of the first embodiment of the present invention is similar to the semiconductor device 20 of the second embodiment, except that the semiconductor device 20 of the second embodiment is not located in the second well. Field area 126 in area 124.

4A and 4B are cross-sectional views, respectively, of the A-A' line and the B-B' line of the semiconductor device in accordance with the third embodiment of the present invention.

Referring to FIGS. 4A and 4B, the semiconductor device 20 of the second embodiment of the present invention is similar to the semiconductor device 30 of the third embodiment. The difference between the two is that the semiconductor element 30 of the third embodiment replaces the fifth doping region 122 of the semiconductor element 20 with the first well region 222 having the first conductivity type; and the second well having the second conductivity type The regions 224a, 224b replace the second well region 124 of the semiconductor component 20. The first well zone 222 is located in the deep well zone 128. The third doped region 118 and the fourth doped region 120 are located in the first well region 222. The second well regions 224a, 224b are all located in the deep well region 128. The first doped region 114a and the second doped region 116a are located in the second well region 224a, and the first doped region 114b and the second doped region 116b are located in the second well region 224b. The first well region 222 and the second well region 224a, 224b are not in contact with each other. There is a distance D1 between the first well region 222 and the second well region 224a; and a distance D2 between the first well region 222 and the second well region 224b. The semiconductor element 30 of the third embodiment can adjust the breakdown voltage of the semiconductor element 30 by adjusting the distances D1, D2. On the other hand, the semiconductor device 30 of the third embodiment can also control the effectiveness of the electrostatic discharge protection of the semiconductor device 30 by adjusting the doping concentration and the doping depth of the first well region 222. In an embodiment, the dopant implanted in the first well region 222 may be, for example, phosphorus or arsenic, and the doping concentration may be, for example, 2 ^{́10 14} /cm ³ to 5 ^{́10 17} /cm ³ , doping. The depth can range from 1000 nm to 4000 nm. The dopant implanted in the second well region 224a, 224b may be, for example, boron, and the doping concentration may be, for example, 2 ^{́10 14} /cm ³ to 1 ́10 ¹⁷ /cm ³ .

5A and 5B are respectively schematic cross-sectional views of the A-A' line and the B-B' line of the semiconductor element in accordance with the fourth embodiment of the present invention.

Referring to FIGS. 5A and 5B, the semiconductor device 10 of the first embodiment of the present invention is similar to the semiconductor device 40 of the fourth embodiment, except that the semiconductor device 40 of the fourth embodiment is not located in the substrate 100. The deep well area 128.

6A and 6B are respectively schematic cross-sectional views of the A-A' line and the B-B' line of the semiconductor element in accordance with the fifth embodiment of the present invention.

Referring to FIGS. 6A and 6B, the semiconductor device 10 of the first embodiment of the present invention is similar to the semiconductor device 50 of the fifth embodiment. The difference between the two is that the semiconductor component 50 of the fifth embodiment has the second well regions 324a, 324b located in the deep well region 128, and the second well regions 324a, 324b are separated from each other. There is a distance D3 between the second well regions 324a, 324b. Since the second well regions 324a, 324b do not extend below the fifth doping region 122, the semiconductor element 50 can maintain the doping concentration of the surface of the fifth doping region 122 to lower the on-state resistance of the semiconductor device 50.

FIG. 7 is a top plan view of a semiconductor device in accordance with another embodiment of the present invention.

Referring to FIG. 7, the present invention provides another semiconductor device 2 including a gate structure 202, a plurality of source regions 204, and a plurality of drain regions 206. The source region 204 and the drain region 206 are arranged in a checkerboard interval. The gate structure 202 can be, for example, a continuous mesh structure disposed on the substrate 100 between the source region 204 and the drain region 206 to surround the source region 204 and the drain region 206. In detail, the gate structure 202 includes a first portion P _1c and a second portion P _2c . The first portion P _{1c is} adjacent to the source region 204 and has a first gate dielectric layer on the substrate (not shown). The second portion P _{2c is} adjacent to the drain region 206 and has a second gate dielectric layer on the substrate (not shown). The conductor layer covers the first gate dielectric layer and the second gate dielectric layer. The thickness of the second gate dielectric layer is greater than the thickness of the first gate dielectric layer (not shown). Since the thickness, material, and formation method of the first gate dielectric layer, the second gate dielectric layer, and the conductor layer of the semiconductor device 2 are the same as the first gate dielectric layer 108a, the second gate dielectric layer 110a, and the conductor layer 112a, This will not be repeated here.

Similarly, the source region 204 of the semiconductor device 2 also includes a first doped region 214 having a first conductivity type and a second doped region 216 having a second conductivity type. The first doped region 214 is located in the substrate 100. The second doped region 216 is located in the first doped region 214. The first doped region 214 surrounds the periphery of the second doped region 216. The drain region 206 includes a third doped region 218 having a first conductivity type and a fourth doped region 220 having a second conductivity type. The third doped region 218 is located in the substrate 100. The fourth doping region 220 is located in the third doping region 218. The third doped region 218 surrounds the periphery of the fourth doped region 220. The doping and doping concentrations of the first doping region 214, the second doping region 216, the third doping region 218, and the fourth doping region 220 of the semiconductor device 2 are the same as the first doping regions 114a and second. The doped region 116a, the third doped region 118, and the fourth doped region 120 are not described herein. Although the structures of the semiconductor elements illustrated in FIG. 1 and FIG. 7 are strips and squares, respectively, the invention is not limited thereto. In other embodiments, the structure of the semiconductor component can be, for example, rectangular, hexagonal, octagonal, circular, or a combination thereof.

FIG. 8A is a voltage current diagram of an ESD test result of a conventional semiconductor device. Fig. 8B is a voltage current diagram of the ESD test result of the semiconductor element of the first embodiment of the present invention.

This test is performed using a Transmission Line Pulse (TLP). Referring to FIG. 8A and FIG. 8B simultaneously, according to the test results, the conventional semiconductor element has the same breakdown voltage state (BV=32 V) as the semiconductor element of the first embodiment, and the trigger voltage of the conventional semiconductor element is obtained. The trigger voltage of the semiconductor device of the first embodiment is about 25 V which is about 50 V. The trigger voltage (25 V) of the semiconductor element of the first embodiment is much smaller than the breakdown voltage (32 V) of the semiconductor element. Further, the TLP current (that is, the secondary breakdown current) of the semiconductor element of the first embodiment is about 2.2 times that of the conventional semiconductor element. It can be seen that the semiconductor device of the present embodiment has better electrostatic discharge protection performance.

In summary, the present invention can reduce the on-state resistance of the device by a thinner second gate dielectric layer. In addition, since the second doped region and the fourth doped region are alternately disposed, the present invention can parallel the second doped region, the first doped region, the substrate, the third doped region, and the fourth doped region to A BJT structure (i.e., a P/N/P and an N/P/N structure) is formed, thereby increasing the secondary breakdown current of the semiconductor device of the present embodiment. In addition, the present invention can also adjust the breakdown voltage of the semiconductor device by using the doping concentration, the doping depth, and the distance between the doped regions of different doping regions. Therefore, the present invention can not only reduce the conduction state of the power semiconductor device. The resistance, the adjustment of the breakdown voltage of the semiconductor element, and the performance of the electrostatic discharge protection of the semiconductor element of the present embodiment can also be improved.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

1, 2, 10, 20, 30, 40, 50‧‧‧ semiconductor components
100‧‧‧Base
102a, 102b, 202‧‧‧ gate structure
104a, 104b, 204‧‧‧ source area
106, 206‧‧ ‧ bungee area
108a, 108b‧‧‧ first gate dielectric layer
110a, 110b‧‧‧second gate dielectric layer
110c‧‧‧ dielectric layer
112a, 112b‧‧‧ conductor layer
114a, 114b, 214‧‧‧ first doped area
116a, 116b, 216‧‧‧ second doped area
118, 218‧‧‧ third doping zone
120, 220‧‧‧ fourth doping zone
122‧‧‧ fifth doping area
124, 224a, 224b‧‧‧ second well area
126‧‧‧ Area
128‧‧‧Shenjing District
130‧‧‧ sixth doping area
200‧‧‧Isolation structure
222‧‧‧First Well Area
D1, D2, D3‧‧‧ distance
S1, S3‧‧‧ first side
S2, S4‧‧‧ second side

P _1a , P _1b , P _1c ‧‧‧ Part 1

P _2a , P _2b , P _2c ‧‧‧ Part II

1 is a top plan view of a semiconductor device in accordance with an embodiment of the invention. 2A and 2B are cross-sectional views, respectively, of the A-A' line and the B-B' line of the semiconductor element in accordance with the first embodiment of the present invention. 3A and 3B are cross-sectional views, respectively, of the A-A' line and the B-B' line of the semiconductor device in accordance with the second embodiment of the present invention. 4A and 4B are cross-sectional views, respectively, of the A-A' line and the B-B' line of the semiconductor device in accordance with the third embodiment of the present invention. 5A and 5B are respectively schematic cross-sectional views of the A-A' line and the B-B' line of the semiconductor element in accordance with the fourth embodiment of the present invention. 6A and 6B are respectively schematic cross-sectional views of the A-A' line and the B-B' line of the semiconductor element in accordance with the fifth embodiment of the present invention. FIG. 7 is a top plan view of a semiconductor device in accordance with another embodiment of the present invention. FIG. 8A is a voltage current diagram of an ESD test result of a conventional semiconductor device. Fig. 8B is a voltage current diagram of the ESD test result of the semiconductor element of the first embodiment of the present invention.

1‧‧‧Semiconductor components

100‧‧‧Base

102a, 102b‧‧‧ gate structure

104a, 104b‧‧‧ source area

106‧‧‧Bungee Area

114a, 114b‧‧‧ first doped area

116a, 116b‧‧‧second doped area

118‧‧‧ Third doped area

120‧‧‧fourth doping zone

S1, S3‧‧‧ first side

S2, S4‧‧‧ second side

P _1a , P _1b ‧‧‧ Part 1

P _2a , P _2b ‧‧‧ Part II

Claims (8)

A semiconductor device comprising: a gate structure on a substrate; a first doped region of a first conductivity type, located in the substrate on a first side of the gate structure; and having a second conductivity a plurality of second doped regions of the type, located in the first doped region, each second doped region being separated from each other; a third doped region having the first conductivity type, located at a first portion of the gate structure a second side of the substrate; and a plurality of fourth doped regions having the second conductivity type, the third doped regions are separated from each other, wherein the second doped regions are The fourth doped regions are staggered. The semiconductor device of claim 1, wherein the gate structure comprises: a first portion adjacent to the first doped region, the first portion having a first gate dielectric layer on the substrate; and a a second portion adjacent to the third doped region, the second portion having a second gate dielectric layer on the substrate, wherein a conductor layer covers the first gate dielectric layer and the second gate dielectric layer And the thickness of the second gate dielectric layer is greater than the thickness of the first gate dielectric layer. The semiconductor device of claim 1, further comprising a first well region having the first conductivity type in the substrate, wherein the The third doped region and the fourth doped regions are located in the first well region. The semiconductor device of claim 3, further comprising a second well region having the second conductivity type, wherein the first doped region and the second doped region are located at the first In the second well zone, the second well zone and the first well zone are not in contact with each other. The semiconductor device of claim 1, further comprising a fifth doped region having the first conductivity type in the substrate, wherein the third doped region and the fourth doped regions are located In the fifth doping region, the fifth doping region extends further below the gate structure. The semiconductor device of claim 5, further comprising a second well region having the second conductivity type in the substrate, wherein the fifth doping region is located in the second well region. The semiconductor device of claim 5, further comprising a field region having the second conductivity type in the substrate, wherein the first doping region and the second doping regions are located in the field region, And the field region and the fifth doping region are in contact with each other. The semiconductor component of claim 7, further comprising a second well region having the second conductivity type located in the substrate, wherein the field region is located in the second well region.