TWI612640B - Memory device and method for fabricating the same - Google Patents

Abstract

A memory element. The memory element includes a substrate, a plurality of semiconductor strip structures, a first doped region, a plurality of second doped regions, a plurality of first contact windows, and a plurality of second contact windows. Each of the semiconductor strip structures extends in a first direction. The first doped region includes a plurality of first portions and second portions. Each first portion is located at a lower portion of the corresponding semiconductor strip structure. The second portion is located on the surface of the substrate and the first portion is coupled to the second portion. Each of the second doped regions is located at an upper portion of the corresponding semiconductor strip structure. Each of the first contact windows is electrically connected to the second portion of the first doped region. Each of the second contact windows is electrically connected to the corresponding second doped region.

Description

Memory element and method of manufacturing same

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a memory device of a common source and a method of fabricating the same.

Non-volatile memory can perform multiple data storage, reading, erasing, etc., and the stored data will not disappear even if the power supply is interrupted. Therefore, non-volatile memory has become a must-have memory component in many electronic products to maintain the normal operation of electrical products when they are turned on.

However, as the size of semiconductor components is shrinking, the short channel effect of conventional horizontal memory devices will become more and more serious. This phenomenon will result in a deterioration of the second bit effect and program disturb in the memory element. Therefore, in order to avoid the above phenomenon, vertical memory devices have been developed in recent years, so that the size of the channel can be reduced while maintaining the same channel length to avoid short channel effects and improve the second bit effect. Stylized interference.

In the vertical memory element, the relative relationship between the elements and the structure of the stacked structure become complicated while the element structures are stacked up. Therefore, how to simplify the relative relationship between the vertical memory elements and the structure of the stacked structure, and maintain the original operational efficiency, is the subject of current research.

The invention provides a memory element and a manufacturing method thereof, which can simplify the relative relationship between the vertical memory elements and the structure of the stacked structure, maintain the original operating efficiency, and are compatible with the existing processes.

The invention provides a memory element comprising a substrate, a plurality of semiconductor strip structures, a first doped region, a plurality of second doped regions, a plurality of word lines, a charge storage layer, a plurality of first contact windows, and a plurality of a second contact window, a first wire, and a plurality of second wires. The substrate includes a plurality of first blocks and a plurality of second blocks. The first block and the second block alternate with each other. Each first block includes two first zones and one second zone, and the second zone is located between the two first zones. A plurality of the above semiconductor strip structures are located on the substrate. Each of the semiconductor strip structures extends in a first direction. The first doped region includes a plurality of first portions and second portions. Each first portion is located at a lower portion of the corresponding semiconductor strip structure. The second portion is located on the surface of the substrate and the first portion is coupled to the second portion. Each of the second doped regions is located at an upper portion of the corresponding semiconductor strip structure. The plurality of word lines are located on the substrate of each of the first regions. Each of the word lines extends along the second direction to cover a portion of the sidewalls and a portion of the top of each of the semiconductor strip structures. The first direction is different from the second direction. The charge storage layer is located between the semiconductor strip structure and the word line. The plurality of first contact windows are located in the second block and the second area and are arranged along the first direction. Each of the first contact windows is electrically connected to the second portion of the first doped region. The plurality of second contact windows are located at least in the second zone. Each of the second contact windows is electrically connected to the corresponding second doped region. The first wire is located on the substrate and extends along the first direction and is electrically connected to the first contact window. The plurality of second wires are located on the substrate. Each of the second wires extends along the first direction and is electrically connected to the second contact window on the corresponding semiconductor strip structure.

In an embodiment of the invention, each of the semiconductor strip structures has a base region. The base region is between the second doped region in the semiconductor strip structure and the first portion of the first doped region. Moreover, in the second block, the second contact window is further included.

In an embodiment of the invention, the second block has a trench, and the trench extends along the second direction. Also, each of the above semiconductor strip structures has a base region. In the first block, the base region is between the second doped region and the first portion of the first doped region. In the second block, the base region is located on the first portion of the first doped region, and the trench is exposed to expose the substrate region.

In an embodiment of the invention, a plurality of third contact windows and a third wire are further included. The third contact window is located in the second block, extends along the second direction, and is electrically connected to the exposed base region of the trench. The third wire is located on the substrate, extends along the first direction, and is electrically connected to the third contact window.

In an embodiment of the invention, a plurality of partial wires are further included in the first block on both sides of the third contact window. Each of the partial wires extends along the first direction and is electrically connected to the second contact window on the corresponding semiconductor strip structure. Moreover, each of the second wires is located above the partial wires on the corresponding semiconductor strip structure and across the third contact window, and is electrically connected to the corresponding partial wires via the plurality of fourth contact windows.

The present invention provides a method of manufacturing a memory element comprising the following steps. A substrate is provided, the substrate comprising a plurality of first blocks and a plurality of second blocks. The first block and the second block alternate with each other. Each first block includes two first zones and one second zone, and the second zone is located between the two first zones. A plurality of semiconductor strip structures are formed on the substrate, wherein each of the semiconductor strip structures extends along the first direction. A first doped region is formed, the first doped region comprising a plurality of first portions and second portions. Each first portion is located at a lower portion of the corresponding semiconductor strip structure. The second portion is located on the surface of the substrate and the first portion is coupled to the second portion. A plurality of second doped regions are formed on an upper portion of each of the semiconductor strip structures. A plurality of word lines are formed on the substrate of each of the first regions. Each of the word lines extends along the second direction to cover a portion of the sidewalls and a portion of the top of each of the semiconductor strip structures, the first direction being different from the second direction. A charge storage layer is formed between the semiconductor strip structure and the word line. A plurality of first contact windows are formed in the second block and the second region, and are arranged along the first direction, and each of the first contact windows is electrically connected to the second portion of the first doped region. A plurality of second contact windows are formed in at least the second region. Each of the second contact windows is electrically connected to the corresponding second doped region. A first wire is formed on the substrate. The first wire extends along the first direction and is electrically connected to the first contact window. A plurality of second wires are formed on the substrate. Each of the second wires extends along the first direction and is electrically connected to the second contact window on the corresponding semiconductor strip structure.

In an embodiment of the invention, the method of forming the semiconductor strip structure, the first doped region and the second doped region includes the following steps. A portion of the substrate is patterned to form a semiconductor strip structure. An ion implantation process is performed to implant dopants on the upper portion of each of the semiconductor strip structures and the surface of the substrate. A thermal tempering process is performed to form the dopants to form a first doped region and a second doped region.

In an embodiment of the invention, the method further includes: removing a portion of the semiconductor strip structure in the second block to form a trench. The trench extends along the second direction to expose the base region of the corresponding semiconductor strip structure.

In an embodiment of the invention, the following steps are further included. Forming a third contact window in the second block, the third contact window extending along the second direction and electrically connecting the exposed base region of the trench. Forming a third wire on the substrate, the third wire extending along the first direction and electrically connected to the third contact window.

In an embodiment of the invention, the following steps are further included. A plurality of partial wires are formed in the first block on both sides of the third contact window. Each of the partial wires extends along the first direction and is electrically connected to the second contact window on the corresponding semiconductor strip structure. Moreover, each of the second wires is located above the partial wires on the corresponding semiconductor strip structure and across the third contact window, and is electrically connected to the corresponding partial wires via the plurality of fourth contact windows.

The present invention provides a memory array comprising the above described memory elements. The memory array includes a plurality of memory cells, a plurality of bit lines, a plurality of common source lines, and a source line. The memory cells are arranged in an array of a plurality of rows and a plurality of columns, and include a first doping region as a source and a second doping region as a drain. Each bit line is coupled to a second doped region of the memory cell of the same row. Each common source line is coupled to a first doped region of a memory cell of the same column. The source line is coupled to the common source line and electrically connected to the first doped region of the memory cell. Each word line is coupled to the gate of the memory cell of the same column.

In an embodiment of the invention, the memory array further includes a base line. The base line is coupled to the base region of the memory cell.

The present invention provides a method of operating a memory array that includes the following steps. Select at least one memory cell. A first voltage is applied to a word line corresponding to the selected memory cell. A second voltage is applied to a bit line corresponding to the selected memory cell. A third voltage is applied to the source line of the memory array.

In an embodiment of the invention, the method for operating the memory array further includes the following steps. A fourth voltage is applied to the base line of the memory array corresponding to the selected memory cell.

Based on the above, the first portion of the first doped region provided by the present invention is connected to the second portion, so that the first doped regions in each of the semiconductor strip structures can be connected to each other. Moreover, since the first contact window is electrically connected to the second portion of the first doped region, the first contact window is electrically connected to the first doped region in each of the semiconductor strip structures. In this way, the relative relationship between the vertical memory elements and the structure of the stacked structure can be greatly simplified, the original operating efficiency can be maintained, and the existing processes are compatible.

The above described features and advantages of the invention will be apparent from the following description.

1A through 1D are schematic top views of a method of fabricating a memory device in accordance with a first embodiment of the present invention. 2A to 2D are schematic cross-sectional views taken along line A-A' of Figs. 1A to 1D, respectively. 3A to 3D are schematic cross-sectional views taken along line B-B' of Figs. 1A to 1D, respectively. 4A to 4D are schematic cross-sectional views taken along line C-C' of Figs. 1A to 1D, respectively. 5A to 5D are schematic cross-sectional views taken along line D-D' of Figs. 1A to 1D, respectively.

Referring to FIGS. 1A, 2A, 3A, 4A, and 5A simultaneously, a substrate 10 is provided. The substrate 10 includes a plurality of first blocks B1 and a plurality of second blocks B2. The first block B1 and the second block B2 alternate with each other. Each first block B1 includes two first areas R1 and one second area R2. The second zone R2 is located between the two first zones R1. The substrate 10 is, for example, a semiconductor substrate, a semiconductor compound substrate, or a silicon on insulator (SOI) substrate. Substrate 10 can include an ion implantation region, such as a source/drain region formed by P-type or N-type ion implantation. The substrate 10 may include a single layer structure or a multilayer structure. The substrate 10 includes, for example, shallow trench isolation (STI). In an embodiment, the substrate 10 is, for example, a germanium substrate or a doped polysilicon.

Next, referring to FIG. 1A, FIG. 2A, FIG. 3A, FIG. 4A and FIG. 5A, a plurality of semiconductor strip structures 20 are formed on the substrate 10, and doped regions 12 and base regions 14 are formed in the semiconductor strip structures 20. And a doped region 16. Each of the semiconductor strip structures 20 extends along the first direction D1. Doped regions 16 are located on top of each of the semiconductor strip structures 20. The doped region 12 includes a plurality of first portions 12a and second portions 12b. Each of the first portions 12a is located at a lower portion of the corresponding semiconductor strip structure 20. The second portion 12b is located on the surface of the substrate 10, and the first portion 12a is coupled to the second portion 12b. The body region 14 is located between the doped region 16 and the first portion 12a of the doped region 12.

The doped region 12/substrate region 14/doped region 16 is, for example, a source/substrate/drain. The doped region 12 and the doped region 16 may be of a first conductivity type; the base region 14 may be of a second conductivity type. The doped region 12/substrate region 14/doped region 16 is, for example, an N+/P/N+ doped region or a P+/N/P+ doped region. Moreover, the doping concentration of the doping region 12 and the doping region 16 may be the same or different; the matrix region 14 may be doped or undoped. In one embodiment, the doping concentration of the base region 14 is, for example, less than the doping concentration of the doped region 12 and the doped region 16. In another embodiment, the thickness of the base region 14 is, for example, greater than the thickness of the doped region 12 and the doped region 16. The thickness of the base region 14 is, for example, 30 to 500 nm. The thickness of the doped region 12 and the doped region 16 is, for example, 20 to 200 nm.

It is noted that since the doped region 12 includes the first portion 12a and the second portion 12b, and the first portion 12a is connected to the second portion 12b. Therefore, the first portions 12a of the doped regions 12 in each of the semiconductor strip structures 20 can be connected to each other by the second portion 12b. In an embodiment, when the doping region 12 is used as a source, for example, the sources in each of the semiconductor strip structures 20 may be electrically connected to each other.

In an embodiment of the invention, the method of forming the semiconductor strip structure 20, the doping region 12, and the doping region 16 is, for example, patterning a portion of the substrate 10 to form the semiconductor strip structure 20. The patterning method is, for example, a lithography of the substrate 10 and an etching process. The dopant is then implanted into the semiconductor strip structure 20 and the substrate 10. The method of implanting the dopant is, for example, an ion implantation process on the substrate 10 to implant dopants on the upper portion of each of the semiconductor strip structures 20 and the surface of the substrate 10. Thereafter, the doped semiconductor strip structure 20 and the substrate 10 are subjected to a thermal tempering process to diffuse the dopants to form the doped regions 12 and the doped regions 16.

Referring to FIGS. 1A, 2A, 3A, 4A, and 5A, a charge storage layer 18 is formed on the substrate 10. The charge storage layer 18 is conformally formed along the top surface and the side surface of the semiconductor strip structure 20. Since the charge storage layer 18 is located on the top surface and the side surface of the semiconductor strip structure 20, the charge storage layer 18 not only has a charge storage function, but also has a word line formed in the doped region 12, the doped region 16 and subsequent processes. 22 (as shown in Figure 5A) the role of electrical isolation. In one embodiment, the charge storage layer 18 is, for example, a composite layer composed of an Oxide-Nitride-Oxide (ONO) layer, and the composite layer may be three or more layers. The method of forming the charge storage layer 18 is, for example, a chemical vapor deposition method or a thermal oxidation method.

Then, a word line material layer (not shown) is formed on the charge storage layer 18, and the word line material layer is along the top surface and the side surface of the charge storage layer 18. The material of the word line is, for example, an N+ doped polysilicon, a P+ doped polysilicon, a metal material, or a combination thereof. Next, the word line material layer is patterned to form a plurality of word lines 22 (e.g., as control gates) on the substrate 10 of each of the first regions R1. Each of the word lines 22 extends along the second direction D2 to cover a portion of the sidewalls and portions of the top portions of each of the charge storage layers 18 of the first region R1 of the substrate 10. That is, the charge storage layer 18 is located between the semiconductor strip structure 20 and the word line 22. The first direction D1 is different from the second direction D2. In an exemplary embodiment, the first direction D1 and the second direction D2 are substantially perpendicular.

Referring to FIGS. 1B, 2B, 3B, 4B, and 5B simultaneously, spacers 24 are formed on each of the word lines 22 and the sides of each of the semiconductor strip structures 20, respectively. Specifically, a spacer material layer (not shown) is conformally formed on the substrate 10 to cover the semiconductor strip structure 20. The material of the spacer material layer is, for example, ruthenium oxide, tantalum nitride or a combination thereof, which can be formed by chemical vapor deposition. Then, an anisotropic etching process is performed to remove a portion of the spacer material layer and a portion of the charge storage layer 18 to form spacers 24 on each of the word lines 22 and the sides of each of the semiconductor strip structures 20, respectively. In one embodiment, the spacers 24 expose the top surface S1 of the charge storage layer 18 on each of the semiconductor strip structures 20 (as shown in FIG. 4B). In another embodiment, to ensure complete removal of the spacer material layer on the top surface S1 of the charge storage layer 18, a portion of the charge storage layer 18 is removed by over etching during the etching process. Therefore, the formed spacer 24 exposes the top surface S2 of the semiconductor layer 16 (as shown in FIG. 2B).

Referring to FIGS. 1C, 2C, 3C, 4C, and 5C simultaneously, a dielectric layer 26 is formed on the substrate 10. Then, using a lithography and etching process, a portion of the dielectric layer 26 and a portion of the charge storage layer 18 are removed to form a plurality of first contact opening 42a in the second block B2 and the second region R2 of the substrate 10; A plurality of second contact opening 44a are formed in at least the second region R2. Each first contact opening 42a exposes the second portion 12b of the doped region 12. Each of the second contact opening 44a exposes the doped region 16 of the semiconductor strip structure 20.

Thereafter, a first contact window 42 and a second contact window 44 are formed in the first contact window opening 42a and the second contact window opening 44a, respectively. The first contact windows 42 are respectively located in the second block B2 and the second area R2 and are arranged along the first direction D1; the second contact window 44 is located at least in the second area R2. In an exemplary embodiment, the first contact window 42 is located in the second block B2 and the second region R2 on one side of the outermost semiconductor strip structure 20 on the partial substrate 10. The second contact window 44 is located in the second zone R2 and the second block B2. Each of the first contact windows 42 is electrically connected to the second portion 12b of the doping region 12. Each of the second contact windows 44 is electrically connected to the doped region 16 of the corresponding semiconductor strip structure 20 . The first contact window 42 and the second contact window 44 are formed by, for example, forming a layer of a conductor material on the substrate 10. The layer of conductor material is, for example, aluminum, copper or an alloy thereof. The method of forming the conductor material layer may be a physical vapor deposition method such as sputtering. Thereafter, the conductive material layer other than the first contact opening 42a and the second contact opening 44a is removed by chemical mechanical polishing or etch back.

Referring to FIG. 1D, FIG. 2D, FIG. 3D, FIG. 4D and FIG. 5D simultaneously, a conductive material layer (not shown) is formed on the substrate 10. Then, the conductive material layer is patterned by a lithography and etching process to form a first wire 72a and a plurality of second wires 74a. The first wire 72a extends along the first direction D1 and is electrically connected to the first contact window 42. The second wire 74a extends along the first direction D1 and is electrically connected to the second contact window 44 on the corresponding semiconductor strip structure 20. The first wire 72a is, for example, a source line; the second wire 74a is, for example, a bit line. The material of the conductor material layer is, for example, doped polysilicon, undoped polysilicon or a combination thereof, and the formation method thereof can be formed by chemical vapor deposition.

1D to 5D, in a first embodiment of the present invention, the memory device 100 includes a substrate 10, a plurality of semiconductor strip structures 20, doped regions 12, a plurality of substrate regions 14, a plurality of doped regions 16, A plurality of word lines 22, a charge storage layer 18, a plurality of first contact windows 42, a plurality of second contact windows 44, a first wire 72a, and a plurality of second wires 74a. The doped region 12 includes a plurality of first portions 12a and second portions 12b, and the first portion 12a is coupled to the second portion 12b. Moreover, the second portion 12b of the doping region 12 can be electrically connected to the first wire 72a through the first contact window 42. The doped region 16 is electrically connected to the second wire 74a via the second contact window 44.

It is worth mentioning that since the first portion 12a of the doped region 12 is connected to the second portion 12b, the first portions 12a of the doped regions 12 in each of the semiconductor strip structures 20 can be connected to each other. That is, when the doped region 12 is, for example, a source of a memory element, the sources in each of the semiconductor strip structures 20 may be connected to each other. Moreover, since the first contact window 42 is electrically connected to the second portion 12b of the doped region 12, the first conductive line 72a is electrically connected to the source in each of the semiconductor strip structures 20, for example. In this way, the relative relationship between the vertical memory elements and the structure of the stacked structure can be greatly simplified, the original operating efficiency can be maintained, and the existing processes are compatible.

6A-6E are top schematic views showing a manufacturing process of a memory element according to a second embodiment of the present invention. 7A to 7E are schematic cross-sectional views taken along line A-A' of Figs. 6A to 6E, respectively. 8A to 8E are schematic cross-sectional views taken along line B-B' of Figs. 6A to 6E, respectively. 9A to 9E are schematic cross-sectional views taken along line C-C' of Figs. 6A to 6E, respectively. 10A to 10E are schematic cross-sectional views taken along line E-E' of Figs. 6A to 6E, respectively.

A part of the manufacturing flow of the memory element 200 of the second embodiment of the present invention may be the same as that of the memory element 100 of the first embodiment. More specifically, substrate 10 in memory element 200, a plurality of semiconductor strip structures 20, doped regions 12, substrate regions 14, a plurality of doped regions 16, a plurality of word lines 22, charge storage layers 18, and gaps The manufacturing process of the wall 24 is, for example, as described above for the memory element 100, and will not be further described herein.

Referring to FIG. 6A, FIG. 7A, FIG. 8A, FIG. 9A and FIG. 10A, after each of the word lines 22 and the side faces of each of the semiconductor strip structures 20 are respectively formed with the spacers 24, the second portion of the substrate 10 is removed. A portion of the semiconductor strip structure 20 in the block B2 forms a trench T (as shown in Figures 6A, 7A and 8A). The trench T extends, for example, along the second direction D2. The trench T exposes the base region 14 (not shown) of the corresponding semiconductor strip structure 20. In the present embodiment, each of the semiconductor strip structures 20 has a base region 14. In the first block B1, the base region 14 is located between the doped region 16 and the first portion 12a of the doped region 12; in the second block B2, the base region 14 is located on the first portion 12a of the doped region 12, And the trench T exposes the base region 14. Next, a liner 28 is conformally formed on the substrate 10 to cover the semiconductor strip structure 20 and the word line 22. The material of the lining layer 28 may be cerium oxide, cerium oxynitride, cerium nitride or a combination thereof, and the forming method may be a chemical vapor deposition method or a physical vapor deposition method.

Referring to FIGS. 6B, 7B, 8B, 9B, and 10B, a dielectric layer 26 is formed on the substrate 10. Then, a portion of the dielectric layer 26 and a portion of the liner 28 are removed by using a lithography and etching process to form a plurality of first contact openings 42a in the second block B2 and the second region R2 of the substrate 10; A plurality of second contact window openings 44a are formed in the second region R2; and a third contact window opening 46a is formed in the second block B2. Each first contact opening 42a exposes the second portion 12b of the doped region 12. Each of the second contact opening 44a exposes the doped region 16 of the semiconductor strip structure 20. The third contact opening 46a exposes a plurality of substrate regions 14 of the plurality of semiconductor strip structures 20.

Thereafter, a first contact window 42, a second contact window 44, and a third contact window 46 are formed in the first contact opening 42a, the second contact opening 44a, and the third contact opening 46a, respectively. The first contact window 42 is located in the second block B2 and the second area R2 and arranged along the first direction D1; the second contact window 44 is located in the second area R2 and arranged along the second direction D2; The contact window 46 is located in the second block B2 and extends along the second direction D2. In an exemplary embodiment, the first contact window 42 is located in the second block B2 and the second region R2 on one side of the outermost semiconductor strip structure 20 on the partial substrate 10. Each of the first contact windows 42 is electrically connected to the second portion 12b of the doping region 12. Each of the second contact windows 44 is electrically connected to the doped region 16 of the corresponding semiconductor strip structure 20 . The third contact window 46 is electrically connected to the exposed base region 14 of the trench T. The method for forming the first contact window 42, the second contact window 44, and the third contact window 46 is as described in the first contact window 42 and the second contact window 44 of the first embodiment, and details are not described herein.

Referring to FIG. 6C, FIG. 7C, FIG. 8C, FIG. 9C, and FIG. 10C, a conductor material layer (not shown) is formed on the substrate 10. Then, the conductive material layer is patterned using a lithography and etching process to form a fourth wire 52, a plurality of partial wires 54, and a fifth wire 56. In an embodiment, the partial wires 54 are located in the first block B1 on both sides of the third contact window 46. The fourth wire 52 extends along the first direction D1 and is electrically connected to the first contact window 42. Each of the partial wires 54 extends along the first direction D1 and is electrically connected to the second contact window 44 on the corresponding semiconductor strip structure 20. The fifth wire 56 extends along the first direction D1 and is electrically connected to the third contact window 46. The material and formation method of the conductor material layer are as described in the first embodiment, and will not be further described herein. Then, a dielectric layer 30 is formed on the substrate 10. The dielectric layer 30 electrically isolates the fourth wire 52, the partial wire 54 and the fifth wire 56 from each other. The material and formation method of the dielectric layer 30 are as described above, and will not be further described herein.

Referring to FIGS. 6D, 7D, 8D, 9D, and 10D, a dielectric layer 32 is formed on the substrate 10. Then, a portion of the dielectric layer 32 is removed by the lithography and etching process to form a plurality of fourth contact opening 60a, a plurality of fifth contact opening 60b and sixth contact opening 60c in the substrate 10. The fourth contact opening 60a exposes the fourth wire 52, the fifth contact opening 60b exposes the partial wire 54, and the sixth contact opening 60c exposes the fifth wire 56. Thereafter, a fourth contact window 61a is formed in the fourth contact window opening 60a, a fifth contact window 61b is formed in the fifth contact window opening 60b, and a sixth contact window 61c is formed in the sixth contact window opening 60c.

Referring to FIG. 6E, FIG. 7E, FIG. 8E, FIG. 9E and FIG. 10E simultaneously, a conductor material layer (not shown) is formed on the substrate 10. Then, the conductor material layer is patterned to form a first wire 72b, a plurality of second wires 74b, and a third wire 76. The first wire 72b extends along the first direction D1 and is electrically connected to the first contact window 42 via the fourth contact window 61a and the fourth wire 52. The second wire 74b extends along the first direction D1 above the local wire 54 on the corresponding semiconductor strip structure 20. Moreover, the second wire 74b is electrically connected to the corresponding partial wire 54 via the fifth contact window 61b across the third contact window 46. The third wire 76 extends along the first direction D1 and is electrically connected to the third contact window 46 via the sixth contact window 61c and the fifth wire 56. The first wire 72b, the second wire 74b, and the third wire 76 are, for example, a source line, a bit line, and a base line, respectively. The material and formation method of the conductor material layer are as described above, and will not be further described herein.

Referring again to FIGS. 1D, 4D, and 5D, the memory device of the first embodiment of the present invention includes a substrate 10, a plurality of semiconductor strip structures 20, a first doped region 12, and a plurality of second doped regions 16 A plurality of word lines 22, a charge storage layer 18, a plurality of first contact windows 42, a plurality of second contact windows 44, a first wire 72, and a plurality of second wires 74.

Referring to FIG. 1D, the substrate 10 includes two first blocks B1 and a second block B2. The second block B2 is located between the two first blocks B1, and each of the first blocks B1 includes a plurality of first regions R1 and a plurality of second regions R2, and the first region R1 and the second region R2 alternate with each other. .

Referring to FIG. 4D, a plurality of semiconductor strip structures 20 are located on the substrate 10. Each of the semiconductor strip structures 20 extends along the first direction D1. The first doped region 12 includes a plurality of first portions 12a and second portions 12b. Each of the first portions 12a is located at a lower portion of the corresponding semiconductor strip structure 20; the second portion 12b is located at a surface of the substrate 10, and the first portion 12a is coupled to the second portion 12b. A plurality of second doped regions 16 are located on an upper portion of each of the semiconductor strip structures 20.

Referring to FIG. 1D and FIG. 5D, a plurality of word lines 22 are located on the substrate 10 of each of the first regions R1. Each word line 22 extends along a second direction D2 covering a portion of the sidewalls and portions of the respective semiconductor strip structures 20. The first direction D1 is different from the second direction D2. The charge storage layer 18 is between the semiconductor strip structure 20 and the word line 22.

Referring to FIG. 1D and FIG. 4D, a plurality of first contact windows 42 are located in the second block B2 and the second region R2, and are arranged along the first direction D1. Each of the first contact windows 42 is electrically connected to the second portion 12b of the first doping region 12. A plurality of second contact windows 44 are at least located in the second region R2, and each of the second contact windows 44 is electrically connected to the corresponding second doping region 16. The first wire 72a is located on the substrate 10 and extends along the first direction D1 and is electrically connected to the first contact window 42. A plurality of second wires 74a are located on the substrate 10, and each of the second wires 74a extends along the first direction D1 and is electrically connected to the second contact window 44 on the corresponding semiconductor strip structure 20.

It is worth mentioning that since the doping region 12 includes the first portion 12a and the second portion 12b, and the first portion 12a is connected to the second portion 12b. Therefore, the first portions 12a of the doped regions 12 in each of the semiconductor strip structures 20 can be connected to each other by the second portion 12b. In an embodiment, when the doping region 12 is used as a source, for example, the sources in each of the semiconductor strip structures 20 may be electrically connected to each other.

Referring to FIG. 6A, FIG. 9A and FIG. 10A, the memory element 200 according to the second embodiment of the present invention has a trench T and a trench T in the second block B2 compared to the memory element 100 of the first embodiment. Extending along the second direction exposes the substrate region 14. In other words, in the first block B1, the base region 14 is located between the doped region 14 and the first portion 12a of the doped region 12; in the second block B2, the base region 14 is located at the first portion 12a of the doped region 12. Upper, and the trench T bare exposes the base region 14.

In addition, the memory element 200 of the second embodiment further includes: a third contact window 46, a fourth wire 52, a plurality of partial wires 54, a fifth wire 56, a fourth contact window 61a, a fifth contact window 61b, and a sixth contact. Window 61c and third wire 76.

Referring to FIG. 6E and FIG. 9E , the third contact window 46 is located in the second block B2 of the substrate 10 and extends along the second direction D2 , and the third contact window 46 is electrically connected to the substrate of the partial semiconductor strip structure 20 . District 14. The third wire 76 is located on the substrate 10 and extends along the first direction D1, and is electrically connected to the base region 14 of the semiconductor strip structure 20 via the sixth contact window 61c, the fifth wire 56, and the third contact window 46. Therefore, when the base region 14 is, for example, a base as a memory element, a voltage can be applied to the substrate by the third wire 76 to control the potential of the substrate. In this way, the potential of the substrate can be clearly known, and the potential of the substrate is prevented from being in a floating state by the coupling effect of other biases.

FIG. 11A is a schematic diagram of a memory array structure according to a first embodiment of the present invention.

Referring to FIG. 11A, FIG. 11A illustrates a plurality of cell strings 301. The memory cell string 301 is transmitted through a plurality of bit lines BL ₁ to BL _n (where n is an integer greater than 1), a source line SL, and a plurality of word lines WL ₁ to WL _2m (where m is an integer greater than 1) Connected to form a memory array in the column direction and the row direction. Each of the first regions R1 (such as the first region R1 in FIG. 1D) is formed by juxtaposing a plurality of memory cell strings 301. In an embodiment, each memory cell string 301 can include 32 memory cells or more memory cells.

The source line SL can be coupled to the first wire 72a (as shown in FIG. 4D) to serially connect the source of each memory cell in the memory array (for example, the doping region 12 in FIG. 4D. At this time, doping Zone 12 is for example a common source line). The bit lines BL ₁ , BL ₂ . . . BL _n can be respectively coupled to the second wires 74 a (as shown in FIG. 4D ) to respectively connect the drains of the plurality of memory cells in the same row in the memory array (for example, FIG. 4D ). Doped region 16). The word lines WL ₁ , WL ₂ ... WL _2m may be connected in series to the gates of the plurality of memory cells in the same column in the memory array. In an embodiment, the bit lines BL ₁ , BL ₂ . . . , BL _n may be coupled to the bit line transistors BLT ₁ , BLT ₂ . . . BLT _{n , respectively} . Bit lines BL ₁ and BL ₃ may be coupled to a global bit line GBL ₁ . Bit lines BL ₂ and BL ₄ may be coupled to global bit line GBL ₂ . A control voltage V ₁ is _a global bit line GBL and _a BLT on / off ₃ applied to the bit line BL through the bit line BLT via transistor ₁ and BL _3.

In an embodiment of the present invention, different sizes of voltages may be applied to the source, the drain, and the gate corresponding to the memory cell M1 for reading, programming, or erasing ( Erase) operation. For example, the method of performing a read operation on the memory cell M1 includes applying a voltage of 10 V to the bit line transistor BLT ₂ to turn it on, thereby causing a control voltage V ₂ (for example, V applied to the global bit line GBL _{2 )} . ₂ =0 V) via the bit line transistor BLT ₂ and the bit line BL ₂ , providing the drain of the memory cell M1 as the drain voltage V _d ; applying 10 V voltage to the source line transistor SLT to turn it on, The control voltage of 1.6V is supplied to the source of the memory cell M1 via the source line SL as the source voltage V _s ; and the word line WL _i connected to the gate of the memory cell M1 is applied, for example, to 0V. A voltage of up to 10V is used as the gate voltage V _g . Thereby, the operation of reading the memory cell M1 can be performed. It should be understood that the scope of the invention is not limited to the particular voltages set forth above. In another embodiment, the voltage of the source, the drain, and the gate corresponding to the memory cell M1 can also be changed to perform a program or erase operation.

FIG. 11B is a schematic diagram of a memory array structure according to a second embodiment of the present invention.

Please refer to FIG. 11B. FIG. 11B illustrates a plurality of memory cell strings 302. The plurality of memory cell strings 302 are via the base line BdL, the plurality of bit lines BL ₁ to BL _n (where n is an integer greater than 1), the source line SL, and the plurality of word lines WL ₁ to WL _2m (where m is An integer greater than 1 is concatenated to be arranged into a memory array in the column direction and the row direction. As with the first embodiment described above, the source line SL can be connected in series with the source of each of the memory cells in the memory array. The bit lines BL ₁ , BL ₃ ... BL _n may be connected in series to the drains of the plurality of memory cells. The word lines WL ₁ , WL ₂ ... WL _2m may be connected in series to the gates of the plurality of memory cells. It should be noted that, in comparison with the first embodiment, the base line BdL of the present embodiment can be coupled to the third lead 76 (shown in FIG. 6E) to serially connect the base of each memory cell in the memory array ( For example, the base region 14) in Figure 9E. That is, in addition to the application of the gate voltage V _d , the source voltage V _{s ,} and the gate voltage V _g , the present embodiment can apply a control voltage of, for example, 0 V to the base line transistor BdLT, via the base line BdL. The substrate to the memory cell M2 is used as the base voltage V _b to control the potential of the substrate.

12A-12B are schematic diagrams of memory elements of a reverse read operation, in accordance with an embodiment of the invention. 13A-13B are schematic diagrams of memory elements of a channel hot electron injection (CHEI) operation according to an embodiment of the invention. 14A-14B are schematic diagrams of memory elements of a band-to-band tunneling induced hot hole (BTBT HH) implantation operation according to an embodiment of the invention. 15A-15B are schematic diagrams of memory elements of a FN (Fowler-Nordheim) hole injection operation, in accordance with an embodiment of the invention. 16A-16B are schematic diagrams of memory elements of an FN electron injection operation, in accordance with an embodiment of the invention.

The memory cells M1 and M2 can be programmed or erased by various methods. For example, the memory cells M1, M2 can be programmed by means of channel hot electron injection or energy banding for the thermal holes caused by tunneling. In addition, the memory cells M1 and M2 can perform the memory cell erasing operation by means of BTBT HH, FN electron injection or FN hole injection. Tables 1 through 3 list the three operating conditions for reading, stylizing, and erasing memory cells. It should be understood that the scope of the invention is not limited to the illustrated methods of operation and operating voltages.

Referring to Table 1, the methods for reading, stylizing, and erasing the memory cells in the operating condition 1 are, for example, reverse reading, channel hot electron injection, and hot hole injection by the band.

Table 1

Referring to Figure 12A, the structure of the memory element is as shown in Figure 1D or 6E above. 20a of the semiconductor stripe structure, for example, with the drain bit line BL ₁ (FIG. 11A or FIG. 11B) is connected, for example, the semiconductor stripe structure 20b is connected to bit line BL _3. The voltage applied to the global bit line GBL ₁ is supplied to the drain of the semiconductor strip structure 20a by turning on the bit line transistor BLT ₁ to select the bit line BL ₁ .

Referring to Table 1, FIG. 12A simultaneously, the operating condition of reading bit 1 (Bit 1) is, for example, applying a read bias to the source terminal of the selected semiconductor strip structure 20a (source voltage V _s =1.6V). a drain voltage V _d =0 V is applied to the drain and a gate voltage V _g =0-12 V is applied to the gate, and the base voltage V _b can be 0 V or a floating state; the unselected semiconductor strip structure 20 _b drain voltage V _d is a floating state (F), to sense the charge on the drain flanking sensing surface. Referring to FIG. 12B, the operation of reading bit 2 (Bit 2) is to apply a read bias to the drain terminal to sense the charge on the source side contact surface to complete the read operation.

Please refer to Table 1 and FIG. 13A at the same time. In operation condition 1, the memory cells are programmed by channel hot electron injection. The operating condition of the programming bit 1 is, for example, applying a gate voltage V _g =12 V to turn on the channel while applying a drain voltage of the intermediate level V _d =4 V, the source voltage V _s =0 V and the base voltage V _b = 0V/F to form an electric field from the source to the drain. When the bias between the source and the drain is relatively large, too much hot electrons are generated on the channel, and some of the hot electrons are injected into the gate for stylization. On the contrary, referring to FIG. 13B, the operating condition of the programming bit 2 is to apply an intermediate level of the source voltage V _s = 4 V to form an electric field from the drain to the source.

Referring to Table 1 and FIG. 14A at the same time, in the operating condition 1, the memory cell is erased by the hot hole injection method caused by the energy band. The operating condition for erasing the bit 1 is, for example, applying a gate voltage V _g = -8 V while applying a drain voltage V _d = 5 V. Under these bias conditions, charged carriers are injected into the charge storage layer 18 by the thermal hole injection caused by energy band tunneling to erase the bit 1. On the contrary, referring to FIG. 14B, the operating condition of the erase bit 2 is to apply the source voltage V _s = 5V.

Referring to Table 2, in the operating condition 2, the methods of reading, programming, and erasing the memory cells are, for example, reverse reading, channel hot electron injection, and FN hole injection, respectively.

Table 2

In the operating condition 2, the operation of stylizing in the manner of channel hot electron injection is as described above, and will not be described herein.

Referring to Table 2, FIG. 15A, and FIG. 15B simultaneously, in operation condition 2, the memory cell can be erased by +FN hole injection or -FN hole injection. Referring to FIG. 15A, the erase operation by the +FN hole injection method is performed, for example, by injecting a hole from the gate 22 to the charge storage layer 18. The operating conditions are, for example, applying a gate voltage V _g = 10 V while applying a drain voltage V _d = -10 V, a source voltage V _s = -10 V, a base voltage V _b = -10 V or floating to be at the source 12 A large electric field is formed between the drain 16 and the gate 22, so that the holes in the gate 22 can enter the charge storage layer 18 by the FN tunneling effect, thereby erasing the data. Referring to FIG. 15B, the erase operation by -FN hole injection is, for example, to inject a hole from the source 12, the substrate 14, and the drain 16 to the charge storage layer 18. The operating condition is, for example, applying a gate voltage V _g = -10 V while applying a drain voltage V _d = 10 V, a source voltage V _s = 10 V, a substrate voltage V _b = 10 V or floating, so that the source 12 and the substrate 14 And the holes in the drain 16 can enter the charge storage region 18 by the FN tunneling effect, thereby erasing the data.

Referring to Table 3, the methods for reading, stylizing, and erasing the memory cells in the operating condition 3 are, for example, reverse reading, thermal hole injection by the energy band, and FN electron injection, as shown in Table 3. Shown.

table 3

In the operating condition 3, the operation of staging the hot hole injection by the energy band can be erased by the method of operating the condition 1 to the hot hole injection caused by the band wear. The operation will not be repeated here.

Referring to Table 3, FIG. 16A and FIG. 16B simultaneously, in the operating condition 3, the memory cell can be erased by +FN electron injection or -FN electron injection. Referring to FIG. 16A, the erase operation by +FN electron injection is performed, for example, by injecting electrons from the source 12, the substrate 14, and the drain 16 to the charge storage layer 18. The operating conditions are, for example, applying a gate voltage V _g = 10 V while applying a drain voltage V _d = -10 V, a source voltage V _s = -10 V, a base voltage V _b = -10 V or floating to be at the source 12 A large electric field is formed between the drain 16 and the gate 22, so that electrons in the source 12, the substrate 14, and the drain 16 can enter the charge storage layer 18 by the FN tunneling effect, thereby erasing the data. Referring to FIG. 16B, in contrast, the erase operation by the -FN electron injection method causes electrons to be injected from the gate 22 to the charge storage layer 18, for example. The operating condition is, for example, applying a gate voltage V _g = -10 V while applying a gate voltage V _d = 10 V, a source voltage V _s = 10 V, a substrate voltage V _b = 10 V or floating, so that electrons are injected from the gate 22 . To the charge storage layer 18.

In addition, the above FN hole injection and FN electron injection operations, in addition to the data that can be used to erase the memory, before the memory cell is subjected to the above-described stylization or erasing operation, the threshold voltage of the memory cell (threshold voltage) , Vt) FN holes or electron injection methods can be used to adjust the starting voltage to meet the desired target value due to process variation or other factors. In an embodiment, the starting voltage can be boosted by FN electron injection. In another embodiment, the starting voltage can be reduced by FN hole injection.

In summary, the present invention can electrically connect the source in each semiconductor strip structure by a first contact window. In this way, the relative relationship between the vertical memory elements and the structure of the stacked structure can be greatly simplified, the original operating efficiency can be maintained, and the existing processes are compatible. And, a voltage can be applied to the substrate by the third wire to control the potential of the substrate. In this way, the potential of the substrate can be clearly known, and the potential of the substrate is prevented from being in a floating state by the coupling effect of other biases.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧Base
12,16‧‧‧Doped area
Section 12a, 12b‧‧‧
12c‧‧‧Doped layer
14‧‧‧basal area
14c‧‧‧ base layer
16c‧‧‧Doped layer
18‧‧‧Charge storage layer
20, 20a‧‧‧Semiconductor strip structure
22‧‧‧ character line
24‧‧‧ spacer
26, 30, 32‧‧‧ dielectric layer
28‧‧‧ lining
42, 44, 46, 61a, 61b, 61c‧‧‧ contact windows
42a, 44a, 46a, 60a, 60b, 60c‧‧‧ contact window openings
52, 56, 72a, 72b, 74a, 74b, 76‧‧‧ wires
54‧‧‧Local wire
100,200‧‧‧ memory components
301, 302‧‧‧ memory strings
B1, B2‧‧‧ blocks
BdL‧‧‧ base line
BdLT‧‧‧ base wire transistor
BL ₁ ~BL _n ‧‧‧ bit line
BLT ₁ ~BLT _n ‧‧‧ bit line transistor
D1, D2‧‧‧ direction
GBL ₁ , GBL ₂ ‧‧‧ global bit line
M1, M2‧‧‧ memory cells
R1, R2‧‧‧
S1, S2‧‧‧ top
SL‧‧‧ source line
SLT‧‧‧ source line transistor
T‧‧‧ Ditch
V ₁ , V ₂ , V _n , V _d , V _g , V _s , V _b ‧‧‧ voltage
WL ₁ ~ WL _2m ‧‧‧ character line

1A through 1D are schematic top views of a method of fabricating a memory device in accordance with a first embodiment of the present invention. 2A to 2D are schematic cross-sectional views taken along line A-A' of Figs. 1A to 1D, respectively. 3A to 3D are schematic cross-sectional views taken along line B-B' of Figs. 1A to 1D, respectively. 4A to 4D are schematic cross-sectional views taken along line C-C' of Figs. 1A to 1D, respectively. 5A to 5D are schematic cross-sectional views taken along line D-D' of Figs. 1A to 1D, respectively. 6A-6E are top schematic views showing a manufacturing process of a memory element according to a second embodiment of the present invention. 7A to 7E are schematic cross-sectional views taken along line A-A' of Figs. 6A to 6E, respectively. 8A to 8E are schematic cross-sectional views taken along line B-B' of Figs. 6A to 6E, respectively. 9A to 9E are schematic cross-sectional views taken along line C-C' of Figs. 6A to 6E, respectively. 10A to 10E are schematic cross-sectional views taken along line E-E' of Figs. 6A to 6E, respectively. FIG. 11A is a schematic diagram of a memory array structure according to a first embodiment of the present invention. FIG. 11B is a schematic diagram of a memory array structure according to a second embodiment of the present invention. 12A-12B are schematic diagrams of memory elements of a reverse read (RR) operation, in accordance with an embodiment of the invention. 13A-13B are schematic diagrams of memory elements of a channel hot electron injection (CHEI) operation, in accordance with an embodiment of the invention. 14A-14B are schematic diagrams of memory elements of a band-to-band through-hole thermal hole injection (BTBT HH) operation, in accordance with an embodiment of the invention. 15A-15B are schematic diagrams of memory elements of an FN hole injection operation according to an embodiment of the invention. 16A-16B are schematic diagrams of memory elements of an FN electron injection operation, in accordance with an embodiment of the invention.

10‧‧‧Base

12,16‧‧‧Doped area

Section 12a, 12b‧‧‧

14‧‧‧basal area

18‧‧‧Charge storage layer

20‧‧‧Semiconductor strip structure

24‧‧‧ spacer

26‧‧‧Dielectric layer

42, 44‧‧‧Contact window

42a, 44a‧‧‧Contact window opening

72a, 74a‧‧‧ wires

Claims (14)

A memory element comprising: a substrate comprising a plurality of first blocks and a plurality of second blocks, the first blocks and the second blocks alternate, each first block comprising two a first region and a second region, the second region being located between the two first regions; a plurality of semiconductor strip structures on the substrate, wherein each semiconductor strip structure is along a first direction Extending; a first doped region comprising a plurality of first portions and a second portion, each first portion being located at a lower portion of the corresponding semiconductor strip structure, the second portion being located on a surface of the substrate, the first portions Connected to the second portion; a plurality of second doped regions, each second doped region being located at an upper portion of the corresponding semiconductor strip structure; a plurality of word lines located at the base of each of the first regions Each of the word lines extends along a second direction to cover a portion of the sidewalls and a portion of the top portions of the plurality of semiconductor strip structures, the first direction being different from the second direction; a charge storage layer located in the semiconductors Strip structure and some A plurality of first contact windows are disposed in the second block and the second regions, and are arranged along the first direction, and each of the first contact windows is electrically connected to the first doped region The second contact portion is located at least in the second regions, and each of the second contact windows is electrically connected to the corresponding second doped region; a first wire is located on the substrate The first wire extends along the first direction and is electrically connected to the first contact windows; and a plurality of second wires are located on the substrate, and each of the second wires extends along the first direction. And electrically connected to the corresponding second contact windows on the semiconductor strip structure. The memory device of claim 1, wherein: each of the semiconductor strip structures has a base region, the second doped region in the semiconductor strip structure and the first doped region Between the portions; and in the second blocks, the second contact windows are further included. The memory device of claim 1, wherein: the plurality of trenches have a trench in the second block, the trench extends along the second direction; and each of the semiconductor strip structures has a substrate region, wherein And in the first block, the base region is located between the second doped region and the first portion of the first doped region; and in the second block, the base region is located at the first block The first portion of a doped region, and the trench exposes the substrate region. The memory device of claim 3, further comprising: a plurality of third contact windows respectively located in the second blocks, the third contact window extending along the second direction, and the third contact The window is electrically connected to the exposed base regions of the trench; and a third wire is disposed on the substrate, extending along the first direction, and electrically connected to the third contact windows. The memory device of claim 4, further comprising: a plurality of partial wires, the first blocks located on opposite sides of the third contact window, each of the partial wires extending along the first direction, And electrically connected to the corresponding second contact windows on the semiconductor strip structure, and each of the second wires is located above the corresponding partial wires on the corresponding semiconductor strip structure and spans the first The three contact windows are electrically connected to the corresponding partial wires via a plurality of fourth contact windows. A method of manufacturing a memory device, comprising: providing a substrate comprising a plurality of first blocks and a plurality of second blocks, wherein the first blocks and the second blocks alternate with each other The block includes two first regions and a second region, the second region being located between the two first regions; forming a plurality of semiconductor strip structures on the substrate, wherein each of the semiconductor strip structures Extending in a first direction; forming a first doped region, the first doped region comprising a plurality of first portions and a second portion, each first portion being located at a lower portion of the corresponding semiconductor strip structure, the Two portions are located on a surface of the substrate, and the first portions are connected to the second portion; a plurality of second doped regions are formed on an upper portion of each of the semiconductor strip structures; a plurality of word lines are formed, each On the substrate of the first region, each word line extends along a second direction to cover a portion of the sidewalls and a portion of the top portions of the plurality of semiconductor strip structures, the first direction being different from the second direction; forming a charge Storage layer, for these Between the conductor strip structure and the word lines; forming a plurality of first contact windows, in the second blocks and the second regions, arranged along the first direction, each first contact window Electrically connecting the second portion of the first doped region; forming a plurality of second contact windows, at least in the second regions, each second contact window electrically connecting the corresponding second doped region Forming a first wire on the substrate, the first wire extending along the first direction and electrically connected to the first contact windows; and forming a plurality of second wires on the substrate A second wire extends along the first direction and is electrically connected to the corresponding second contact window on the semiconductor strip structure. The method of fabricating a memory device according to claim 6, wherein the method of forming the semiconductor strip structures, the first doped regions and the second doped regions comprises: patterning a portion of the substrate to Forming the semiconductor strip structures; performing an ion implantation process to implant dopants on the upper portion of each of the semiconductor strip structures and the surface of the substrate; and performing a thermal tempering process to cause the dopants Forming the first doped region and the second doped regions. The method of manufacturing the memory device of claim 6, further comprising: removing portions of the semiconductor strip structures in the second blocks to form a trench extending along the second direction The trench exposes the matrix regions of the corresponding semiconductor strip structures. The method of manufacturing the memory device of claim 8, further comprising: forming a plurality of third contact windows, wherein each of the second blocks extends along the second direction, and Each of the third contact windows is electrically connected to the exposed base regions of the trench; and a third wire is formed on the substrate, the third wire extends along the first direction, and the third contact window Electrical connection. The method for manufacturing a memory device according to claim 9, further comprising: forming a plurality of partial wires, wherein each of the partial wires extends along the first direction and corresponds to The second contact windows on the semiconductor strip structure are electrically connected, and each of the second wires is located above the corresponding partial wires on the corresponding semiconductor strip structure and spans the third contact windows. And electrically connected to the corresponding partial wires via a plurality of fourth contact windows. A memory array comprising the memory element according to any one of claims 1 to 5, wherein the memory array comprises: a plurality of memory cells arranged in an array of a plurality of rows and a plurality of columns, the memory cells comprising a first doped region of the source and the second doped regions as a drain; a plurality of bit lines, each bit line coupled to the second of the memory cells of the same row a plurality of common source lines, each common source line being coupled to the first doped region of the memory cells of the same column; and a source line coupled to the common source lines And electrically connecting to the first doped region of the memory cells, wherein each word line is coupled to a plurality of gates of the memory cells of the same column. The memory array of claim 11, further comprising a base line coupled to a plurality of base regions of the memory cells. A method of operating a memory array according to any one of claims 11 to 12, the method comprising: selecting at least one memory cell; applying a first voltage to a selected memory cell a word line; applying a second voltage to a bit line corresponding to the selected memory cell; and applying a third voltage to the source line of the memory array. An operation method as described in claim 13 further comprising applying a fourth voltage to the base line corresponding to the selected memory cell.