TWI611514B - Fuse elements and methods for forming the same - Google Patents

Abstract

The fuse element includes a metal layer disposed on the substrate, the metal layer includes an intermediate section, a first block, and a second block, and the first block and the second block are electrically connected to both ends of the intermediate section, respectively. The fuse element also includes a dielectric layer overlying the intermediate section, the first and second blocks, a first passivation layer disposed on the dielectric layer, and a second passivation layer disposed on the first passivation layer a first and a second passivation layer and a portion of the dielectric layer, and an opening above the intermediate portion, and a protective film disposed on the bottom of the opening and a portion of the sidewall and covering the first passivation layer exposed by the opening .

Description

Fuse element and method of forming same

The present invention relates to a fuse element in a semiconductor device, and more particularly to a fuse element having a protective film and a method of forming the same.

In the fabrication of semiconductor devices, defects in any of the transistors or diodes in an integrated circuit (IC) tend to cause failure of the overall wafer. In general, densely packed integrated circuits tend to generate more defects internally than stacked loose integrated circuits. Therefore, as the size of the semiconductor device becomes smaller and smaller, and the stack of the integrated circuit becomes denser and denser, the process yield of the wafer is greatly reduced.

In order to solve this problem, some redundant circuits connected to the fuse elements may be added to the semiconductor device. If the circuit is found to be defective after the end of the process of the semiconductor device, the fuse element can be used to replace the defective circuit with a backup circuit.

Although currently existing fuse elements and their formation methods are sufficient for their intended use, they are not fully compliant in all respects, so the technology of fuse elements in semiconductor devices still has a need for efforts. .

The present disclosure provides an embodiment of a fuse element and its formation law. The fuse element of the present disclosure provides an opening through the first passivation layer, the second passivation layer and a portion of the dielectric layer over the intermediate portion of the metal layer (also referred to as the fuse portion of the fuse element) When the laser is used to blow down the middle section, the energy of the laser can be precisely controlled to align with the middle section without damaging nearby components. On the other hand, since the opening above the middle portion of the metal layer exposes a portion of the dielectric layer, in order to prevent the dielectric layer of this portion from reacting with the outside water, the present disclosure provides some embodiments in which further openings are formed. The protective film improves the ability of the fuse element to resist moisture, thereby increasing the life of the fuse element.

According to some embodiments, a fuse element is provided. The fuse element comprises a metal layer disposed on the substrate, the metal layer comprising an intermediate section, a first block and a second block, and the first block and the second block are electrically connected to both ends of the intermediate section, respectively. The fuse element also includes a dielectric layer overlying the intermediate section, the first block, and the second block. The fuse element further includes a first passivation layer disposed on the dielectric layer, and a second passivation layer disposed on the first passivation layer. In addition, the fuse element includes an opening through the first passivation layer and the second passivation layer and a portion of the dielectric layer, and is located above the intermediate portion, and the protective film is disposed on the bottom of the opening and a portion of the sidewall, and covers the opening The first passivation layer exposed.

According to some embodiments, a method of forming a fuse element is provided. The method for forming a fuse element comprises forming a metal layer on a substrate, the metal layer comprising an intermediate segment, a first block and a second block, and the first block and the second block are electrically connected to the middle portion respectively End. The method of forming the fuse element also includes forming a dielectric layer overlying the intermediate section, the first block, and the second block. The method of forming the fuse element further comprises forming a first passivation layer on the dielectric layer And forming a second passivation layer on the first passivation layer. In addition, the method of forming the fuse element includes forming an opening over the intermediate portion of the metal layer, the opening passing through the first passivation layer and the second passivation layer and a portion of the dielectric layer, and forming a protective film at the bottom of the opening and a portion The sidewalls of the portions cover the first passivation layer exposed by the openings.

100,200‧‧‧Fuse components

101‧‧‧Base

103, 107‧‧‧ dielectric layer

105, 105'‧‧‧ metal layer

105a‧‧‧First block

105b‧‧‧ Middle section

105c, 105d‧‧‧Second block

109a‧‧‧First guide hole

109b, 109c‧‧‧ second guide hole

111a‧‧‧First conductive pad

111b‧‧‧Second conductive pad

113‧‧‧First passivation layer

115‧‧‧Second passivation layer

117a, 117b‧‧‧ patterned photoresist layer

119‧‧‧ trench

120‧‧‧ openings

125, 225‧‧ ‧ protective film

130a, 230a‧‧‧ first hole

130b, 230b‧‧‧ second hole

We can better understand the point of view of the disclosure by the following detailed description in conjunction with the accompanying drawings. It is worth noting that some features may not be drawn to scale according to industry standard practice. In fact, the dimensions of different features may be increased or decreased for clarity of discussion.

1A-1I are schematic cross-sectional views showing different stages of forming a fuse element in accordance with some embodiments of the present disclosure; and FIGS. 2A-2B are diagrams showing different stages of forming a fuse element in accordance with further embodiments of the present disclosure. Schematic diagram of the section.

The following disclosure provides many different embodiments or examples for implementing the fuse elements of the provided semiconductor devices. Specific examples of the components and their configurations are described below to simplify the disclosure. Of course, these are merely examples and are not intended to limit the disclosure. For example, a reference to a first component formed over a second component in the description may include embodiments in which the first and second components are in direct contact, and may also include additional components formed between the first component and the second component. Embodiments that make them in direct contact. Furthermore, the disclosure may repeat reference numerals and/or letters in different examples. This repetition is for the sake of brevity and clarity, and is not intended to represent the various embodiments discussed and/or Or the relationship between forms.

Some variations of the embodiments are described below. In the different figures and illustrated embodiments, like reference numerals have been used to It will be appreciated that additional operations may be provided before, during, and after the method, and that some of the recited operations may be substituted or deleted for other embodiments of the method.

The present disclosure provides an embodiment of forming a fuse element. 1A-1I is a cross-sectional view showing the different stages of forming the fuse element 100 shown in FIG. 1 in accordance with some embodiments of the present disclosure.

According to some embodiments, as shown in FIG. 1A, a dielectric layer 103 is formed on the substrate 101, and a metal layer 105 is formed on the dielectric layer 103. The substrate 101 may be made of tantalum or other semiconductor material, or the substrate 101 may comprise other elemental semiconductor materials such as germanium (Ge). In some embodiments, substrate 101 can be made of a compound semiconductor, such as tantalum carbide, gallium nitride, gallium arsenide, indium arsenide, or indium phosphide. In some embodiments, substrate 101 is made of an alloy semiconductor such as germanium, tantalum carbide, gallium arsenide or indium gallium phosphide. In some embodiments, substrate 101 comprises a silicon-on-insulator (SOI) substrate. In some embodiments, substrate 101 comprises an epitaxial layer. For example, substrate 101 has an epitaxial layer overlying the bulk semiconductor. In some embodiments, substrate 101 can be a lightly doped P-type or N-type substrate.

In some embodiments, the dielectric layer 103 may be made of tantalum oxide, tantalum nitride, hafnium oxynitride or other suitable dielectric material, and the metal layer 105 may be aluminum, copper, nickel, tungsten, other suitable metallic materials or Combination of the foregoing Made. In other embodiments, the metal layer 105 is not limited to a metallic material and may be made of other conductive materials (eg, depositing an amorphous germanium, which is recrystallized to produce polycrystalline germanium).

In some embodiments, the dielectric layer 103 and the metal layer 105 are chemical vapor deposition (CVD), low-pressure CVD (LPCVD), and plasma enhanced chemical vapor. Plasma enhanced CVD (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD), spin coating, other suitable processes, or the foregoing The combination is formed.

Following the foregoing, as shown in Fig. 1B, the metal layer 105 is patterned to form a metal layer 105' comprising a first block 105a, a middle segment 105b, and second blocks 105c and 105d. It should be noted that the intermediate section 105b is disposed between the first block 105a and the second block 105c and 105d, and the first block 105a and the second block 105c and 105d are electrically connected to the intermediate section 105d, respectively. Both ends. Although the first block illustrated in FIG. 1B is composed of one block 105a and the second block is composed of two blocks 105c and 105d, in other embodiments, the first block and the second block may be of other numbers. Block composition. In some embodiments, after the photoresist layer (not shown) is disposed on the metal layer 105 by a spin coating process, the photoresist layer is exposed and developed to form a patterned photoresist layer of a desired pattern (not drawn) Show). Next, the pattern of the patterned photoresist layer is transferred to the underlying metal layer 105 to form a metal layer 105'. In some embodiments, an anisotropic etching process, such as reactive ion etch (RIE), may be utilized. The exposed and unprotected metal layer 105 is removed while using the patterned photoresist layer as a mask, thereby forming a first block 105a, a middle segment 105b, and a second on the substrate 101 and the dielectric layer 103. Metal layers 105' of blocks 105c and 105d.

According to some embodiments, as shown in FIG. 1C, a dielectric layer 107 is formed on the dielectric layer 103, and the dielectric layer 107 covers the dielectric layer 103 including the first block 105a, the middle segment 105b, and the second block. Metal layers 105' of 105c and 105d. The material and process of the dielectric layer 107 are the same or similar to the dielectric layer 103, and will not be described herein.

Next, referring to FIG. 1C, a first via hole 109a and second via holes 109b and 109c are formed in the dielectric layer 107. In some embodiments, the first guiding hole 109a is disposed above the first block 105a and electrically connected to the first block 105a, and the second guiding hole 109b is disposed above the second block 105c, and The second block 105c is electrically connected, and the other second guiding hole 109b is disposed above the other second block 105d and electrically connected to the second block 105d.

The method of forming the first via holes 109a and the second via holes 109b and 109c includes forming a plurality of holes in the dielectric layer 107, the holes passing through the dielectric layer 107 and exposing the first block 105a and the second block, respectively. 105c and 105d, then, a conductive material is filled into the holes, and a planarization process, such as a chemical mechanical polishing (CMP) process, is performed to remove the conductive material outside the holes and on the dielectric layer 107.

In addition, the first via hole 109a and the second via hole 109b and 109c may be made of aluminum, copper, nickel, tungsten, other suitable metallic materials, or a combination of the foregoing. In some embodiments, the first via 109a and the second vias 109b and 109c may be made of a different material than the first block 105a, the intermediate segment 105b, and the second blocks 105c and 105d, for example, the first guide The hole 109a and the second pilot holes 109b and 109c are made of tungsten, and the first block 105a, the intermediate section 105b, and the second blocks 105c and 105d are made of an aluminum-copper alloy.

According to some embodiments, as shown in FIG. 1D, a first conductive pad 111a and a second conductive pad 111b are formed on the dielectric layer 107, and the first conductive pad 111a and the second conductive pad 111b are respectively located in the first block 105a. And above the second blocks 105c and 105d. In some embodiments, a conductive layer (not shown) and a mask layer (not shown) may be deposited on the dielectric layer 107. Then, the lithography process and the etching process are performed to pattern the mask layer, and then the pattern of the patterned mask layer is transferred to the conductive layer by an etching process to form the first conductive pad 111a and the second conductive pad 111b.

It should be noted that the first via hole 109a is electrically connected to the first conductive pad 111a and the first block 105a, and the second via holes 109b and 109c are electrically connected to the second conductive pad 111b and the second block 105c and 105d. On the other hand, the intermediate section 105b is completely covered by the dielectric layer 107, and no via holes and conductive pads are formed on the intermediate section 105b.

According to some embodiments, as shown in FIG. 1E, a first passivation layer 113 is formed on top surfaces and sidewalls of the first conductive pad 111a and the second conductive pad 111b, and the first passivation layer 113 extends to the first conductive pad 111a. And a dielectric layer 107 between the second conductive pad 111b. In some embodiments, the first The passivation layer 113 may be made of tantalum oxide, tantalum nitride, hafnium oxynitride or other suitable materials. In addition, the first passivation layer 113 is by chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), physics. Formed by vapor deposition (PVD), spin coating, other suitable processes, or a combination of the foregoing.

Next, referring to FIG. 1E, a second passivation layer 115 is formed on the first passivation layer 113. Specifically, the second passivation layer is conformally formed on the first passivation layer 113. In some embodiments, the material and process of the second passivation layer 115 are the same or similar to the first passivation layer 113, and are not described herein. In the present embodiment, the first passivation layer 113 is formed of hafnium oxide, and the second passivation layer 115 is formed of tantalum nitride.

According to some embodiments, as shown in FIG. 1F, patterned photoresist layers 117a and 117b are formed on the second passivation layer 115. The step of forming the patterned photoresist layers 117a and 117b includes first forming a photoresist layer (not shown) on the second passivation layer 115, and patterning the photoresist layer by a lithography process. The lithography process includes photoresist coating (eg, spin coating), soft baking, mask alignment, exposure, post-exposure bake, photoresist development, washing and drying (eg, hard bake).

More specifically, the patterned photoresist layer 117a is located above the first conductive pad 111a and covers the second passivation layer 115 on the sidewall of the first conductive pad 111a, and the patterned photoresist layer 117b is located at the first The upper surface of the second conductive pad 111b covers the second passivation layer 115 on the sidewall of the second conductive pad 111b. In other words, the patterned photoresist layer 117a covers and directly contacts the second passivation layer 115 on the top surface and sidewalls of the first conductive pad 111a, and the patterned photoresist layer 117b covers and directly contacts the second conductive pad. A second passivation layer 115 on the top surface and sidewalls of 111b.

In addition, the patterned photoresist layers 117a and 117b do not cover the second passivation layer 115 above the intermediate portion 105b, that is, there are trenches 119 between the patterned photoresist layers 117a and 117b, and the trenches 119 are located at the intermediate portion 105b. Above. In other embodiments, the patterned photoresist layers 117a and 117b may not extend onto the second passivation layer 115 on the sidewalls of the first conductive pad 111a and the second conductive pad 111b, that is, the patterned photoresist layer 117a and 117b may be on only the top surface of the second passivation layer 115 without having a downwardly extending portion.

Following the foregoing, as shown in FIG. 1G, with the patterned photoresist layers 117a and 117b as masks, an etching process is performed to remove portions of the first passivation layer 113 and portions of the second passivation layer above the intermediate portion 105b. 115 and a portion of the dielectric layer 107 to form an opening 120 that does not expose the intermediate portion 105b. In other words, the opening 120 passes through the first passivation layer 113, the second passivation layer 115, and a portion of the dielectric layer 107, and a portion of the dielectric layer 107 is located between the opening 120 and the intermediate portion 105b.

According to some embodiments, as shown in FIG. 1H, a protective film 125 is formed on the bottom and a portion of the sidewall of the opening 120, and the protective film 125 covers the first passivation layer 113 exposed by the opening 120. In other words, the protective film 125 covers the dielectric layer 107 and the first passivation layer 113 exposed by the opening 120, but does not cover the second passivation layer 115. In the present embodiment, the protective film 125 is formed by a nitrogen heat treatment process. At a high temperature, a dielectric layer 107 containing yttria and a first passivation layer 113 containing yttrium oxide exposed by the nitrogen and the opening 120 are introduced. Performing a reaction at the bottom and one of the openings 120 A thin protective film 125 containing bismuth oxynitride is formed on the side walls of the minute. In some embodiments, the temperature of the nitrogen heat treatment process is in the range of from about 300 °C to about 700 °C. In this embodiment, nitrogen does not react with the second passivation layer 115 containing tantalum nitride.

Then, as shown in FIG. 1I, the first hole 130a and the second hole 130b are formed through the first passivation layer 113 and the second passivation layer 115, and the first hole 130a and the second hole 130b are respectively located on the first conductive pad 111a. And the second conductive pad 111b. The first hole 130a and the second hole 130b may be formed by an etching process. After forming the first hole 130a and the second hole 130b, the fuse element 100 is completed. In addition, the first conductive pad 111a and the second conductive pad 111b are electrically connected to the external circuit through the first hole 130a and the second hole 130b, respectively.

2A-2B are cross-sectional schematic views showing different stages of forming fuse element 200 in accordance with further embodiments of the present disclosure. The 2A picture is the process of continuing the 1G picture.

Next, as shown in FIG. 2A, after the opening 120 is formed, the protective film 225 is conformally formed on the second passivation layer 115 and on the sidewalls and the bottom of the opening 120. In the present embodiment, the protective film 225 contains tantalum nitride and is formed by a chemical vapor deposition (CVD) process. In other embodiments, the protective film 225 may comprise other water repellent materials, such as: Si ₃ N _4, SiON, or a combination of the foregoing.

Then, as shown in FIG. 2B, the first passivation layer 113, the second passivation layer 115, and the protective film 225 are passed through to form the first hole 230a and the second hole 230b, and the first hole 230a and the second hole 230b are respectively located. First A conductive pad 111a and a second conductive pad 111b. The first hole 230a and the second hole 230b may be formed by an etching process. After the first hole 230a and the second hole 230b are formed, the process of the fuse element 200 is completed. In addition, the first conductive pad 111a and the second conductive pad 111b are electrically connected to the external circuit through the first hole 230a and the second hole 230b, respectively.

The fuse element 100 of FIG. 1I differs from the fuse element 200 of FIG. 2B in the material, position, and thickness of the protective film 125 and the protective film 225. The protective film 225 of the fuse element 200 covers the second passivation layer 115 exposed by the sidewalls of the opening 120 and extends to the second passivation layer 115 outside the opening 120, compared to the protective film 125 of the fuse element 100. Further, the thickness of the protective film 225 is larger than the thickness of the protective film 125. In general, since the protective film 225 of the fuse element 200 has a wide coverage and a large thickness, its water vapor resistance is better, and the protective film 125 has a smaller thickness. When the intermediate section 105b is subjected to the laser sintering process in the subsequent application, the lower energy laser can be used without more damage to the nearby components, and the energy of the laser can be more accurately controlled to be aligned with the intermediate section 105b.

The metal component of the present disclosure is disposed through the first passivation layer, the second passivation layer, and a portion of the dielectric layer over the intermediate portion of the metal layer, but does not expose the opening of the intermediate portion. Since there is only a part of the thin dielectric layer above the middle section, the laser beam melting process can be used in the subsequent middle section, and the lower energy laser can be used without accurately destroying the nearby components. The energy of the control laser is directed at the middle section. In another aspect, the fuse element of the present disclosure further forms a protective film thinner than the first and second passivation layers in the opening above the middle portion of the metal layer to prevent the opening from being exposed. The dielectric layer above the middle section reacts with the outside water vapor, thereby improving the ability of the fuse element to resist moisture and increasing the life of the fuse element.

The above summary of the several embodiments is characterized in that the subject matter of the present disclosure can be more fully understood by those of ordinary skill in the art. Those having ordinary skill in the art should understand that they can design or modify other processes and structures based on the present disclosure to achieve the same objects and/or advantages as the embodiments described herein. It is also to be understood by those of ordinary skill in the art that the present invention is not limited to the spirit and scope of the disclosure, and that they can be practiced without departing from the spirit and scope of the disclosure. Various changes, substitutions and substitutions.

100‧‧‧Fuse components

101‧‧‧Base

103, 107‧‧‧ dielectric layer

105a‧‧‧First block

105b‧‧‧ Middle section

105c, 105d‧‧‧Second block

109a‧‧‧First guide hole

109b, 109c‧‧‧ second guide hole

111a‧‧‧First conductive pad

111b‧‧‧Second conductive pad

113‧‧‧First passivation layer

115‧‧‧Second passivation layer

120‧‧‧ openings

125‧‧‧Protective film

130a‧‧‧First hole

130b‧‧‧Second hole

Claims (20)

A fuse element comprising: a metal layer disposed on a substrate, wherein the metal layer comprises an intermediate segment, a first block and a second block, and the first block and the second block Electrically connected to the two ends of the intermediate section; a dielectric layer covering the intermediate section, the first block and the second block; a first passivation layer disposed on the dielectric layer; a second passivation layer disposed on the first passivation layer; an opening passing through the first passivation layer and the second passivation layer and a portion of the dielectric layer, and located above the intermediate portion; and a protective film And disposed on the bottom of the opening and a portion of the sidewall, and covering the first passivation layer exposed by the opening. The fuse element of claim 1, wherein the opening does not expose the intermediate section. The fuse element of claim 1, wherein the first passivation layer is tantalum oxide and the second passivation layer is tantalum nitride. The fuse element of claim 1, further comprising: a first conductive pad and a second conductive pad disposed on the dielectric layer and located in the first block and the second block respectively Upper, wherein the first passivation layer covers the top surface and the sidewall of the first conductive pad and the second conductive pad. The fuse element of claim 4, further comprising: a first via hole disposed in the dielectric layer, electrically connecting the first conductive pad and the first block; and a second a via hole disposed in the dielectric layer, electrically connecting the second conductive pad and The second block. The fuse element of claim 1, wherein the protective film covers the dielectric layer exposed by the opening, and the second passivation layer is not covered. The fuse element of claim 6, wherein the protective film is bismuth oxynitride. The fuse element of claim 4, further comprising: a first hole and a second hole respectively located on the first conductive pad and the second conductive pad, and passing through the first passivation layer and The second passivation layer. The fuse element of claim 1, wherein the protective film further covers the second passivation layer. The fuse element of claim 9, wherein the protective film is tantalum nitride. The fuse element of claim 4, further comprising: a first hole and a second hole respectively located on the first conductive pad and the second conductive pad, and passing through the first passivation layer, The second passivation layer and the protective film. A method of forming a fuse element, comprising: forming a metal layer on a substrate, wherein the metal layer comprises a middle segment, a first block and a second block, and the first block and the second block The blocks are electrically connected to the two ends of the intermediate segment respectively; a dielectric layer is formed to cover the intermediate segment, the first block and the second block; and a first passivation layer is formed on the dielectric layer Forming a second passivation layer on the first passivation layer; Forming an opening above the intermediate segment, wherein the opening passes through the first passivation layer and the second passivation layer and a portion of the dielectric layer; and forming a protective film on the bottom of the opening and a portion of the sidewall And covering the first passivation layer exposed by the opening. The method for forming a fuse element according to claim 12, further comprising: forming a first conductive pad and a second conductive pad on the dielectric layer, and respectively located in the first block and the first Above the two blocks, the first passivation layer covers the top surface and sidewalls of the first conductive pad and the second conductive pad. The method of forming a fuse element according to claim 13, wherein the forming the opening comprises: forming a patterned photoresist layer on the second passivation layer; and using the patterned photoresist layer For masking, the first passivation layer, portions of the second passivation layer, and portions of the dielectric layer over portions of the intermediate segment are etched away to form the opening that does not expose the intermediate segment. The method of forming a fuse element according to claim 14, wherein the patterned photoresist layer further covers the second passivation layer on sidewalls of the first conductive pad and the second conductive pad. The method of forming a fuse element according to claim 12, wherein the step of forming the protective film comprises a nitrogen heat treatment process, and the protective film does not cover the second passivation layer. The method for forming a fuse element according to claim 13 , further comprising: forming a first hole and a second hole through the first passivation layer and the second A passivation layer is disposed on the first conductive pad and the second conductive pad, respectively. The method of forming a fuse element according to claim 12, wherein the step of forming the protective film comprises a chemical vapor deposition process, and the protective film further covers the second passivation layer. The method for forming a fuse element according to claim 13 , further comprising: forming a first hole and a second hole through the first passivation layer, the second passivation layer and the protective film, respectively Located on the first conductive pad and the second conductive pad. The method for forming a fuse element according to claim 13 , further comprising: forming a first via hole in the dielectric layer, electrically connecting the first conductive pad and the first block; and forming A second via is electrically connected to the second conductive pad and the second block in the dielectric layer.