TWI609474B - Electrostatic Discharge Protective Circuit and Electrostatic Discharge Protective Deep Submicron Device Thereof - Google Patents

Description

Electrostatic discharge protection circuit and its electrostatic discharge protected deep submicron semiconductor element

The present invention is a deep submicron semiconductor component, and more particularly an electrostatic discharge protected deep submicron semiconductor component.

Since the internal components of the integrated circuit are easily damaged by electrostatic discharge, the electrostatic discharge protection engineering is particularly important for the integrated circuit. Referring to FIG. 6, since the static electricity is easily discharged through the input/output pad 52 of the integrated circuit 50 to the internal component 51, an electrostatic discharge protection circuit 511 is disposed on each of the input/output pads 52, mainly including mutual strings. Connected to a PMOS device MP and an NMOS device MN; wherein the series connection node of the PMOS device MP and the NMOS device MN is connected to the corresponding input/output pad 52, and the gate G and the source S of the PMOS device MP are connected to the system power supply The high potential terminal VDD, and the gate G and the source S of the NMOS device are connected to the low potential terminal VSS of the system power supply.

Referring to FIG. 7A and FIG. 7B, the semiconductor structure of the NMOS device MN of the ESD protection circuit 511 is formed by forming a gate structure 60 on the upper surface of a P-type well 501 of a P-type semiconductor substrate 500. Then, the gate structure 60 is used as a mask to form an n-light doped region 62 to the P-well 501. Thereafter, a gate insulating layer sidewall 61 is formed on both outer sides of the gate structure 60, and then The gate structure 60 and the gate insulating layer sidewall 61 serve as a shadow mask to form an N+ heavily doped region 63 toward the P-type well; therefore, the junction of the adjacent n-light doped region 62 and the N+ heavily doped region 63 Will be with the nearest gate insulation sidewall 61 cuts. The lower side of the gate structure 20 of the NMOS device MN is formed with an n-light doped region 62 and an N+ doped region 63, respectively, for use as the drain S and the source D of the NMOS device.

Since the NMOS device MN is connected to the input/output pad 52, in order to protect the internal internal circuit 51 from electrostatic damage, when the electrostatic input contacts the input/output pad 52, the conduction speed is higher than the component conduction speed of the internal circuit 11. Faster to discharge the ESD current to the low potential VSS of the system power supply to achieve ESD protection. Therefore, in order to speed up the conduction speed of the NMOS device MN, a metal germanide layer 64 is formed on the upper surface of each of the N+ heavily doped regions 63 to provide a low contact resistance and increase the operation rate.

However, as semiconductor technology evolves, components of integrated circuits shrink from micron size to deep submicron size (MOS gate width is less than 0.18um), although integrated circuits thus increase component integration, but also because The deep submicron integrated circuit layout rule (VLSI layout rule) is relatively narrow, so that the distance between the drain and the source of the PMOS and NMOS components of the ESD protection circuit is too close, resulting in weakened antistatic capability; The size of the NMOS device is reduced, and the electrostatic discharge current is more likely to pass through the surface channels of the PMOS and NMOS devices, thereby burning the PMOS and NMOS devices.

Therefore, the deep sub-micron components of the electrostatic discharge protection circuit of the integrated circuit need to further improve the electrostatic discharge tolerance and avoid electrostatic damage.

In view of the current shortcomings of insufficient electrostatic discharge resistance of deep submicron elements for electrostatic protection, the main object of the present invention is to provide an electrostatic discharge protection circuit and an electrostatic discharge protected deep submicron semiconductor element.

The main technical means for achieving the above purpose is that the deep submicron element with electrostatic discharge protection comprises: a gate structure formed on a semiconductor substrate; The sidewalls of the two gate insulating layers are respectively formed on two opposite outer sides of the gate structure; the two lightly doped regions are respectively formed in the semiconductor substrate and are respectively located under the sidewalls of the corresponding gate insulating layer; The doped regions are respectively formed in the semiconductor substrate and are respectively located at the outer sides of the corresponding lightly doped regions; wherein a boundary between the densely doped regions corresponding to one of the drains and the adjacent lightly doped regions thereof Positioned outside the sidewall of the nearest gate insulating layer and maintaining a space; a first metal telluride layer is formed on the dense doped region corresponding to the drain for a first contact layer Formed thereon; a second metal telluride layer is formed on the concentrated doped region corresponding to a source, a second contact layer is formed thereon; and a first electrostatic discharge protection doped region Formed under the lightly doped region corresponding to the drain, and the impurity polarity of the doped is different from the impurity polarity of the lightly doped region.

It can be seen from the above that the present invention mainly pushes out the boundary between the heavily doped region corresponding to a drain of a deep submicron semiconductor device and its adjacent lightly doped region, and makes the junction with the nearest gate. The sidewalls of the pole insulating layer are spaced apart from each other without being aligned with the sidewalls of the gate insulating layer; thus, the drain and source of the deep submicron semiconductor component are not too close due to the small layout rule of the deep submicron process, effectively increasing the depth Electrostatic discharge withstand capability of sub-micron components.

The main technical means for achieving the above purpose is that the ESD protection circuit comprises: a plurality of parallel first deep submicron semiconductor components and a plurality of parallel second deep submicron semiconductor components connected in series, and a series connection node An input/output pad for connecting to an integrated circuit; wherein: each of the first deep sub-micron semiconductor devices has a gate structure, a sidewall of the two gate insulating layer, and two lightly doped regions on a semiconductor substrate, a second concentrated doped region, a first metal telluride layer, a second metal telluride layer and a first electrostatic discharge protective doped region, the connection relationship between the first and second deep micron semiconductors The components are the same, and are not described herein again; wherein two adjacent first deep submicron semiconductor components share the same heavily doped region of the corresponding drain, so that the plurality of parallel first deep submicron semiconductor components constitute a multi-finger semiconductor And the second deep submicron semiconductor device has a gate structure, a sidewall of the two gate insulating layer, a second lightly doped region, a second dense doped region, a first metal germanide layer, and the second deep submicron semiconductor device. a second metal halide layer and a first electrostatic discharge protection doped region are connected in the same manner as the front deep micron semiconductor device, and are not described herein again; wherein two adjacent second deep submicron semiconductor components are A concentrated doped region of the same corresponding drain is shared such that the plurality of parallel second deep submicron semiconductor components form a multi-finger semiconductor structure.

The first and second deep submicron semiconductor components of the electrostatic discharge protection circuit of the present invention also push the boundary between the concentrated doped region corresponding to the drain and the adjacent lightly doped region thereof to make the boundary Keeping a space from the sidewall of the nearest gate insulating layer without being aligned with the sidewall of the gate insulating layer; thus, the drain and source of the first and second deep sub-micron semiconductor components are not due to the deep submicron process The smaller layout rules are too close, improving the electrostatic discharge withstand capability of deep sub-micron components, and also enhancing the electrostatic discharge withstand capability of the ESD protection circuit.

10‧‧‧Integrated circuit

100‧‧‧P type semiconductor substrate

101‧‧‧P-type well

101’‧‧‧N-well

11‧‧‧Internal circuits

111‧‧‧Electrostatic discharge protection circuit

12‧‧‧Input/Output Pads

20, 20a’‧‧‧ gate structure

201, 201'‧‧‧ gate insulation sidewall

21a, 21a', 21b, 21b'‧‧‧ lightly doped areas

22a, 22a', 22b, 22b'‧‧‧ concentrated doped area

221a, 221b‧‧‧N-type well

221a’, 221b’‧‧‧P-type well

23a, 23b‧‧‧P type electrostatic discharge protection doping area

23a', 23b'‧‧‧N type electrostatic discharge protection doping area

24a, 24a', 24b‧‧‧ metal telluride layers

25‧‧‧Contact layer

50‧‧‧Integrated circuit

500‧‧‧P type semiconductor substrate

501‧‧‧P-type well

51‧‧‧Internal circuits

511‧‧‧Electrostatic discharge protection circuit

52‧‧‧Input/Output Pads

60‧‧‧ gate structure

61‧‧‧ gate insulation sidewall

62‧‧‧lightly doped area

63‧‧‧Densely doped area

64‧‧‧metal telluride layer

Figure 1 is a circuit diagram of an electrostatic protection circuit of the present invention.

2A is a top plan view of a semiconductor structure of a first preferred embodiment of a deep submicron device of the present invention.

Figure 2B is a longitudinal cross-sectional view of Figure 2A.

Figure 3A is a top plan view of a semiconductor structure of a second preferred embodiment of a deep submicron device of the present invention.

Figure 3B is a longitudinal cross-sectional view of Figure 2A.

4A is a top plan view of a semiconductor structure of a third preferred embodiment of the deep submicron device of the present invention.

Figure 4B is a longitudinal cross-sectional view of Figure 2A.

Figure 5A is a top plan view of a semiconductor structure of a fourth preferred embodiment of the deep submicron device of the present invention.

Figure 5B is a longitudinal cross-sectional view of Figure 2A.

Figure 6 is a circuit diagram of an electrostatic protection circuit.

Fig. 7A is a plan view showing the semiconductor structure of the NMOS device in the static electricity protection circuit of Fig. 6.

Fig. 7B is a longitudinal sectional view of Fig. 7A.

The present invention is directed to deep sub-micron components for electrostatic discharge protection to improve their electrostatic discharge withstandability. The technical contents of the present invention will be specifically described below in the following examples.

First, referring to FIG. 1 , the electrostatic discharge protection circuit 111 of the present invention includes a plurality of parallel PMOS devices MP1 and MP2 and a plurality of parallel NMOS devices MN1 and MN2 connected in series, and the serial connection is connected to an integrated circuit 10 . An input/output pad 12 and an internal circuit 11; wherein the gate G and the source S of each of the PMOS devices MP1 and MP2 are connected in common to the high potential VDD of the system power supply of the integrated circuit 10, and each NMOS device MN1 The gate G and the source S of the MN 2 are connected in common to the low potential VSS of the system power supply of the integrated circuit 10.

Referring to FIG. 2A and FIG. 2B, the semiconductor structure of the first preferred embodiment of the deep sub-micron device of the present invention is taken as an example of the semiconductor structure of two NMOS devices MN1 and MN2 of FIG. Each of the NMOS devices MN1 and MN2 includes a gate structure 20, two gate insulating sidewalls 201, and two n-light doped regions 21a. 21b, two N+ heavily doped regions 22a, 22b and a P-type ESD protection doped region 23a.

The gate structure 20 is formed on the upper surface of the P-type well 101, and the two gate insulating layer sidewalls 201 are respectively formed on two opposite outer walls of the gate structure 20, and the two n-light doped regions 21a And 21b are respectively formed in the P-type well 101, and are located under the corresponding sidewalls 201 of the gate insulating layer, and the two N+ are heavily doped The regions 22a, 22b are respectively formed in the P-type well 101 and are respectively located at the outer sides of the corresponding n-light doped regions 21a, 21b; wherein the N + heavily doped region 22a corresponding to the drain D and its adjacent n- The junction between the lightly doped regions 21a is located outside the nearest gate insulating layer sidewall 201 and is spaced apart from the nearest gate insulating layer sidewall 201. Thus, the present invention is electrostatically charged. The n-lightly doped region 21a of the drain-protected deep sub-micron NMOS device corresponding to the drain D of the prior art NMOS device is longer than the n-lightly doped region of the drain D corresponding to the prior art NMOS device. Preferably, in a 0.18 um deep submicron process using a shallow trench isolation (STI) process, the spacing is about 1.5 to 2 um, but not limited thereto.

Since the electrostatic discharge protection circuit 111 of the present invention includes a plurality of parallel NMOS elements MN1 and MN2, in order to save layout space, as shown in FIG. 2A, two adjacent NMOS elements MN1 and MN2 share the same samarium structure, that is, a common 汲The N+ heavily doped region 22a of the pole D forms a semiconductor structure of the plurality of parallel NMOS elements MN1, MN2 to form a multi-finger semiconductor structure.

In this embodiment, the boundary between the N+ dense doped region 22a corresponding to the drain D of each NMOS device MN1, MN2 and its adjacent n-light doped region 21a is located at the junction with the nearest gate. Outside the layer sidewall 201 and maintaining a spacing d, the trigger voltage of the parasitic bipolar junction transistor (NPN BJT; not shown) of each NMOS device MN1, MN2 is increased, so that the voltage cannot be increased. The internal circuit component is effectively protected; therefore, in the embodiment, a P-type ESD protection doping region 23a is further formed under the n-light doped region 21a corresponding to the drain D to reduce the parasitic bicarrier of the NMOS device. The trigger voltage of the junction transistor ensures that the input/output pad 12 is electrostatically contacted, and each of the NMOS devices MN1, MN2 can be turned on quickly.

In addition, in order to allow the electrostatic discharge current to vent to a lower-layer path, a metal telluride layer 24a is formed on the upper surface portion of the N+ densely doped region 22a corresponding to each NMOS device drain D to appropriately increase the 汲The resistance between the metal telluride layer 24a of the pole D and the gate insulating layer sidewall 201 of the gate structure 20; that is, the upper surface of the N+ heavily doped region 22a corresponding to the drain D of each NMOS device Between the side of the metal telluride layer 24a and the side of the gate insulating layer sidewall 201 thereof A metal telluride layer is formed again. In this embodiment, the contact layer 25 of the drain is formed on the metal germanide layer 24a, and a metal germanide is formed on the N+ doped region 22b corresponding to the source S of each of the NMOS devices MN1 and MN2. The layer 24b further forms the source contact layer 25 on the metal halide layer 24b.

Referring to FIG. 3A and FIG. 3B, the semiconductor structure of the second preferred embodiment of the deep sub-micron device of the present invention is also exemplified by the semiconductor structure of two NMOS devices MN1 and MN2 of FIG. The structure is substantially the same as that of FIG. 2A and FIG. 2B except that the outer side and the bottom surface of the N+ doped region 22a corresponding to the drain D of each of the NMOS devices MN1 and MN2 are covered by an N-type well 221a to provide an electrostatic discharge. The deep discharge path improves the current-resistance of the NMOS device and also increases the breakdown voltage in the vertical direction of the NMOS devices MN1 and MN2.

Referring to FIG. 4A and FIG. 4B, the semiconductor structure of the third preferred embodiment of the deep sub-micron device of the present invention is also exemplified by the semiconductor structure of two NMOS devices MN1 and MN2 of FIG. The same as FIG. 3A and FIG. 3B, except that the source S of each of the NMOS devices MN1, MN2 corresponds to the junction between the N+ doped region 22b and the adjacent n-light doped region 21b, and is located recently. The gate insulating layer sidewall 201 is outside the sidewall 201 and is not spaced apart from the nearest gate insulating layer sidewall 201; thus, the corresponding source of the deep submicron NMOS devices MN1, MN2 of the present invention having electrostatic discharge protection The n-lightly doped region 21b of the pole S is longer than the n-lightly doped region of the drain of the corresponding NMOS element of the prior art; in addition, the n-lightly doped region corresponding to the source S of each of the NMOS elements MN1, MN2 A P-type ESD protection doping region 23b is formed under the 21b, and a metal telluride layer 24a is partially formed on the upper surface of the N+ densely doped region 22b corresponding to the source S, and the contact layer 25 of the source S is formed. On the metal telluride layer 24a. In addition, the outer side and the bottom surface of the N+ doped region 22a corresponding to the source S of each of the NMOS devices MN1 and MN2 are covered by an N-type well 221b to provide a deeper discharge path during electrostatic discharge, and the NMOS device is improved. The current-resistance of MN1 and MN2 also increases the breakdown voltage in the vertical direction of NMOS devices MN1 and MN2.

Referring to FIG. 5A and FIG. 5B, the semiconductor structure of the fourth preferred embodiment of the deep submicron device of the present invention is exemplified by the semiconductor structures of the two PMOS devices MP1 and MP2 of FIG. An N-type well 101' of the P-type semiconductor substrate 100; wherein each of the PMOS devices MP1, MP2 includes a gate structure 20', two gate insulating sidewalls 201', and two p-light doped regions 21a' 21b', two P+ heavily doped regions 22a', 22b' and an N-type ESD protection doped regions 23a', 23b'. In order to save the layout space, as shown in FIG. 5A, the two adjacent PMOS devices MP1 and MP2 share the same drain structure, that is, the P+ dense doped region 22'a sharing the corresponding drain, so that the plurality of parallel PMOS devices MP1 are connected. The semiconductor structure of MP2 constitutes a multi-finger semiconductor structure.

The gate structure 20' is formed on the upper surface of the N-type well 101', and the two gate insulating layer sidewalls 201' are respectively formed on two opposite outer walls of the gate structure 20', and the two p-light The doped regions 21a', 21b' are respectively formed in the N-type well 101' and are located under the corresponding gate insulating layer sidewall 201'. The two P+ heavily doped regions 22a', 22b' are respectively formed in the N The well 101' is located at the outer side of the corresponding p-light doped regions 21a', 21b'; wherein the P+ heavily doped region 22a' corresponding to the drain D and its adjacent p-light doped region The junction between 21a' is located outside of the nearest gate insulating sidewall 201' and maintains a spacing d so that it is not aligned with the nearest gate insulating sidewall 201'.

In addition, a surface portion of the P+ densely doped region 22a' corresponding to the drain D of each of the PMOS devices MP1 and MP2 forms a metal telluride layer 24a', and the drain D is formed on the metal halide layer 24a'. Contact layer 25'. As shown in FIG. 2B, a metal germanide layer is formed on the P+ dense doped region 22b' corresponding to the source S of each of the PMOS devices MP1 and MP2 of the present embodiment, and the metal halide layer is formed on the metal halide layer. a contact layer of the source; or, as shown in FIG. 4B, between the P+ doped region 22b' of the corresponding source S of each of the PMOS devices MP1, MP2 and the adjacent p-light doped region 21b' The junction may be located outside the nearest gate insulating layer sidewall 201' and maintained at a spacing d, and the P+ heavily doped region 22b' corresponding to the source S of each of the PMOS devices MP1 and MP2 is only partially formed. Metal telluride layer 24a'. Further, the p-light doped region 21a' corresponding to the drain D of each of the PMOS devices MP1, MP2 and/or the p- corresponding to the source S The lightly doped regions 21b' are squared to have N-type electrostatic discharge protection doped regions 23a', 23b', respectively. The outer side and the bottom surface of the P+ doped region 22a' corresponding to the drain D of each of the PMOS devices MP1 and MP2 are covered by a P-type well 221a' to provide a deeper discharge path during electrostatic discharge; The outer side and the bottom surface of the N+ doped region 22b' corresponding to the source S of each of the PMOS devices MP1 and MP2 may be covered by a P-type well 221b'.

In summary, since the drains of the PMOS and NMOS devices in the ESD protection circuit are directly connected to the corresponding input/output pads, the present invention mainly relates to the P+/ corresponding to the drain of the deep submicron element of the ESD protection. The N+ heavily doped region is pushed outwardly from the junction of the adjacent p-/n-light doped regions such that the junction is located outside the sidewall of the most gate insulating layer and is spaced apart from the gate. The sidewalls of the layers are aligned such that the drain and source are not too close to the smaller layout rules of the deep sub-micron process, effectively improving the electrostatic discharge withstand capability of the deep sub-micron components.

The above is only the embodiment of the present invention, and is not intended to limit the scope of the present invention. The present invention has been disclosed by the embodiments, but is not intended to limit the invention, and any one of ordinary skill in the art, In the scope of the technical solutions of the present invention, equivalent modifications may be made to the equivalents of the embodiments of the present invention without departing from the technical scope of the present invention. Any simple modifications, equivalent changes and modifications made to the above embodiments are still within the scope of the technical solutions of the present invention.

100‧‧‧P type semiconductor substrate

101‧‧‧P-type well

20‧‧‧ gate structure

201‧‧‧ gate insulation sidewall

21a, 21b‧‧‧ lightly doped area

22a, 22b‧‧‧Densely doped area

23a‧‧‧P type electrostatic discharge protection doping area

24a, 24b‧‧‧ metal telluride layer

25‧‧‧Contact layer

Claims (8)

An electrostatic discharge protected deep submicron semiconductor device comprising: a gate structure formed on a semiconductor substrate; sidewalls of the two gate insulating layers respectively formed on opposite sides of the gate structure; The regions are respectively formed in the semiconductor substrate and respectively located under the sidewalls of the corresponding gate insulating layer; the second heavily doped regions are respectively formed in the semiconductor substrate and are respectively located outside the corresponding lightly doped regions Where the boundary between the densely doped region and the adjacent lightly doped region corresponding to one of the drains is located outside the sidewall of the nearest gate insulating layer and is spaced apart; a first metal deuteration a layer of a portion formed on the densely doped region corresponding to the drain for forming a first contact layer thereon; a second metal telluride layer formed on the source corresponding to the source a doped region on which a second contact layer is formed; and a first ESD protection doped region formed under the lightly doped region corresponding to the drain and doped impurities The polarity is different from the polarity of the impurity in the lightly doped region. The deep-micron-semiconductor component protected by the electrostatic discharge according to claim 1, wherein the densely doped region and the bottom surface corresponding to the drain are covered by a dopant-doped region. An electrostatic discharge protected deep submicron semiconductor device according to claim 2, wherein: a boundary between the concentrated doped region corresponding to the source and its adjacent lightly doped region is located at the nearest gate insulating layer A second ESD protection doped region is formed under the lightly doped region corresponding to the source, and the doped impurity polarity is different from the impurity polarity of the lightly doped region; A second metal deuteration layer is formed on the concentrated doped region corresponding to the source. The deep-micron semiconductor device of the electrostatic discharge protection according to claim 3, wherein the concentrated doped region and the bottom surface corresponding to the source are covered by a common impurity-doped region. The electrostatic discharge protected deep submicron semiconductor device according to claim 4, wherein the semiconductor substrate comprises a P-type semiconductor substrate and a P-type well; each of the lightly doped regions is formed in the P-type well, and is a n a lightly doped region; each of the heavily doped regions is formed in the P-type well as an N+ heavily doped region; the first and second ESD protection doped regions are formed in the P-type well, both a P-type ESD protection doping region; and each of the same impurity polarity doped regions are formed in the P-type well, each being an N-type doped region. The electrostatic discharge protected deep submicron semiconductor device according to claim 4, wherein the semiconductor substrate comprises a P-type semiconductor substrate and an N-type well; each of the lightly doped regions is formed in the N-type well, which is a p a lightly doped region; each of the heavily doped regions is formed in the N-type well as a P+ heavily doped region; the first and second ESD protection doped regions are formed in the N-type well, both An N-type ESD protection doped region; and each of the same impurity polarity doped regions are formed in the N-type well, each being a P-type doped region. An ESD protection circuit comprising a plurality of parallel first deep submicron semiconductor components and a plurality of parallel second deep submicron semiconductor components connected in series, wherein a series of nodes is connected to an input/output of an integrated circuit The first deep submicron semiconductor component of any one of claims 1 to 5, wherein the two adjacent first deep submicron semiconductor components are Sharing a concentrated doped region of the same corresponding drain to form a plurality of parallel first deep submicron semiconductor components to form a multi-finger semiconductor structure; Each of the second deep submicron semiconductor components is an electrostatic discharge protected deep submicron semiconductor component according to any one of claims 1 to 4, wherein two adjacent second deep submicron semiconductor components share the same A heavily doped region corresponding to the drain causes the plurality of parallel second deep sub-micron semiconductor components to form a multi-finger semiconductor structure. The electrostatic discharge protection circuit of claim 7, wherein: the gates and the source lines of the plurality of parallel first deep submicron semiconductor components are commonly connected to a low potential end of a system power supply of the integrated circuit; The gates and the source lines of the plurality of parallel deep second-micron semiconductor devices are connected in common to the high potential terminal of the system power supply of the integrated circuit.