TWI609380B - Five-transistor single port static random access memory with fast read speed - Google Patents

Description

5T單埠 static random access memory with high read speed

The invention relates to a 5T單埠Static Random Access Memory (SRAM) with high read speed, in particular to effectively improve the standby performance of the SRAM, and can effectively improve the reading speed, and can SRAM that effectively reduces leakage current, reduces half-selected cell interference during reading, and avoids unnecessary power consumption.

The 6T conventional static random-access memory (SRAM) as shown on FIG. 1a, which includes a memory array (memory array), the memory array by a plurality of system memory blocks (memory block, MB _1, MB ₂ and so on) is composed, for each block of memory is more of rows of memory cells) and a plurality of memory cell rows (a plurality of columns of memory cells ) is composed of a plurality of memory cell columns (a plurality, each A column of memory cells and each row of memory cells each include a plurality of memory cells; a plurality of word lines (word lines, WL ₁ , WL _{2 ,} etc.), each word line corresponding to a plurality of columns of memory One of the unit cells; and a plurality of bit line pairs (BL ₁ , BLB ₁ ... BL _m , BLB _{m ,} etc.), each bit line pair corresponding to the plurality of line memory cells One row, and each bit line pair is composed of one bit line (BL ₁ ... BL _m ) and one complementary bit line (BLB ₁ ... BLB _m ).

Figure 1b shows the circuit diagram of a 6T static random access memory (SRAM) cell. The PMOS transistors (P1) and (P2) are called load transistors and NMOS transistors (M1). And (M2) are called driving transistors, NMOS transistors (M3) and (M4) are called access transistors, WL is word line, and BL and BLB They are a bit line and a complementary bit line, respectively. Since the 單埠SRAM cell requires 6 transistors, and when reading logic 0, in order to avoid the initial moment of the read operation (initial Instant) Another drive transistor is turned on. The initial instantaneous voltage (V _AR ) of node A must satisfy equation (1): V _AR = V _DD × (R _M1 ) / (R _M1 + R _M3 ) < V _TM2 ( 1)

Wherein, V _AR represents the initial instantaneous voltage of the reading of the node A, R _M1 and R _M3 respectively represent the on-resistances of the NMOS transistor (M1) and the NMOS transistor (M3), and V _DD and V _TM2 respectively represent the power supply The voltage and the threshold voltage of the NMOS transistor (M2), which results in a current drive capability ratio (ie, cell ratio) between the drive transistor and the access transistor is usually set between 2.2 and 3.5 (refer to 98) US Patent No. US76060B2, No. 2, lines 8-10, October 20, 2008).

The HSPICE transient analysis simulation results of the 6T SRAM cell in the write operation shown in Figure 1b, as shown in Figure 2, are simulated using TSMC 90 nm CMOS process parameters.

One way to reduce the number of transistors in a 6T static random access memory (SRAM) cell is disclosed in FIG. Figure 3 shows a circuit diagram of a 5T SRAM cell with only a single bit line, compared to the 6T SRAM cell of Figure 1b, such a 5T SRAM. The bulk cell has one transistor and one less bit line than the 6T SRAM cell, but the 5T SRAM cell does not change the PMOS transistors P1 and P2 and the NMOS transistor M1. The problem of writing logic 1 is quite difficult in the case of the channel width to length ratio of M2 and M3 (i.e., maintaining the same transistor channel width to length ratio as the 6T SRAM cell). Considering that the node A on the left side of the memory cell originally stores a logic 0, since the charge of the node A is transmitted only from the bit line (BL) alone, the logic 0 previously written in the node A is overwritten with a logic 1 write. The initial instantaneous voltage (V _AW ) is equal to equation (2): V _AW = V _DD × (R _M1 ) / (R _M1 + R _M3 ) (2) where V _AW represents the initial instantaneous voltage of the write of node A, R _M1 And R _M3 respectively indicate the on-resistances of the NMOS transistor (M1) and the NMOS transistor (M3). Comparing Equation (1) with Equation (2), the initial transient voltage (V _AW ) is smaller than the NMOS transistor (M2). The threshold voltage (V _TM2 ), and thus the operation of writing logic 1 cannot be completed. The 5T SRAM cell shown in Figure 3, the HSPICE transient analysis simulation result during the write operation, as shown in Figure 4, is simulated using the TSMC 90 nm CMOS process parameters. The simulation results confirm that the 5T SRAM cell with a single bit line has a problem in writing logic 1 that is quite difficult.

To date, many methods have been proposed to solve the above-mentioned 5T SRAM cell write logic 1 method. The first method is to lower the voltage level supplied to the memory cell lower than the power supply during writing. Supply voltage (V _DD ) to facilitate writing to logic 1 (assuming node A originally stores logic 0, but now writes logic 1) by increasing the on-resistance of driving transistor NMOS transistor M1 for write operation The "Memory System" proposed in the patent document 1 (US Pat. 2 (5T static random access memory for reducing the power supply voltage during write operation) and Patent Document 3 (No. TW I534802B, May 21, 105) proposed in 2nd (No. TW I426514B, February 11, 103) The proposed "semiconductor storage", etc., can effectively solve the problem of writing logic 1 difficult, but since these methods need to set dual power and/or discharge paths, and these methods must be supplied to the memory when writing The voltage level of the unit cell is pulled low below the power supply The voltage (V _DD ) returns the voltage level supplied to the memory cell to the power supply voltage (V _DD ) after the writing is completed, thus causing unnecessary power consumption.

The second method is to redesign the channel width to length ratio of the PMOS transistors P1 and P2 and the NMOS transistors M1, M2, and M3, for example, Non-Patent Document 4 (Satyan and Nalam et al., "5T SRAM with asymmetric sizing for improved read stability IEEE Journal of Solid-State Circuits. , Vol . 46. No. 10, pp 2431-2442, Oct. 2011.), except that the channel width to length ratios of the PMOS transistors P1 and P2 are different and the NMOS transistor M1 is used. The channel width to length ratio is not the same as M2, thus reducing the static noise margin (SNM).

The third method is to raise the word line (WL) voltage level of the gate of the access transistor M3 supplied to the memory cell to be higher than the power supply voltage (V _DD ) during writing to facilitate writing logic. 1 (suppose node A originally stores logic 0, but now wants to write logic 1), by reducing the on-resistance of access transistor M3 to enable the drive transistor NMOS transistor M2 to turn on during the initial write. The operation of writing logic 1 is as described in Patent Document 5 (No. TW I404065B, August 1, 102), "Serial Random Access Memory (Word), which improves the word line voltage level during a write operation, Since the word line (WL) voltage level of the gate of the access transistor M3 supplied to the memory cell is pulled up to be higher than the power supply voltage (V _DD ), the half of the write is increased. Half-selected cell disturbance is selected.

The fourth method is to raise the source voltage level of the driving transistor NMOS transistor M1 to be higher than the ground voltage during writing, so as to write logic 1 (assuming node A originally stores logic 0, but now wants to write Logic 1), by increasing the threshold voltage level of the driving transistor NMOS transistor M1, so that the driving transistor NMOS transistor M2 can be turned on during the initial writing. In the operation of writing logic 1, for example, "單埠 Static Random Access Memory (7)" proposed in Patent Document 6 (June No. TW I536382B, June 1, 105), Patent Document 7 (April 11, 105) "單埠 單埠 随机 529 529 529 TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW (6)" and so on.

The fifth method is to increase the threshold voltage of the driving transistor NMOS transistor M1 while reducing the threshold voltage of the access transistor M3 by writing with a back gate bias technique to facilitate writing logic. 1 (suppose node A originally stores logic 0, but now wants to write logic 1), by increasing the threshold voltage level of the driving transistor NMOS transistor M1, so that the initial phase of writing can drive the transistor NMOS Crystal M2 conducts and completes the operation of writing logic 1, but the method requires the use of a split well to increase process complexity and is therefore less useful.

The sixth method is to redesign the connection relationship between the PMOS transistors P1 and P2 and the NMOS transistors M1, M2, and M3, for example, Non-Patent Document 9 (Chua-Chin Wang et al., "A single-ended disturb-free 5T loadless SRAM with leakage sensor and read delay compensation using 40nm process", 2014 International Symposium on Circuits and Systems, pp 1126-1129, June 2014.) and Non-Patent Document 10 (shyam Akashe et al., "High density and low leakage Current based 5T SRAM cell using 45nm technology", 2011 International Conference on Nanoscience, Engineering and Technology (ICONSET), pp 346-350, Nov. 2011.) and the like.

Although the above-mentioned technologies can effectively solve the problem of writing logic 1 difficult, these technologies do not consider the simultaneous use of the word line voltage level conversion circuit and the high voltage level control circuit to effectively reduce The half-selected cell interference during reading can also effectively improve the reading speed, so there is still room for improvement.

In view of this, the main object of the present invention is to propose a high reading speed of 5T. 單埠Static random access memory, which can improve the reading of the semi-selected cell interference during reading by the word line voltage level conversion circuit and the high voltage level control circuit. Take the speed.

A secondary object of the present invention is to provide a 5T單埠 static random access memory with high read speed, which can effectively improve the reading speed by the control circuit, and can be improved by the two-stage read control. While reading speed, it also avoids unnecessary power consumption.

The invention provides a 5T單埠 static random access memory with high read speed, which mainly comprises a memory array, a plurality of control circuits (2), a plurality of precharge circuits (3), and a standby start circuit ( 4) a plurality of word line voltage level conversion circuits (5) and a plurality of high voltage level control circuits (6), the memory array is composed of a plurality of columns of memory cells and a plurality of rows of memory cells Each column of memory cells is provided with a control circuit (2), a word line voltage level conversion circuit (5), and a high voltage level control circuit (6), and each row of memory cells is provided with a precharge. The circuit (3), by means of the plurality of control circuits (2) and the plurality of high-voltage level control circuits (6), in order to increase the reading speed while avoiding unnecessary Power consumption, on the other hand, by the plurality of word line voltage level conversion circuits (5) to effectively reduce half-selected cell interference during reading, in the write mode, by the plurality of control circuits (2) in order to effectively prevent the same problem of writing logic 1 When the type, may be by the plurality of control circuits (2) effective to reduce the leakage current, and to start the stand-by circuit design (4), in order to effectively promote the fast static random-access memory into standby mode.

1‧‧‧SRAM cell

2‧‧‧Control circuit

3‧‧‧Precharge circuit

4‧‧‧Standby start circuit

5‧‧‧Word line voltage level conversion circuit

6‧‧‧High voltage level control circuit

P11‧‧‧First PMOS transistor

P12‧‧‧Second PMOS transistor

M11‧‧‧First NMOS transistor

M12‧‧‧Second NMOS transistor

M13‧‧‧ Third NMOS transistor

A‧‧‧ storage node

B‧‧‧ Inverting storage node

BL‧‧‧ bit line

WLC‧‧‧ word line control signal

VDD‧‧‧Power supply voltage

VH‧‧‧ high voltage node

VL1‧‧‧ first low voltage node

VL2‧‧‧ second low voltage node

S‧‧‧Standby mode control signal

/S‧‧‧Inverted standby mode control signal

M21‧‧‧4th NMOS transistor

M22‧‧‧ Fifth NMOS transistor

M23‧‧‧ sixth NMOS transistor

M24‧‧‧ seventh NMOS transistor

M25‧‧‧8th NMOS transistor

M26‧‧‧Ninth NMOS transistor

M27‧‧‧ tenth NMOS transistor

M28‧‧‧11th NMOS transistor

RC‧‧‧ read control signal

RGND‧‧‧Accelerated reading voltage

/RC‧‧‧Inverted read control signal

/WC‧‧‧Inverted write control signal

INV‧‧‧ third inverter

D1‧‧‧First delay circuit

P31‧‧‧ Third PMOS transistor

P‧‧‧Precharge signal

M41‧‧‧12th NMOS transistor

P41‧‧‧4th PMOS transistor

C‧‧‧ node

D2‧‧‧second delay circuit

WL‧‧‧ character line

VDDH‧‧‧High power supply voltage

P51‧‧‧ Fifth PMOS transistor

M51‧‧‧Thirteenth NMOS transistor

M52‧‧‧ fourteenth NMOS transistor

P61‧‧‧6th PMOS transistor

P62‧‧‧ seventh PMOS transistor

I63‧‧‧fourth inverter

BLB ₁ ^... BLB _m ‧‧‧complementary bit line

BLB‧‧‧complementary bit line

MB ₁ ^... MB _k ‧‧‧ memory block

WL ₁ ^... WL _n ‧‧‧ character line

BL ₁ ^... BL _m ‧‧‧ bit line

I ₁ , I ₂ , I ₃ ‧‧‧ leakage current

M1 ^... M4‧‧‧ NMOS transistor

P1 ^... P2‧‧‧ PMOS transistor

WC‧‧‧ write control signal

Figure 1a shows a conventional static random access memory; Figure 1b shows a schematic circuit diagram of a conventional 6T static random access memory cell; and Fig. 2 shows a conventional 6T static random access memory cell. The write operation timing chart; the third figure shows the circuit diagram of the conventional 5T static random access memory unit cell; the fourth figure shows the write operation timing chart of the conventional 5T static random access memory unit cell; 5 is a schematic circuit diagram showing a preferred embodiment of the present invention; FIG. 6 is a simplified circuit diagram showing a preferred embodiment of the present invention in FIG. 5 during writing; and FIG. 7 is a view showing the fifth drawing; FIG. 8 is a simplified circuit diagram showing a preferred embodiment of the present invention in the fifth embodiment of the present invention; and FIG. 9 is a preferred embodiment of the present invention shown in FIG. Simplified circuit diagram during standby.

According to the above main object, the present invention provides a 5T單埠 static random access memory, which mainly includes a memory array composed of a plurality of column memory cells and a plurality of row memory cells. Each column of memory cells and each row of memory cells includes a plurality of memory cells (1); a plurality of control circuits (2), each column of memory cells is provided with a control circuit (2); Charging circuit (3), each row of memory cells is provided with a pre-charging circuit (3); a standby starting circuit (4), the standby starting circuit (4) prompts the SRAM to quickly enter the standby mode to effectively improve the standby performance of the SRAM a plurality of word line voltage level conversion circuits (5), each column memory cell is provided with a word line voltage level conversion circuit (5); and a plurality of high voltage level control circuits (6), each column Memory cell design Set a high voltage level control circuit (6).

For convenience of explanation, the static random access memory shown in FIG. 5 has only one memory cell (1), one word line (WL), one bit line (BL), and one control circuit (2). A precharge circuit (3), a standby start circuit (4), and a word line voltage level conversion circuit (5) and a high voltage level control circuit (6) are described as an embodiment. The memory cell (1) includes a first inverter (composed of a first PMOS transistor P11 and a first NMOS transistor M11) and a second inverter (by a second PMOS) The crystal P12 is formed by a second NMOS transistor M12 and a third NMOS transistor (M13), wherein the first inverter and the second inverter are coupled to each other, that is, the first The output of the inverter (ie node A) is connected to the input of the second inverter, and the output of the second inverter (ie node B) is connected to the input of the first inverter, and the first The output of the inverter (node A) is used to store the data of the SRAM cell, and the output of the second inverter (node B) is used to store the inverted data of the SRAM cell. It should be noted here that the first NMOS transistor (M11) and the second NMOS transistor (M12) have the same channel width to length ratio, the first PMOS transistor (P11) and the second PMOS transistor. (P12) also has the same channel width to length ratio.

Referring again to FIG. 5, the control circuit (2) is composed of a fourth NMOS transistor (M21), a fifth NMOS transistor (M22), a sixth NMOS transistor (M23), and a seventh NMOS device. Crystal (M24), an eighth NMOS transistor (M25), a ninth NMOS transistor (M26), a tenth NMOS transistor (M27), an eleventh NMOS transistor (M28), a read control Signal (RC), a third inverter (INV), a first delay circuit (D1), an accelerated read voltage (RGND), a write control signal (WC), and an inverted write control signal ( /WC), a standby mode control signal (S) and an inverting standby mode The control signal (/S) is composed of. a source, a gate and a drain of the fourth NMOS transistor (M21) are respectively connected to a ground voltage, the reverse standby mode control signal (/S) and a second low voltage node (VL2); a source, a gate and a drain of the NMOS transistor (M22) are respectively connected to the second low voltage node (VL2), the standby mode control signal (S) and a first low voltage node (VL1); The source of the six NMOS transistor (M23) is connected to the ground voltage, and the gate is connected to the drain and connected to the first low voltage node (VL1); the source of the seventh NMOS transistor (M24) The gate and the drain are respectively connected to the drain of the eighth NMOS transistor (M25), the read control signal (RC) and the first low voltage node (VL1); and the eighth NMOS transistor (M25) a source, a gate and a drain are respectively connected to the accelerated read voltage (RGND), an output of the first delay circuit (D1), and a source of the seventh NMOS transistor (M24); the first a delay circuit (D1) is coupled between an output of the third inverter (INV) and a gate of the eighth NMOS transistor (M25); an input of the third inverter (INV) is for receiving the Read control signal ( RC), and the output is connected to the input of the first delay circuit (D1); the source, the gate and the drain of the ninth NMOS transistor (M26) are respectively connected to a ground voltage, the tenth NMOS transistor a drain of (M27) and the first low voltage node (VL1); a source, a gate and a drain of the tenth NMOS transistor (M27) are respectively connected to the ground voltage, the write control signal (WC) And a gate of the ninth NMOS transistor (M26); and a source, a gate and a drain of the eleventh NMOS transistor (M28) are respectively connected to the inverted standby mode control signal (/S) The inverted write control signal (/WC) and the gate of the ninth NMOS transistor (M26). It should be noted here that the inverted standby mode control signal (/S) is obtained by the standby mode control signal (S) via an inverter, and the inverted write control signal (/WC) is The write control signal (WC) is obtained via another inverter.

It is worth noting here that the drain of the eleventh NMOS transistor (M28), the drain of the tenth NMOS transistor (M27), and the gate of the ninth NMOS transistor (M26) are connected together. And forming a node (C), when the write control signal (WC) is a logic low level, the voltage level of the node (C) is the logic level of the inverted standby mode control signal (/S), and When the write control signal (WC) is at a logic high level, the voltage level of the node (C) is the ground voltage; since the voltage level of the node (C) during the write operation is always a ground voltage, a high-stability write operation; further, due to the hold mode, the voltage level of the node (C) is the power supply voltage (V _DD ) deducting the threshold voltage of the eleventh NMOS transistor (M28) (V _TM28 ) voltage level, so when entering the write mode (when WC is logic high), the charge stored in the node (C) must be discharged enough to turn off the node (C) The ninth NMOS transistor (M26) of the gate also has a faster completion of the write operation.

The control circuit (2) is designed to control the voltage level of the first low voltage node (VL1) and the second low voltage node (VL2) according to different operation modes, and select the unit cell in the write mode. The source voltage (ie, the first low voltage node VL1) of the driving transistor (ie, the first NMOS transistor M11) closer to the bit line (BL) is set to be a predetermined voltage higher than the ground voltage (ie, The gate-source voltage V _{GS(M23) of} the sixth NMOS transistor (M23) and the source voltage of the other driving transistor (ie, the second NMOS transistor M12) in the selected unit cell (ie, the second The low voltage node VL2) is set to the ground voltage to prevent the difficulty of writing logic 1.

In the first stage of the read mode, the source voltage of the driving transistor (ie, the first NMOS transistor M11) closer to the bit line (BL) in the cell is selected (ie, the first low voltage node VL1) Setting the accelerated read voltage (RGND) to be lower than the ground voltage, the comparison The accelerated read voltage (RGND) with a low ground voltage can effectively increase the read speed, and in the second phase of the read mode, the drive transistor closer to the bit line (BL) in the selected unit cell (ie, The source voltage of the first NMOS transistor M11) is set back to the ground voltage to reduce unnecessary power consumption, wherein the second phase of the read mode is separated from the first phase by the read control signal (RC) from the logic low level to the logic high level, and until the gate voltage of the eighth NMOS transistor (M25) is sufficient to turn off the eighth NMOS transistor (M25), the value can be obtained by The falling delay time of the third inverter (INV) is adjusted with the delay time provided by the first delay circuit (D1).

In the standby mode, the source voltage of the driving transistor in all the memory cells is set to the predetermined voltage higher than the ground voltage to reduce the leakage current; and in the hold mode, the driving power in the memory cell is The source voltage of the crystal is set to the ground voltage to maintain the original retention characteristics. The detailed operating voltage levels are shown in Table 1.

The inverted write control signal (/WC) in Table 1 is a write control signal (WC) an inverted signal, and the write control signal (WC) is an AND gate operation result of the write signal (W) and the word line (WL) signal, at this time only When the write signal (W) signal and the word line (WL) signal are both at a logic high level, the write control signal (WC) is a logic high level; the read control signal (RC) is a read signal ( R) The result of the AND operation of the word line (WL) signal. It is worth noting here that the read control signal (RC) during the non-read mode is set to the level of the accelerated read voltage (RGND) to prevent leakage of the seventh NMOS transistor (M24). Current.

Referring to FIG. 5, the precharge circuit (3) is composed of a third PMOS transistor (P31) and a precharge signal (P), and the source and gate of the third PMOS transistor (P31). And a drain line connected to the power supply voltage (VDD), the precharge signal (P) and the bit line (BL), respectively, to facilitate the precharge signal (P) by a logic low level during precharge To precharge the bit line (BL) to the level of the power supply voltage (VDD).

Referring to FIG. 5 again, the standby starting circuit (4) is composed of a fourth PMOS transistor (P41), a twelfth NMOS transistor (M41), a second delay circuit (D2), and the reverse standby. The mode control signal (/S) is composed of. The source, the gate and the drain of the fourth PMOS transistor (P41) are respectively connected to the power supply voltage (VDD), the inverted standby mode control signal (/S) and the twelfth NMOS transistor ( a drain of M41); a source, a gate and a drain of the twelfth NMOS transistor (M41) are respectively connected to the output of the first low voltage node (VL1) and the second delay circuit (D2) a drain of the fourth PMOS transistor (P41); an input of the second delay circuit (D2) is connected to the inverted standby mode control signal (/S), and an output of the second delay circuit (D2) is connected To the gate of the twelfth NMOS transistor (M41).

Please refer to FIG. 5 again, the word line voltage level conversion circuit (5) is composed of a Five PMOS transistors (P51), a thirteenth NMOS transistor (M51), a fourteenth NMOS transistor (M52), the read control signal (RC), the inverted write control signal (/WC) An inverted read control signal (/RC) and a word line control signal (WLC). a source, a gate and a drain of the fifth PMOS transistor (P51) are respectively connected to the word line (WL), the inverted write control signal (/WC) and the word line control signal (WLC) The source, gate and drain of the thirteenth NMOS transistor (M51) are respectively connected to the word line control signal (WLC), the read control signal (RC) and the word line (WL) And the source, the gate and the drain of the fourteenth NMOS transistor (M52) are respectively connected to the word line control signal (WLC), the inverted read control signal (/RC) and the word Yuan line (WL).

The detailed operating voltage level of the word line voltage level conversion circuit (5) is shown in Table 2.

Where V _TM51 represents the threshold voltage of the thirteenth NMOS transistor (M51). It should be noted here that the present invention uses two-stage read control to improve the reading speed while avoiding unnecessary power consumption, and on the other hand, the word line voltage level conversion circuit ( 5), in order to effectively lower the word line voltage of the access transistor applied to the selected cell during the read operation to be lower than the power supply voltage (ie, VDD-V _TM51 ) to effectively reduce the half selection during reading Cell interference.

Referring again to FIG. 5, the high voltage level control circuit (6) is composed of a sixth PMOS transistor (P61), a seventh PMOS transistor (P62), a fourth inverter (I63), and a high a power supply voltage (VDDH), wherein a source, a gate, and a drain of the sixth PMOS transistor (P61) are respectively connected to the power supply voltage (VDD), the read control signal (RC), and a a high voltage node (VH), a source, a gate and a drain of the seventh PMOS transistor (P62) are respectively connected to the high power supply voltage (VDDH), and the output of the fourth inverter (I63) The high voltage node (VH), the input of the fourth inverter (I63) is for receiving the read control signal (RC), and the output is connected to the gate of the seventh PMOS transistor (P62). It is worth noting here that the first inverter is connected between the power supply voltage (VDD) and the first low voltage node (VL1), and the second inverter is connected to the high voltage node. (VH) is between the second low voltage node (VL2).

The working principle of the preferred embodiment of the present invention in FIG. 5 is as follows:

(I) write mode

Before the start of the write operation, the inverted write control signal (/WC) is at a logic high level, such that the eleventh NMOS transistor (M28) is turned on (ON), and the tenth NMOS transistor (M27) is made. OFF (OFF), since the inverted standby mode control signal (/S) is at a logic high level at this time, then the drain of the eleventh NMOS transistor (M28) is at a logic high level, and the logic high level should be The drain of the eleventh NMOS transistor (M28) turns on the ninth NMOS transistor (M26) and causes the low voltage node (VL1) to be grounded.

During the write operation, the write control signal (WC) is at a logic high level, such that the tenth NMOS transistor (M27) is turned on (ON), and the tenth NMOS transistor (M27) is turned off. A ground voltage is applied, the NMOS transistor (M26) is turned off, and the low voltage node (VL1) is equal to the gate voltage V _{GS (M26) of} the sixth NMOS transistor (M23). This effectively prevents the difficulty of writing logic 1. Figure 6 is a simplified circuit diagram of the preferred embodiment of the invention of Figure 5 during writing.

Next, how the write operation of the preferred embodiment of the present invention in FIG. 6 is completed depends on the four write states of the SRAM.

(1) Node A originally stores a logic 0, but now wants to write a logic 0:

Before the write operation occurs (the word line control signal WLC is a ground voltage), the first NMOS transistor (M11) is turned "ON". Since the first NMOS transistor (M11) is ON, the word line control signal (WLC) is turned from Low (ground voltage) to High (the power supply voltage VDD) when the write operation starts. When the voltage of the word line control signal (WLC) is greater than the threshold voltage of the third NMOS transistor (M13) (ie, the access transistor), the third NMOS transistor (M13) is turned from OFF (OFF) to Turn on (ON). At this time, because the bit line (BL) is the ground voltage, the node A will maintain the original ground voltage until the end of the write cycle.

(2) Node A originally stores logic 0, but now wants to write logic 1:

Before the write operation occurs (the word line control signal WLC is a ground voltage), the first NMOS transistor (M11) is turned "ON". Since the first NMOS transistor (M11) is ON, when the writing operation starts, the word line control signal (WLC) is turned from Low (ground voltage) to High (the power supply voltage VDD) when the character is When the voltage of the line control signal (WLC) is greater than the threshold voltage of the third NMOS transistor (M13), the third NMOS transistor (M13) is turned from OFF to ON, because the bit is The line (BL) is the voltage level of the power supply voltage (VDD), and because the first NMOS transistor (M11) is still ON and the node B is at a voltage level close to the power supply voltage (VDD) The initial state of the voltage level, so the first PMOS transistor (P11) is still OFF (OFF), and the initial transient voltage (V _AWI ) of the node A satisfies the equation (3): V _AWI = VDD × ( R _M11 +R _M23 )/(R _M13 +R _M11 +R _M23 )>V _TM12 (3)

Wherein, V _AWI represents the initial transient voltage of the node A, and R _M11 , R _M13 and R _M23 represent the first NMOS transistor (M11), the third NMOS transistor (M13) and the sixth NMOS transistor, respectively. (M23) the on-resistance, and VDD and _VTM12 respectively represent the power supply voltage (V _DD ) and the threshold voltage of the second NMOS transistor (M12), since one is provided at the first low voltage node (VL1) It is equal to the voltage level of the gate-source voltage V _{GS (M23)} of the sixth NMOS transistor (M23), so the voltage level of the node A can be easily set to be less than the conventional 5T static random memory of FIG. The voltage level of the node A of the memory cell is much higher. The much higher voltage division voltage level is sufficient to turn on the second NMOS transistor (M12), thus causing the node B to discharge to a lower voltage level, and the lower voltage level of the node B causes the first The on-resistance (R _M11 ) of an NMOS transistor (M11) exhibits a higher resistance value, and the higher resistance value of the first NMOS transistor (M11) obtains a higher voltage level at the node A. The higher voltage level of the node A is again passed through the second inverter (composed of the second PMOS transistor P12 and the second NMOS transistor M12), so that the node B exhibits a lower voltage level, the node The lower voltage level of B is again passed through the first inverter (composed of the first PMOS transistor P11 and the first NMOS transistor M11), so that the node A obtains a higher voltage level, and thus cycles The node A can be charged to the power supply voltage (VDD) to complete the logic 1 write operation.

It should be noted here that the first low voltage node (VL1) originally stores a logic 0 at the node A, and has a gate-source voltage V equal to the sixth NMOS transistor (M23) during the writing of the logic 1. The voltage level of _{GS (M23)} , after writing logic 1, will have the level of the ground voltage due to discharge through the ninth NMOS transistor (M26).

(3) Node A originally stores logic 1, but now wants to write logic 1:

Before the write operation occurs (the word line control signal WLC is the ground voltage), the first PMOS transistor (P11) is turned "ON". When the word line control signal (WLC) is turned from Low (ground voltage) to High (the power supply voltage VDD), since the node A is the voltage level of the power supply voltage (V _DD ), and the bit line ( BL) is the voltage level of the power supply voltage (VDD), thus keeping the third NMOS transistor (M13) in an OFF state; at this time, since the first PMOS transistor (P11) is still ON Therefore, the voltage of the node A is maintained at the voltage level of the power supply voltage (VDD) until the end of the write cycle.

(4) Node A originally stores logic 1, but now wants to write logic 0:

Before the write operation occurs (the word line control signal WLC is a ground voltage), the first PMOS transistor (P11) is turned "ON". When the word line control signal (WLC) is turned from Low (ground voltage) to High (the power supply voltage VDD), and the voltage of the word line control signal (WLC) is greater than the critical value of the third NMOS transistor (M13) At the time of voltage, the third NMOS transistor (M13) is turned from off (OFF) to on (ON). At this time, since the bit line (BL) is Low (ground voltage), the node A and the first A low voltage node (VL1) discharges to complete the logic 0 write operation until the end of the write cycle.

Figure 6 shows a preferred embodiment of the invention, HSPICE during write operation The results of the transient analysis simulation, as shown in Fig. 7, are simulated using the TSMC 90 nm CMOS process parameters. From the simulation results, it can be confirmed that the 5T static random access memory proposed by the present invention can be written by Increasing the voltage level of the first low voltage node (VL1) during the ingress period effectively avoids the problem that it is difficult to write the logic 1 in the 5T SRAM cell with a single bit line.

(II) Read mode (read mode)

Before the start of the read operation, the inverted write control signal (/WC) and the inverted standby mode control signal (/S) are both logic high levels, so that the eleventh NMOS transistor (M28) is turned on, and The tenth NMOS transistor (M27) is turned off, so that the node C is at a logic high level, and the node C of the logic high level turns on the ninth NMOS transistor (M26), and makes the first low voltage node (VL1) Grounded voltage. On the other hand, since the read control signal (RC) is at a logic low level, the seventh NMOS transistor (M24) is turned off (OFF), and the eighth NMOS transistor (M25) is turned "ON".

It is worth noting here that during pre-charging before the start of the read operation, the pre-charge signal (P) is at a logic low level, whereby the corresponding bit line (BL) is precharged to the power supply. The voltage (V _DD ) level, however, because the operating voltage of, for example, a process technology of 20 nm or less will fall below 1 volt, which will cause the reading speed to decrease and the specification cannot be satisfied. Therefore, the present invention proposes a two-stage reading. Control is taken to increase the reading speed and meet the specifications while avoiding unnecessary power consumption.

The preferred embodiment of the present invention shown in FIG. 5 is controlled by two stages to improve the reading speed while avoiding unnecessary power consumption. In the first stage of the reading operation, the reading is performed. The control signal (RC) is at a logic high level, so that the seventh NMOS transistor (M24) leads Therefore, since the eighth NMOS transistor (M25) is still turned on at this time, the first low voltage node (VL1) is approximately at an accelerated read voltage (RGND) lower than the ground voltage, and the ground voltage is low. The accelerated read voltage (RGND) can effectively increase the read speed.

In the second phase of the read operation, although the read control signal (RC) is still at a logic high level, the seventh NMOS transistor (M24) is still turned on, but since the eighth NMOS transistor is at this time (M25) is turned off, so that the first low voltage node (VL1) is grounded via the turned-on ninth NMOS transistor (M26), thereby effectively reducing unnecessary power consumption. It is worth noting here that the second phase of the read operation is separated from the first phase by a time equal to the read control signal (RC) transitioning from a logic low level to a logic high level, and to the The gate voltage of the eight NMOS transistor (M25) is sufficient to turn off the eighth NMOS transistor (M25), and the value thereof can be decreased by the delay time of the third inverter (INV) and the first delay circuit. (D1) The delay time provided is adjusted. Furthermore, regardless of the first phase of the read operation or the second phase, the ninth NMOS transistor (M26) is turned on (because the gate of the ninth NMOS transistor (M26) is extremely logic high. ). Figure 8 is a simplified circuit diagram of the preferred embodiment of the invention of Figure 5 during reading.

Next, how the preferred embodiment of the present invention in FIG. 8 is used to improve the reading speed by the control circuit (2) and the high voltage level control circuit (6) according to the two read states of the SRAM. It also avoids unnecessary power consumption, and on the other hand, the word line voltage level conversion circuit (5) is used to effectively reduce the half-selected cell interference during reading.

(1) Read logic 1 (node A stores logic 1):

Before the reading operation occurs, the first NMOS transistor (M11) is turned off (OFF) and the second NMOS transistor (M12) is turned on (ON), and the node A and the node B are respectively the power supply voltage (VDD) and the ground voltage, and the bit line (BL) is equal to the power supply voltage (VDD) due to the precharge circuit (3). During the reading, the word line control signal (WLC) is the threshold voltage of the thirteenth NMOS transistor (M51) (ie, V _DD -V _TM51 ) for the power supply voltage, and since the node A is The voltage level of the power supply voltage (VDD) is such that the third NMOS transistor (M13) is in an OFF state, thereby effectively maintaining the bit line (BL) as the power supply voltage until the read cycle Finish and successfully complete the operation of reading logic 1. It is worth noting here that during the read operation, the word line control signal (WLC) is the threshold voltage of the thirteenth NMOS transistor (M51) (ie, VDD-V _TM51 ). Therefore, the half-selected cell interference at the time of reading can be effectively reduced. In addition, in the first stage of the read operation, the first initial voltage voltage (V _RVL1I ) of the first low voltage node (VL1) when reading logic 1 must satisfy equation (4): V _RVL1I = RGND × R _M26 /(R _M26 +R _M24 +R _M25 )>-V _TM11 (4) to effectively prevent half-selected cell interference during reading, wherein V _RVL1I indicates that the first low voltage node (VL1) is read The logic 1 reads the initial instantaneous voltage, RGND represents the accelerated read voltage, R _M26 represents the on-resistance of the ninth NMOS transistor (M26), and R _M24 represents the on-resistance of the seventh NMOS transistor (M24). R _M25 represents the on-resistance of the eighth NMOS transistor (M25), and V _TM11 represents the threshold voltage of the first NMOS transistor (M11); in the second phase of the read operation, the first low voltage node The voltage of (VL1) (V _RVL1 ) can be expressed by equation (5): V _RVL1 = ground voltage (5) Thereby, unnecessary power consumption can be effectively reduced.

Furthermore, in order to effectively reduce the half-selected cell interference during reading and effectively reduce the leakage current, the absolute value of the accelerated read voltage (RGND) can be set more conservatively than the first NMOS transistor (M11). The threshold voltage (V _TM11 ), that is, |RGND|<V _TM11 (6), where |RGND| and V _TM11 respectively represent the absolute value of the accelerated read voltage and the threshold voltage of the first NMOS transistor (M11).

(2) Read logic 0 (node A stores logic 0):

Before the reading operation occurs, the first NMOS transistor (M11) is turned on (ON) and the second NMOS transistor (M12) is turned off (OFF), and the node (A) and the node (B) are respectively The ground voltage is the high power supply voltage (VDDH), and the bit line (BL) is equal to the power supply voltage (VDD) due to the precharge circuit (3). Because the first NMOS transistor (M11) is ON, when the reading operation starts, the word line control signal (WLC) is turned from Low (ground voltage) to High (the power supply voltage is applied to the thirteenth NMOS). The threshold voltage VDD-V _{TM51 of the} transistor M51). When the voltage of the word line control signal (WLC) is greater than the threshold voltage of the third NMOS transistor (M13), the third NMOS transistor (M13) is turned from OFF to ON. The initial instantaneous voltage (V _AR0I ) of this node A must satisfy equation (7): V _AR0I = VDD × (R _M11 + (R _M24 + R _M25 ) ∥ R _M26 ) / (R _M13 + R _M11 + (R _M24 +R _M25 )∥R _M26 )+RGND×(R _M11 +R _M13 )∥R _M26 /(R _M24 +R _M25 +(R _M11 +R _M13 )∥R _M26 )×R _M13 /(R _M11 +R _M13 ) <V _TM12 (7) to avoid turning on the second NMOS transistor (M12), wherein V _AR0I represents the initial instantaneous voltage when node A reads logic 0, R _M11 , R _{M13 ,} R _{M24 ,} R _M25 And the first NMOS transistor (M11), the third NMOS transistor (M13), the seventh NMOS transistor (M24), the eighth NMOS transistor (M25), and the ninth NMOS device are respectively represented by R _M26 The on-resistance of the crystal (M26), and VDD, RGND, and _VTM12 represent the power supply voltage (VDD), the accelerated read voltage (RGND), and the threshold voltage of the second NMOS transistor (M12), respectively. It is worth noting here that the accelerated read voltage (RGND) is designed to be lower than the ground voltage and the absolute value of the accelerated read voltage is designed to be smaller than the threshold voltage of the first NMOS transistor (M11). Furthermore, the word line control signal (WLC) of the present invention during reading is set such that the power supply voltage is _{biased against} the threshold voltage (VDD-V _TM51 ) of the thirteenth NMOS transistor (M51). The aspect can effectively reduce the half-selected cell interference at the time of reading, and on the other hand, it is easier to satisfy the equation (7) by increasing the on-resistance (R _M13 ) of the third NMOS transistor (M13).

Moreover, during the read logic 0, since the node B is the high power supply voltage (VDDH), and the first low voltage node (VL1) is a voltage lower than the ground voltage, due to the high power supply voltage (VDDH) The system is set higher than the power supply voltage (VDD), and therefore, the reading speed can be effectively increased by increasing the conduction degree of the first NMOS transistor (M11). It is worth noting here that the high power supply voltage (VDDH) is set higher than the power supply voltage (VDD) but lower than the high power supply voltage (VDDH) and the second PMOS transistor (P12) threshold voltage. The sum of the absolute values |V _TP12 |, that is, VDD < VDDH < VDD + | V _TP12 | (8) where |V _TP12 | represents the absolute value of the threshold voltage of the second PMOS transistor (P12).

(III) Standby mode

First, how the standby start circuit (4) of FIG. 5 causes the 單埠SRAM to quickly enter the standby mode to effectively improve the standby performance of the SRAM: First, the reverse standby mode control signal (/S) before entering the standby mode. Is logic High, the logic high inversion standby mode control signal (/S) causes the fourth PMOS transistor (P41) to be turned off (OFF), and the twelfth NMOS transistor (M41) is turned on (ON); Then, after entering the standby mode, the inverted standby mode control signal (/S) is logic Low, and the inverted standby mode control signal (/S) of the logic Low causes the fourth PMOS transistor (P41) to be turned on (ON). ), but during the initial period of the standby mode (the initial period is equal to the inverted standby mode control signal (/S) from the logic High to the logic Low, to the gate of the twelfth NMOS transistor (M41) The voltage is sufficient to turn off the twelfth NMOS transistor (M41), which can be adjusted by a delay time provided by the second delay circuit (D2), and the twelfth NMOS transistor (M41) is still Turned on (ON), then the first low voltage node (VL1) can be quickly charged to reach the sixth NMOS battery The voltage level of the threshold voltage (V _TM23 ) of the crystal (M23), that is, the 單_埠 SRAM can quickly enter the standby mode. It is worth noting here that after the initial period of the standby mode, the twelfth NMOS transistor (M41) is turned off and the supply current is stopped.

Referring to FIG. 5, in the standby mode, the standby mode control signal (S) is a logic high level, and the inverted standby mode control signal (/S) is a logic low level, and the logic low level is the reverse standby. The mode control signal (/S) may cause the fourth NMOS transistor (M21) in the control circuit (2) to be turned off (OFF), and the logic high level of the standby mode control signal (S) causes the fifth The NMOS transistor (M22) is turned on (ON), and the fifth NMOS transistor (M22) is used as an equalizer, so that the fifth NMOS transistor (M22) in an on state can be used. The voltage level of the first low voltage node (VL1) is equal to the voltage level of the second low voltage node (VL2), and the voltage levels are equal to the critical value of the sixth NMOS transistor (M23) Voltage level of voltage (V _TM23 ). Figure 9 is a simplified circuit diagram of the preferred embodiment of the invention of Figure 5 during standby.

Next, how to reduce leakage current in the standby mode of the present invention will be described. Referring to FIG. 9, FIG. 9 depicts a leakage current I ₁ generated when the embodiment of the present invention is in the standby mode. I ₂ , I ₃ , wherein it is assumed that the output of the first inverter (ie, node A) in the SRAM cell is a logic Low (it is worth noting here that the second low voltage node (VL2) due to the standby mode The voltage level is maintained at the voltage level of the threshold voltage (V _TM23 ) of the sixth NMOS transistor (M23), so the voltage level of the node A is the logic Low and is maintained at the voltage level of the V _TM23 ) And the output of the second inverter (ie, node B) is logic High (power supply voltage VDD). Referring to the prior art of FIG. 1b and the embodiment of the present invention of FIG. 9, the comparison between the static random access memory of the present invention and the 6T SRAM of FIG. 1b in terms of leakage current is first described. Leakage current I _{1 of the} third NMOS transistor (M13), since the voltage level of the node A is maintained at the voltage level of the V _{TM 23} in the standby mode, and the word line (WL) is assumed to be in the standby mode. The ground voltage is set, and the bit line (BL) is set to the power supply voltage (VDD) in the standby mode, so the gate-source voltage (V _GS ) of the third NMOS transistor (M13) of the present invention is Negative value, in contrast to the standby mode, the gate-source voltage (V _GS ) of the prior art NMOS transistor (M3) of Figure 1b is equal to 0, according to the Gate Induced Drain Leakage (GIDL) effect or As can be seen from the results of Figures 3(A) and 3(B) of the US Pat. No. 6,865,119, filed on Mar. 8, 2005, the sub-critical current of the gate-source voltage of -0.1 volt is approximately the gate source for the NMOS transistor. The pole voltage is 1% of the subcritical current at 0 volts, and thus is caused by the GIDL effect and flows through the present invention. A third NMOS transistor (M13) of the drain current I ₁ is much smaller than the prior art of FIG. 1b of the NMOS transistor (M3) are; Furthermore, the present invention is the third NMOS transistor (M13) of the drain-source voltage (V _DS ) _deducts the voltage level of the V _TM23 for the power supply voltage (VDD), and the source voltage of the NMOS transistor (M3) of the conventional 1b to 6T static random access memory (V3) in the standby mode (V) _DS ) is equal to the power supply voltage (VDD), according to the Drain-Induced Barrier Lowering (DIBL) effect, the third NMOS transistor (M13) flowing through the present invention due to the DIBL effect The leakage current I _{1 is} also smaller than that of the prior art NMOS transistor (M3) of FIG. 1b; as a result, the leakage current I ₁ flowing through the third NMOS transistor (M13) of the present invention is much smaller than that of the prior art of FIG. Transistor (M3).

Next, regarding the leakage current I ₂ flowing through the first PMOS transistor (P11), the source of the first PMOS transistor (P11) is the power supply voltage (VDD) due to the standby mode, and the first PMOS The drain of the transistor (P11) is maintained at the voltage level of the _VTM23 , so the source drain voltage (V _SD ) of the first PMOS transistor (P11) of the present invention is the power supply voltage (VDD). _Deducting the voltage level of the _VTM23 , in contrast to the standby mode, the source drain voltage (V _SD ) of the prior art PMOS transistor (P1) of FIG. 1b is equal to the power supply voltage (VDD), according to the DIBL effect, Therefore, the leakage current I ₂ flowing through the first PMOS transistor (P11) of the present invention will be smaller than that of the prior art PMOS transistor (P1) of FIG.

Finally, regarding the leakage current I ₃ flowing through the second NMOS transistor (M12), since the voltage level of the second low voltage node (VL2) is maintained at the voltage level of the _VTM23 in the standby mode, the node A The voltage level is also maintained at the voltage level of the V _TM23 , and the voltage level of the node B is equal to the power supply voltage (VDD) and the base of the second NMOS transistor (M12) is the ground voltage, so the present invention The base-source voltage (V _BS ) of the second NMOS transistor (M12) is a negative value, and the 汲 source voltage (V _DS ) of the second NMOS transistor (M12) is the power supply voltage (VDD). _Deducting the voltage level of the V _TM23 , in contrast to the standby mode, the base-source voltage (V _BS ) of the prior art NMOS transistor (M2) of FIG. 1b is equal to 0, and the source of the NMOS transistor (M2) The voltage (V _DS ) is equal to the power supply voltage (VDD). According to the body effect and the DIBL effect, the leakage current I ₃ flowing through the second NMOS transistor (M12) of the present invention is much smaller than that of the first FIG. The NMOS transistor (M2) of the art. It can be seen from the above analysis that the 5T static random access memory proposed by the present invention has a lower leakage current than the prior art of FIG. 1b.

(IV) retention mode

In the hold mode, since the first low voltage node (VL1) and the second low voltage node (VL2) are both set to a ground voltage, the working principle is the same as that of the conventional 5T SRAM cell with a single bit line in FIG. This is not repeated here.

【Effects of invention】

The 5T單埠 static random access memory with high read speed proposed by the invention has the following effects:

(1) High design freedom: Since the present invention reads logic 0, the storage node (A) is _pulled down to a threshold voltage (V _TM12 ) lower than the second NMOS transistor (M12), and there are two mechanisms, one for By the word line voltage level conversion circuit (5), the word line voltage applied to the access transistor of the selected cell (ie, the third NMOS transistor M13) is pulled down to a lower power supply voltage (ie, VDD). -V _TM51 ), the other is to pull the storage node (A) by the accelerated read voltage (RGND) below the ground voltage, thus having the effect of high design freedom;

(2) Effectively reducing half-selected cell interference during reading: the present invention can be applied to the access cell of the selected cell by a word line voltage level conversion circuit (5) during a read operation ( That is, the word line voltage of the third NMOS transistor M13) is _pulled down to be lower than the power supply voltage (ie, VDD-V _TM51 ), which on the one hand can reduce the reading of the third NMOS transistor (M13) in the half selected cell. Taking interference, on the other hand, can effectively reduce the read interference of the first NMOS transistor (M11) in the half-selected cell by reducing the accelerated read voltage (RGND) required to satisfy equation (7). Reduce the efficacy of half-selected cell interference during reading;

(3) High read speed and avoiding unnecessary power consumption: The present invention employs a two-stage read operation in which the first low voltage node (VL1) is set to a ground voltage in the first phase of the read operation. The low acceleration read voltage (RGND) is matched with the high voltage level control circuit (6) to pull the high voltage node (VH) higher than the voltage level of the power supply voltage (V _DD ), thereby being effective Increasing the reading speed, and in the second phase of the reading operation, the first low voltage node (VL1) is set back to the ground voltage to reduce unnecessary power consumption;

(4) Quick entry standby mode: Since the present invention is provided with a standby start circuit (4) to prompt the SRAM to quickly enter the standby mode, and thereby seek to improve the standby performance of the 單埠SRAM;

(5) The problem of avoiding the difficulty of writing logic 1: The present invention can effectively prevent the problem of writing logic 1 by the plurality of control circuits (2) during the write operation;

(6) Low standby current: since the present invention is in the standby mode, the fifth NMOS transistor (M22) in an on state can be made such that the voltage level of the first low voltage node (VL1) is equal to the first The voltage level of the two low voltage nodes (VL2) is such that the voltage levels are equal to the level of the threshold voltage of the sixth NMOS transistor (M23), so the present invention also has the effect of low standby current;

(7) Number of low-voltage crystals: For an SRAM array having 1024 columns and 1024 rows, the conventional 1b-Fig. 6T static random access memory array requires a total of 1024 × 1024 × 6 = 6,291,456 transistors, and the present invention proposes The static random access memory requires only 1024 x 1024 x 5 + 1024 x 24 + 6 = 5,257,462 transistors, which reduces the number of transistors by 16.3%.

(8) Effectively prevent the problem that the standby mode control signal (S) temporarily becomes a logic high level due to an unexpected factor due to an unexpected factor, and the write cannot be smoothly performed: since the logic 1 is written, the node (C) The voltage level is always the ground voltage, so that it is possible to effectively prevent the standby mode control signal (S) from temporarily becoming a logic high level due to an unexpected factor when the logic 1 is written, resulting in a problem that the writing cannot be smoothly performed.

While the invention has been particularly shown and described, the embodiments of the invention may Therefore, all changes in the relevant technical scope are included in the scope of the patent application of the present invention.

1‧‧‧SRAM cell

2‧‧‧Control circuit

3‧‧‧Precharge circuit

4‧‧‧Standby start circuit

5‧‧‧Word line voltage level conversion circuit

6‧‧‧High voltage level control circuit

P11‧‧‧First PMOS transistor

WC‧‧‧ write control signal

P12‧‧‧Second PMOS transistor

M11‧‧‧First NMOS transistor

M12‧‧‧Second NMOS transistor

M13‧‧‧ Third NMOS transistor

A‧‧‧ storage node

B‧‧‧ Inverting storage node

BL‧‧‧ bit line

WLC‧‧‧ word line control signal

VDD‧‧‧Power supply voltage

VH‧‧‧ high voltage node

VL1‧‧‧ first low voltage node

VL2‧‧‧ second low voltage node

S‧‧‧Standby mode control signal

/S‧‧‧Inverted standby mode control signal

M21‧‧‧4th NMOS transistor

M22‧‧‧ Fifth NMOS transistor

M23‧‧‧ sixth NMOS transistor

M24‧‧‧ seventh NMOS transistor

M25‧‧‧8th NMOS transistor

M26‧‧‧Ninth NMOS transistor

M27‧‧‧ tenth NMOS transistor

M28‧‧‧11th NMOS transistor

RC‧‧‧ read control signal

RGND‧‧‧Accelerated reading voltage

/RC‧‧‧Inverted read control signal

/WC‧‧‧Inverted write control signal

INV‧‧‧ third inverter

D1‧‧‧First delay circuit

P31‧‧‧ Third PMOS transistor

P‧‧‧Precharge signal

M41‧‧‧12th NMOS transistor

P41‧‧‧4th PMOS transistor

C‧‧‧ node

D2‧‧‧second delay circuit

WL‧‧‧ character line

VDDH‧‧‧High power supply voltage

P51‧‧‧ Fifth PMOS transistor

M51‧‧‧Thirteenth NMOS transistor

M52‧‧‧ fourteenth NMOS transistor

P61‧‧‧6th PMOS transistor

P62‧‧‧ seventh PMOS transistor

I63‧‧‧fourth inverter

Claims (10)

A 5T單埠 static random access memory with high read speed, comprising: a memory array consisting of a plurality of columns of memory cells and a plurality of rows of memory cells, each column of memory The unit cell and each row of memory cells comprise a plurality of memory cells (1); a plurality of control circuits (2), each column of memory cells is provided with a control circuit (2); a plurality of precharge circuits ( 3), each row of memory cells is provided with a pre-charging circuit (3); a standby starting circuit (4), the standby starting circuit (4) prompts the 5T static random access memory to quickly enter the standby mode to effectively Improving the standby performance of the 5T static random access memory; a plurality of word line voltage level conversion circuits (5), each column memory cell is provided with a word line voltage level conversion circuit (5) to effectively reduce Half selected cell interference during reading; and a plurality of high voltage level control circuits (6), each column of memory cells is provided with a high voltage level control circuit (6) to improve reading when logic 0 is read Speed; where each memory cell (1) contains more A first inverter is composed of a first PMOS transistor (P11) and a first NMOS transistor (M11) connected to a power supply voltage (VDD) and a first inverter Between the first low voltage node (VL1); a second inverter consisting of a second PMOS transistor (P12) and a second NMOS transistor (M12), the second inverter is connected Between a high voltage node (VH) and a second low voltage node (VL2); a storage node (A) formed by the output of the first inverter; an inverted storage node (B) Formed by the output of the second inverter; a third NMOS transistor (M13) is connected between the storage node (A) and a bit line (BL), and the gate is connected to a word line control signal (WLC); wherein the first inverter and the second inverter are connected in an alternating coupling manner, that is, an output end of the first inverter (ie, the storage node A) Connected to an input of the second inverter, and an output of the second inverter (ie, the inverting storage node B) is connected to an input of the first inverter; and each control circuit ( 2) More includes: a fourth NMOS Crystal (M21), a fifth NMOS transistor (M22), a sixth NMOS transistor (M23), a seventh NMOS transistor (M24), an eighth NMOS transistor (M25), and a ninth NMOS device Crystal (M26), a tenth NMOS transistor (M27), an eleventh NMOS transistor (M28), a read control signal (RC), a third inverter (INV), a first delay circuit (D1), an accelerated read voltage (RGND), a write control signal (WC), an inverted write control signal (/WC), a standby mode control signal (S), and an inverted standby mode control signal (/S); wherein the source, the gate and the drain of the fourth NMOS transistor (M21) are respectively connected to a ground voltage, the inverted standby mode control signal (/S) and the second low voltage node (VL2); a source, a gate and a drain of the fifth NMOS transistor (M22) are respectively connected to the second low voltage node (VL2), the standby mode control signal (S) and the first low voltage a node (VL1); a source of the sixth NMOS transistor (M23) is connected to the ground voltage, and a gate is connected to the drain and connected to the first low voltage node (VL1); the seventh NMOS The source of the transistor (M24), The pole and the drain are respectively connected to the drain of the eighth NMOS transistor (M25), the read control signal (RC) and the first low voltage node (VL1); and the eighth NMOS transistor (M25) a source, a gate and a drain are respectively connected to the accelerated read voltage (RGND), an output of the first delay circuit (D1), and a source of the seventh NMOS transistor (M24); the first delay circuit (D1) is connected between the output of the third inverter (INV) and the gate of the eighth NMOS transistor (M25); the input of the third inverter (INV) is for receiving the read a control signal (RC), and an output is connected to an input of the first delay circuit (D1); a source, a gate and a drain of the ninth NMOS transistor (M26) are respectively connected to the ground voltage, the first a drain of a ten NMOS transistor (M27) and the first low voltage node (VL1); a source, a gate and a drain of the tenth NMOS transistor (M27) are respectively connected to the ground voltage, the writing a control signal (WC) and a gate of the ninth NMOS transistor (M26); a source, a gate and a drain of the eleventh NMOS transistor (M28) are respectively connected to the inverted standby mode control signal ( /S), the inversion a control signal (/WC) and a gate of the ninth NMOS transistor (M26); wherein, a drain of the tenth NMOS transistor (M27), a drain of the eleventh NMOS transistor (M28), and The gates of the ninth NMOS transistor (M26) are connected together to form a node (C), and the logic high level of the node (C) is the power supply voltage (V _DD ) deducting the eleventh NMOS The voltage level of one of the threshold voltages (V _TM28 ) of the transistor (M28), so when the 5T 單_{埠 SRAM} is in the non-write mode (this corresponds to the inverted write control signal (/WC) When the logic level is high, the node (C) _deducts the voltage level of the threshold voltage (V _TM28 ) of the eleventh NMOS transistor (M28) for the power supply voltage (V _DD ), instead The voltage level of the power supply voltage (V _DD ) can have a lower power consumption; and when the subsequent write mode is entered (in this case, the write control signal (WC) is a logic high level), The charge stored in the node (C) can be quickly discharged through the tenth NMOS transistor (M27) to be sufficient to turn off the ninth NMOS transistor (M26) having the node (C) as a gate, so Quickly enter the write mode; further, since the voltage level of the node (C) during the write operation is always the ground voltage, it also has a high-stability write operation; wherein, for the non-read mode The read control signal (RC) is set to the level of the accelerated read voltage (RGND) during the period to prevent leakage current during the non-read mode of the seventh NMOS transistor (M24); The startup circuit (4) is designed to rapidly charge the parasitic capacitance at the first low voltage node (VL1) to the threshold voltage of the sixth NMOS transistor (M23) during an initial period of entering the standby mode ( _VTM23 The voltage level of each word line; further, each word line voltage level conversion circuit (5) further comprises: a fifth PMOS transistor (P51), a thirteenth NMOS transistor (M51), a fourteenth NMOS transistor (M52), the read control signal (RC), the inverted write control signal (/WC), an inverted read control signal (/RC), and the word line control signal (WLC); The source, the gate and the drain of the fifth PMOS transistor (P51) are respectively connected to a word line (WL), and the inverted write control signal (/WC) And a word line control signal (WLC); a source, a gate and a drain of the thirteenth NMOS transistor (M51) are respectively connected to the word line control signal (WLC), and the read control signal ( RC) and the word line (WL); and the source, gate and drain of the fourteenth NMOS transistor (M52) are respectively connected to the word line control signal (WLC), the inversion read a control signal (/RC) and the word line (WL); wherein each word line voltage level conversion circuit (5) selects the word line (WL) of the selected unit cell during the read operation The power supply voltage (V _DD ) is converted to the power supply voltage (VDD) which is supplied to the word line after being _{biased against} the threshold voltage (V _TM51 ) of the thirteenth NMOS transistor (M51) (ie, VDD-V _TM51 ). a control signal (WLC); and during a write operation, the power supply voltage (VDD) of the word line (WL) of the selected unit cell is supplied to the word line control signal (WLC); finally, each A high voltage level control circuit (6) further comprises: a sixth PMOS transistor (P61), a seventh PMOS transistor (P62), a fourth inverter (I63), and a high power supply voltage (VDDH) Composition of the sixth PMOS transistor ( a source, a gate and a drain of P61) are respectively connected to the power supply voltage (VDD), the read control signal (RC) and the high voltage node (VH), and the seventh PMOS transistor (P62) a source, a gate and a drain are respectively connected to the high power supply voltage (VDDH), an output of the fourth inverter (I63) and the high voltage node (VH), and the fourth inverter (I63) The input is for receiving the read control signal (RC) and the output is connected to the gate of the seventh PMOS transistor (P62). 5T單埠 static random access memory with high read speed as described in claim 1, wherein each precharge circuit (3) is composed of a third PMOS transistor (P31) and a pre a charging signal (P); wherein the source, the gate and the drain of the third PMOS transistor (P31) are respectively connected to the power supply voltage (VDD), the precharge signal (P) and the corresponding a bit line (BL) for precharging the corresponding bit line (BL) to the power supply voltage (VDD) by a logic low level precharge signal (P) during a precharge period Level. 5T單埠 SRAM having a high read speed as described in claim 2, wherein the standby start circuit (4) is a fourth PMOS transistor (P41), a tenth a second NMOS transistor (M41), a second delay circuit (D2) and the inverted standby mode control signal (/S); wherein the source, gate and 汲 of the fourth PMOS transistor (P41) The poles are respectively connected to the power supply voltage (VDD), the reverse standby mode control signal (/S) and the drain of the twelfth NMOS transistor (M41); the twelfth NMOS transistor (M41) a source, a gate, and a drain are connected to the first a low voltage node (VL1), an output of the second delay circuit (D2) and a drain of the fourth PMOS transistor (P41); an input of the second delay circuit (D2) is connected to the inverted standby mode control The signal (/S), and the output of the second delay circuit (D2) is connected to the gate of the twelfth NMOS transistor (M41). 5T單埠 static random access memory with high read speed as described in claim 3, wherein the first NMOS transistor (M11) in each memory cell (1) is The second NMOS transistor (M12) has the same channel width to length ratio, and the first PMOS transistor (P11) and the second PMOS transistor (P12) also have the same channel width to length ratio. 5T單埠 SRAM having a high read speed as described in claim 4, wherein the accelerated read voltage (RGND) in each control circuit (2) is set to be low. At the ground voltage, and the absolute value of the accelerated read voltage (RGND) is set such that the voltage level of the first low voltage node (VL1) is less than the threshold voltage of the first NMOS transistor (M11) during reading. (V _TM11 ). 5T單埠 SRAM having a high read speed as described in claim 5, wherein an absolute value of the accelerated read voltage (RGND) is set to be smaller than the first NMOS transistor ( This threshold voltage (V _TM11 ) of M11). 5T單埠 SRAM having a high read speed as described in claim 1, wherein the high power supply voltage (VDDH) is set higher than the power supply voltage (VDD) but low. The sum of the high power supply voltage (VDDH) and the absolute value of the second PMOS transistor (P12) threshold voltage |V _TP12 |, that is, VDD < VDDH < VDD + | V _TP12 |. 5T單埠 SRAM having a high read speed as described in claim 1, wherein the storage node (A) originally stores a logic 0, and the write logic 1 writes an initial The instantaneous voltage (V _AWI ) satisfies the following equation: V _AWI = VDD × (R _M11 + R _M23 ) / (R _M13 + R _M11 + R _M23 ) > V _TM12 where V _AWI indicates that the storage node (A) is stored by the logic 0 is written to write the initial instantaneous voltage of logic 1, and R _M11 , R _M13 and R _M23 respectively represent the first NMOS transistor (M11), the third NMOS transistor (M13) and the sixth NMOS transistor ( The on-resistance of M23), and VDD and _VTM12 represent the threshold voltage of the power supply voltage (VDD) and the second NMOS transistor (M12), respectively. The 5T單埠 static random access memory with high read speed as described in claim 1 wherein the read operation of each memory cell (1) can be subdivided into two stages. In the first stage of the reading operation, the first low voltage node (VL1) is set to a voltage lower than the ground voltage to effectively increase the reading speed, and one of the reading operations is The second stage is to reduce the unnecessary power consumption by setting the first low voltage node (VL1) back to the ground voltage, and the time between the second phase of the read operation and the first phase is equal to the read. Taking the control signal (RC) from the logic low level to the logic high level, until the gate voltage of the eighth NMOS transistor (M25) is sufficient to turn off the eighth NMOS transistor (M25), which can be The falling delay time of the third inverter (INV) is adjusted with a delay time provided by the first delay circuit (D1). The 5T單埠 static random access memory with high read speed as described in claim 1 wherein the initial instantaneous voltage (V _AR0I ) of the storage node A when reading logic 0 satisfies the following equation :V _AR0I =VDD ×(R _M11 +(R _M24 +R _M25 )∥R _M26 )/(R _M13 +R _M11 +(R _M24 +R _M25 )∥R _M26 )+RGND×(R _M11 +R _M13 ) ∥R _M26 /(R _M24 +R _M25 +(R _M11 +R _M13 )∥R _M26 )×R _M13 /(R _M11 +R _M13 )<V _TM12 where V _AR0I indicates that the storage node A reads logic 0 The initial instantaneous voltage, R _M11 , R _{M13 ,} R _{M24 ,} R _M25 and R _M26 respectively represent the first NMOS transistor (M11), the third NMOS transistor (M13), and the seventh NMOS transistor (M24) The on-resistance of the eighth NMOS transistor (M25) and the ninth NMOS transistor (M26), and VDD, RGND, and _VTM12 respectively represent the power supply voltage (VDD), the accelerated read voltage (RGND), and The threshold voltage of the second NMOS transistor (M12).