TWI608562B - Structure of wafer carrier - Google Patents

Description

Wafer carrier disk structure

The present invention relates to a wafer carrier disk, and more particularly to a structure for a wafer carrier disk that facilitates flip-alignment and stack alignment.

In the general wafer (IC) process, the wafer is usually placed on the carrier, and the carrier has a plurality of receiving slots for placing the wafer, so the wafer carrier (IC Tray) is on the back of the wafer and transports the wafer to the customer. On the end is a carrying container of importance.

Chip on Glass (COG) is an advanced packaging technology that interconnects wafers and substrates. Flip Chip technology uses anisotropic conductive film (ACF) as the intermediate interface. The wafer of the block is bonded to the substrate; when applied to the liquid crystal display, since the substrate is glass, it is called COG. The wafer process includes grinding, cutting, provoking, visual inspection and packaging. The polishing process is a process of thinning the wafer. The polishing process is a process of rough grinding and fine grinding of the back surface of the wafer to thin the wafer, which belongs to mechanical grinding.

The cutting process is to cut the wafer into wafers for later die bonding and wire bonding and flip chip bonding. The provocation is that the wafer is picked out from the wafer and placed on the wafer carrier tray. Finally, the selected wafer is visually inspected according to the customer's specifications, and the wafer carrier tray is placed in the packaging material required by the customer, and the package is packaged. Shipped for finished products.

When the wafer is pressed against the substrate, for example, conductive glass, the wafer is first taken out from the wafer carrier and the wafer is pressed against the substrate. However, different pressing devices press the wafer in the direction of the substrate, for example, the gold bumps of the wafer must be pressed upwards to be pressed against the substrate or the gold bumps of the wafer must be directed toward The film is pressed down to the substrate, so when the direction in which the wafer is placed on the wafer carrier does not conform to the direction in which the pressing device presses the wafer in the substrate, the operator must first flip all the wafers placed on the wafer carrier and place them on the wafer carrier. The disk is so inefficient and time consuming. Based on this problem, the existing industry has developed a double-sided wafer carrier disk, but the cost of the double-sided wafer carrier disk is higher than that of the single-sided wafer carrier disk.

In order to facilitate transportation and space saving, the wafer carrier trays may be stacked on each other, but the wafer carrier trays must be stacked together according to a specific stacking direction. Conventionally, the wafer carrier trays do not have a special foolproof mechanism to prevent stacking errors, so that wafers are prone to occur. The orientation of the carrier disk stack is wrong, and it is easy to cause an abnormality when the wafer is pressed against the substrate. In addition, after the wafer is placed on the wafer carrier, a protective paper is placed over the wafer carrier to cover the wafer, such as Tavik paper, to protect the wafer. However, the wafer carrier does not have the structure of a fixed protective paper. The protective paper is easily offset, and if the protective paper is offset, the stack of the wafer carrier is likely to be poor.

As can be seen from the above, the conventional wafer carrier has the following disadvantages. The first point is that the operator does not easily flip the wafer from the conventional single-sided wafer carrier and is placed in the wafer carrier, and the error rate is high. The cost is increased. The second point: the cost of the double-sided wafer carrier is higher than that of the single-sided wafer carrier. The double-sided wafer carrier not only has high mold cost, but also has high procurement cost for the double-sided wafer carrier. The stability of the disk process is poor. Thirdly, the conventional wafer carrier does not have a special anti-dwelling mechanism for stacking direction, so it is easy to cause the direction of stacking of the wafer carrier. In the fourth point, the conventional wafer carrier cannot fix the protective paper. The protective paper is easily offset, and the wafer carrier tray stacking is likely to be poor.

In view of the above disadvantages of the prior art, the present invention further improves the structure of a conventional wafer carrier disk, and invents a structure of a wafer carrier disk. The present invention provides a wafer carrier disk having a plurality of inverted substrates. Loading the alignment member and the plurality of stacked alignment members, the flip-chip alignment members are convenient for the operator to reverse the wafer carrier tray on which the wafer is placed and carried on another wafer The disk is flipped over the other wafer carrier tray, thereby increasing the success rate of the wafer inversion, and the stacked alignment members are disposed asymmetrically on the wafer carrier tray to achieve the stacking direction limitation. The protective paper can be fixed to avoid paper offset.

One of the objects of the present invention is to provide a wafer carrier structure that facilitates flipping a wafer carrier and flipping it onto another wafer carrier to flip the wafer in the wafer carrier and place it in the other wafer carrier. Thus, the labor cost of the inverted wafer can be reduced, and the wafer is indeed placed in the wafer carrier to increase the success rate of the operation.

It is an object of the present invention to provide a wafer carrier disk structure having a structure that limits the stacking direction to increase the accuracy of the wafer carrier disk stack.

SUMMARY OF THE INVENTION One object of the present invention is to provide a wafer carrier disk structure capable of holding a protective sheet for protecting a wafer to avoid a positional deviation of the protective paper placement and avoiding a situation in which the wafer carrier disk stack is defective.

The invention discloses a structure of a wafer carrier disk, which mainly comprises a plurality of wafer receiving slots and a plurality of flip-chip alignment members, wherein the flip-chip alignment members are disposed on an upper surface of the wafer carrier tray. In addition, the wafer carrier tray further includes a plurality of stacked alignment members disposed on the wafer carrier tray, and the stacked alignment members are arranged asymmetrically.

The present invention discloses a structure of a wafer carrier disk, which is applied to a flip chip to invert a wafer. The wafer carrier disk mainly includes a first carrier disk and a second carrier disk. The first carrier disk includes a plurality of first carrier disks. The alignment member and the plurality of first wafer receiving slots, the second carrier tray comprises a plurality of second flip-chip alignment members and a plurality of second wafer receiving slots, the second flip-chip alignment members corresponding to The first flip-chip alignment member, the second flip-chip alignment members of the second carrier tray are coupled to the first flip-chip alignment members of the first carrier tray, the first carrier tray and the first carrier tray Two carrier disk flip After being inverted, the plurality of wafers placed in the first wafer receiving slots of the first carrier are inverted and placed in the second wafer receiving slots of the second carrier.

The present invention discloses a structure of another wafer carrier, which limits the stacking direction of the wafer carrier. The main carrier includes a first carrier and a second carrier. The first carrier includes a plurality of first stacks. And a plurality of first chip accommodating slots, wherein the first stack aligning members are disposed on the upper surface of the first carrier platter and are arranged in an asymmetric manner, and the second carrying trays comprise a plurality of second stack aligning positions And a plurality of second chip accommodating slots, wherein the second stack aligning members correspond to the first stacking aligning members, and are disposed on the bottom surface of the second carrying tray, and the second of the second carrying trays The stacking member is matched to the first stacking members of the first carrier, and the second carrier is stacked on the first carrier.

Furthermore, a protective paper is disposed on the first chip receiving slots, and the protective paper is disposed between the first stacked alignment members, and the protective paper is fixed to the first chip receiving slots. on.

10‧‧‧First carrier

110‧‧‧First substrate

120‧‧‧ first frame

1210‧‧‧First chip receiving slot

1220‧‧‧Second frame receiving groove

130‧‧‧First stacking alignment

140‧‧‧ Third stacking alignment

20‧‧‧Second carrier

210‧‧‧second substrate

220‧‧‧ second frame

2210‧‧‧Second wafer receiving slot

2220‧‧‧The first frame accommodates the slot

230‧‧‧Second stacking alignment

240‧‧‧Four stacking alignment

310‧‧‧First Opposite Angle

320‧‧‧ second alignment angle

40‧‧‧Protection paper

50‧‧‧ wafer

11‧‧‧First carrier

111‧‧‧First substrate

121‧‧‧ first frame

1211‧‧‧First chip receiving slot

131‧‧‧First flip-up alignment

132‧‧‧ Third inverted counterparts

141‧‧‧ third stacking alignment

21‧‧‧Second carrier

211‧‧‧second substrate

221‧‧‧ second frame

2211‧‧‧Second wafer receiving slot

231‧‧‧Second stacking alignment

241‧‧‧Second flip-chip alignment

242‧‧‧fourth stacking alignment

FIG. 1A is a schematic diagram of the operation of the stacking tray of the first embodiment of the present invention; FIG. 1B is a second schematic diagram of the operation of the stacking tray of the first embodiment of the present invention; Figure: is a schematic view of a fixed protective paper according to a first embodiment of the present invention; the third drawing is a schematic structural view of a second embodiment of the present invention; and Figure 4A is the third embodiment of the present invention. FIG. 4 is a schematic diagram of the operation of the inverted wafer of the third embodiment of the present invention; FIG. 4C is an inverted view of the third embodiment of the present invention. Schematic diagram of the operation of the wafer; FIG. 4D is a schematic diagram of the operation of the inverted wafer of the third embodiment of the present invention; FIG. 5 is a schematic structural view of the fourth embodiment of the present invention; Figure 6 is a schematic diagram 1 of the operation of the stacking tray of the fifth embodiment of the present invention; and Figure 6 is a schematic diagram of the operation of the stacking tray of the fifth embodiment of the present invention; Figure 6C is a schematic view showing the operation of the inverted wafer of the fifth embodiment of the present invention.

In order to provide a better understanding and understanding of the features and advantages of the present invention, the preferred embodiments and the detailed description are as follows: the present invention is to solve the prior art. Regarding the problem of the structure of the wafer carrier, in the process of pressing the wafer on the substrate, the wafer placed in the wafer carrier sometimes needs to be flipped over and placed in the wafer carrier. If the wafer is manually flipped one by one, the error rate is high. Moreover, it takes time, and the cost of placing the wafer by using the double-sided wafer carrier is high, and the process of the double-sided wafer carrier is less stable. In addition, the mechanism for preventing the stacking direction from being wrong is poor. Moreover, the conventional wafer carrier can not fix the protective paper on the wafer carrier. To overcome the above problems, the present invention provides a structure of a wafer carrier.

First, please refer to FIG. 1A and FIG. 1B, which are schematic diagrams of operation and operation of the stacking carrier of the first embodiment of the present invention; as shown in the figure, this embodiment is a second The carrier trays 20 are stacked on a first carrier tray 10, and the plurality of first stack alignment members 130 of the first carrier tray 10 are coupled to the plurality of second stack alignment members 230 of the second carrier tray 20, The second carrier 20 is stacked on the first carrier 10 .

The first carrier 10 includes a first substrate 110, a first frame 120, and the first stack alignment member 130. The first frame 120 is disposed on the first substrate 110. The first frame 120 is smaller than the first substrate 110, and the first frame 120 has a plurality of first wafer receiving grooves 1210. The first stacked alignment members 130 are asymmetrically disposed on the first frame 120. And the second carrier 20 is stacked on the first carrier 10, the second carrier 20 The second substrate 210 is disposed on the second substrate 210, and the second frame 220 is smaller than the second substrate 210. The second frame 220 is disposed on the second substrate 210. The second substrate 210, and the second frame 220 has a plurality of second wafer receiving grooves 2210, and the second stacked alignment members 230 correspond to the first stacked alignment members 130, and are disposed on the second substrate The bottom surface of the second substrate 210 is disposed on the bottom surface of the second carrier 20 . The above asymmetric arrangement means that the same position is not provided in the relative position of the carrier. As shown in FIG. 1A, the positions of the first stack alignment members 130 disposed on the left and right sides of the first frame body 120 are not the same, that is, located on the left and right sides of the first carrier tray 10. The first stack alignment members 130 of the circumference are not symmetrical, that is, the first stack alignment members 130 are arranged asymmetrically.

The first carrier tray 10 of the present invention has the first stack alignment members 130 disposed asymmetrically, and the second carrier tray 20 has the second stack alignments corresponding to the first stack alignment members 130. When the second carrier tray 20 is to be stacked on the first carrier tray 10, the corresponding positions of the first stack alignment member 130 and the second stack alignment members 230 are stacked. The second carrier trays 20 can be stacked on the first carrier trays 10, and the second carrier trays 20 can be stacked on the first carrier trays 10 such that the second carrier trays 20 are The stacking direction stacked on the first carrier 10 is limited.

The first stack alignment member 130 of the present invention is a convex member, and the second stacked alignment members 230 corresponding to the first stacked alignment member 130 are concave members, but the present invention does not The first stacking member 130 and the second stacking member 230 are respectively required to be a convex member and a concave member, which may be a concave member, a convex member or a combination of a convex member and a concave member. The stacking alignment member 130 can be coupled to the second stacking alignment members 230 in a manner of fitting, fixing or mating.

In addition, a first frame accommodating groove 2220 is disposed on the bottom surface of the second substrate 210 of the second carrier 20, and the second stack aligning member 230 is disposed in the first frame accommodating groove 2220. The first stacking member 130 is coupled to the second stacking member 230, and the first housing 120 is received. In the first frame receiving groove 2220, the stack stability between the first carrier 10 and the second carrier 20 is increased.

Furthermore, the first carrier tray 10 is further provided with a plurality of third stack alignment members 140. The third stack alignment members 140 are disposed on the bottom surface of the first substrate 110. The third stack alignment members 140 are disposed on the bottom surface of the first substrate 110. Corresponding to a plurality of stacked alignment members disposed symmetrically on another carrier, the other carrier is the same or similar to the second carrier 20, such that when the first carrier 10 is to be stacked on the other carrier The third stack alignment member 140 of the first carrier tray 10 must correspond to the stacked alignment members disposed asymmetrically on the other carrier tray. The first carrier tray 10 can be stacked on the stacker. This is another carrier disk. It can be seen from the above that the present invention uses the asymmetric alignment members on the carrier trays to make the stacking direction between the carrier trays restrictive. The third stacking member 140 is not limited to the convex member, the female member, or the combination of the male member and the female member. The third stacked alignment member 140 and the corresponding stacked alignment member are embedded with each other. Combine, fix or match.

Further, a second frame accommodating groove 1220 is disposed on the bottom surface of the first carrier 10, and the third stack aligning member 140 is disposed in the second frame accommodating groove 1220, and the third stacked pair The frame member 140 is coupled to the plurality of stacked alignment members of the other carrier, and the frame of the other carrier is received in the second frame receiving slot 1220 to increase the first carrier 10 and the other carrier. Stacking stability between the carrier trays.

In addition, the second carrier tray 20 is further provided with a plurality of fourth stack alignment members 240, and the fourth stack alignment members 240 are asymmetrically disposed on the periphery of the second frame 220, and the fourth stack pair The position member 240 corresponds to a plurality of stacked alignment members asymmetrically disposed at the bottom of the other carrier tray, and the other carrier tray is the same or similar to the first carrier tray 10, such that when the other carrier tray is to be stacked on the first When the second carrier tray 20 is above, the stacking alignment members at the bottom of the other carrier tray must correspond to the fourth stack alignment members 240 asymmetrically disposed by the second carrier tray 20, and the other carrier The disk can be stacked on the second carrier 20 so that the second carrier 20 and the other carrier The stacking direction between the discs is restrictive. The present invention does not limit the fourth stack alignment member 240 to be a convex member, a concave member or a combination of a convex member and a concave member. The fourth stacked alignment member 240 is coupled to the corresponding stacked alignment member to be embedded with each other. Combine, fix or match.

The second carrier 20 of the present invention is stacked on the first carrier 10 , and the second substrate 210 of the second carrier 20 is stacked on the first substrate 110 of the first carrier 10 . In addition, one corner of the first substrate 110 serves as a first alignment angle 310, and one corner of the second substrate 210 serves as a second alignment angle 320, and the shape of the second alignment angle 320 corresponds to the first The shape of the alignment angle 310 is such that when the second carrier 20 is to be stacked on the first carrier 10, the first alignment angle 310 and the second alignment angle 320 are used for direct visual observation by the operator. The stacking direction of the first carrier 10 and the second carrier 20 is known. In an embodiment of the invention, the first alignment angle 310 and the second alignment angle 320 are both chamfered.

It can be seen from the above description and the illustration that in the embodiment of the present invention, the structure of the second carrier 20 is the same as that of the first carrier 10, so that it is convenient to develop the mold and the production carrier, and only need to use the same mold. The carrier tray of the present invention can be produced at a reduced cost. In addition, the first stack alignment members 130 of the first carrier 10 are not necessarily disposed on the periphery of the first frame 120, and may be disposed on the periphery of the first substrate 110 or on the periphery of the first substrate 110. The periphery of the first frame 120 and the periphery of the first substrate 110 are disposed at other suitable positions according to the use requirements. The fourth stack alignment members 240 located on the second carrier 20 may also be disposed on the periphery of the second substrate 210. In other words, the first stack alignment member 130 and the fourth stack alignment member 240 of the present invention are respectively disposed on the upper surfaces of the first carrier tray 10 and the second carrier tray 20, and the The second stacking member 230 and the third stacking member 140 are respectively disposed on the bottom surface of the second carrier 20 and the first carrier 10 .

In addition, please refer to the second figure, which is a schematic view of the fixed protection paper of the first embodiment of the present invention; as shown in the figure, the present invention further extends to the first wafer receiving slots 1210. A protective paper 40 is disposed between the first stacking aligning members 130, and the first stacking aligning members 130 are disposed around the first accommodating accommodating slots 1210. The protective paper 40 is limited to the first stacked alignment members 130, and the first stacked alignment members 130 are coupled to the second stacked alignment members 230, such that the protective paper 40 is limited to the first A wafer receiving groove 1210 prevents the protective paper 40 from being easily offset, and does protect the wafer without causing a problem of poor wafer carrier stacking. The protective paper 40 is a Tavik paper.

Please refer to the third figure, which is a schematic structural view of the second embodiment of the present invention. As shown in the figure, in the embodiment, the first stack alignment member 130 is aligned with the fourth stack. The member 240 is a strip-shaped protrusion, and the second stack-aligning member 230 and the third stack-aligning member 140 are strip-shaped recesses. Referring to FIG. 1A, the first stack alignment member 130 and the fourth stack alignment member 240 are cylindrical protrusions, and the second stack alignment member 230 is The third stacking aligning members 140 are cylindrical recesses, and thus it is understood that the present invention does not limit the shape of the stacked aligning members. The shapes of the first stacking aligning members 130 are corresponding to the shapes of the second stacking aligning members 230, and are combined with each other in a manner of fitting, fixing or mating, and the third stacking aligning members 140 are The combination of the corresponding stacked alignment members is also combined with the mutual fitting, fixing or matching described in this paragraph, and the manner in which the fourth stacked alignment member 240 is combined with the corresponding stacked alignment member is the same. It is also combined with the mutual fitting, fixing or matching described in this paragraph.

Please refer to FIG. 4A to FIG. 4D, which are diagrams 4 to 4 of the operation of the inverted wafer according to the third embodiment of the present invention; as shown in the figure, the embodiment is shown in the first place. The plurality of wafers 50 of the disk 11 are carried and are placed in a second carrier disk 21. The plurality of first flip-chip alignment members 131 of the first carrier tray 11 and the plurality of second flip-chip alignment members 241 of the second carrier tray 21 cooperate with each other, so that the first carrier tray 11 can be flipped. The plurality of first wafer receiving slots 1211 of the first carrier tray 11 are corresponding to the plurality of second wafer receiving slots 2211 of the second carrier tray 21, and are disposed on the second carrier tray 21 Some of the first wafer receiving slots 1211 The wafers 50 are inverted and placed in the second wafer receiving grooves 2211 of the second carrier 21 . The second flip-chip alignment members 241 of the second carrier tray 21 correspond to the first flip-chip alignment members 131 of the first carrier tray 11 , and the first flip-chip alignment members 131 . The first stacked alignment members 130 can be identical to the previous embodiments.

The first carrier 11 includes a first substrate 111, a first frame 121, and the first flip-chips 131. The first frame 121 is disposed on the first substrate 111, and The first frame body 121 has the first wafer receiving slots 1211, and the first flip-chip alignment members 131 are asymmetrically disposed on the periphery of the first frame body 121. The device 131 may be disposed on the periphery of the first substrate 111 or on the periphery of the first frame 121 and the periphery of the first substrate 111. The wafers 50 are respectively placed on the first wafers. Placed in the slot 1211. The second carrier 21 includes a second substrate 211, a second frame 221, and the second flip-chip alignment member 241. The second frame 221 is disposed on the second substrate 211, and The second frame body 221 has the second chip receiving slots 2211, and the second flip-chip alignment members 241 are disposed on the periphery of the second frame body 221 corresponding to the first flip-chip alignment members 131. on.

When the wafers 50 placed on the first carrier 11 are flipped and placed in the second carrier 21, first, as shown in FIG. 4A, the second flips according to the second carrier 21 are Corresponding positions of the aligning member 241 and the first flip-chip aligning members 131 of the first carrying tray 11 are turned over the second carrying tray 21 on the first carrying tray 11 to make the second wafers The slots 2211 correspond to the first wafer receiving slots 1211, and the second wafer receiving slots 2211 correspond to the wafers 50 disposed in the first wafer receiving slots 1211. Then, as shown in FIG. 4B, after the first carrier 11 is flipped together with the second carrier 21, as shown in FIG. 4C, the first carrier 11 is placed on the second carrier. The wafers 50 are placed in the second wafer receiving slots 2211 of the second carrier 21 from the first wafer receiving slots 1211 of the first carrier 11 . most Thereafter, the first carrier 11 is flipped over from the second carrier 21, as shown in FIG. 4D, that is, the operation of flipping the wafers 50 and placing them in the second carrier 21 is completed.

As described above, the wafer carrier of the present invention can be utilized for inverting a wafer, and the second flip-off members 241 of the second carrier 21 are first located on the first of the first carrier 11 The first carrier accommodating disk 11 is flipped over the first carrier disk 11 so that the first chip accommodating slots 1211 of the first carrier disk 11 correspond to the second carrier. The second wafer accommodating grooves 2211 of the disk 21 are connected to each other, and the flipping between the two is reversed, so that the wafers 50 are placed in the second chip accommodating grooves 2211. The above method eliminates the labor cost of wafer inversion, and increases the success rate of wafer inversion operation, and is relatively cheaper than the cost of using the double-sided wafer carrier disk in the past, and the process stability of the double-sided wafer carrier disk is poor. .

The first flip-chip alignment member 131 of the present invention is a convex member, and the second flip-chip alignment members 241 corresponding to the first flip-chip alignment members 131 are concave members, but The invention does not limit that the first flip-chip alignment member 131 and the second flip-chip alignment members 241 must be convex members and concave members, respectively, and the two may be concave members, convex members or convex members and concave members. In combination, the first flip-chip alignment members 131 can be coupled to the second flip-chip alignment members 241 in a manner of fitting, fixing or mating.

5 is a schematic structural view of a fourth embodiment of the present invention; as shown in the figure, in the embodiment, the first flip-chip alignment members 131 include strip-shaped convex members and concave portions. And the second flip-chip alignment members 241 also include strip-shaped protrusions and recesses to match the two. Referring to FIG. 4A, the first flip-chip alignment member 131 and the second flip-chip alignment member 241 shown in FIG. 4A are respectively a cylindrical convex member and a cylindrical concave member, so that the present invention can be understood. The shapes of the flip-chip alignment members are not limited, and the shapes of the first flip-chip alignment members 131 correspond to the shapes of the second flip-chip alignment members 241 to fit, fix or cooperate with each other. Other ways to combine.

Please refer to FIG. 6A to FIG. 6C respectively, which is a schematic diagram of the operation of the stacked carrier tray and the operation of the inverted wafer according to the fifth embodiment of the present invention; as shown in the figure, the present embodiment The third embodiment (the fourth A figure) is different in that the second carrier 21 is further provided with a plurality of second stack alignment members 231, and the second stack alignment members 231 correspond to the first flip-chip alignment members. The second stacking member 231 is disposed on the bottom surface of the second substrate 211, and the second stacking member 231 is matched to the first flip-chip alignment member 131, so that the second carrier tray 21 can be stacked on the first carrier tray. Above 11. As can be seen from the above, the first flip-chip alignment members 131 have a stacking function, and are the same as the stacking functions of the first stacked alignment members 130 shown in FIG.

Furthermore, the first carrier tray 11 is further provided with a plurality of third stack alignment members 141. The third stack alignment members 141 are asymmetrically disposed on the bottom surface of the first substrate 111, and the second carrier tray 21 is further Further, a plurality of fourth stack aligners 242 are disposed, and the fourth stack aligners 242 are disposed on the periphery of the second frame 221, and the fourth stacks are disposed on the periphery of the second stack 221 The aligning member 242 can be coupled to the third stacking member 141. As shown in FIG. 6B, other carrier trays that are the same as the first carrier tray 11 are stacked on the second carrier tray 21.

In addition, a plurality of third flip-chip alignment members 132 are disposed on the first carrier tray 11 , and the third flip-chip alignment members 132 correspond to the fourth stack alignment members 242 of the second carrier tray 21 . That is, the third flip-chip alignment members 132 are matched with the fourth stack alignment members 242. Thus, as shown in FIG. 6C, the second carrier tray 21 can be inverted and placed on the first carrier tray 11. Thereafter, the first carrier 11 and the second carrier 21 are flipped in accordance with the action shown in FIG. As shown in FIG. 4C, the first carrier tray 11 is placed on the second carrier tray 21, that is, the second wafer receiving slots 2211 of the second carrier tray 21 correspond to the first carrier tray. The first wafer accommodating grooves 1211 of the first and second accommodating grooves 2211 are inverted.

It can be seen from the above that the first flip-chip alignment members 131 of the first carrier 11 have the function of stacking alignment and the fourth of the second carrier 21, in addition to the function of inverted alignment. In addition to the function of stack alignment, the stacked alignment member 242 also has the function of inverted alignment. by The above description and the illustration show that the first carrier 11 of this embodiment is identical to the second carrier 21, and is convenient for production.

In summary, the present invention provides a structure of a wafer carrier disk having a plurality of flip-chip alignment members placed when the plurality of wafers placed on one carrier disk are flipped over and placed on another carrier disk. The flip-chip alignment members of one of the carrier pads of the wafer are mated with the flip-chip alignment members of the other carrier tray on which the wafer is not placed, so that the carrier tray on which the wafers are placed can be flipped and inverted On this other carrier, the wafers are thus flipped over and indeed placed in the other carrier. The wafer carrier of the present invention can be used to flip a wafer to invert a wafer, which reduces the cost of inverting the wafer and increases the success rate and efficiency of the inverted wafer.

In addition, the wafer carrier of the present invention further includes a plurality of stacked alignment members, the stacked alignment members are asymmetrically disposed on the carrier tray, and the second carrier tray is to be stacked on the first carrier tray. The stacked alignment members of the disk must be matched with the stacked alignment members of the first carrier, and the second carrier can be stacked on the first carrier, because the stacked alignment members are arranged asymmetrically. Therefore, the stacking alignment members limit the stacking direction of the two carrier trays, so as to avoid the stacking direction error when the two carrier trays are stacked, and the function of limiting the stacking direction.

Furthermore, a protective paper is disposed on the plurality of wafer receiving slots of the carrier, and the protective paper is disposed between the stacked alignment members, and the stacked alignment members fix the protective paper for protecting the wafer, so the protective paper It is confined to the first wafer receiving grooves to prevent the protective paper from deviating from the chip receiving grooves, thereby avoiding the problem of poor stacking of the wafer carrier disks.

Therefore, the present invention is a novelty, progressive and available for industrial use. It should be in accordance with the patent application requirements of the Chinese Patent Law. It is undoubtedly the invention patent application, and the Prayer Council will grant the patent as soon as possible. .

However, the above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, so that the shapes, structures, features, and spirits described in the claims of the present invention are equally changed. Modifications are intended to be included in the scope of the patent application of the present invention.

11‧‧‧First carrier

111‧‧‧First substrate

121‧‧‧ first frame

1211‧‧‧First chip receiving slot

131‧‧‧First flip-up alignment

132‧‧‧ Third inverted counterparts

141‧‧‧ third stacking alignment

21‧‧‧Second carrier

211‧‧‧second substrate

221‧‧‧ second frame

2211‧‧‧Second wafer receiving slot

231‧‧‧Second stacking alignment

241‧‧‧Second flip-chip alignment

242‧‧‧fourth stacking alignment

Claims (18)

A structure of a wafer carrier disk, which is adapted to be flip-chip mounted on another wafer carrier disk, comprising: a plurality of chip receiving grooves; and a plurality of first flip-chip alignment members disposed on the upper surface of the wafer carrier disk Wherein the upper surface of the other wafer carrier has a plurality of second flip-chip alignment members, and the first flip-chip pair is opposite when the upper surface of the wafer carrier is opposite the upper surface of the other wafer carrier The bit members respectively correspond to the second flip-chip alignment members, so that the upper surface of the wafer carrier disk is fixed on the other chip by the first flip-chip alignment members and the second flip-chip alignment members The upper surface of the carrier. The structure of the wafer carrier of claim 1, further comprising: a substrate; and a frame disposed on the substrate, wherein the chip receiving slots are disposed in the frame; wherein the first The flip-chip alignment member is disposed on the substrate or/and the frame. The structure of a wafer carrier according to claim 2, wherein a corner of the substrate is a pair of corners. The structure of the wafer carrier according to claim 1, wherein the first flip-chip alignment members are arranged asymmetrically. The structure of the wafer carrier according to claim 1, further comprising: a plurality of stacked alignment members disposed on the wafer carrier, the stacked alignment members being arranged asymmetrically. The structure of the wafer carrier according to claim 5, wherein a protective paper is further disposed on the wafer receiving grooves, and the protective paper is disposed between the stacked alignment members. A structure of a wafer carrier, comprising: a first carrier, comprising a plurality of first flip-chip alignment members and a plurality of first wafer receiving slots, wherein the first flip-chip alignment members are disposed on the first An upper surface of the carrier tray; and a second carrier tray comprising a plurality of second flip-chip alignment members and a plurality of second wafer receiving slots, wherein the second flip-chip alignment members are disposed on the second carrier tray When the upper surface of the first carrier tray faces the upper surface of the second carrier tray, the second flip-chip alignment members respectively correspond to the first flip-chip alignment members; The second flip-chip alignment members of the two carrier trays are coupled to the first flip-chip alignment members of the first carrier tray, and the first carrier tray and the second carrier tray are inverted and inverted, and then placed on the first carrier tray The plurality of wafers of the first wafer receiving slots of the first carrier are flipped and are placed in the second wafer receiving slots of the second carrier, and The upper surface of the first carrier tray can be fixed to the upper surface of the second carrier tray by the first flip-chip alignment member and the second flip-chip alignment members. The structure of the wafer carrier of claim 7, wherein the first carrier further comprises: a first substrate; and a first frame disposed on the first substrate, the first wafers The first carrier is disposed on the first substrate or/and the first frame; the second carrier further includes: a second substrate; a second frame is disposed on the second substrate, and the second chip receiving slots are disposed on the second frame; wherein the second flip-chip alignment members are disposed on the second substrate or/and the The second frame. The structure of the wafer carrier tray of claim 7, wherein the first flip-chip alignment members and the second flip-chip alignment members are arranged asymmetrically. The structure of the wafer carrier of claim 7, wherein the second carrier further comprises a plurality of stacked alignment members, the stacked alignment members corresponding to the first of the first carrier The aligning member is disposed on the bottom surface of the second carrier, and the stacked aligning members of the second carrier can be coupled to the first flip aligning members of the first carrier The bottom surface of the two carrier trays can be stacked on the first A carrier on the upper surface of the disk. The structure of the wafer carrier of claim 7, wherein the first carrier further comprises a plurality of stacked alignment members, the stacked alignment members are disposed on the bottom surface of the first carrier, and are non- Symmetrical arrangement. A structure of a wafer carrier, comprising: a first carrier, comprising a plurality of first flip-chip alignment members and a plurality of first wafer receiving slots, wherein the first flip-chip alignment members are disposed on the first Carrying the upper surface of the disk, and the first flip-chip alignment members are arranged asymmetrically, the first flip-chip alignment members are further used as a plurality of first stack alignment members; and a second carrier tray includes a plurality of a second stacking alignment member, a plurality of second flip-chip alignment members and a plurality of second wafer receiving slots, wherein the second stacked alignment members correspond to the first stacked alignment members, and are disposed on the second The bottom surface of the second carrier tray is disposed on the bottom surface of the second carrier tray, and when the upper surface of the second carrier tray faces the upper surface of the first carrier tray, The first flip-chip alignment members respectively correspond to the second flip-chip alignment members; wherein the second stack alignment members of the second carrier tray can be matched to the first stacks of the first carrier tray Aligning the second carrier tray on the first carrier, or on the first carrier The face of the second carrier The upper surface of the first carrier tray can be fixed to the upper surface of the second carrier tray by the first flip-chip alignment member and the second flip-chip alignment members. The structure of the wafer carrier of claim 12, wherein the first carrier further comprises: a first substrate; and a first frame disposed on the first substrate, the first wafers The first stacking member is disposed on the first substrate or/and the first frame; the second carrier further includes: a second substrate; The second frame is disposed on the second substrate, and the second substrate receiving slots are disposed on the second frame; wherein the second stacked alignment members are disposed on the bottom surface of the second substrate. The structure of the wafer carrier tray of claim 12, wherein the first carrier tray further comprises a plurality of third stack alignment members, wherein the third stack alignment members are disposed on the first carrier tray The bottom surface is arranged asymmetrically. The structure of the wafer carrier tray of claim 12, wherein the second carrier tray further comprises a plurality of fourth stack alignment members, wherein the fourth stack alignment member is disposed on the second carrier tray The upper surface is arranged asymmetrically. The wafer carrier tray according to claim 15 of the patent application scope The structure, wherein the first carrier tray further comprises a plurality of third flip-chip alignment members, the third flip-chip alignment members of the first carrier tray are disposed on the upper surface of the first carrier tray, and corresponding to the The third stacking alignment member of the second carrier tray, the third flip-chip alignment member of the first carrier tray when the upper surface of the first carrier tray faces the upper surface of the second carrier tray And the plurality of first stacking aligning slots of the second carrier, the first carrier and the second carrier are inverted and inverted, and the plurality of first accommodating slots of the first carrier are placed The wafers are flipped and placed in the second wafer receiving slots of the second carrier. The structure of the wafer carrier of claim 12, wherein a protective paper is further disposed on the first wafer receiving grooves, and the protective paper is disposed between the first stacked alignment members. . The structure of the wafer carrier of claim 12, wherein a corner of the first carrier is a first alignment angle, and a corner of the second carrier is a second alignment angle. The shape of the second alignment angle corresponds to the shape of the first alignment angle.