TWI607581B - Light-emitting diode chip - Google Patents

Description

Light-emitting diode chip

The present invention relates to a light emitting diode wafer.

The present patent application claims the priority of the German Patent Application No. 10 2015 109 796.6, the entire disclosure of which is incorporated herein by reference.

It is an object of the present invention to provide a light emitting diode wafer having a reduced switching time.

A light emitting diode chip is provided. The light emitting diode chip is designed to emit electromagnetic radiation during operation. In particular, the wavelength of the electromagnetic radiation may be in the red and/or infrared range of the electromagnetic spectrum. The peak wavelength of this electromagnetic radiation can be at least 600 nm and up to 1000 nm. "Spike wavelength" here and below refers to the wavelength at which the spectrum of electromagnetic radiation emitted during operation has a maximum value, particularly the global maximum.

According to at least one embodiment of the light-emitting diode chip, it comprises a first semiconductor layer. An active region is epitaxially grown on the first semiconductor layer. For example, the epitaxial growth is achieved by molecular beam epitaxy (MBE) or metal organic vapor phase epitaxy (MOVPE). The active zone can emit electromagnetic radiation during operation.

The light emitting diode wafer has a main extension surface that extends in the lateral direction. The light emitting diode wafer has a thickness perpendicular to the lateral direction, that is, in the stacking direction. Such a thickness of the light-emitting diode wafer is small relative to the maximum extent of the light-emitting diode wafer in the lateral direction. The "thickness" of a layer here and below always refers to its maximum range in the stacking direction.

The active zone includes at least one quantum well layer. The active region may additionally have at least two quantum well layers and at least one barrier layer disposed between the at least two quantum well layers. In particular, the active region may comprise a plurality of barrier layers and a plurality of quantum well layers, which are sequentially stacked, for example, in the stacking direction. Here, one barrier layer may be surrounded by two quantum well layers and/or a quantum well layer may be surrounded by two barrier layers, respectively.

A quantum well layer is characterized in particular by a charge carrier, in particular an electron, which undergoes a quantization of its energy-specific state due to its confinement. This limitation can be achieved, for example, by a barrier layer. In particular, a plurality of barrier layers may be present, wherein the two barrier layers may be adjacent to one of the plurality of quantum well layers on both sides. Additionally, there may be first and/or second intervening layers that may respectively adjoin the quantum well layer, with the first and/or second intervening layers also confining the charge carriers. In the interior of the quantum well layer, the degree of freedom of movement of the charge carriers can be limited to at least one spatial dimension.

The first semiconductor layer and the at least one quantum well layer may each be formed of or consist of a (compound-) semiconductor material. In particular, the respective materials of the first semiconductor layer and the quantum well layer have a crystal structure.

Further, the barrier layer which is present when necessary may be formed of or composed of a (compound-) semiconductor material. In particular, the barrier layer The material has a crystal structure. The material of the quantum well layer may have a band gap smaller than the band gap of the material of the barrier layer. In addition, the material of the first semiconductor layer may have a band gap smaller than that of the material of the quantum well layer and/or the energy band gap of the material of the barrier layer. Also, the first and second intervening layers may be formed of or consist of a (compound-) semiconductor material.

The light-emitting diode wafer may additionally have a second semiconductor layer which is located behind the active region in the stacking direction and is disposed on a side of the active region away from the first semiconductor layer. The second semiconductor layer may likewise comprise or consist of a (compound-) semiconductor material. For example, the first semiconductor layer is a p-conductive semiconductor layer and the second semiconductor layer is an n-conductive semiconductor layer.

A first intervening layer may be disposed between the first semiconductor layer and the active region. Further, a second intervening layer may be disposed between the second semiconductor layer and the active region. In particular, the first intervening layer and/or the second intervening layer may be directly adjacent to a quantum well layer, respectively. The active zone can be grown directly on the first intervening layer. For example, a quantum well layer may be surrounded by two barrier layers or surrounded by a barrier layer and a first or second intervening layer.

According to at least one embodiment of the light-emitting diode chip, the active region is compressively tensioned. In particular, at least one of the quantum well layers is compressively tensioned.

When a material deposition (especially epitaxial deposition) on a layer is on a reference layer, if the parallel lattice constant of the layer extending along at least one lateral direction is different from the natural lattice constant of the layer, the layer For example, quantum well layers, here and below, are particularly considered to be tensioned. In the case of a quantum well layer, the reference layer can in particular be a substrate. Another way or additionally, The reference layer can be a barrier layer or a first intervening layer. In particular, the parallel lattice constant of the layer is equal to the lattice constant of the reference layer. When the layer is compressively stretched, the parallel lattice constant of the layer may be less than the natural lattice constant of the material of the layer. Furthermore, the vertical lattice constant of the layer extending in the stacking direction may be greater than the natural lattice constant of the layer material when compressed tightly.

The tensile force of one layer can be explained by the tensile coefficient. The tensile coefficient of the layer is derived from the quotient of the difference between the natural lattice constant a _{2 of the} reference layer and the natural lattice constant a ₁ of the layer relative to the natural lattice constant of the grown layer, which may be derived from the formula (a ₁ - a ₂ ) / a ₁ to describe. A positive tensile coefficient is obtained in the case of a compression tension, and a negative tensile coefficient is obtained in the case of a tensile tension.

The compressive tensile force of the quantum well layer may indicate that the crystal structure of the material of the quantum well layer has, at least in part, no natural lattice constant of the material of the quantum well layer. In particular, the lattice constant of the material of the quantum well layer may at least partially employ the lattice constant of the material of the barrier layer - or the first intervening layer. In this case, the barrier layer present in the case and/or the first intervening layer which is present when required can likewise be tensioned.

Furthermore, a layer sequence, for example, an active region, can be described by the average tensile force of the layer sequence. The average tensile force of a sequence of layers having a plurality of layers is obtained by weighting the arithmetic mean of the tensile coefficients of the layers. This weighting is performed for each of the thicknesses of the layers. The average tensile force of the active zone is thus the arithmetic mean of the weighting of the at least one quantum well layer and the tensile layer of the barrier layer present in the active zone relative to the respective thickness.

The tensile force of the active zone can be determined, for example, at a bend in the layers of the active zone, particularly the quantum well layer and the barrier layer present as the case requires. In the case of a compression tension, the active zone is particularly convexly curved. In the case of a stretch tension, there may be a concave curvature of the active area. Here, the terms "bump" and "recess" refer to a substrate on which a first semiconductor layer is grown and which is disposed in front of the first semiconductor layer in the stacking direction.

In accordance with at least one embodiment of a light-emitting diode wafer, an active region grown epitaxially on the first semiconductor layer is provided having at least one quantum well layer that is compression-tensioned.

According to at least one embodiment of the light-emitting diode chip, the active region comprises at least two quantum well layers and at least one barrier layer disposed between the at least two quantum well layers. The active region may in particular comprise a quantum well structure.

In the light-emitting diode wafer, in particular, the concept of shortening the switching time by the change of the crystal structure in the inside of the layer grown in the epitaxial manner is followed. Here, it has surprisingly been shown that the result of the compression tension is to achieve the desired shortening of the switching time. The switching time of the so-called optoelectronic semiconductor component refers in particular to the rise time and fall time of the switching pulse of the optoelectronic semiconductor component.

The compressive tensile force of the quantum well layer can cause bending of the band structure in the region of the quantum well layer. This can alleviate the phenomenon of electrons in the quantum well layer and thus achieve faster switching times. However, due to the bending of the band structure, the induction phenomenon of the hole whose effective mass is larger than that of the electron can be deteriorated in the quantum well layer. So live in the LED with the LED A situation in which the sexual region is not subjected to - or only slightly compressed by compression, for example, causes a decrease in light efficiency.

According to at least one embodiment of the light-emitting diode chip, the first semiconductor layer is epitaxially grown on a substrate. The substrate may, for example, comprise or consist of germanium, gallium arsenide and/or germanium. The average tensile force of the active zone relative to the substrate is at least 600 parts per million, preferably at least 1000 ppm and particularly preferably at least 2000 ppm.

According to at least one embodiment of the light-emitting diode chip, at least one of the quantum well layers is subjected to pseudomorph compression. When a layer of tensile force is not decomposed in the layer or only a small portion is decomposed in the layer in the form of dislocation and/or fracture, the layer is said to be subjected to pseudomorphic tension. In particular, at least one quantum well layer has a thickness that is less than the critical layer thickness of the quantum well layer. The "critical layer thickness" of a layer herein and below refers to the material-specific upper limit of the pseudo-crystal growth of the layer. In particular, the critical layer thickness of the quantum well layer is related to the natural lattice constant of the material of the quantum well layer and the difference in lattice constants of the material of the barrier layer and/or the first intervening layer that may be present.

According to at least one embodiment of the light-emitting diode chip, the tensile coefficient of the quantum well layer is numerically greater than the tensile coefficient of the barrier layer by at least 7500 ppm, preferably at least 15000 ppm. For example, in the case of averaging with reference to the material of the substrate (10), the value of the tensile coefficient of the quantum well layer is at least 5000 ppm and at most 25000 ppm.

According to at least one embodiment of the light-emitting diode chip, each quantum well layer is subjected to pseudo-compression compression, and the tensile coefficients of the quantum well layers are respectively at least 7500 ppm more than the tensile coefficient of the barrier layer, which is preferred. It is at least 15,000 ppm more.

According to at least one embodiment of the light-emitting diode chip, which emits electromagnetic radiation during operation, the peak wavelength of the electromagnetic radiation is at least 750 nm, preferably at least 850 nm, and at most 1000 nm, preferably the most 940 nm. In other words, the light-emitting diode wafer emits electromagnetic radiation in the infrared range of the electromagnetic spectrum. In particular, a light-emitting diode wafer can emit broadband radiation. In other words, the half-value width of the intensity distribution of the electromagnetic radiation as a function of wavelength can be at least 20 nm, preferably at least 50 nm.

According to at least one embodiment of the light-emitting diode chip, at least one of the quantum well layers has a thickness of at least 2 nm, preferably at least 3 nm, and at most 6 nm, preferably up to 5 nm. Meter. In particular, the thickness of the at least one quantum well layer is less than the critical layer thickness of the quantum well layer. In addition, the thickness of each barrier layer can be at least 3 times the thickness of the quantum well layer.

According to at least one embodiment of the light-emitting diode chip, at least one of the quantum well layers is mainly gallium arsenide (GaAs). In other words, the quantum well layer includes gallium and arsenic. Here, at least 5% and up to 44% of the gallium atoms may be replaced by indium atoms and/or aluminum atoms. In other words, the quantum well layer may be formed of or composed of In _x Al _y Ga _1-xy As, wherein x 1,0 y 1 and x+y 1.

Thus, the gallium atoms and/or arsenic atoms inside the quantum well layer can be replaced by heavier atoms and thus especially larger atoms, such as indium atoms. This substitution of lighter atoms will increase the natural lattice constant of the material of the quantum well layer when compared to the substitution of a few atoms in a material. This makes it easier to prepare a compression-tensioned quantum well layer.

According to at least one embodiment of the light-emitting diode chip, at least one quantum well layer is formed of In _x Ga _1-x As. Here, 0.08 x 1, the priority is 0.16 x 1. The quantum well layer therefore has a high indium-doping. The lattice constant of In _x Ga _1-x As, especially the natural lattice constant, increases particularly with the amount of indium that rises.

The at least one quantum well layer may in particular have a thickness which is at most 90% of the thickness of the quantum well layer of another form of light-emitting diode wafer, preferably up to 80% and particularly preferably up to 70% The other form of light emitting diode chip emits electromagnetic radiation having a peak wavelength of at least 1000 nanometers.

An increase in the concentration of indium in the quantum well layer can result in a reduction in the band gap in the quantum well layer. This has the effect of lengthening the emission wavelength of the light-emitting diode wafer. The length of the emission wavelength can be avoided by the decrease in the thickness of the quantum well layer. Thus, the electromagnetic radiation emitted by the operation of the light-emitting diode wafer may additionally have a peak wavelength of less than 1000 nm.

According to at least one embodiment of the light-emitting diode chip, the barrier layer is subjected to a pseudo-grain stretching force. Taking the substrate as a reference, the tensile layer has a tensile coefficient of at least -10000 ppm and at most -500 ppm. Taking the substrate as a reference, it is preferred that the tensile modulus of the barrier layer is at most -2000 ppm, and particularly preferably at most -3000 ppm.

By the pseudo-stretching tensioning of the barrier layer, in particular, a strongly compressively tensioned quantum well layer can be prepared, wherein a part of the large compression tension is compensated by the tensile tension. Thus, the average tensile force of the active zone can be less than the tensile force of the quantum well layer and thus, for example, can prevent bending of the active zone. In addition, by the compensation of the tensile force, pseudo-crystal growth of a plurality of quantum well layers can be achieved and the formation of dislocation can be prevented in the active region.

According to at least one embodiment of the light-emitting diode chip, the barrier layer is formed of Al _y Ga _1-y As _b P _1-b , wherein 0.09 b 1, the priority is 0.18 b 1, and 0 y 1. The increase in the phosphorus concentration b in the barrier layer causes the lattice constant of the material of the barrier layer, particularly the natural lattice constant, to become smaller and thus cause the tensile tension of the barrier layer.

According to at least one embodiment of the light-emitting diode chip, the intensity signal has a rise time during a switching pulse, which is at most 10 nanoseconds, preferably at most 6 nanoseconds, and/or has a fall time, which is at most 12 nanoseconds, the priority is up to 7 nanoseconds. The switching pulse can be related to a predetermined duration between the starting and closing processes of the optoelectronic semiconductor component. In particular, the intensity signal is related to the intensity of the electromagnetic radiation emitted during the switching pulse period as a function of time during operation of the light-emitting diode wafer. The rise time refers in particular to the duration required to increase the intensity signal from 10% of the maximum intensity to 90% of the maximum intensity at the start of the light-emitting diode wafer. Further, the fall time refers to the duration required when the light-emitting diode wafer is turned off to reduce the intensity signal from 90% of the maximum intensity to 10% of the maximum intensity. Rise time or fall time is especially compatible with a switching pulse The width or slope of the rising or falling side edges of the wave's intensity signal is related. The switching pulse of the light-emitting diode chip thus has a short switching time.

Short switching times of light-emitting diode chips are advantageous when used in the field of time-of-flight measurement, for example, for game consoles, cameras, mobile phones, distance measurements, and/or auto focus measurements.

According to at least one embodiment of the light-emitting diode chip, no resonator is provided. This light-emitting diode wafer is therefore not particularly a laser diode wafer. The resonator is in particular a configuration consisting of at least two mirrors, between which an electromagnetic field of at least one mode can be stored, in particular an electromagnetic field in the visible range of the electromagnetic spectrum, which in particular becomes a standing wave.

The light-emitting diode wafers described herein will be described in detail below in accordance with various embodiments and associated drawings.

10‧‧‧Substrate

11‧‧‧First semiconductor layer

12‧‧‧Second semiconductor layer

13‧‧‧First intervening layer

14‧‧‧Second intervening

2‧‧‧active area

20‧‧‧Quantum wells

20d‧‧‧The thickness of the quantum well layer

21‧‧‧ barrier

31‧‧‧ (pull) layer

32‧‧‧ reference layer

a ₁ ‧‧‧first lattice constant

a ₂ ‧‧‧second lattice constant

a _s ‧‧‧Vertical lattice constant

a _p ‧‧‧ parallel lattice constant

t _r ‧‧‧ rise time

t _f ‧‧‧fall time

Im‧‧‧Maximum intensity signal

I‧‧‧ intensity signal

M1‧‧‧ first measurement

M2‧‧‧ second measurement

M3‧‧‧ third measurement

M4‧‧‧ fourth measurement

z‧‧‧Stacking direction

Figure 1 shows an embodiment of a light emitting diode wafer as described herein.

2A and 2B show an embodiment of the crystal structure of the light-emitting diode wafer described herein.

Figure 3 shows the intensity signal of the switching pulse wave of one embodiment of the light-emitting diode wafer described herein.

Figure 4 shows the rise time or fall time.

Elements of the same, identical or identical functions in the various figures are provided with the same reference numerals. The size ratios between the various elements shown in the various figures and figures are not necessarily drawn to scale. Conversely, individual components have been shown in greater detail for clarity and/or ease of understanding.

The light-emitting diode wafer described herein is detailed in accordance with the schematic cutaway view of FIG. The light-emitting diode wafer includes a first semiconductor layer 11, a first intermediate layer 13, an active region 2, a second intermediate layer 14, and a second semiconductor layer 12 which are arranged to overlap each other in the stacking direction z in the order described above. The active zone 2 is directly adjacent to the first intervening layer 13 and the second intervening layer 14.

The active region 2 includes a plurality of quantum well layers 20 and a plurality of barrier layers 21 disposed between the two quantum well layers 20, respectively. Each quantum well layer 20 has a thickness 20d in the stacking direction.

A substrate 10 is disposed on one side of the first semiconductor layer 11 away from the active region 2, and the first semiconductor layer 11 is epitaxially grown on the substrate 10. For example, the substrate is formed of germanium, germanium, and/or gallium arsenide. Another aspect of the embodiment shown in FIG. 1 is that the substrate 10 can also be peeled off during the manufacturing process, and the light-emitting diode wafer does not include the substrate 10.

The mode of operation of the light-emitting diode wafer described herein is detailed in accordance with the schematic diagrams of FIGS. 2A and 2B. Fig. 2A shows the crystal structure of a layer 31 and a reference layer 32 in an unadjusted state and thus in an untensioned state. Fig. 2B shows the crystal structure of the layer 31 and the reference layer 32 in an adjusted state and thus in a tensioned state.

The layer 31 is shown to have a first lattice constant a ₁ in an untensioned state as shown in Fig. 2A, which may be the natural lattice constant of the material of the layer 31. The reference layer 32 has a second lattice constant a ₂ in an untensioned state, which is smaller than the first lattice constant a ₁ in the state shown. The second lattice constant a ₂ may be a natural lattice constant of the material of the reference layer 32. Alternatively, the second lattice constant a ₂ is not equal to the natural lattice constant of the material of the reference layer 32, but the crystal structure of the reference layer 32 itself is subjected to tensile force.

The reference layer 32 additionally has a second lattice constant a _{2 in} a state of being pulled as shown in FIG. 2B. However, this layer 31 now has a parallel lattice constant a _p and a vertical lattice constant a _s due to the pseudo crystal pulling force. The vertical lattice constant a _s extends along the stacking direction z, but the parallel lattice constant a _p extends perpendicular to the stacking direction z along a lateral direction. The parallel lattice constant a _p is substantially equal to the second lattice constant a ₂ and thus smaller than the first lattice constant a ₁ , but the vertical lattice constant a _{s is} greater than the first lattice constant a ₁ and the second lattice Constant a ₂ .

The parallel lattice constant a _p has been adjusted for the second lattice constant a ₂ . In particular, the parallel lattice constant a _p is equal to the second lattice constant a ₂ . The crystal structure of layer 31 is thus compacted in the transverse direction and layer 31 is subjected to a compressive tensile force. Below the critical layer thickness of layer 31, such compression in the transverse direction can be balanced by an increase in the vertical lattice constant a _s .

The layer 31 shown in FIGS. 2A and 2B may be, for example, one of the quantum well layers 20. The reference layer 32 can then be the first intervening layer 13 or the barrier layer 21 adjacent to the quantum well layer 20.

The principles described in relation to the compression tensions in relation to the 2A and 2B diagrams in the different lattice constants a ₁ , a ₂ , a _s , a _p can also be applied to the tensile force after the necessary corrections. For example, in the case where the barrier layer 21 is used as the layer 31 and the quantum well layer 20 is used as the reference layer 32, the stretch tension can be applied. In other words, if the layer 31 has a first lattice constant a _{1 in} a state where it is not subjected to a tensile force, which is smaller than the second lattice constant a _{2 of} the reference layer 32, a growth occurs when the layer 32 is grown on the reference layer 32. Stretched layer 31 of tension. In the state of the tensile tension, the layer 31 has a parallel lattice constant a _p which is greater than the vertical lattice constant a _s .

Figure 3 shows the intensity signal for the planning of the switching pulse of the light-emitting diode wafer described herein. This intensity signal shows that the intensity signal I of the electromagnetic radiation of the switching pulse emitted by the LED chip during operation is normalized as a function of time t with respect to the maximum intensity signal I _m . At time t=0, the light-emitting diode wafer is activated. After starting, the intensity signal I rises as a function of time, then is fixed at the maximum value I _m and then falls again. The rise time t _r here refers to the duration required for the intensity signal I to rise from 10% of the maximum intensity signal I _m to 90% of the maximum intensity signal Im. In addition, the fall time t _f refers to: decrease the intensity signal I from 90% of the maximum intensity signal I _m to the time duration required for 10% of the maximum intensity signal I _m.

Figure 4 shows the switching times for different embodiments of the LED wafers described herein. Here, the rise time t _r and the fall time t _f when the different measurements M1, M2, M3, and M4 are different are displayed. Each of the light-emitting diode wafers to which the measurement belongs includes 11 barrier layers 21, respectively.

The quantum well layer 20 of the first measurement M1 is subjected to a tensile tension. In particular, in comparison with the substrate 10, the active region 2 of the light-emitting diode wafer of the first measurement M1 has an average tensile force of -1500 ppm. The quantum well layer 20 of the second measurement M2 is not subjected to tensile forces in the range of measurement accuracy. In particular, the active region 2 of the second LED of the second measurement M2 has an average tensile force of 50 ppm when compared with the substrate 10. The quantum well layer 20 of the third measurement M3 has a small compression pull. The active region 2 of the third LED of the third measurement M3 has an average tensile force of 700 ppm when compared with the substrate 10. The quantum well layer 20 of the fourth measurement M4 has a large compression tension. The active region 2 of the fourth LED of the fourth measurement M4 has an average tensile force of 1200 ppm when compared with the substrate 10.

Further, the barrier layers 21 of the LEDs of the third measurement M3 and the fourth measurement M4 are respectively doped to the barrier layer 21 of the light-emitting diode wafer higher than the first measurement M1 and the second measurement M2. For example, the barrier layers 21 may be doped with a p-conductive dopant material, respectively.

The light-emitting diode wafer of the first measurement M1 has a rise time t _{r of} 10.7 nanoseconds. Fall time t _f of the first measurement M1 is 13.2 nanoseconds. The second LED of the second measurement M2 has a rise time t _{r of} 9.8 nanoseconds and a fall time t _{f of} 11.7 nanoseconds. The third measurement M3 light-emitting diode wafer has a rise time t _{r of} 6.9 nanoseconds and a fall time t _{f of} 4.4 nanoseconds. The fourth LED of measurement M4 has a rise time t _{r of} 6.2 nanoseconds and a fall time t _{f of} 4.4 nanoseconds.

Due to the compressive tensile force of the quantum well layer 20 of the third measurement M3 and the fourth measurement M4 of the light-emitting diode wafer, the switching time, in particular the rise time t _r and the fall time t _f , is shortened. In addition, the increase in the compression tension in the quantum well layer 20 of the fourth measurement M4 light-emitting diode wafer causes the rise time t _{r to} be further shortened compared to the quantum well layer 20 of the third measurement M3 which is subjected to a weak tensile force. .

The invention is not limited to the description made in accordance with the various embodiments. Instead, the present invention encompasses each new feature and each combination of features, and in particular, each combination of the various features in the various claims, when the associated feature or the associated combination is not The invention is also in the middle or in the examples.

2‧‧‧active area

10‧‧‧Substrate

11‧‧‧First semiconductor layer

12‧‧‧Second semiconductor layer

13‧‧‧First intervening layer

14‧‧‧Second intervening

20‧‧‧Quantum wells

20d‧‧‧The thickness of the quantum well layer

21‧‧‧ barrier

z‧‧‧Stacking direction

Claims (15)

A light-emitting diode wafer comprising: an active region (2) grown epitaxially on a first semiconductor layer (11) having at least one quantum well layer (20), wherein the active region (2) is compressed Pulling force, and the intensity signal has a rise time (t _r ) of up to 10 nanoseconds during the switching of the pulse wave and/or a fall time (t _f ) of up to 12 nanoseconds. The light-emitting diode chip of claim 1, wherein the active region (2) comprises at least two quantum well layers (20) and at least one barrier layer disposed between the at least two quantum well layers (20) ( twenty one). The light-emitting diode chip of claim 1, wherein the first semiconductor layer (11) is epitaxially grown on a substrate (10) and the average tensile force of the active region (2) relative to the substrate (10) It is at least 600 ppm in value. The light-emitting diode chip of claim 2, wherein the quantum well layers (20) are respectively subjected to pseudo-crystalline compression tension and the tensile coefficients of the quantum well layers (20) are numerically compared to the barrier layer (21) The tensile coefficient is at least 7500 ppm. The light-emitting diode wafer of claim 1, which emits electromagnetic radiation during operation, the peak wavelength of the electromagnetic radiation being at least 750 nm and at most 1000 nm. The light-emitting diode wafer of claim 1, wherein the at least one quantum well layer (20) has a thickness (20d) of at least 2 nanometers and at most 6 nanometers. The light-emitting diode chip of claim 1, wherein the at least one quantum well The layer (20) is predominantly gallium arsenide (GaAs), with at least 5% and up to 44% of the gallium atoms being replaced by indium atoms and/or aluminum atoms. The light-emitting diode chip of claim 1, wherein the at least one quantum well layer (20) is formed of In _x Ga _1-x As, wherein 0.08 x 1. The light-emitting diode chip of claim 2, wherein the barrier layer (21) is subjected to a pseudo-grain stretching force, and the substrate (10) is used as a reference, and the tensile layer (21) has a tensile coefficient of at least -10000 ppm and at most -500ppm. The light-emitting diode wafer of claim 2, wherein the barrier layer (21) is formed of Al _y Ga _1-y As _b P _1-b , wherein b 0.09. The light-emitting diode chip of claim 1, which does not have a resonator. The light-emitting diode chip of claim 1, wherein the first semiconductor layer (11) is epitaxially grown on a substrate (10) and the average tensile force of the active region (2) relative to the substrate (10) It is at least 1000 ppm in value. The light-emitting diode chip of claim 1, wherein the first semiconductor layer (11) is epitaxially grown on a substrate (10) and the average tensile force of the active region (2) relative to the substrate (10) It is at least 2000 ppm in value. The light-emitting diode chip of claim 2, wherein the quantum well layers (20) are respectively subjected to pseudo-crystalline compression tension and the tensile coefficients of the quantum well layers (20) are numerically compared to the barrier layer (21) The tensile coefficient is at least 15000 ppm. The light-emitting diode wafer of claim 1, wherein the at least one quantum well layer (20) has a thickness (20d) of at least 3 nanometers and at most 5 nanometers.