TWI607457B - Solid state device and data writing method thereof - Google Patents

Description

Solid state storage device and data writing method thereof

The present invention relates to a solid state storage device and a control method thereof, and more particularly to a solid state storage device and a data writing method when a flush command is received.

Solid State Device (SSD) uses NAND flash memory as the main storage component, while flash memory is a non-volatile memory. That is, when data is written to the flash memory, the data is saved in the flash memory even if the system power is turned off.

Please refer to FIG. 1A, which is a schematic diagram of a cell arrangement of a flash memory in a solid state storage device. The flash memory 105 is arranged by a plurality of cells into a memory array, and each cell includes a floating gate transistor. In the programming, the hot carrier is injected into the floating gate of the floating gate transistor, and the threshold voltage of the floating gate transistor can be changed according to the number of injected hot carriers ( Voltage Voltage), and in turn determines the storage state of the unit cell. Moreover, in the erasing, the hot carrier is ejected from the floating gate of the floating gate transistor. Furthermore, a row of cells can be controlled by word lines WL(n-1), WL(n), WL(n+1). That is, the action of one word line can program a column of cells corresponding to the word line.

According to different designs, flash memory can be divided into single-level cell (SLC) and multi-level cell flash memory. The multi-layer cell may further include a double-level cell, a triple-level cell, or a flash memory of more layers of cells.

Please refer to FIG. 1B, which is a schematic diagram showing the relationship between the storage state and the threshold voltage in various flash memories. In a single-layer cell flash memory, each cell can store one bit of data (1 bit/cell). Therefore, depending on the amount of hot carrier injection, the floating gate transistor in the unit cell can generate two threshold voltage distributions to represent two different storage states. For example, a cell with a low threshold voltage can be considered a cell with a storage state of "0"; a cell with a high threshold voltage can be considered a cell with a storage state of "1". Of course, the storage state “0” and the storage state “1” herein are only two storage states that are different, and may of course be represented by the first storage state and the second storage state. For example, a cell with a threshold voltage near 0V can be considered a cell with a first storage state; a cell with a threshold voltage of around 10V can be considered a cell with a second storage state.

Similarly, in a two-layer cell flash memory, each cell can store two bits of data (2 bits/cell). Therefore, according to the amount of hot carrier injection, in the unit cell The floating gate transistor produces four threshold voltage distributions that represent four distinct storage states. For example, the threshold voltage is available from low to high to sequentially represent the storage state "00", the storage state "01", the storage state "10", and the storage state "11".

In a three-layer cell flash memory, each cell can store three bits of data (3 bits/cell). Therefore, depending on the amount of hot carrier injection, the floating gate transistor in the unit cell can produce eight threshold voltage distributions to represent eight different storage states. For example, the threshold voltage is available from low to high to sequentially represent the storage state "000", the storage state "001", the storage state "010", the storage state "011", the storage state "100", the storage state "101", and the storage. State "110" and storage state "111".

It can be seen from the above description that when programming the flash memory, the amount of hot carrier injection of the unit cell can be controlled, and the threshold voltage of the unit cell can be changed and the storage state can be changed. However, in addition to the single-layer cell flash memory during programming, it is only necessary to perform a program procedure on the cell to achieve the desired threshold voltage, that is, to achieve the desired storage state. When other multi-layer cell flash memory is programmed, most of the cells are programmed to reach the desired threshold voltage, that is, to achieve the desired storage state.

Please refer to FIG. 2 , which is a schematic diagram of programming of a three-layer cell flash memory (hereinafter referred to as TLC flash memory). For example, as shown by the solid line in FIG. 2, when the cell of the TLC flash memory is to be programmed to the storage state "100", the unit cell is subjected to three programming procedures. In the first programming procedure, the threshold voltage of the cell of the TLC flash memory is first changed to a threshold voltage close to the storage state "111". Then, in the second programming process, change to near storage The threshold voltage of the state "101". Finally, in the third programming procedure, the threshold voltage of the storage state "100" is changed to program the cell to the storage state "100".

As can be seen from the above description, when programming the TLC flash memory, the corresponding programming program is determined according to the storage state to be programmed. For example, as shown by the dotted line in FIG. 2, assuming that the cell of the TLC flash memory is to be programmed to the storage state "011", the threshold voltage of the cell is first changed to the near storage state "000". The threshold voltage is then changed to a threshold voltage close to the storage state "010", and finally changed to a threshold voltage of the storage state "011" to program the cell to the storage state "011". Similarly, the three programming procedures of other storage states can be deduced by analogy, and will not be described again. Generally speaking, when programming a multi-layer flash memory, the threshold voltage of the unit cell is gradually changed through multiple programming procedures, so that the threshold voltage of the unit cell finally falls within the corresponding threshold voltage range corresponding to the storage state. .

According to the above, since the multi-layer cell flash memory is programmed in the programming action, the cell must be programmed a plurality of times to achieve the desired threshold voltage and the cell is programmed to the desired storage state. If the programming procedure of the unit cell does not reach the required number of programming, it means that the data to be stored to the unit cell has not been stored in the unit cell, so that the data to be stored to the unit cell cannot be read from the unit cell.

In general, when flash memory writes data, it is written to the flash memory in units of pages. The size of the page can be defined by the flash memory manufacturer, for example, each page can be 2K bytes, 4K bytes or 8K bytes. Taking a page of 4K bytes size as an example, the written data includes: user data, coded data and other related materials, which are 4224 bytes (that is, 4224×8 bits).

In other words, if a single-layer cell flash memory is used to store a 4K bytes page of data, it is necessary to use a (4224 × 8) number of single-layer cells for storage. Furthermore, since the data density of the two-layer cell flash memory is high, each cell can store two bits of data (2 bits/cell), so the number of (4224×8) two-layer cells can be stored. Two pages of information (2 × 4224 bytes). Similarly, in a three-layer cell flash memory, a (4224 × 8) number of three-layer cells can store three pages of data (3 × 4224 bytes).

Furthermore, each word line of the flash memory can be set to contain the above (4224 × 8) number of cells to simultaneously perform programming operations on the above (4224 × 8) number of cells. In other words, in a three-layer cell flash memory, the cell of each word line can store three pages of data, and the cell of each word line has to undergo three programming procedures to complete the word. The programming action of the unit cell of the element line. In addition, in the design structure of the partial multi-layer cell flash memory, when programming the multi-layer cell flash memory, the cell of the same word line is not continuously programmed a plurality of times to complete the word line. The programming action of the unit cell. The following describes the programming operation of the TLC flash memory.

Please refer to FIG. 3, which is a schematic diagram of a solid state storage device. The solid state storage device 300 includes a controller 301, a buffer 307 and a TLC flash memory 305. Controller 301 is coupled to buffer 307 and TLC flash memory 305. Moreover, the controller 301 utilizes an external bus bar 310 and a host 320 to transfer instructions and data.

Basically, when host 320 provides host data to be written When the TLC flash memory 305, the controller 301 first performs the ECC encoding process on the host data, and encodes the host data as the host write data in the buffer 307. Thereafter, the controller 301 performs a programming operation in a timely manner, and stores the host write data in the buffer 307 in the TLC flash memory 305. The buffer 307 is an SRAM or a DRAM, and the temporarily stored data is invisible as the power supply disappears; the external bus 310 can be a USB bus, an IEEE 1394 bus, a PCIe bus, or a SATA bus.

In addition, due to the characteristics of the multi-layer cell flash memory, its program order has certain specifications. Please refer to FIG. 4A and FIG. 4B , which are schematic diagrams showing the programming sequence of the TLC flash memory. The following description uses a 4K bytes page as an example. The host write data of one page includes: user data, coded data and other related materials, which are 4224 bytes (that is, 4224×8 bits).

Basically, the TLC flash memory 305 has a plurality of blocks, each of which has a plurality of pages, and the host write data of each three pages can be correspondingly stored to the same word line. 4A and 4B are only taken as an example of an open block in the TLC flash memory 305, and the programming order is illustrated by corresponding word lines. When this open block is full, it will be set to a closed block by the controller 301. Thereafter, the controller 301 looks for another blank block in the TLC flash memory 305 and sets it as an open block. Next, the host write data is stored in the open block in the same programming order.

As shown in FIG. 4A, the solid state storage device 300 receives 12 pages of host data, and after the ECC encoding process, sequentially generates a total of 12 pages of host write data of A to L temporarily stored in the buffer 307.

As previously mentioned, each word line in the TLC flash memory 305 can store three pages of data. For example, as shown in FIG. 4A, the host write data of pages A to C will be stored in the TLC cell of the first word line. Similarly, the host write data of the D~F page will be stored in the TLC cell of the second word line; the host write data of the G~I page will be stored in the TLC crystal of the third word line. In the cell; the host write data of the Jth to the Lth page will be stored in the TLC unit cell of the fourth character line.

Furthermore, when the TLC flash memory 305 is programmed in accordance with the specification of the specification, the programming sequence is as shown in FIG. 4B. First, the controller 301 activates the first word line to perform the first programming process (1st); then, the second character line operates to perform the second programming process (2nd); then, the action first word The third line, the third programming program (3rd); then, the third character line is operated, and the fourth programming program (4th) is performed; then, the second character line is operated, and the fifth programming program (5th) is performed. Then, the first character line is operated to perform the sixth programming procedure (6th); then, the fourth character line is operated, and the seventh programming procedure (7th) is performed; then, the third character line is operated, and the third Eight programming procedures (8th); then, the second character line is acted upon for the ninth programming procedure (9th).

As can be seen from the programming sequence shown in FIG. 4B, in the TLC flash memory 305, the programming process of three times requires the TLC cell of a particular word line to be in a programmed state. As shown in FIG. 4B, the controller 301 is edited six times. The program completes the three-time programming of the TLC cell of the first word line and causes the TLC cell of the first word line to be in a programmed state. Further, the controller 301 performs a three-time programming process of the first word line in the first programming program (1st), the third programming program (3rd), and the sixth programming program (6th), respectively, to make the first The TLC cell of the word line reaches the threshold voltage corresponding to the host write data of pages A~C, so that the host write data of the A~C page is stored in the TLC cell of the first word line.

Therefore, when the controller 301 completes the first programming process (1st), the third programming process (3rd), and the sixth programming process (6th), it can be confirmed that the TLC cell of the first word line is completed programming. State, meaning that the host write data of pages A~C has been stored in the TLC cell of the first word line. Similarly, when the controller 301 completes the second programming process (2nd), the fifth programming process (5th), and the ninth programming process (9th), it can be confirmed that the TLC cell of the second word line is completed. The programming state, that is, the host write data of the D~F page has been stored in the TLC cell of the second word line.

In addition, after the controller 301 completes the ninth programming procedure (9th), if the host 320 still does not provide other new host data, at this time, since there is no host write data in the buffer 307, it can be stored in the TLC flash memory. The TLC unit cell of the fifth word line in body 305. Therefore, limited by the programming order limitation of the TLC flash memory 305, when the controller 301 cannot program the TLC cell of the fifth word line, the controller 301 cannot perform the TLC crystal of the fourth word line. The cell and the TLC cell of the third word line perform subsequent programming procedures. In other words, in the TLC flash memory 305, the TLC cell of the third word line is only subjected to a secondary programming process, and the TLC cell of the fourth word line is only programmed once, so the third word line And the first The TLC cell of the four-character line is not yet programmed.

Therefore, after waiting for the host 320 to provide new host data and convert it to the host write data storage to the buffer 307, the controller 301 can again operate according to the programming order, and sequentially make the TLC cell of the third word line. The TLC cell with the fourth word line becomes the programmed state. In other words, the TLC cell of the third word line still needs to be programmed once to complete the programming state, and the TLC cell of the fourth word line still needs to undergo a secondary programming process to complete the programming state.

Basically, when a TLC cell of a word line is in a programmed state (after three programming procedures), its stored data can be read via the ECC decoding procedure of the controller 301. Conversely, when the TLC cell of a word line is not yet programmed (not through three programming procedures), since the TLC cell has not reached the corresponding threshold voltage, the corresponding stored data will not pass through the controller 301. The ECC decoding program is correctly read. For example, the TLC cell of the third word line is not yet programmed, and in this state, the host write data of the Gth to the Gth page corresponding to the storage will not be able to pass the ECC decoding process of the controller 301. Was read correctly.

As can be seen from the above description, the TLC cell of the third word line and the TLC cell of the fourth word line in FIG. 4B are all not yet programmed, and the controller 301 must wait until the host 320 provides other new hosts. After the data, the programming procedure can be continued according to the programming order of the TLC flash memory 305, so that the TLC cell of the third word line and the TLC cell of the fourth word line can be completed, and The data stored in it can be read correctly.

When the host 320 transmits a flush command, the controller 301 must confirm that the host write data temporarily stored in the buffer 307 has been stored in the TLC flash memory 305, that is, temporarily stored in the storage buffer 307. The unit cells written by the host are all in the programmed state. Then, the controller 301 can clear the temporary data in the buffer 307.

Taking FIG. 4B as an example, since the host does not transfer the new host data, when the host 320 transmits a flush command, in order to write the data of the host of the Gth to the Lth page in the buffer 307. Stored in the TLC cell of the third word line and the TLC cell of the fourth word line, the controller 301 first generates the redundant write data to be temporarily stored in the buffer 307, and then executes The programming action stores the write data in buffer 307 to TLC flash memory 305.

Please refer to FIG. 5A, which is a flow chart of a data writing method of a conventional solid state storage device. This flowchart is mainly for explaining the action flow when the solid state storage device 300 receives the clear command. In the normal operation, when receiving a write command from the host, the controller 301 can receive the host data and convert it to the host write data for temporary storage in the buffer 307.

When the controller 301 receives the clear command from the host 320 (step S502), in order to store the host write data temporarily stored in the buffer 307 to the TLC flash memory 305. The controller 301 generates redundant write data temporarily stored in the buffer 307 (step S504). Thereafter, the controller 301 performs a programming operation to store the written data in the buffer 307 to the open area of the TLC flash memory 305 according to the programming order. Block (step S506).

Please refer to FIG. 5B and FIG. 5C , which are schematic diagrams showing the programming state of the written data when the conventional solid state storage device receives the clear instruction. Assume in the case of FIG. 4B that host 320 generates a clear command to solid state storage device 300.

It can be seen from the flow steps of Figure 5A. In order to store the host write data temporarily stored in the buffer 307 to the TLC flash memory 305, the controller 301 generates 6 pages of redundant write data (Ra~Rf) temporarily stored in the buffer 307, such as the 5B. The figure shows.

Next, as shown in FIG. 5C, the controller 301 performs a program operation to store the write data in the buffer 307 to the open block of the TLC flash memory 305 according to the programming order.

That is, the controller 301 operates the fifth character line to perform the tenth programming procedure (10th); then, the fourth character line is operated, and the eleventh programming procedure (11th) is performed; then, the third character is operated. Line, perform the twelfth programming procedure (12th); then, operate the sixth character line, perform the thirteenth programming procedure (13th); then, operate the fifth character line, and perform the fourteenth programming procedure ( 14th); Next, the fourth character line is operated, and the fifteenth programming procedure (15th) is performed.

Obviously, as can be seen from FIG. 5C, after the fifteenth programming procedure (15th), the TLC cell of the third word line and the TLC cell of the fourth word line have become the completed programming state. In other words, when the conventional solid state storage device receives the clear command, the controller 301 first generates redundant write data to be temporarily stored in the buffer 307. Thereafter, the controller 301 performs a programming operation to write in the buffer 307. The data is stored in the TLC flash memory 305 according to the programming order, and the host write data temporarily stored in the buffer 307 can be stored in the open block of the TLC flash memory 305.

Since the conventional solid state storage device 300 receives the clear command, the controller 301 must first generate redundant write data to be temporarily stored in the buffer 307. It is assumed that the host 320 continuously sends a clear command during the transfer of the host material. Then, the controller 301 must also correspondingly generate redundant write data temporarily stored in the buffer 307, and store the redundant write data to the TLC flash memory 305. As shown in FIG. 6, since the host 320 continuously transmits a clear command during the process of transferring the host data. Therefore, the host write data (Ho) and the redundant write data (R) are interspersed in an open block of the TLC flash memory 305.

As is well known, redundant write data (R) is invalid data. When the host 320 continuously sends a clear command during the transfer of the host data, the TLC flash memory 305 will waste space to store invalid data and reduce the use efficiency of the solid state storage device 300.

The invention relates to a data writing method for a solid-state storage device, the solid-state storage device having a flash memory comprising a plurality of blocks, the data writing method comprising the steps of: receiving a clear command; One of the host write data is stored in an open block of the flash memory according to a programming order; performing a garbage collection operation, which is obtained from a closed block of the flash memory a collected write data is temporarily stored in the buffer; and the host write data in the buffer and the collected write data are stored in the programming block to the open block of the flash memory .

The present invention relates to a solid state storage device connected to a host, the solid state storage device comprising: a buffer; a controller connected to the host and the buffer, wherein the controller receives a host data and converts it into a The host write data is temporarily stored in the buffer; and a flash memory is connected to the controller; wherein, when receiving the host to issue a clear command, the controller writes the host data according to a programming sequence Storing to an open block of the flash memory; the controller performs a garbage collection operation, obtaining a collected write data from a closed block of the flash memory and temporarily storing the data in the buffer; And the controller stores, according to the programming sequence, a write data in the buffer to the open block of the flash memory, wherein the write data is the host write data or the collected write data. .

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

300, 700‧‧‧ solid storage devices

301, 701‧‧ ‧ controller

305, 705‧‧‧TLC flash memory

307, 707‧‧ ‧ buffer

310, 710‧‧‧ External busbars

320, 720‧‧‧ host

S502~S506‧‧‧Step procedure

S802~S808‧‧‧Step process

FIG. 1A is a schematic diagram showing a cell arrangement of a flash memory in a solid state storage device.

FIG. 1B is a schematic diagram showing the relationship between the storage state and the threshold voltage in various flash memories.

Figure 2 is a schematic diagram of the programming of a three-layer cell flash memory.

Figure 3 is a schematic diagram of a solid state storage device.

4A and 4B are schematic diagrams showing the programming sequence of the TLC flash memory.

FIG. 5A is a flow chart showing a method for writing data of a conventional solid state storage device.

FIG. 5B and FIG. 5C are schematic diagrams showing the programmed state of the written data when the conventional solid state storage device receives the clear command.

Figure 6 is a schematic diagram of the storage of data in the TLC flash memory after the conventional solid state storage device receives the multiple clear command.

FIG. 7 is a schematic view of the solid state storage device of the present invention.

FIG. 8A is a flow chart showing a method for writing data of the solid-state storage device of the present invention.

FIG. 8B and FIG. 8C are schematic diagrams showing the programming state of the written data when the solid-state storage device receives the clear command according to the present invention.

FIG. 9 is a schematic diagram showing the storage of data in the TLC flash memory after the solid state storage device receives the multiple clear command.

The invention provides a solid state storage device and a data writing method thereof, which can be applied to a data writing method when a solid state storage device receives a clearing instruction.

Please refer to FIG. 7 , which is a schematic diagram of a solid state storage device. The solid state storage device 700 includes a controller 701, a buffer 707 and a flash Memory 705. The controller 701 is connected to the buffer 707 and the flash memory 705. Moreover, the controller 701 utilizes an external bus 710 and the host 720 to transfer instructions and data. The controller 701 cannot continuously perform a programming process on the cell in the flash memory 705 a plurality of times. In the embodiment of the present invention, the flash memory 705 can be a multi-layer cell flash memory and has a specific programming order.

When the host 720 provides the host data to be written to the flash memory 705, the controller 701 first performs the ECC encoding process on the host data, and encodes the host data into the host write data temporarily stored in the buffer 707. Thereafter, the controller 701 performs a programming operation in a timely manner, and stores the host write data in the buffer 307 in the flash memory 305 according to the program order of the flash memory 705. The buffer 307 is an SRAM or a DRAM, and the temporarily stored data is invisible as the power supply disappears; the external bus 310 can be a USB bus, an IEEE 1394 bus, a PCIe bus, or a SATA bus.

Furthermore, the solid state storage device schematic 700 of the present invention can further perform a garbage collection. The following is a brief introduction to garbage collection.

The flash memory 705 includes a plurality of blocks, and each block includes a plurality of pages. For example, there are 64 pages in a block, and each page has a capacity of 4K bytes. Furthermore, due to the characteristics of the flash memory, the data is written in units of pages, and when erased, the data is erased in units of blocks.

Due to the characteristics of the flash memory, when a page in the block is When an update is required, the controller 701 cannot directly modify the data in the page, so the controller 701 writes the changed material in the blank page of the opened block, and stores the original The page of the data will be treated as an invalid page, and the data in it will be treated as invalid data.

After the host 720 has accessed multiple times, a closed block storing data in the flash memory 705 will have many invalid pages and invalid data, and occupy the space of the flash memory 705. In addition, the closed block will have both an invalid page and a valid page, and the valid page stores valid data.

The so-called garbage collection action means that the controller 701 collects the valid data of the valid pages in the closed block and additionally stores them in the open block. Furthermore, the valid data in the valid page in the closed block is collected as an invalid page. When the pages in the closed block all become invalid pages, that is, after the valid data in the valid page in the closed block is copied to other blocks, the controller 301 can block the closed block ( The block erase action and a blank block is generated, causing the flash memory 705 to release a writable space.

In the process of performing the garbage collection operation, the controller 701 first collects the valid data in the valid page in the closed block, and becomes the collected write data, which is temporarily stored in the buffer 707. Next, the controller 701 performs a programming operation at an appropriate timing, and stores the collected write data in the buffer 707 in the open block in the flash memory 705, and completes a garbage collection operation.

As can be seen from the above description, the controller 701 performs garbage collection operations. At the time, the collected data temporarily stored in the buffer 707 is valid data.

The solid-state storage device and the data writing method thereof disclosed in the present invention are applied to a data writing method of a garbage collection operation when the solid-state storage device receives a clearing instruction.

Please refer to FIG. 8A, which is a flow chart of a method for writing data of the solid state storage device of the present invention. This flowchart is mainly for explaining the action flow when the solid state storage device 700 receives the clear command. In the case of normal operation, upon receiving a write command from the host, the controller 701 can receive the host data and convert it to the host write data for temporary storage in the buffer 707.

When the controller 701 receives the clear command from the host 720 (step S802), in order to store the host write data temporarily stored in the buffer 707 to the flash memory 705. The controller 701 performs a programming operation to store the host write data temporarily stored in the buffer 707 in the programmed order to the open block of the flash memory 705 (step S804). The host write data temporarily stored in the buffer 707 is stored in the cell of the corresponding word line in the open block. Notably, after step S804 is performed, there is also a cell of a partial word line that is not yet in a programmed state. Next, the controller 701 performs a garbage collection operation, and the collected write data is acquired from the closed block of the flash memory 705, and temporarily stored in the buffer 707 (step S806). Thereafter, the controller 701 performs a programming operation to store the write data in the buffer 707 in the programmed order to the open block of the flash memory 705 (step S808).

As can be seen from the above description, when the step S808 is performed, the written data stored in the buffer 707 to the flash memory 705 can be written or searched for the host. Set the write data. The data written by the host and the collected data are all valid data.

Please refer to FIG. 8B and FIG. 8C , which are schematic diagrams showing the programming state of the written data when the solid state storage device receives the clear command according to the present invention. The flash memory 705 in the figure is a TLC flash memory as an example to continue the case of FIG. 4A. Assume that in the case of FIG. 4A, host 720 generates a clear command to solid state storage device 700.

The flow steps according to Fig. 8A of the present invention are known. In order to store the host write data temporarily stored in the buffer 707 to the flash memory 705, the controller 701 performs a programming operation to store the host write data temporarily stored in the buffer 707 to the flash memory 705 according to the programming order. Open block. At this time, the controller 701 first stores the host write data temporarily stored in the buffer 707 in the TLC unit cell of the corresponding word line in the open block. After the controller 701 completes the programming action, the TLC cell of the third word line and the TLC cell of the fourth word line are in a programmed state. Next, the controller 701 performs a garbage collection operation, and the collected write data is obtained from the closed block of the flash memory 705, and temporarily stored in the buffer 707. Therefore, after the garbage collection operation is completed, as shown in FIG. 8B. For example, the controller 701 obtains at least 6 pages of collected data (Ga~Gf) and temporarily stores it in the buffer 707. Wherein, the collected data of the Ga~Gc page is stored in the TLC unit cell of the fifth character line; the collected data of the Gd~Gf page is stored in the TLC of the sixth character line. In the unit cell.

Then, as shown in FIG. 8C, the controller 701 performs a programming operation. The write data in the buffer 707 is stored in the programmed order to the open block of the flash memory 705.

That is, the controller 701 operates the TLC unit cell of the fifth character line to perform the tenth programming procedure (10th); then, the TLC unit cell of the fourth character line is operated, and the eleventh programming procedure (11th) is performed. Then, the TLC unit cell of the third word line is operated to perform the twelfth programming procedure (12th); then, the TLC unit cell of the sixth character line is operated, and the thirteenth programming procedure (13th) is performed; The TLC unit cell of the fifth character line is operated to perform the fourteenth programming procedure (14th); then, the TLC unit cell of the fourth character line is operated to perform the fifteenth programming procedure (15th).

Obviously, as shown in FIG. 8C, after the fifteenth programming procedure (15th) is completed, the TLC cell of the third word line and the TLC cell of the fourth word line are already in a programmed state, and are stored to The written data of the open block of the flash memory 705 is valid data.

As can be seen from the above description, when the solid state storage device 700 of the present invention receives the clear command, the controller 701 stores the host write data temporarily stored in the buffer 707 according to the programming order to the open block of the flash memory 705, and controls The 701 may perform the garbage collection operation to obtain the collected write data, and further store it together with the host write data temporarily stored in the buffer 707 according to the programming order to the open block of the flash memory 705, and use The cells of the corresponding word line written by the host in the storage buffer 707 are all in a programmed state. Since the collected data acquired by the controller 701 is all valid data, it can be ensured that the written data stored in the open block of the flash memory 705 is valid data.

Furthermore, it is assumed that the host 720 continuously sends a clear command during the transfer of the host material. According to an embodiment of the present invention, the controller 701 may perform a plurality of garbage collection actions to obtain the collected write data and program it along with the host write data to the flash memory 705. Therefore, as shown in FIG. 9, the host write data (Ho) and the collected write data (Gx) are interspersed in the open block of the flash memory 705, and the host writes the data (Ho) and collects the data. The written data (Gx) is valid data.

In the embodiment of the present invention, when the solid state storage device 700 receives the clear command, the controller 701 may perform a garbage collection action according to a preset amount of data to obtain the collected write data. In other words, the controller 701 performs a garbage collection operation until the collected data amount of the written data reaches the preset data amount and is temporarily stored in the buffer 707.

Basically, the preset amount of data is an amount of additional data that can be stored by the host temporarily stored in the buffer 707 to be completely stored in the flash memory 705. In other words, the preset amount of data is the amount of additional data that can be used to store the data written by the host in buffer 707 as needed to complete the programmed state.

Taking the TLC flash memory as an example, the controller 701 needs to provide at least 6 pages of additional data amount to reliably store the host write data in the buffer 707 to the flash memory 705. For example, in the example of FIG. 8B, the preset data amount is 6 pages of data amount, and the controller 701 obtains the 6-page collected data (Ga~Gf) and temporarily stores it in the buffer 707, and can be temporarily stored together with the temporary storage. The host write data in the buffer 707 is also programmed into the flash memory 705 to actually store the host write data to the flash memory. The TLC unit cell of the third word line and the fourth word line in the body 705 is recalled.

In addition, in order to increase the stability of the data stored in the word line cell, if the cell of the next word line of a particular word line is in a programmed state, it can increase the data stability of the cell of the particular word line. Sex. For example, as shown in FIG. 8C, the TLC cell for storing the fourth word line of the host write data (J~L) has completed the programming state. However, in order to make the host write data (J~L) stored in the TLC cell of the fourth word line more stable, the controller 701 may further change the TLC cell of the fifth word line to complete the programming state. This means that the word line of the unit cell with the programmed state is additionally added. In the example of FIG. 8B, in order to additionally add a word line having a cell in which the program state is completed, it is intended that the controller 701 needs to provide at least 9 pages of data even if the TLC cell of the fifth word line becomes a programmed state. The quantity means that the preset amount of data is 9 pages of data, so that the TLC unit cell of the fifth character line can be completed to complete the programming state, so as to improve the data stability of the TLC unit cell of the fourth character line.

In the embodiment of the present invention, the amount of preset data and the number of additional character lines having a unit cell having a completed programming state are not limited thereto, and those skilled in the art can determine the required degree of data stability according to the required degree of data stability. The number of word lines having the unit cell in the programmed state is additionally increased, and the corresponding preset amount of data is determined accordingly.

Furthermore, in accordance with an embodiment of the present invention, after the controller 701 receives the clear command and performs the garbage collection operation, the host write data temporarily stored in the buffer 707 and the collected write data are successively programmed according to the programming order. Write to the open block of the flash memory. Generally, when the controller 701 receives the clear command, And storing the host write data temporarily stored in the buffer 707 according to the programming order to the open block of the flash memory 705, if the remaining space of the open block is larger than the collected data amount of the written data, In the manner shown in FIG. 8A, the write data temporarily stored in the buffer 707 is written to the open block of the flash memory 705. After confirming that the host write data has been written into the flash memory 705, that is, after storing the unit cells written by the host to complete the programming state, the data in the buffer 707 can be cleared, and the host 720 clear command is returned. The execution is complete.

Moreover, when the controller 701 receives the clear command and stores the host write data temporarily stored in the buffer 707 according to the programming order to the open block of the flash memory 705, if the open block is already full. At the same time, if the remaining space of the open block is smaller than the collected data amount of the data to be written, the controller 701 only needs to fill the open block and perform a block close action. After confirming that the open block has become the closed block, the data in the buffer 707 can be cleared, and the host 720 clear command has been executed.

In addition, in the embodiment of the present invention, the data of the clear buffer 707 can be determined according to the preset data amount and the remaining space of the open block. The reply host 720 clears the timing at which the instruction has been executed.

In an embodiment of the present invention, when the solid state storage device 700 receives the clear command and stores the temporarily stored host data in the buffer 707 in the programmed order to the open block of the flash memory 705, the controller 701 The garbage collection action can be performed in stages to obtain a part of the collected data, and then according to the programming The order stores the write data to the open block of the flash memory 705. Thereafter, the controller 701 performs the garbage collection operation again to obtain the collected data of the next part, and then stores the written data to the open block of the flash memory 705 again according to the programming order. Thus, until it is confirmed that the host write data has been written into the flash memory 705, the data in the buffer 707 can be cleared, and the host 720 clear command has been executed. In other words, in this embodiment, the controller 701 does not obtain the required collected data by the garbage collection action at one time, but performs the garbage collection operation in stages and stores the written data to the flash memory according to the programming order. Body 705. Similarly, in this embodiment, the data of the clear buffer 707 and the timing at which the reply host 720 clear instruction has been executed may also be determined according to the preset data amount and the remaining space of the open block.

According to the above description, since the collected write data (Gx) is valid data, by using the data writing method proposed by the present invention, when receiving the clear command, the controller 705 obtains the collected write through the garbage collecting action. The input data, in place of the conventional redundant write data, is programmed into the flash memory 705 along with the host write data, which will enable the space of the flash memory 705 to be effectively used to store valid data and improve The efficiency of use of the solid state storage device 700.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

S802~S808‧‧‧Step process

Claims (12)

A method for writing data of a solid-state storage device, the solid-state storage device having a flash memory comprising a plurality of blocks, the data writing method comprising the steps of: when receiving a clear command, the solid-state storage device performs the following steps Writing a host write data in a buffer to an open block of the flash memory according to a programming sequence; performing a garbage collection operation to obtain a collection from a closed block of the flash memory Write the data and temporarily store it in the buffer; the host write data in the buffer and the collected write data are stored in the programming block to the open block of the flash memory; and clear The data temporarily stored in this buffer. The data writing method of claim 1, wherein upon receiving a write command, a host data of a host is received and converted into a host write data temporarily stored in the buffer. For example, the data writing method described in claim 1 is characterized in that the host write data and the collected data are valid data. The method for writing data according to claim 1, wherein the data writing method further comprises the steps of: confirming that the host write data has been stored in the flash memory; Clear the data temporarily stored in this buffer. A data writing method for a solid-state storage device, the solid-state storage device having a flash memory comprising a plurality of blocks, the data writing method comprising the steps of: receiving a clear command; writing a host in a buffer The input data is stored in an open block of the flash memory according to a programming order; a garbage collection operation is performed, and a collected write data is obtained from a closed block of the flash memory and temporarily stored in the buffer The host write data in the buffer and the collected write data are stored in the programming block to the open block of the flash memory; the host in the buffer is written into the data After the storage block is stored in the open block of the flash memory, when a remaining storage space of the open block is less than a predetermined amount of data, the host writes the data and stores the collected data. Up to the opening block of the flash memory, until the opening block is full and performing a block closing operation, stopping storing the collected written data to the flash memory; and clearing the temporary In the data buffer. The method for writing data according to claim 5, wherein when the clearing instruction is received, the garbage collecting operation is performed according to the preset amount of data, wherein the preset amount of data ensures that the host can write data. Completely according to the programming order Save to the flash memory. The data writing method of claim 5, wherein the flash memory comprises a plurality of word lines, each of the word lines corresponding to a plurality of unit cells, and storing the host write data to When the unit cells corresponding to a particular word line are subjected to a specific number of programming procedures, the cells corresponding to the particular word line become a fully programmed state, wherein upon receiving the clear command And performing the garbage collection operation according to the preset data amount, wherein the preset data amount ensures that the cells storing the host write data can be in the fully programmed state according to the programming order. A solid state storage device is connected to a host, the solid state storage device includes: a buffer; a controller connected to the host and the buffer, wherein the controller receives a host data and converts it into a host write data temporarily And stored in the buffer; and a flash memory connected to the controller; wherein, when receiving the host to issue a clear command, the controller performs the following steps: storing the host write data according to a programming order Up to an open block of the flash memory; performing a garbage collection operation, obtaining a collected write data from a closed block of the flash memory and temporarily storing the data in the buffer; according to the programming sequence Storing a write data in the buffer to the open block of the flash memory, wherein the write data is a write data of the host or the collected write data; And clearing the data temporarily stored in the buffer. The solid state storage device of claim 8, wherein when the host issues the clear command, the controller confirms that the host write data has been stored in the flash memory, and the buffer is temporarily stored in the buffer. Information in the middle. The solid state storage device of claim 8, wherein when the host issues the clear command, the controller writes the host write data in the buffer to the flash memory according to the programming order. After the opening block, when a remaining storage space of the opening block is less than a predetermined amount of data, the controller stores the written data to the opening block of the flash memory until the opening is started. After the block is full and a block closing operation is performed, the stored data stored in the buffer is stopped and the data temporarily stored in the buffer is cleared. The solid state storage device of claim 10, wherein when the clearing instruction is received, the garbage collection operation is performed according to the preset amount of data, wherein the preset amount of data ensures that the host writes data according to This programming sequence is completely stored to the flash memory. The solid state storage device of claim 10, wherein the flash memory comprises a plurality of word lines, each of the word lines corresponding to a plurality of unit cells, and storing the host write data to a The unit cells corresponding to a particular word line After performing a specific number of programming procedures, the cells corresponding to the specific word line become a fully programmed state, and when the clear command is received, the garbage collection is performed according to the preset data amount. The action, wherein the predetermined amount of data ensures that the cells storing the host write data can be in the fully programmed state according to the programming order.