TWI606557B - Semiconductor package component and semiconductor component package method - Google Patents

Description

Semiconductor package component and semiconductor component package method

The present invention relates to a semiconductor package technology, and more particularly to a temporary carrier substrate for a semiconductor package, and a semiconductor package component obtained by using the temporary carrier substrate package.

With the evolution of semiconductor technology, semiconductor products have developed different package configurations. In order to meet the trend of thin and light electronic products, semiconductor package has also developed a chip scale package (CSP). Such a wafer size package is characterized in that only its package size is only equal or slightly larger than the wafer, and therefore, the size and volume of the package component can be effectively reduced.

Referring to FIG. 1, the process of the foregoing wafer-sized package is substantially as shown in FIG. 1. As shown in FIG. 1(a), a first carrier 11 having a first release layer 111 is provided. Next, as shown in FIG. 1(b), the plurality of semiconductor wafers 200 are bonded to the first release layer 111 by the flip-chip method, and the semiconductor wafers 200 are distributed in a gap. Then, as shown in FIGS. 1(c) and (d), a molding compound such as an epoxy resin is formed in a molding manner to fill the semi-conductive material. The gap between the body wafers 200 covers the encapsulant layer 12 of the semiconductor wafers 200, and a portion of the encapsulant layer 12 is removed to expose the inactive surfaces 202 of the semiconductor wafers 200. Next, as shown in FIGS. 1(e) and (f), a second carrier 13 having a second release layer 131 on one surface, and a second release layer 131 and the non-semiconductor wafer 200 are further disposed. The active surface 202 and the surface of the encapsulant layer 12 are connected, and then the first carrier 11 is removed to expose the active surface 201 of the semiconductor wafer 200. Thereafter, as shown in FIG. 1(g), the active surface is further activated. The surface of the surface 201 and the encapsulant layer 12 forms an electrical connection line 14 for external electrical connection. Finally, as shown in FIG. 1(h), the electrical connection line 14 is connected to a third carrier board 15, and The second carrier board 13 is removed, and the encapsulating layer 12 is cut away from the surface of the third carrier board 15 (as indicated by an arrow in the figure), thereby obtaining a single package and the package size and the semiconductor. A semiconductor package component of comparable wafer size.

The foregoing process, as shown in FIG. 1(e), is because the bonding interface of the second release layer 131 of the second carrier 13 and the encapsulant layer 12 is closely adhered, but the entire component packaging process needs to be performed. a plurality of high-temperature processes, for example, when the first carrier 11 is removed, the first release layer 111 is usually removed by heat (>130 ° C) to remove the first carrier 11; or A high-temperature process such as high-temperature (about >300 ° C) sputtering, dielectric layer baking of a wiring build-up structure, or reflow of conductive bumps used in forming the electrical connection line 14. And these high-temperature processes cause the volatile substances contained in the polymer material for encapsulation or the absorbed moisture to volatilize from the second carrier plate 13 The bonding interface of the second release layer 131 and the encapsulant layer 12 is discharged, or is extruded from the side of the electrical connection line 14 because the volatile gas cannot be discharged, thereby causing the second carrier plate 13 and the encapsulant layer. 12 peeling, making the package transition structure uneven, warped, resulting in process errors (such as drilling error or line alignment error, unevenness, etc.) when the electrical connection line 14 is subsequently formed, or causing the electrical connection line 14 to break. .

Accordingly, it is an object of the present invention to provide a carrier for a semiconductor package.

Therefore, the carrier for semiconductor package of the present invention comprises a carrier substrate and a patterned connection layer formed on one surface of the carrier substrate.

Further, another object of the present invention is to provide a semiconductor package component.

The semiconductor package component comprises a carrier for a semiconductor package, at least one semiconductor wafer, and an encapsulant layer as described above.

The at least one semiconductor wafer has an active surface, an inactive surface opposite to the active surface, and a side connecting the active surface and the inactive surface. The at least one semiconductor wafer is connected to the patterned connection layer of the carrier via the inactive surface. The encapsulant layer covers a side surface of the at least one semiconductor wafer and a surface on which the carrier substrate is exposed, and exposes the active surface of the at least one semiconductor wafer.

Furthermore, it is still another object of the present invention to provide a semiconductor component package Loading method.

The packaging method includes a first bonding step, a packaging step, a second bonding step, and a first carrier removal step.

The first bonding step is to prepare at least one semiconductor wafer having an active surface and an inactive surface opposite to the active surface, and connecting the active surface of the at least one semiconductor wafer to a first carrier.

The encapsulating step is to form an encapsulant layer covering the exposed surface of the at least one semiconductor wafer and the first carrier.

The second bonding step is to provide a second carrier, the second carrier has a second carrier substrate, and a patterned connection layer formed on one of the surfaces of the second carrier substrate, the second carrier The board is connected to the surface of the encapsulant layer away from the first carrier by the patterned connection layer.

The first carrier removing step is to remove the first carrier to expose the active surface of the at least one semiconductor wafer.

The effect of the present invention is that the connecting layer of the carrier is formed into a patterned connecting layer having a gap by patterning the connecting layer, and therefore, when the carrier substrate having the patterned connecting layer is used as a semiconductor chip package When the substrate is carried, the volatile gas generated by the high-temperature process of the packaging material can be leaked through the gap, and the influence of the volatile gas on the subsequent process can be avoided.

11‧‧‧First carrier board

111‧‧‧First release layer

12‧‧‧Package layer

13‧‧‧Second carrier board

131‧‧‧Second release layer

14‧‧‧Electrical connection lines

15‧‧‧ Third carrier board

200‧‧‧Semiconductor wafer

201‧‧‧Active surface

202‧‧‧Inactive surface

41‧‧‧Second carrier substrate

42‧‧‧patterned connection layer

5‧‧‧Electrical connection lines

51‧‧‧Electrical connection structure

52‧‧‧Conducting components

421‧‧‧Connecting block

422‧‧‧ channel

6‧‧‧ third carrier

61‧‧‧ Third carrier substrate

62‧‧‧Combination layer

203‧‧‧ side

300‧‧‧Semiconductor package wafer

2‧‧‧ first carrier

21‧‧‧First carrier substrate

22‧‧‧Adhesive layer

3‧‧‧Package layer

4‧‧‧Second carrier

91‧‧‧First joining step

92‧‧‧Packaging steps

93‧‧‧Second joint step

94‧‧‧First carrier removal step

95‧‧‧Electrical connection line formation steps

96‧‧‧Cutting steps

Other features and effects of the present invention will be apparent from the following description of the drawings, wherein: FIG. 1 is a schematic flow diagram of a conventional semiconductor wafer size package; FIG. 2 is a semiconductor package obtained by the first embodiment package. 3 is a schematic flow chart of the first embodiment; FIG. 4 is a schematic flow chart of the first embodiment; FIG. 5 is a schematic structural view of the semiconductor package component obtained by the second embodiment; 6 is a text flow chart of the second embodiment; and FIG. 7 is a schematic flow chart of the second embodiment.

Before the present invention is described in detail, it should be noted that in the following description, similar elements are denoted by the same reference numerals.

Referring to FIG. 2, a first embodiment of the semiconductor device packaging method of the present invention is for fabricating a semiconductor package component as shown in FIG.

The semiconductor package component has a second carrier 4, a plurality of semiconductor wafers 200 formed on the surface of the second carrier 4 and spaced apart from each other, and an encapsulant layer 3 filled in the gaps between the semiconductor wafers 200.

In detail, the second carrier 4 includes a carrier substrate 41 and a patterned connection layer 42 formed on one surface of the carrier substrate 41. The patterned connection layer 42 has a plurality of connection blocks 421, and Channels 422 defining the connection blocks 421, and The surface of the carrier substrate 41 is exposed to the outside through the channel. In the present embodiment, the connecting blocks 421 are distributed on the surface of the carrier substrate 41 by the gaps of the channels 422 and arranged in an array.

The semiconductor wafers 200 respectively correspond to the positions of the connecting blocks 421, wherein each of the semiconductor wafers 200 has an active surface 201, an inactive surface 202 opposite to the active surface 201, and a connecting active surface 201. And the side surface 203 of the inactive surface 202, and the semiconductor wafers 200 are respectively connected to the connecting blocks 421 by their inactive surfaces 202.

The encapsulant layer 3 is filled over the gap between the semiconductor wafers 200 to cover the side surfaces 203 of the semiconductor wafers 200, and the active surface 201 of the semiconductor wafers 200 is exposed to the encapsulant layer 3.

Referring to FIG. 3, the first embodiment of the semiconductor device packaging method includes a first bonding step 91, a packaging step 92, a second bonding step 93, and a first carrier removing step 94.

Referring to FIG. 3 and FIGS. 4(a) and 4(b), the first bonding step 91 connects at least one semiconductor wafer 200 to a first carrier 2.

The semiconductor wafer 200 can have one or more, and each of the semiconductor wafers 200 has an active surface 201, an inactive surface 202 opposite to the active surface 201, and a side connecting the active surface 201 and the inactive surface 202. 203. The semiconductor wafer 200 can be an active component such as a transistor, or a passive component such as a resistor, an inductor, or a capacitor. And when there are a plurality of semiconductor wafers 200, the functions of the semiconductor wafers 200 may be the same or different. In the present embodiment, a plurality of semiconductor wafers 200 having the same function will be described as an example.

The first carrier 2 has a first carrier substrate 21 and an adhesive layer 22 formed on one surface of the first carrier substrate 21. The first carrier substrate 21 may be selected from a material having a supporting load such as glass or a polymer, and the adhesive layer 22 may be selected from a pyrolytic adhesive or a photo-debonding adhesive to lose heat. Sex, easy to remove the glue.

In detail, the first bonding step 91 is to respectively bond the semiconductor wafers 200 with the active surface 201 and the adhesive layer 22 of the first carrier 2, wherein the semiconductor wafers 200 form a gap with each other. The semiconductor wafers 200 are spaced apart from each other and are preferably arranged in an array arrangement on the first carrier 2 .

Then, the encapsulating step 92 is performed. Referring to FIG. 3 and FIGS. 4(c) and 4(d), an encapsulant covering the semiconductor wafers 200 is formed on the exposed surfaces of the semiconductor wafers 200 and the first carrier 2. Layer 3.

In detail, the encapsulating step 92 can use a molding or a bonding method to transfer a polymer material (such as an epoxy resin) for encapsulation to a polymer material or a gel material by means of molding or filming. Filling the gap between the semiconductor wafers 200 to form an encapsulant layer 3 covering the semiconductor wafers 200, and then grinding and removing the encapsulant layer from the surface of the encapsulant layer 3 away from the first carrier 2 3 up to the semiconductor wafers The inactive surface 202 of 200 is exposed.

It should be noted that the foregoing polishing of the encapsulant layer 3 can thin the overall thickness of the encapsulant layer 3, and reduce the volume of the subsequently produced package components. However, the actual package requirements can be used without grinding. The inactive surface 202 of the semiconductor wafer 200 is not exposed.

Then, the second joining step 93 is performed with reference to FIGS. 3 and 4(e) and (f). A second carrier 4 is provided, and the second carrier 4 is connected to the surface of the encapsulant 3 away from the first carrier 2 .

The second carrier 4 has a second carrier substrate 41 and a patterned connection layer 42 formed on one surface of the second carrier substrate 41. The patterned connection layer 42 has a plurality of connection blocks 421 and a channel 422 defining the connection blocks 421. The connecting blocks 421 may be selected from the same photo-debonding material or thermal debonding material as the adhesive layer 22, and may be formed by using lithography, laser ablation, printing, inkjet, etc., and the connecting blocks 421 The position will correspond to the arrangement of the semiconductor wafers 200.

In detail, the second bonding step 93 is to connect the second carrier 4 to the inactive surface 202 exposed by the semiconductor wafers 200 by the connecting blocks 421. Since the connection surface of the second carrier 4 and the semiconductor wafers 200 and the encapsulant layer 3 is non-hermetic by the channel 422, the gas generated by the encapsulant layer 3 during the subsequent process can be By venting the channel 422 of the patterned connection layer 42 Maintain the stability of the overall structure. Preferably, the end of the channel 422 communicates with the outside to form a passage (not shown), which allows the vented gas to further escape to the outside.

It should be noted that, when the encapsulation step 92 does not perform the polishing of the encapsulant layer 3, since the inactive surface 202 of the semiconductor wafer 200 is not exposed, when the second bonding step 93 is performed, the first The second carrier 4 is directly attached to the encapsulant layer 3.

Then, the first carrier removing step 94 is performed to remove the first carrier 2 to expose the active surface 201 of the semiconductor wafers 200.

In detail, the first carrier removing step 94 can be differently removed according to the material of the adhesive layer 22 of the first carrier 2, for example, when the adhesive layer 22 is made of a thermal debonding material. The adhesive layer 22 can be detached from the semiconductor wafers 200 by heating the adhesive layer 22 and leaving the adhesive layer 22 viscous. Alternatively, when the adhesive layer 22 is made of a photo-debonding material, the adhesive layer 22 can be detached from the semiconductor wafers 200 by irradiating light of a predetermined wavelength, thereby obtaining a structure as shown in FIG. Semiconductor package components.

In the foregoing packaging process of the semiconductor device, since the second carrier 4 having the patterned patterned connection layer 42 is used, when the step 94 is performed, the package layer is removed when the first carrier 2 is removed. 3 Whether the gas generated by heat during heating or illumination can be vented through the passage 422 of the second carrier 4, it can be avoided (as shown in FIG. 1) because the second carrier 13 is The encapsulant layer 12 and the semiconductor wafer 200 The sealing surface is sealed, so that the gas generated by the encapsulating layer 12 during the process is discharged from the bonding interface, which causes the second carrier 13 to be peeled off from the encapsulating layer 12.

It should be noted that the second carrier 4 having the patterned connection layer 42 can be used as a temporary carrier substrate for a package process which is generally packaged with a package material and subjected to other high-temperature processes and substrate conversion, for example, Fan-Out Wafer Level Package (FOWLP) or 3D IC Through Silicon Via Package for temporarily carrying the carrier substrate of the wafer, which can effectively avoid high temperature process The disadvantages caused by the gases produced by the process.

Referring to FIG. 5, a second embodiment of the semiconductor device packaging method of the present invention is for fabricating a semiconductor package component as shown in FIG.

The semiconductor package component includes a third carrier 6 and a semiconductor package wafer 300 connected to the third carrier 6.

The third carrier 6 has a third carrier substrate 61 and a bonding layer 62 formed on the surface of the third carrier substrate 61.

The semiconductor package wafer 300 has an encapsulant layer 3, a plurality of semiconductor wafers 200 embedded in the encapsulant layer 3, and an electrical connection line 5. The active surface 201 and the inactive surface 202 of the semiconductor wafer 200 are exposed to the encapsulant layer 3, and the electrical connection line 5 is formed on the active surface 201 of the semiconductor wafer 200 and the encapsulant a layer 3 surface having a distribution formed on the semiconductor wafers 200 The active surface 201 and the electrical connection structure 51 on the surface of the encapsulant layer 3 and the conductive element 52 for electrically connecting the semiconductor wafers 200 to the outside, and the semiconductor package wafer 300 is the electrical connection line 5 and the third The bonding layer 62 of the carrier 6 is bonded. Since the descriptions of the semiconductor wafers 200 and the encapsulant layer 3 are the same as those of the semiconductor package of the first embodiment, they will not be described again.

Referring to FIG. 6, the second embodiment of the semiconductor device packaging method includes a first bonding step 91, a packaging step 92, a second bonding step 93, a first carrier removing step 94, and an electrical connection line formation. Step 95 and a cutting step 96. The steps 91 to 94 are the same as those of the first embodiment. Therefore, the description will not be repeated. The present embodiment only describes the electrical connection line forming step 95 and the cutting step 96.

With reference to FIG. 6 and FIG. 7, the electrical connection line forming step 95 is performed in the first carrier removing step 94, after the first carrier 2 is removed, and the active surface 201 of the semiconductor wafers 200 is exposed. Further, the active surface 201 of the semiconductor wafer 200 is formed to form an electrical connection line 5 electrically connectable to the outside.

In detail, the electrical connection line 5 has an electrical connection structure 51 distributed on the active surface 201 of the semiconductor wafer 200 and the surface of the encapsulant layer 3, and a conductive connection for electrically connecting the semiconductor wafers 200 to the outside. Element 52. The electrical connection line 5 is formed by a series of semiconductor lithography, plating, electroplating, and reflow soldering processes. Since the distribution pattern and related processes of the electrical connection line 5 are well known to those skilled in the art, therefore, More explanations.

Since the high-temperature process is also used in the formation process of the electrical connection line 5, the channel 422 of the second carrier 4 can be reused to cause the package layer 3 to be generated during the high-temperature process of the step 95. The gas is dissipated outside, and the gas is prevented from damaging the bonding interface of the encapsulant layer 3 and the second carrier 4, or the electrical connection structure 51 is destroyed, thereby maintaining the stability of the semiconductor package component 300 and improving the overall process. Yield.

The cutting step 96 is to first connect the electrical connection line 5 to a third carrier 6. The third carrier 6 has a third carrier substrate 61 and a bonding layer 62 formed on the surface of the third carrier substrate 61. Preferably, the electrical connection line 5 is only inserted into the bonding layer 62, and the bonding layer 62 can be connected to the electrical connection line 5 having a different structural type.

In detail, the cutting step 96 is to first connect the electrical connection line 5 to the bonding layer 62 of the third carrier 6, and then remove the second carrier 4 to make the semiconductor wafer 200 inactive. The surface 202 and the encapsulant layer 3 are exposed to obtain the semiconductor package component 300 as shown in FIG. 5, and finally cut from the gap between the encapsulant layer 3 and the semiconductor wafers 200 (as indicated by the arrow in FIG. 5) ), a semiconductor package component in a single package can be obtained. Thereafter, the single-package semiconductor package component is removed from the third carrier 6 and electrically connected to other semiconductor package substrates (not shown) by the electrical connection line 5 to obtain different package components.

In summary, the present invention maps the connection layer of the second carrier 4 The connection layer of the second carrier 4 is formed into a patterned connection layer 42 having a via 422 (gap). Therefore, when the second carrier 4 having the patterned connection layer 42 is used as the semiconductor wafer 200 When the substrate is temporarily loaded in the packaging process, the volatilized gas generated by the high-temperature process of the encapsulating material (the encapsulant layer 3) can be vented through the channel 422, thereby avoiding the destruction of the package structure due to the extrusion of the volatilized gas. The problem of the subsequent process is affected, so the object of the present invention can be achieved.

However, the above is only the embodiment of the present invention, and the scope of the invention is not limited thereto, and all the simple equivalent changes and modifications according to the scope of the patent application and the patent specification of the present invention are still Within the scope of the invention patent.

200‧‧‧Semiconductor wafer

201‧‧‧Active surface

202‧‧‧Inactive surface

203‧‧‧ side

3‧‧‧Package layer

4‧‧‧Second carrier

41‧‧‧Second carrier substrate

42‧‧‧patterned connection layer

421‧‧‧Connecting block

422‧‧‧ channel

Claims (8)

A semiconductor package component comprising: a carrier substrate having a carrier substrate and a patterned connection layer formed on one surface of the carrier substrate; at least one semiconductor wafer having an active surface, an active surface The at least one semiconductor wafer is connected to the patterned connection layer of the carrier via the inactive surface and the side of the active surface and the non-active surface; and an encapsulant layer covering the at least one a side surface of the semiconductor wafer, and exposing the active surface of the at least one semiconductor wafer. The semiconductor package component of claim 1, further comprising an electrical connection line on the active surface of the at least one semiconductor wafer and electrically connected to the at least one semiconductor wafer. A semiconductor device packaging method comprising: a first bonding step of preparing at least one semiconductor wafer, the at least one semiconductor wafer having an active surface and an inactive surface opposite to the active surface, the active surface of the at least one semiconductor wafer Connected to a first carrier; a packaging step to form an encapsulant layer covering the exposed surface of the at least one semiconductor wafer and the first carrier; and a second bonding step to provide a second carrier The second carrier has a second carrier substrate, and a patterned connection layer formed on one surface of the second carrier substrate. The second carrier is separated from the package layer by the patterned connection layer. The surfaces of the first carrier are connected; and A first carrier removing step removes the first carrier to expose the active surface of the at least one semiconductor wafer. The semiconductor device package method of claim 3, wherein the patterned connection layer has at least one connection block corresponding to the at least one semiconductor wafer, and a channel defining the at least one connection block, and the second carrier The surface of the substrate is exposed to the outside through the channel. The semiconductor device package method of claim 4, wherein the encapsulating step further removes the encapsulant layer from the encapsulant layer away from the surface of the first carrier to the inactive surface of the at least one semiconductor wafer Exposed, and the second bonding step is performed by connecting at least one connecting block of the patterned connecting layer to the exposed inactive surface of the at least one semiconductor wafer. The semiconductor device package method of claim 3, further comprising: an electrical connection line forming step performed after the first carrier removing step, wherein the active surface of the at least one semiconductor package wafer forms an external interface Electrical connection line for electrical connection. The semiconductor device package method of claim 6, further comprising: a cutting step performed after the electrical connection line forming step, connecting the electrical connection line to a third carrier, and then removing the second carrier The surface of the inactive surface of the at least one semiconductor wafer and the surface of the encapsulant layer are exposed, and finally the surface of the encapsulant layer is cut to obtain a single-chip semiconductor package component. The semiconductor device package method of claim 3, wherein the first carrier has an adhesive layer connected to the at least one semiconductor wafer, and the adhesive layer and the patterned connection layer are respectively selected from the group consisting of photo-debonding materials. Or pyrolytic binder material.