TWI604535B - Method for manufacturing graphene field effect transistor - Google Patents

Description

Method for manufacturing graphene field effect transistor

The invention relates to a method for preparing a graphene field effect transistor, in particular to a method for preparing an independent dual gate graphene field effect transistor.

The carbon atoms of graphene are arranged in a honeycomb crystal lattice, which is a single-layer two-dimensional crystal, almost transparent, and has high hardness, high thermal conductivity, high electron mobility, low electrical resistance and the like. Graphene has the potential to replace ruthenium as a transistor material, so that it can achieve small size, high speed, low energy consumption, low heat production and the like.

The main methods for preparing graphene include thermal decomposition and chemical vapor deposition (CVD). The thermal decomposition method uses monocrystalline niobium carbide (SiC) as a material, which is expensive, and this method is easy to form island-like distributed graphene, and it is difficult to prepare graphene having a large area and a single thickness.

At present, chemical vapor deposition is more commonly used in the industry. The chemical vapor deposition method places a metal substrate (such as nickel) in an atmosphere of a precursor (such as methane, ethylene, etc.), deposits carbon atoms on the surface of the substrate to form graphene by high temperature annealing, and then removes the metal substrate by etching to obtain graphite. Olefin. Chemical vapor deposition can obtain a large area of graphene and can effectively control the growth of graphene; however, due to the interaction with the metal substrate, the graphene partial properties are lost, and Poor continuity, easy to generate wrinkles or cracks. Next, the graphene must be transferred to a suitable substrate to prepare a transistor.

At present, a known process is to form a ruthenium dioxide layer on a ruthenium substrate, form a catalytic metal layer on the ruthenium dioxide layer, form a graphene layer on the catalyzed metal layer, and then transfer. In order to protect the graphene layer in the transfer step, a polymer is coated thereon. The ruthenium substrate and the ruthenium dioxide layer are stripped, and the catalytic metal layer is removed by chemical etching. Then, the protective polymer is removed by a solvent, and then the graphene is subjected to a desired substrate to complete the transfer step. A subsequent transistor preparation procedure is then performed.

In the conventional process, the transfer step may damage the graphene structure, especially for graphene formed on a metal with high chemical stability. Due to the interaction between the two, the transfer step may cause the excellent properties of graphene to be lost. Thereby affecting the performance of the subsequent transistor.

For the structure of the conventional graphene field effect transistor, please refer to the figures 1(A) to 1(C). Figure 1(A) shows the back-gate field effect transistor. Figure 1(B) is a top-gate field effect transistor with a graphene channel, exfoliated graphene, or grown on a metal and transferred to a surface-covered dioxide Graphene on the wafer. Figure 1(C) shows the top gate field effect transistor with an epitaxial-graphene channel.

Accordingly, there is still a need for a process for graphene transistors.

The invention provides a method for manufacturing an independent double-gate graphene field effect transistor, which comprises: forming a germanium telluride (SiGe) epitaxial layer on a germanium substrate; implanting carbon ions into the substrate; thermal annealing Directly synthesizing a cerium carbide (SiC) precipitate, wherein the lanthanum carbide is aligned with the crystal lattice of the bismuth telluride; the graphene is selectively grown on the surface of the tantalum carbide; Forming a dielectric layer on the graphene and patterning; forming a source and a drain on the graphene, and forming a gate on the dielectric layer.

In an embodiment, the germanium substrate can be, for example, a germanium wafer.

In one embodiment, after the siGe epitaxial layer is formed, the substrate is subjected to a photoresist coating and patterning step.

In one embodiment, the carbon ion implantation is performed at a temperature of 400-600 °C.

In one embodiment, the carbon ion implantation is performed on a surface region of the SiGe epitaxial layer to obtain a carbon peak (C peak), and the concentration is similar to the germanium content (eg, 80%-120% of the germanium content, for example, 90-110%). ) or the same. The energy and dose of ion implantation can be selected according to this condition.

In one embodiment, the niobium carbide precipitate is β-SiC.

In one embodiment, the step of selectively growing graphene is performed by using methane as a graphene precursor and under an atmosphere of argon or hydrogen. In one embodiment, the graphene growth temperature is 600-1500 °C.

In one embodiment, the selectively grown graphene is a single layer. In another embodiment, the selectively grown graphene is a multilayer.

In one embodiment, the graphene formed in this step is an isolated graphene ribbon having a larger energy gap. In an embodiment, the energy gap can exceed 300 meV.

In one embodiment, the patterned pattern width of the dielectric layer is less than 10 nm.

In an embodiment, a source and a drain are formed on the graphene, and a front-gate is formed on the dielectric layer.

In an embodiment, the back gate and the front gate of the dual gate are isolated from the channel material by a gate dielectric layer.

1, 2, 3, 4 ‧ ‧ graphene field effect transistor

11, 21‧‧‧ back gate

12, 22‧‧‧矽 crystal layer

13, 23, ‧ ‧ cerium oxide layer

14, 24, 34, 44‧‧‧ graphene layer

15, 25, 35, 46‧‧‧ source

16, 26, 36, 47‧‧ ‧ bungee

27, 37, 45‧‧‧ dielectric layer

28, 38, 38‧‧‧ top gate

31‧‧‧Semi-insulating tantalum carbide layer

41‧‧‧矽 substrate

42‧‧‧矽化锗层

43‧‧‧Carbide layer

48‧‧‧Metal gate

49‧‧‧Carbon ion implantation area

The first (A) to (C) diagrams show a conventional graphene field effect transistor structure.

Figure 2 is a diagram showing an independent dual gate graphene field effect transistor structure in accordance with an embodiment of the present invention.

3(A) through 3(F) are diagrams showing the steps of preparing a double gate graphene field effect transistor structure in accordance with an embodiment of the present invention.

The method of the present invention will now be described in more detail in conjunction with the accompanying drawings in which the preferred embodiment of the invention Favorable effect. Therefore, the following description is to be understood as a broad understanding of the invention, and not as a limitation of the invention.

In the interest of clarity, not all features of the actual embodiments are described. In the following description, well-known functions and structures are not described in detail as they may obscure the present invention in unnecessary detail. It should be understood that in the development of any actual embodiment, a large number of implementation details must be made to achieve a particular goal of the developer, such as changing from one embodiment to another in accordance with the limitations of the system or related business. In addition, such development work should be considered complex and time consuming, but is only routine work for those of ordinary skill in the art.

The invention is more specifically described in the following paragraphs by way of example with reference to the drawings. Advantages and features of the present invention will be apparent from the description and appended claims. Need to explain Yes, the drawings are in a very simplified form and all use non-precise proportions, only to facilitate the purpose of facilitating the description of the embodiments of the present invention.

Referring to FIG. 2, in the embodiment, the independent double gate graphene field effect transistor structure of the present invention comprises: a germanium substrate 41 (ie, a back gate), a germanium telluride layer 42, a tantalum carbide layer 43, graphene. Layer 44, dielectric layer 45, source 46, drain 47, and metal gate 48 (ie, the front gate).

According to an embodiment of the present invention, the steps of preparing the double gate graphene field effect transistor structure are referred to the figures 3(A) to 3(F).

Referring to Figure 3(A), a substrate 41, such as a germanium wafer, is provided. Referring to FIG. 3(B), a SiGe epitaxial layer 42 is formed on the germanium substrate 41, and then the substrate is cleaned. The substrate may be subjected to a photoresist coating and patterning step as needed.

Referring to FIG. 3(C), a carbothermal ion implantation step is performed to form a carbon ion implantation region 49 on the SiGe epitaxial layer 42. In one embodiment, the carbon ion implantation region 49 has a width of 4-12 nm; in the preferred embodiment, the carbon ion implantation region 49 has a width of 6-8 nm. Carbon ion implantation can be carried out at 1-100 KeV, ion dose 1 x 10 ¹⁵ to 1 x 10 ¹⁸ ions/cm ² at a temperature of 400-600 °C. Then, the photoresist strip can be removed. A rapid thermal annealing (RTA) step is carried out under the conditions of a temperature of 400-1200 ° C and a treatment of 1-1000 seconds to form β-SiC.

The graphene layer 44 is selectively grown on the carbon ion implantation region 49 with reference to the third (D) diagram. In an embodiment, the graphene layer 44 is at 600-1500 ° C with methane (CH ₄ ) as a precursor and is formed under an argon or hydrogen atmosphere. The graphene layer 44 can be a single layer or multiple layers. The graphene layer 44 can be a separately grown graphene ribbon having a larger energy gap, for example, the energy gap can exceed 300 meV.

Referring to FIG. 3(E), a dielectric material is deposited by atomic layer deposition (ALD) and patterned to form a dielectric layer 45. The dielectric layer is a high k dielectric layer.

Referring to FIG. 3(F), a source 46, a drain 47, and a metal gate 48 (ie, a front gate) are formed. The source 46 and the drain 47 are formed on the graphene layer 44 and The electrical layer 45 is spaced apart and the metal gate 48 is formed on the dielectric layer 45, the dual gate being isolated from the channel material by a gate dielectric layer.

According to the independent double-gate graphene field effect transistor obtained by the invention, a graphene layer can be formed on a desired substrate to avoid damage caused by the transfer step. The graphene field effect transistor of the invention can maintain the excellent properties of graphene, such as high hardness, high thermal conductivity, high electron mobility and low electrical resistance, and achieves product performances of small size, high speed, low energy consumption and low heat production.

The above description of the specific embodiments is intended to be illustrative of the invention, and is not intended to limit the invention. It will be understood by those skilled in the art that various changes or modifications may be made to the present invention without departing from the scope of the appended claims.

4‧‧‧ Graphene field effect transistor

41‧‧‧矽 substrate

42‧‧‧矽化锗层

43‧‧‧Carbide layer

44‧‧‧graphene layer

45‧‧‧Dielectric layer

46‧‧‧ source

47‧‧‧汲polar

48‧‧‧Metal gate

Claims (7)

A method for fabricating an independent dual gate graphene field effect transistor, comprising: forming a germanium telluride (SiGe) epitaxial layer on a germanium substrate; implanting carbon ions into the substrate, wherein the carbon ion implant is A carbon peak (Cpeak) is obtained in a surface region of the epitaxial layer of the bismuth telluride; a thermal annealing is performed to directly synthesize a cerium carbide (SiC) precipitate, wherein the lanthanum carbide is aligned with the crystal lattice of the bismuth telluride; and the surface of the tantalum carbide is selectively grown. Graphene; forming a dielectric layer on the graphene and patterning, wherein the patterned pattern has a width of less than 10 nm; and forming a source and a drain on the graphene, and forming on the dielectric layer Gate. The method of claim 1, further comprising performing photoresist coating and patterning after the formation of the epitaxial layer of germanium oxide. The method of claim 1, wherein the carbon ion implantation is performed at a temperature of 400 to 600 °C. The method of claim 1, wherein the niobium carbide precipitate is β-SiC. The method of claim 1, wherein the step of selectively growing graphene forms a single layer or a plurality of layers of graphene. The method of claim 1, wherein the step of selectively growing graphene forms a separately grown graphene ribbon. The method of claim 6, wherein the graphene ribbon has an energy gap of more than 300 meV.