TWI604446B - Resistive random-access memory structure and method for fabricating the same - Google Patents

Description

Resistive random access memory structure and manufacturing method thereof

The present invention relates to a resistive random access memory structure, and more particularly to a resistive random access memory structure in which a sidewall of a transition metal oxide layer is not aligned with a sidewall of a bottom electrode, and a method of fabricating the same.

Non-volatile memory has the advantage that the stored data does not disappear after power-off, and is therefore a necessary memory element for many electrical products to maintain normal operation. At present, resistive random access memory (RRAM) is a kind of non-volatile memory actively developed in the industry. It has low write operation voltage, short write erase time, long memory time, and non-destructive memory. Sexual reading, multi-state memory, simple structure and small required area have great potential for application in personal computers and electronic devices in the future.

However, in the production of resistive random access memory, as the size of the device is reduced, it is necessary to maintain the uniformity of the resistive random access memory structure and to avoid damage to the bottom electrode in the process. The challenge needs to be overcome. Therefore, a new resistive random access memory structure and its improved process are needed.

The invention provides a resistive random access memory structure and a manufacturing method thereof, which can reduce the damage of the bottom electrode by subsequent processes.

An embodiment of the present invention provides a resistive random access memory structure, comprising: a first dielectric layer formed on a substrate; a plurality of bottom electrodes respectively buried in the first dielectric layer; a transition metal oxide The layer covers the bottom electrode and extends to a portion of the first dielectric layer, wherein the shortest distance between the bottom electrode and the sidewall of the transition metal oxide layer is a first distance, and the first distance is between 10 nm and 200 μm.

An embodiment of the present invention also provides a method for fabricating a resistive random access memory structure, comprising: forming a first dielectric layer on a substrate; patterning the first dielectric layer to form a plurality of openings; forming a plurality a bottom electrode is in the opening; forming a transition metal oxide layer covering the bottom electrode and extending to a portion of the first dielectric layer, wherein the shortest distance between the bottom electrode and the sidewall of the transition metal oxide layer is a first distance, and the first distance Between 10 nm and 200 μm; and forming a top electrode on the transition metal oxide layer.

In the resistive random access memory structure of the present invention, the transition metal oxide layer covers the plurality of bottom electrodes, and the sidewalls of the transition metal oxide layer are located outside the sidewalls of the bottom electrode. Thereby, the bottom electrode can be damaged by subsequent processes.

10‧‧‧Optoelectronics

12‧‧‧Metal plug

14‧‧‧metal layer

15‧‧‧Common source wire

16‧‧‧ bottom electrode contact plug

100‧‧‧Resistive random access memory structure

102‧‧‧Base

104‧‧‧First dielectric layer

104s‧‧‧ upper surface

105‧‧‧Light resistance

106‧‧‧First opening

108'‧‧‧ bottom electrode material

108‧‧‧ bottom electrode

108s‧‧‧ upper surface

110’‧‧‧Transition metal oxide materials

110‧‧‧Transition metal oxide layer

112', 206'‧‧‧ Oxygen Reactive Materials

112‧‧‧Oxygen reaction layer

113', 204', 208'‧‧‧ barrier material

113, 204, 208‧‧ ‧ barrier layer

114'‧‧‧ top electrode material

114‧‧‧ top electrode

116’‧‧‧Second dielectric material

116‧‧‧Second dielectric layer

118‧‧‧ Third dielectric layer

120‧‧‧second opening

122‧‧‧Interlayer plug

124‧‧‧Active area

202'‧‧‧4th dielectric layer material

202‧‧‧fourth dielectric layer

203‧‧‧Opening 206 discontinuous oxygen reaction layer

W‧‧‧first width

D‧‧‧First distance

1A-1H are schematic cross-sectional views showing a process for forming a resistive random access memory structure in accordance with an embodiment of the present invention.

2A-2E are diagrams showing formation of a resistive random according to another embodiment of the present invention Schematic diagram of the process profile for accessing the memory structure.

FIG. 3 is a top perspective view showing the structure of the resistive random access memory of FIG. 1H.

The disclosure of the present specification provides many different embodiments or examples to implement various features of the present invention. The disclosure of the present specification is a specific example of the various components and their arrangement in order to simplify the description of the invention. Of course, these specific examples are not intended to limit the invention. For example, if the disclosure of the present specification describes forming a first feature member on or above a second feature member, it means that the first feature member and the second feature member formed are directly The embodiment of the contact includes an embodiment in which an additional feature is formed between the first feature component and the second feature component, and the first feature component and the second feature component may not be in direct contact with each other. . Furthermore, different examples in the description of the invention may use repeated reference symbols and/or words. These repeated symbols or words are not intended to limit the relationship between the various embodiments and/or the appearance structures for the purpose of simplicity and clarity.

In addition, spatially related terms such as "lower", "lower", "lower", "above", "above", etc. are used to readily express the components or features and other components in this specification. Or the relationship of feature parts. These spatially related terms encompass different orientations of the device in use or operation, in addition to the orientation depicted in the drawings. The device may have different orientations (rotated 90 degrees or other orientations), and the spatially related terms used herein may also be interpreted the same.

Here, the terms "about" and "about" are usually expressed within 20% of a given value or range, preferably within 10%, and more preferably within 5%. The quantity given here is an approximate quantity, meaning that the meaning of "about" or "about" may be implied without specific explanation.

1A-1H is a schematic cross-sectional view showing a process of forming a resistive random access memory structure 100 in accordance with an embodiment of the present invention. Referring to FIG. 1A, a substrate 102 having a plurality of transistors 10 and an interlayer dielectric layer 103 formed thereon is provided. In some embodiments, the substrate 102 can be a germanium substrate, a germanium germanium substrate, a tantalum carbide substrate, a silicon-on insulator (SOI) substrate, a multi-layered substrate, a gradient substrate, or Hybrid orientation substrate and the like. In one embodiment, substrate 102 is a wafer. In some embodiments, the material of the interlayer dielectric layer 103 may include hafnium oxide, tantalum nitride, hafnium oxynitride, fluorosilicate glass (FSG), black diamond, low dielectric constant material. (low-k dielectrics), combinations of the above, or other suitable dielectric materials. The interlayer dielectric layer 103 can be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), thermal oxidation process, or other suitable process. In addition, a plurality of metal plugs 12, a metal layer 14, a common source lead 15 and a bottom electrode contact plug 16 are electrically connected to the transistor 10 in the interlayer dielectric layer 103, as shown in FIG. 1A. In some embodiments, a portion of the transistor 10 is a dummy transistor.

Next, please continue to refer to FIG. 1A to form a first dielectric layer 104 on the interlayer dielectric layer 103. The first dielectric layer 104 may comprise hafnium oxide, tantalum nitride, hafnium oxynitride, fluorosilicate glass (FSG), black diamond, low Low-k dielectrics, combinations of the above, or other suitable dielectric materials. The first dielectric layer 104 can be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), thermal oxidation processes, or other suitable processes.

Next, as shown in FIG. 1B, the first dielectric layer 104 is patterned, and a plurality of first openings 106 are formed in the first dielectric layer 104. The first openings 106 will form a bottom electrode 108 in a subsequent process (eg, Figure 1D)). In some embodiments, a patterned photoresist layer 105 can be formed on the first dielectric layer 104 by performing a lithography process. Next, an etching process is performed, the photoresist layer 105 is used as an etch mask, the first dielectric layer 104 is etched, and a plurality of first openings 106 are formed in the first dielectric layer 104. In some embodiments, the etch process can include a dry etch process, such as a reactive ion etching (RIE) process. In some embodiments, the first opening 106 exposes the bottom electrode contact plug 16 in the interlayer dielectric layer 103. After the first opening 106 is formed, the photoresist 105 is removed.

Next, referring to FIG. 1C, a bottom electrode material 108' is formed on the first dielectric layer 104. In this embodiment, the bottom electrode material 108' fills the first opening 106 and extends onto the first dielectric layer 104. In some embodiments, the method of forming the bottom electrode material 108' may be physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or other suitable process. In some embodiments, the material of the bottom electrode material 108' may be titanium (Ti), titanium nitride (TiN), platinum (Pt), tungsten (W), aluminum (Al), titanium aluminum nitride (TiAlN). , a combination thereof, or a material similar thereto. In some embodiments, after the bottom electrode material 108' is formed, the portion of the bottom electrode material 108' outside the first opening 106 is removed, and the bottom electrode 108 is formed in the first opening 106, as shown in Figure 1D. In some embodiments, a planarization process (eg, a chemical machine) can be performed a chemical mechanical polishing (CMP) process to remove a portion of the bottom electrode material 108' that is outside the first opening 106 (eg, a portion on the first dielectric layer 104) to form the bottom electrode 108 The first opening 106 is as shown in FIG. 1D. In some embodiments, the bottom electrode 108 is electrically coupled to the transistor 10 in the substrate by a metal plug 12, a metal layer 14, and a bottom electrode contact plug 16. In this embodiment, by the planarization process, the bottom electrode 108 buried in the first dielectric layer 104 can be formed, and the flat upper surface 108s can be effectively formed on the bottom electrode 108, and the upper surface 108s can be The upper surface 104s of the first dielectric layer 104 is substantially flush, thereby improving the uniformity of the subsequently formed transition metal oxide layer and the top electrode, and reducing variations in the electrical characteristics of the resistive random access memory structure 100. It should be noted that although three bottom electrodes 108 are formed in the first dielectric layer 104 in FIG. 1D, in other embodiments, the number of bottom electrodes 108 may be more than three, for example, four or more. .

Next, referring to FIG. 1E, a transition metal oxide material 110', a top electrode material 114', and a second dielectric material 116' are sequentially formed on the first dielectric layer 104 and the bottom electrode 108. In an embodiment, the transition metal oxide material 110' may comprise an oxide of a transition metal such as titanium dioxide (TiO ₂ ), hafnium oxide (HfO ₂ ), zirconium dioxide (ZrO ₂ ), aluminum oxide (Al _{2 )} O ₃ ), tantalum pentoxide (Ta ₂ O ₅ ), nickel oxide (NiO), zinc oxide (ZnO), combinations thereof or materials similar thereto. In some embodiments, the transition metal oxide material 110' can be formed using physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD) processes. In some embodiments, the top electrode material 114' may comprise titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), copper (Cu), tungsten (W), aluminum (Al), titanium nitride. Aluminum alloy (TiAlN), combinations thereof, or similar materials. In some embodiments, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electron beam vacuum evaporation (E-beam evaporation), or sputtering can be used to form Top electrode material 114'. In some embodiments, the second dielectric material 116' may be hafnium oxide, tantalum nitride, hafnium oxynitride, fluorosilicate glass (FSG), black diamond, low dielectric constant material (low- k dielectrics), combinations of the above, or other suitable dielectric materials. The second dielectric material 116' can be formed by chemical vapor deposition (CVD), or other suitable process. In some embodiments, an oxygen-reactive material 112' may be additionally formed between the transition metal oxide material 110' and the top electrode material 114' as needed. In some embodiments, the oxygen reactive material 112' may be titanium (Ti), hafnium (Hf), tantalum (Ta), zirconium (Zr), aluminum (Al), nickel (Ni), combinations thereof, or the like. . The oxygen reactant material 112' can be formed using physical vapor deposition (PVD), chemical vapor deposition (CVD), or other suitable process. In some embodiments, a barrier layer material 113' can be formed between the oxygen reactive material 112' and the top electrode material 114'. In some embodiments, the barrier layer material 113 ′ can serve as a diffusion barrier layer to prevent oxygen atoms in the transition metal oxide layer 110 from diffusing into the top electrode 114 via the oxygen reaction layer 112 to cause resistive random access memory. Damage to the performance of the body structure 100. In some embodiments, the barrier layer material 113' includes a metal oxynitride MNxOy, wherein M can be tantalum (Ta), titanium (Ti), tungsten (W), hafnium (Hf), nickel (Ni), aluminum ( Al), a nitrogen element (such as lanthanum, cerium), cobalt (Co) or zirconium (Zr), the proportion of N is about 5% to 30%. For example, the barrier layer material 113' may be aluminum oxide (Al ₂ O ₃ ), zirconium oxide (ZrO 2 ), hafnium oxide (HfO 2 ), tantalum pentoxide (Ta ₂ O ₅ ), or other suitable materials. The barrier layer material 113' can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or other suitable processes.

Next, referring to FIG. 1F, the transition metal oxide material 110', the oxygen reactive material 112', the barrier layer material 113', the top electrode material 114', and the second dielectric material 116' are patterned to form the transition metal oxide layer 110. The oxygen reaction layer 112, the barrier layer 113, the top electrode 114, and the second dielectric layer 116, and a portion of the first dielectric layer 104 is exposed. In this embodiment, a continuously distributed top electrode 114 may cover the plurality of bottom electrodes 108. In some embodiments, the transition metal oxide material 110', the oxygen reactive material 112', the barrier layer material are sequentially patterned using a lithography and anisotropic etching process (eg, a reactive ion etching (RIE) process). 113', top electrode material 114' and second dielectric material 116'. In some embodiments, the transition metal oxide layer 110, the oxygen reactive layer 112, the barrier layer 113, the top electrode 114, and the second dielectric layer 116 cover the plurality of bottom electrodes 108 and extend over portions of the first dielectric layer 104. .

Since in the process of performing the reactive ion etching (RIE) process described above, the plasma generated by the process reacts with the adjacent bottom electrode 108, causing damage to the bottom electrode 108. Therefore, in an embodiment of the present invention, The sidewall of the transition metal oxide layer 110 is away from the bottom electrode 108, and the transition metal oxide layer 110 covers the plurality of bottom electrodes 108, thereby avoiding damage caused by the plasma generated by the process, thereby further reducing the resistance of the resistive random access memory structure 100. Variation of sexual characteristics. In some embodiments, as shown in FIG. 1F, the bottom electrode closest to one of the sidewalls of the transition metal oxide layer 110 has a first width W, and the shortest distance between the bottom electrode 108 and the sidewall of the transition metal oxide layer 110 is one. The first distance D, the first distance D ranges between 10 nm and 200 μm, for example about 1.5 μm. In some embodiments, the adjacent two bottom electrodes 108 can have a minimum pitch P as shown in FIG. 1F. Preferably, the first distance D may be between one tenth and ten times the minimum pitch P. Lift For example, when the minimum pitch P is 100 nm, the first distance D may be selected from any value between 10 nm and 1000 nm. The first width W ranges between about 100 nm and 200 nm, such as about 150 nm. In some embodiments, the first distance D is not less than the first width W. In some embodiments, the ratio W:D of the first width W to the first distance D is between 1:1 and 1:2000.

In addition, the number of bottom electrodes 108 covered by one continuous transition metal oxide layer 110 may exceed two. Therefore, except for the bottom electrode 108 located at the outermost side of the transition metal oxide layer 110, each of the remaining bottom electrodes 108 is completely covered by the transition metal oxide layer 110, and thus is not damaged by the plasma. Furthermore, by limiting the range of the first distance D to be between 10 nm and 200 μm, the bottom electrode 108 located at the outermost side of the transition metal oxide layer 110 is not damaged by the plasma. Preferably, the first distance D may be not less than the first width W.

Next, referring to FIG. 1G, a third dielectric layer 118 is formed on the substrate 102 and covers the second dielectric layer 116 and the exposed first dielectric layer 104. In some embodiments, the material of the third dielectric layer 118 may be tantalum oxide, tantalum nitride, hafnium oxynitride, fluorosilicate glass (FSG), black diamond, low dielectric constant material (low) -k dielectrics), combinations of the above, or other suitable dielectric materials. The third dielectric layer 118 can be formed by chemical vapor deposition (CVD), high density plasma chemical vapor deposition (HDPCVD), or other suitable process. Next, a third opening 120 is formed by patterning the third dielectric layer 118 and the second dielectric layer 116 by a lithography and anisotropic etching process (eg, a reactive ion etching (RIE) process, and exposing a portion Top electrode 114. In some embodiments, the second opening 120 is offset from any of the bottom electrodes 108 below it, as in Figure 1H. Show. In this embodiment, the second opening 120 can be disposed corresponding to the common source wire 15 . Thereby, the second opening 120 is offset from the active area 124 (as shown in FIG. 1H), which may reduce the damage that may be caused to the top electrode 114 in the active area 124 by the process of making the second opening 120. The active regions 124 are working areas of the resistive random access memory structure 100.

Referring to FIG. 1H, the second opening 120 is filled with a conductive material, and then an etch-back process or a planarization process such as a chemical mechanical polishing (CMP) process is performed to remove the top surface of the third dielectric layer 118. The upper conductive material is formed in the second opening 120 to electrically connect the via plug 122 to the top electrode 114, that is, the fabrication of the resistive random access memory structure 100 is completed. In some embodiments, the material of the via plug may comprise tungsten (W), copper (Cu), combinations thereof, or materials similar thereto. In this embodiment, one via plug 122 can correspond to a plurality of bottom electrodes 108, as shown in the figure, so that a plurality of bottom electrodes 108 can be controlled by a single via plug 122, thereby controlling the interlayer layers. A plurality of transistors 10 in the dielectric layer 103.

Figure 3 is a perspective top view of the resistive random access memory structure 100 of Figure 1H. The 1H map is drawn along the line A-A' in Fig. 3. Referring to FIG. 3, in the random access memory structure 100, a plurality of transition metal oxide layers 110 are arranged in an array. There are, for example, four bottom electrodes 108 formed in the range of each transition metal oxide layer 110. The bottom electrode 108 has a shortest first distance D from the sidewall of the transition metal oxide layer 110, and the first distance D ranges between 10 nm and 200 μm. As described above, since the distance between the sidewall of the transition metal oxide layer 110 and the sidewall of the bottom electrode 108 is sufficiently far, the damage of the bottom electrode 108 by the plasma can be avoided, thereby reducing the resistance. Variations in the electrical properties of the random access memory structure 100.

Still referring to FIG. 3, in the range of each transition metal oxide layer 110, a via plug 122 is disposed between the two bottom electrodes 108, thereby avoiding a reactive ion etching process in the active region 124. The top electrode 114 causes damage, which in turn reduces variations in the electrical characteristics of the resistive random access memory structure 100.

FIG. 3 only shows that two via plugs 122 and four bottom electrodes 108 are formed in a range of transition metal oxide layer 110. However, in other embodiments, more bottom electrode 108 and top electrode 114 may be formed in the range of one transition metal oxide layer 110.

2A-2E is a cross-sectional view showing a process of forming a resistive random access memory structure 100 according to another embodiment of the present invention. First, referring to FIG. 2A, a transition metal oxide material 110' is formed on the first dielectric layer 104 and the bottom electrode 108 of the resistive random access memory structure 100 as shown in FIG. 1D. In some embodiments, the method and material for forming the transition metal oxide material 110' is similar to the transition metal oxide material 110' of FIG. 1E and will not be described herein. Next, a dielectric material is formed on the transition metal oxide material 110' by a deposition process such as chemical vapor deposition (CVD), spin coating, or other suitable process, and patterned. A fourth dielectric layer material 202' having a plurality of openings 203 is formed. In some embodiments, the fourth dielectric layer material 202' may comprise cerium oxide (SiO ₂ ), cerium oxynitride (SiON), tantalum nitride (SiN), borophosphorite glass (BPSG), phosphorous Phosphate glass (PSG), other suitable materials, or a combination of the above. In some embodiments, the openings 203 are respectively disposed on the bottom electrode 108 as shown in FIG. 2A. In some embodiments, the opening 203 has a width of between about 0.05 [mu]m and 0.2 [mu]m.

Next, referring to FIG. 2B, a barrier layer material 204' is conformally formed in the opening 203 and extended to the fourth dielectric layer material 202'. That is, after the barrier layer material 204' is filled in the opening 203, the surface of the barrier layer material 204' located in the opening 203 is still lower than the surface of the barrier layer material 204' located on the fourth dielectric layer material 202'. . That is, the thickness of the barrier layer material 204' is less than the depth of the opening 203, and is not sufficient to fill the opening 203. In some embodiments, the material of the barrier layer material 204' comprises a metal oxynitride MNxOy, wherein M can be tantalum (Ta), titanium (Ti), tungsten (W), hafnium (Hf), nickel (Ni), Aluminum (Al), a nitrogen element (such as lanthanum, cerium), cobalt (Co) or zirconium (Zr), the proportion of N is about 5% to 30%. For example, the barrier layer material 204' can be aluminum oxide (Al ₂ O ₃ ), zirconium oxide (ZrO 2 ), hafnium oxide (HfO 2 ), tantalum pentoxide (Ta ₂ O ₅ ), or other suitable materials. The barrier layer material 204' can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or other suitable process. Next, an oxygen-reactive material 206' is deposited to fill the opening 203 and extend over the barrier layer material 204'. In some embodiments, the oxygen reactive material 206' can be titanium (Ti), hafnium (Hf), tantalum (Ta), zirconium (Zr), aluminum (Al), nickel (Ni), combinations thereof, or the like. . The oxygen reactive material 206' can be formed using physical vapor deposition (PVD), chemical vapor deposition (CVD), or other suitable process.

Next, referring to FIG. 2C, a planarization process (for example, a chemical mechanical polishing (CMP) process) is performed to remove the portion of the barrier layer material 204' and the oxygen-reactive material 206' located outside the opening 203 (ie, at the first A portion of the four dielectric layer material 202') forms a discontinuous oxygen reactive layer 206 in the opening 203 and a plurality of barrier layers 204. In some embodiments, the discontinuous oxygen reaction layer 206 includes a plurality of mutually isolated segments that are respectively located in the opening 203 and Correspondingly disposed on the bottom electrode 108. The barrier layer 204 is located on the bottom and sidewalls of the opening 203 and surrounds each of the mutually isolated sections of the discontinuous oxygen reactive layer 206, as shown in FIG. 2C. By the planarization process described above, the upper surface of the discontinuous oxygen reactive layer 206 can be substantially coplanar with the upper surface of the fourth dielectric layer material 202', which can enhance the uniformity of the subsequently formed top electrode, thereby reducing Variation in the electrical characteristics of the resistive random access memory structure 100.

Thereafter, a barrier layer material 208' is formed over the fourth dielectric layer material 202', the barrier layer 204, and the discontinuous oxygen reactive layer 206. The method and material for forming the barrier layer material 208' are similar to the barrier layer material 204' of Figure 2B and will not be described herein. Next, a top electrode material 114' and a second dielectric material 116' are sequentially formed on the barrier layer material 208' as shown in Fig. 2C. The method and material for forming the top electrode material 114' and the second dielectric material 116' are similar to the top electrode material 114' and the second dielectric material 116' in Fig. 1E and will not be described herein.

Next, referring to FIG. 2D, a patterning process is performed to pattern the transition metal oxide material 110', the fourth dielectric layer material 202', the barrier layer material 208', the top electrode material 114', and the second dielectric material. 116', a transition metal oxide layer 110, a fourth dielectric layer 202, a barrier layer 208, a top electrode 114, and a second dielectric layer 116 are formed, and a portion of the first dielectric layer 104 is exposed. In some embodiments, the transition metal oxide layer 110 covers the plurality of bottom electrodes 108 and extends over portions of the first dielectric layer 104.

Next, referring to FIG. 2E, a third dielectric layer 118 is formed on the substrate 102, covering the second dielectric layer 116 and the exposed first dielectric layer 104, and then forming a via plug 122 through the third dielectric layer. The electrical layer 118 and the second dielectric layer 116 are electrically connected to the top electrode 114, that is, the resistive randomization is completed. The creation of the access memory structure 100.

As shown in FIG. 2E, in some embodiments of the present invention, the discontinuous oxygen reaction layer 206 can precisely control the conductive filaments in the transition metal oxide layer 110 to be formed on the corresponding discontinuous oxygen reaction layer 206 and the bottom electrode 108. The position of the discontinuous oxygen reaction layer 206 and the bottom electrode 108 to form the conductive filaments is away from the sidewall of the resistive random access memory structure 100, thereby preventing the formation of the conductive filaments from being caused by the patterning process. The damage of the plasma, and thus the discontinuous oxygen reaction layer 206, can also greatly improve the endurance performance. In addition, by completely covering the discontinuous oxygen reaction layer 206 by the barrier layer 204 and the barrier layer 208, the conductive filaments can be promoted to be confined to the region where the transition metal oxide layer 110 and the discontinuous oxygen reaction layer 206 are aligned. High-density oxygen vacancies can further improve the characteristics of high temperature data retention (HTDR) at high temperatures.

In summary, in an embodiment of the present invention, the upper surface 108s of the bottom electrode 108 and the upper surface of the first dielectric layer 104 are planarized using a planarization process in the fabrication of the resistive random access memory structure. The 104s are substantially coplanar, thereby enhancing the uniformity of the subsequently formed transition metal oxide layer 110 and the top electrode 114. In addition, the present invention can make the plasma generated by the reactive ion etching process of the patterned transition metal oxide layer 110 away from the bottom electrode 108 by having the bottom electrode 108 and the sidewall of the transition metal oxide layer have a first distance D. Avoid damage to the bottom electrode 108. The present invention is also provided by dislocating the second opening 120 from any of the bottom electrodes 108 underneath. The dislocation manner is provided by a reactive ion etching process for patterning the third dielectric layer 118 and the second dielectric layer 116. The generated plasma is away from the top electrode 114 to avoid damage to the top electrode 114. Furthermore, The invention further reduces the damage of the respective bottom electrodes 108 to the plasma generated by the process by covering a plurality of bottom electrodes 108 with a transition metal oxide layer 110. The above advantages can greatly reduce variations in the electrical characteristics of the resistive random access memory structure 100. Moreover, the present invention can also control the plurality of bottom electrodes 108 by a single via plug 122, thereby simultaneously controlling the plurality of transistors 10 located in the interlayer dielectric layer 103.

In another embodiment of the present invention, the discontinuous oxygen reaction layer 206 may cause the conductive filaments in the transition metal oxide layer 110 to be away from the sidewalls of the transition metal oxide layer to avoid damage to the process plasma, thereby improving durability. Endurance performance. In addition, the barrier layer 204 and the barrier layer 208 completely encapsulate the discontinuous oxygen reaction layer 206, which can limit the conductive filaments to obtain high-density oxygen vacancies, thereby improving data retention capability (HTDR) at high temperatures. characteristic.

The above is a brief description of the features of several embodiments of the present disclosure, and those of ordinary skill in the art will be able to understand the detailed description of the present disclosure. It should be understood by those of ordinary skill in the art that the present invention may be readily utilized as the basis of the embodiments of the present disclosure. It is to be understood that those skilled in the art can understand that the structure or the process of the above-described equivalents are not departing from the spirit and scope of the disclosure, and may be modified or replaced without departing from the spirit and scope of the disclosure. The scope of the invention is therefore defined by the scope of the appended claims.

10‧‧‧Optoelectronics

12‧‧‧Metal plug

14‧‧‧metal layer

15‧‧‧Common source wire

16‧‧‧ bottom electrode contact plug

100‧‧‧Resistive random access memory structure

102‧‧‧Base

103‧‧‧Interlayer dielectric layer

104‧‧‧First dielectric layer

108‧‧‧ bottom electrode

110‧‧‧Transition metal oxide layer

112‧‧‧Oxygen reaction layer

113‧‧‧Barrier layer

114‧‧‧ top electrode

116‧‧‧Second dielectric layer

118‧‧‧ Third dielectric layer

122‧‧‧Interlayer plug

124‧‧‧Active area

Claims (14)

A resistive random access memory structure includes: a first dielectric layer formed on a substrate; a plurality of bottom electrodes respectively buried in the first dielectric layer; and a transition metal oxide layer covering the bottom And extending to a portion of the first dielectric layer, wherein a shortest distance between the bottom electrode and a sidewall of the transition metal oxide layer is a first distance, and the first distance is between 10 nm and 200 μm, wherein the closest The bottom electrode of the sidewall of the transition metal oxide layer has a first width, and the first distance is not less than the first width; and a top electrode is formed on the transition metal oxide layer. The resistive random access memory structure of claim 1, wherein the ratio of the first width to the first distance is between 1:1 and 1:2000. The resistive random access memory structure of claim 1, wherein the bottom electrodes comprise a minimum pitch, and the first distance is between one tenth and ten times the minimum pitch. The resistive random access memory structure of claim 1, wherein the upper surface of the bottom electrode is substantially flush with the upper surface of the first dielectric layer. The resistive random access memory structure according to claim 1, further comprising an oxygen reaction layer between the top electrode and the transition metal oxide layer, wherein the oxygen reaction layer comprises titanium, germanium and antimony. , zirconium, aluminum, nickel or a combination thereof. The resistive random access memory structure according to claim 5, wherein the oxygen reaction layer has a plurality of isolated segments, respectively corresponding to The bottom electrodes. The resistive random access memory structure of claim 1, further comprising: a second dielectric layer disposed on the top electrode; and a via plug buried in the second dielectric layer And electrically connected to the top electrode, wherein the via plug is disposed offset from any of the bottom electrodes. A method of fabricating a resistive random access memory structure includes: forming a first dielectric layer on a substrate; patterning the first dielectric layer to form a plurality of first openings; forming a plurality of bottom electrodes And forming a transition metal oxide layer covering the bottom electrodes and extending to a portion of the first dielectric layer, wherein a shortest distance between the bottom electrode and a sidewall of the transition metal oxide layer is a first distance, And the first distance is between 10 nm and 200 μm, wherein the bottom electrode of the sidewall closest to the transition metal oxide layer has a first width, and the first distance is not less than the first width; and a top electrode is formed The transition metal oxide layer. The method of manufacturing a resistive random access memory structure according to claim 8, wherein the ratio of the first width to the first distance is between 1:1 and 1:2000. The method of fabricating a resistive random access memory structure according to claim 8, wherein the bottom electrodes comprise a minimum pitch, and the first distance is one tenth to ten times the minimum pitch between. The method of manufacturing a resistive random access memory structure according to claim 8, wherein the forming of the bottom electrode comprises: Forming a bottom electrode material to fill the first openings and extending on the first dielectric layer; and performing a planarization process to remove portions of the bottom electrode material outside the first openings, The bottom electrodes are formed in an opening, wherein upper surfaces of the bottom electrodes are substantially flush with an upper surface of the first dielectric layer. The method for fabricating a resistive random access memory structure according to claim 11, further comprising forming an oxygen reaction layer between the top electrode and the transition metal oxide layer, wherein the oxygen reaction layer comprises titanium, Niobium, tantalum, zirconium, aluminum, nickel or a combination thereof. The method for manufacturing a resistive random access memory structure according to claim 12, wherein the oxygen reaction layer has a plurality of mutually isolated segments corresponding to the bottom electrodes. The method for fabricating a resistive random access memory structure according to claim 8 , further comprising: forming a second dielectric layer on the top electrode; and forming a via plug in the second dielectric And electrically connected to the top electrode, wherein the via plug is disposed offset from any of the bottom electrodes.