TWI602293B - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Description

Semiconductor device and method of manufacturing semiconductor device

The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device.

In recent years, CMOS technology has been upgraded, and SoC (System on a Chip), which is a hybrid of analog circuits and digital circuits, has been used for various purposes. In such a hybrid wafer, various isolation techniques are used in order to reduce noise transmitted from the digital circuit to the analog circuit. For example, the distance from the noise source of the digital circuit to the analog circuit can be increased, and an insulating layer such as STI (Shallow Trench Isolation) or DTI (Deep Trench Isolation) can be formed inside the substrate to form a Guard Ring or a triple well. A well layer such as (Triple Well) is a high-resistance substrate, or a combination of these methods.

[Advanced technical literature] [Patent Literature]

[Patent Document 1] Japanese Patent Laid-Open Publication No. 2001-345428

[Patent Document 2] Japanese Patent Laid-Open Publication No. 2004-253633

With the analogy. The high integration or high frequency of the digital mixed-wafer wafer causes a situation in which the noise transmitted to the substrate cannot be sufficiently blocked in the above-described isolation technique. Due to the high integration, it is difficult to obtain a sufficient distance between the analog circuit and the digital circuit, and there is a case where the noise is transmitted in a field deeper than the above-mentioned insulating layer or well layer. Further, when a high frequency signal of 1 GHz or more is used, the impedance of the triple well structure is small, and a sufficient noise blocking effect cannot be obtained.

One of the objects exemplified in a certain aspect of the present invention is to provide a technique for improving noise interruption characteristics between a plurality of circuit domains formed on a semiconductor substrate.

A semiconductor device according to a certain aspect of the present invention includes: a first circuit field provided on a main surface of a semiconductor substrate; and a second circuit field provided on a side of a first circuit region of a main surface; and a first isolation structure; This is formed in the first circuit field, and the second isolation structure is formed between the first circuit domain and the second circuit domain, and has a higher resistance region than the semiconductor substrate.

Another aspect of the present invention is a method of manufacturing a semiconductor device.

This method includes a step of preparing a semiconductor substrate having a first circuit region provided on a main surface and a second circuit region disposed beside the first circuit region of the main surface; a step of disposing on a main surface of the semiconductor substrate, the mask having an opening corresponding to a field between the first circuit region and the second circuit region; and ionizing the main surface from the mask, and 1 The field between the circuit field and the second circuit field forms a step of forming a higher resistivity field than the semiconductor substrate.

Further, any combination of the above-described constituent elements, or the constituent elements or expressions of the present invention, between the method, the device, the system, and the like, is also effective as an aspect of the present invention.

According to the present invention, the noise interruption characteristics between the plurality of circuit domains formed on the semiconductor substrate can be improved.

E1‧‧‧1st circuit area

E2‧‧‧2nd circuit area

10‧‧‧Semiconductor device

12‧‧‧Semiconductor substrate

12a‧‧‧Main face

12b‧‧‧Back

14‧‧‧Three-well structure

24‧‧‧ retaining ring

40‧‧‧1st isolation structure

50‧‧‧2nd isolation structure

52‧‧‧Ditch type high resistance field

56‧‧‧Flat type high resistance field

60‧‧‧ mask

62‧‧‧ openings

Fig. 1 is a cross-sectional view schematically showing a structure of a semiconductor device of an embodiment.

FIG. 2 is a top view schematically showing a configuration of the semiconductor device of FIG. 1. FIG.

FIG. 3 is a view schematically showing a method of manufacturing the semiconductor device of FIG. 1. FIG.

4 is a graph showing an example of a specific resistance distribution of a semiconductor substrate after ion irradiation.

5(a) to 5(c) are diagrams schematically showing the relationship between the ion species used for ion irradiation and the shape of the high resistance region to be formed.

FIG. 6 is a cross-sectional view schematically showing an effect obtained by the semiconductor device.

Fig. 7 is a graph showing the communication characteristics of the isolation structure.

Fig. 8 is a graph showing the communication characteristics of the isolation structure.

FIG. 9 is a cross-sectional view schematically showing a structure of a semiconductor device according to a modification.

FIG. 10 is a view schematically showing a method of manufacturing the semiconductor device of FIG. 9. FIG.

11(a) and 11(b) are cross-sectional views schematically showing a method of forming a groove-type high resistance region according to a modification.

FIG. 12 is a graph showing an example of a specific resistance distribution of a semiconductor substrate after ion irradiation.

Hereinafter, the form for carrying out the invention will be described in detail. Further, the configurations described below are illustrative and are not intended to limit the scope of the invention. In the description of the drawings, the same components are denoted by the same reference numerals, and the overlapping description will be appropriately omitted. Moreover, in the following description In the various cross-sectional views, the thickness or size of the semiconductor substrate or other layers is not necessarily the actual size or ratio for the convenience of description.

1 is a cross-sectional view schematically showing a structure of a semiconductor device 10 of an embodiment, and FIG. 2 is a top view of the semiconductor device 10. The semiconductor device 10 is an integrated circuit (IC) such as a system LSI or a system-on-chip. The semiconductor device 10 includes a first circuit region E1 and a second circuit region E2 which are formed on the principal surface 12a of the semiconductor substrate 12. For example, an analog circuit is formed in the first circuit domain E1, and a digital circuit is formed in the second circuit domain E2.

In the present embodiment, the first isolation structure 40 is formed in the first circuit region E1, and the second isolation structure 50 is formed in the separation region E3 between the first circuit region E1 and the second circuit region E2. The first isolation structure 40 is a conventional isolation structure such as a triple well structure 14 or a retainer 24 . On the other hand, the second isolation structure 50 is an isolation structure different from the conventional type, which is formed by a trench-type high-resistance field 52 having a depth d of 20 μm or more from the principal surface 12a. In the present embodiment, by providing the second isolation structure 50 in the first isolation structure 40, the noise interruption characteristic between the first circuit area E1 and the second circuit area E2 is improved.

The semiconductor device 10 is provided with a semiconductor substrate 12. The semiconductor substrate 12 has a resistivity of 100 Ω. A low-resistance semiconductor substrate of cm or less, for example, a p-type germanium (Si) wafer fabricated by the Czochralski (CZ) method. The wafer fabricated by the CZ method is compared with a high-resistance wafer fabricated by a floating region (FZ) method, and the resistivity is low, and the price is high. should.

In the present specification, a direction orthogonal to the principal surface 12a of the semiconductor substrate 12 is referred to as an up-down direction or a depth direction, and a direction from the semiconductor substrate 12 toward the main surface 12a side is referred to as an upper direction or an upper side, and is referred to as The direction of the opposite back surface 12b of the main surface 12a is referred to as a lower direction or a lower side. Further, a direction parallel to the main surface 12a is referred to as a lateral direction or a horizontal direction.

The first circuit domain E1 is an analog component field 20 including a semiconductor element in which a transistor or a diode constituting the analog circuit is formed. The analog element field 20 is an impurity diffusion layer provided with a well region, a source/drain region, a contact region, and the like for forming a semiconductor element. The analog element field 20 is provided inside the p well 18, and the p well 18 is provided inside the n well 16. The n well 16 and the p well 18 form a so-called triple well structure 14 to reduce noise entering the analog element domain 20.

In the analog component field 20, a retainer 24 for reducing noise is provided. The retainer 24 is a field in which the conductive surface of the main surface 12a is high so as to be able to surround the source/drain region or the contact region. The retainer 24 is formed of a metal layer or a high-concentration impurity layer or the like and is connected to the ground terminal 28. In the illustrated example, the retainer 24 is formed around the p-type contact area 22 that is coupled to the analog signal terminal 26 to reduce noise entering the analog signal terminal 26.

The second circuit field E2 is a digital device field 30 including a semiconductor element in which a transistor or a diode constituting a digital circuit is formed. The digital component field 30 is provided with a well region for forming a semiconductor element, a source/drain region, a contact region, and the like. Graphical example in digital The component area 30 is formed with a p-type contact area 32 that is connected to the digital signal terminal 36.

The separation area E3 is located between the first circuit area E1 and the second circuit area E2, and forms a trench type high resistance field 52. The trench type high resistance region 52 is a field having a higher resistivity than the body region 12d of the semiconductor substrate 12, and has 100 Ω. Resistivity above cm. The resistivity of the trench type high resistance field 52 is, for example, 500 Ω. Above cm, ideally 1kΩ. More than cm.

The trench type high resistance region 52 is formed to have a certain depth d from the back surface 12b on the opposite side from the main surface 12a of the semiconductor substrate 12. The trench type high resistance region 52 is formed deeper than the impurity diffusion layer or the triple well structure 14 formed in the analog element region 20 or the digital device region 30. The depth d of the trench type high resistance region 52 is 20 μm or more, and preferably about 50 μm to 200 μm. By expanding the depth d of the trench-type high-resistance field 52, the noise reduction effect between the analog component field 20 and the digital component field 30 can be improved.

The groove-type high-resistance field 52 has a small width w1 in the lateral direction of the main surface 12a, and a width w2 in the lateral direction near the bottom portion 52d of the back surface 12b. Here, the horizontal direction means a direction in which the first circuit area E1 and the second circuit area E2 are adjacent to each other, and the horizontal direction of the paper surface of FIGS. 1 and 2 . As shown in the figure, the groove-type high-resistance field 52 is formed to have a wider width in the lateral direction as it leaves the main surface 12a. By enlarging the width w2 of the bottom portion 52d in the lateral direction, the propagation path of the noise signal under the bottom portion 52d can be elongated along the groove-type high resistance region 52, thereby improving the noise reduction effect.

The trench type high resistance region 52 is formed by irradiating an ion beam to the body region 12d of the semiconductor substrate 12 of the low resistance substrate. Once the wafer is ionized, the ions will reach a depth corresponding to the acceleration energy of the ions. At this time, a lattice defect is formed in the vicinity of the region including the arrival, and the crystal is regularly (periodically) disordered. In such a field where there are many lattice defects, the electrons are easily scattered, and the movement of electrons is hindered. That is, in the field where localized lattice defects are generated by ion irradiation, the resistivity increases. In this way, a high resistance field can be formed.

Further, the position or range in the depth direction in which the resistivity increases due to ion irradiation can be adjusted by appropriately selecting the acceleration energy or the ion species of the ion irradiation and the irradiation amount. For example, the depth position formed in the high resistance region can be adjusted by adjusting the acceleration energy of the ions at the time of ion irradiation. Further, the range in the depth direction (half-value width) or the width in the lateral direction in which the high-resistance region is formed can be adjusted by appropriately selecting the ion species used for ion irradiation. Further, by performing a plurality of ion irradiations while changing the acceleration energy, a thicker high resistance region can be formed in the depth direction.

In the present embodiment, for example, light ions such as hydrogen (H) or helium (He) are irradiated with an acceleration energy of 5 MeV or more and 100 MeV or less. As the means for irradiating the ion beam of such acceleration energy, a cyclotron method or a Van de Graaff type device can be used. By using such irradiation conditions, ions can be brought from the vicinity of the main surface 12a of the semiconductor substrate 12 to a position having a depth of 100 μm or more in the germanium wafer.

Next, a method of manufacturing the semiconductor device 10 of the present embodiment will be described.

FIG. 3 is a view schematically showing a manufacturing process of the semiconductor device 10, and shows a state in which the trench-type high-resistance field 52 is formed by ion irradiation. First, it is prepared to form the triple well structure 14 in the first circuit domain E1, and to form the semiconductor substrate 12 of the circuit component in the analog component field 20 and the digital component field 30. Next, the mask 60 is placed on the main surface 12a, and the ion beam IB is irradiated from the mask 60 to the main surface 12a of the semiconductor substrate 12. The mask 60 is provided with an opening 62 at a position corresponding to the separation area E3, and passes the ion beam IB toward the separation area E3 to shield the ion beam IB toward the first circuit area E1 and the second circuit area E2. By shielding the ion beam IB toward the first circuit area E1 and the second circuit area E2, the resistivity of the analog element field 20 or the digital element field 30 is prevented from becoming high by ion irradiation.

The separation field E3 in which the ion beam IB is irradiated among the semiconductor substrates 12 is formed with a groove type high resistance region 52. The trench type high resistance region 52 is composed of a plurality of high resistance regions 53 to 55 as shown in the figure. The first high-resistance field 53 formed in the vicinity of the principal surface 12a is formed by irradiating the ion beam IB having a low acceleration energy. The third high-resistance field 55 formed at a position deeper from the principal surface 12a is formed by irradiating the ion beam IB having a high acceleration energy. The second high-resistance field 54 formed between the first high-resistance field 53 and the third high-resistance field 55 is formed by irradiating the ion beam IB having an intermediate acceleration energy. By irradiating the ion beam IB a plurality of times while changing the acceleration energy, the groove type high resistance can be expanded. The thickness d of the field 52. Further, by performing ion irradiation from the main surface 12a side of the semiconductor substrate 12, a high resistance region can be formed in the vicinity of the main surface 12a, that is, from the direct surface of the main surface 12a.

After the trench type high resistance region 52 is formed by the process shown in FIG. 3, heat treatment may be applied to the semiconductor substrate 12. The temperature of the heat treatment is an imaginary upper limit temperature at the time of use of the semiconductor device, for example, 100 ° C or 200 ° C. Since the heat treatment changes in the resistivity in a part of the trench type high resistance field 52, the resistivity is lowered depending on the place. When the semiconductor device 10 is used in the range of the operating upper limit temperature by performing the heat treatment in advance, the influence of the decrease in the resistivity in the field of high resistance after the event can be reduced. Thereby, the change in the resistivity after the event can be suppressed, and the reliability of the semiconductor device 10 can be improved.

Such a heat treatment can also be carried out in a so-called "post-engineering" which is a project including dicing a wafer to be diced, and bonding the diced wafer to the mounting substrate by wire bonding, and Resin to seal the wafer. For example, in a process of sealing a wafer with a resin, by heating the wafer to a temperature necessary for curing the resin, heat treatment can be performed while sealing treatment. In addition, heat treatment may be applied as a different process from the resin sealing process.

4 is a graph showing an example of a specific resistance distribution of a semiconductor substrate after ion irradiation. This figure shows the result of irradiating the ion of ³ He ²⁺ at a depth of 13 μm, 28 μm, and 48 μm from the main surface of the semiconductor substrate at a dose of 10 ¹³ /cm ² . As shown, it can be seen that the resistivity of the substrate will be from about 30 Ω in the range from the main surface to a depth of about 60 μm. Cm increases to about 3kΩ. Cm. Further, it can be seen that even when heat treatment is added after ion irradiation, it is about 2 kΩ. A high resistance region of cm or more is formed with a thickness of about 60 μm. By thus changing the acceleration energy to illuminate the ion beam to different depth positions, a thick high resistance field can be formed.

In addition, when the acceleration energy is changed to illuminate the ion beam to different depth positions, the p-type substrate which is diffused with a p-type dopant such as boron (B) or aluminum (Al) is more diffused than phosphorus (P) or arsenic (As). An n-type substrate such as an n-type dopant is more likely to form a high resistance field. In other words, the p-type substrate is more likely to increase in resistivity than the n-type substrate. Therefore, by using a p-type substrate, a high-resistance field having a larger depth d can be formed.

5(a) to 5(c) are diagrams schematically showing the relationship between the ion species used for ion irradiation and the shapes of the high resistance regions 52a, 52b, 52c to be formed. Fig. 5(a) shows a case where a divalent 氦4 ion ( ⁴ He ²⁺ ) is used as an ion species to form a trench-type high-resistance region 52a having a depth of about 150 μm. When the width w1 of the main surface 12a in the lateral direction is 50 μm, the width w2 of the bottom portion 52d in the lateral direction is about 64 μm. (b) of FIG. 5 is a case where the divalent 氦3 ion ( ³ He ²⁺ ) is used as the ion species. When the width w1 of the main surface 12a in the lateral direction is 50 μm, the width w2 of the bottom portion 52d in the lateral direction is 70 μm. . (c) of FIG. 5 is a case where the monovalent hydrogen ion ( ¹ H ⁺ ) is used as the ion species. When the width w1 of the main surface 12a in the lateral direction is 50 μm, the width w2 of the bottom portion 52d in the lateral direction is about 80 μm. By changing the ion species in this manner, the lateral expansion of the trench-type high resistance region 52 can be adjusted. In particular, by the light hydrogen ions, the groove-type high-resistance field 52 having a large width w2 in the lateral direction of the bottom portion 52d can be formed.

FIG. 6 is a cross-sectional view schematically showing an effect obtained by the semiconductor device 10. This figure shows the propagation of noise from the p-type contact area 32 connected to the digital signal terminal 36 to the p-type contact area 22 connected to the analog signal terminal 26. The noise 71 propagating in the lateral direction in the vicinity of the main surface 12a is attenuated by the trench type high resistance region 52, and is further attenuated by the triple well structure 14 or the retainer 24 to reach the p-type contact region 22. Similarly, the noise 72 that propagates in a lateral direction deeper than the analog element domain 20 is also attenuated by the trench high resistance region 52, the triple well structure 14 and the retainer 24, reaching the p-type contact region 22. Further, the noise 73 which propagates in the deep direction at the deep position is below the bottom portion 52d which is wide in the lateral direction width w2, and the propagation distance becomes long, whereby the signal intensity is attenuated. According to the semiconductor device 10 as described above, by providing the trench-type high-resistance field 52 at the position between the analog component field 20 and the digital device region 30, the influence of the noise signal generated in the digital circuit on the analog circuit side can be reduced.

Fig. 7 and Fig. 8 are graphs showing the transmission characteristics S ₂₁ of the isolation structure of the embodiment. This graph is a measure of the signal strength input to the digital signal terminal 36 of FIG. 1 and the signal intensity output to the analog signal terminal 26, and the S parameter is calculated and found. Further, a groove-type high-resistance field 52 in which the width w1 of the main surface 12a is 50 μm, the width w2 of the bottom portion 52d is 58 μm, and the depth d is 60 μm is formed as the second isolation structure 50 of Fig. 1 . Further, a semiconductor device in which at least a part of the triple well structure 14, the retainer 24, and the trench type high resistance region 52 are not provided is prepared, and the same measurement is performed as a comparative example.

In FIG. 7, a graph 80 is a comparative example in which the triple-well structure 14, the retainer 24, and the groove-type high-resistance field 52 are not provided. The graph 81 is a comparative example in which only the retainer 24 is provided, and the graph 82 is a guard. Embodiments of the ring 24 and the trench type high resistance field 52. As shown in the figure, by combining the retainer 24 and the groove-type high-resistance field 52, compared with the case where only the retainer 24 is provided, it is known that the isolation effect is increased by -5 dB to -10 dB.

In FIG. 8, the graph 80 is the same as that of FIG. 7, the graph 83 is a comparative example in which the triple-well structure 14 and the retainer 24 are provided, and the graph 84 is a view showing the provision of the triple-well structure 14, the retainer 24, and the trench-type high resistance. An embodiment of field 52. As shown in the figure, by combining the triple well structure 14 and the retainer 24 with the combined trench type high resistance field 52, compared with the case where only the triple well structure 14 and the retainer 24 are provided, it is known that the isolation is increased by -5dB to -10dB. effect.

By combining the trench-type high-resistance field 52 as the second isolation structure 50 in this manner, the noise interruption function can be improved more than in the case of using only the first isolation structure 40 such as the triple-well structure 14 or the retainer 24 . According to the present embodiment, since the trench-type high-resistance region 52 reaching the position deeper than the impurity diffusion layer is provided, the noise signal transmitted to the deep region of the semiconductor substrate 12 can be effectively reduced. In addition, since the groove-type high-resistance field 52 is formed so that the width in the lateral direction becomes larger as it becomes deeper, the effect of reducing noise can be improved more than in the case of forming a vertical high-resistance field.

(Modification 1)

FIG. 9 is a view schematically showing the configuration of a semiconductor device 110 according to a modification. Sectional view. The semiconductor device 110 is different from the above-described embodiment in that the combination trench type high resistance region 152 and the planar high resistance region 154 are used as the second isolation structure 150. Hereinafter, description will be given focusing on differences from the embodiment.

The second isolation structure 150 has a trench type high resistance region 152 and a planar high resistance region 154. The trench type high resistance region 152 is configured in the same manner as the trench type high resistance region 52 of the above-described embodiment. The planar high resistance region 154 is formed deeper than the trench type high resistance region 152, and extends in the lateral direction in the first circuit domain E1 and the separation domain E3. The planar high resistance region 154 is provided in such a manner as to form a high resistance region continuous with the trench type high resistance region 152, and is formed in such a manner that a low resistance region is not generated between the trench type high resistance region 152. The planar high resistance region 154 is provided to avoid the second circuit region E2, and is formed so as not to have a high resistance region below the digital device region 30.

FIG. 10 is a view schematically showing a method of manufacturing the semiconductor device 110, showing a process of forming the planar high resistance region 154. First, similarly to the process shown in FIG. 3, a trench type high resistance region 152 is formed in the separation region E3 of the semiconductor substrate 12. Next, a mask 160 is disposed on the back surface 12b, and the ion beam IB is irradiated from the mask 160 to the back surface 12b of the semiconductor substrate 12. The mask 160 is provided with an opening 162 at a position corresponding to the fourth circuit area E1 and the separation area E3, and passes the ion beam IB toward the first circuit area E1 and the separation area E3 to shield the ion beam toward the second circuit area E2. IB. Thereby, the planar high resistance region 154 can be formed at a position at a predetermined depth from the back surface 12b.

According to the present modification, by forming the planar high-resistance field 154 by the trench-type high-resistance field 152, the noise signal propagated under the bottom portion 52d of the trench-type high-resistance field 52 can be made as shown in FIG. More reduced. By continuously forming the trench type high resistance region 152 and the planar high resistance region 154, the low resistance region is not formed between the two, and the high resistance region can surround the periphery of the analog component region 20. Thereby, the effect of reducing the noise signal from the digital component field 30 to the analog component field 20 can be further improved.

Further, according to the present modification, since the planar high-resistance field 154 is not formed below the digital device field 30, the noise signal generated in the digital device field 30 can be moved to the field below the digital device field 30. 12d. As a result, in comparison with the case where the planar high resistance region 154 is also provided in the second circuit region E2, the ratio of the noise signal from the digital device domain 30 to the analog component region 20 can be reduced. Thereby, the noise shielding characteristics of the second isolation structure 150 can be improved.

(Modification 2)

11(a) and 11(b) are cross-sectional views schematically showing a method of forming the trench type high resistance region 252 according to the modification. In the present modification, by providing the ion beam IB irradiated onto the principal surface 12a of the semiconductor substrate 12 at a predetermined incident angle θ, the groove-type high resistance region 252 having a wider width in the lateral direction of the bottom portion 252d can be formed. For example, after the main surface 12a of the semiconductor substrate 12 is vertically irradiated with the ion beam IB to form the first high-resistance field 252a, as shown in FIG. 11(a), the ion beam IB is obliquely irradiated, and the first high voltage is applied. A second high resistance region 252b is formed beside the resistance region 252a. Next, as shown in FIG. 11(b), by irradiating the ion beam IB obliquely in the opposite direction, a third high-resistance field is formed on the side opposite to the second high-resistance field 252b via the first high-resistance field 252a. 252c. Further, the trench type high resistance region 252 may be formed only by the process of obliquely irradiating the ion beam IB without using the process of irradiating the ion beam IB vertically.

According to the present modification, the width w3 of the bottom portion 252d of the trench type high resistance region 252 can be enlarged as compared with the case where only the first high resistance region 252a is formed. Thereby, the noise reduction effect of the trench type high resistance field 252 can be further improved. Further, in the present modification, since the width w1 in the lateral direction of the vicinity of the principal surface 12a is kept small, even if the field in which the groove-type high-resistance field 252 is formed is close to the component field, it can be prevented from being formed on the main body. The influence of the high resistance of the component area in the vicinity of the surface 12a.

The present invention has been described above based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various design changes can be made, and various modifications can be made, and such modifications are also within the scope of the present invention and are understood by those skilled in the art.

In the above embodiment, the case where the acceleration energy of the irradiated ions is changed to perform the ion irradiation three times is shown. In the modification, the acceleration energy may be changed, and only one ion irradiation may be performed, or the irradiation conditions may be changed to perform ion irradiation twice or more times. By increasing the acceleration energy to increase the number of shots, a thicker high-resistance field can be formed to enhance the characteristics of the inductor element. On the other hand, the cost of ion irradiation can be reduced by reducing the number of irradiations. Therefore, the best ion The number of irradiations is appropriately adjusted in accordance with the depth of the high resistance region necessary for the second isolation structure 50. Specifically, it is preferable to adjust the number of ion irradiations in the range of 2 to 7 times.

In the above-described embodiment, the case where the main surface 12a of the semiconductor substrate 12 is ion-irradiated to form the trench-type high-resistance field is shown. In the modified example, ion irradiation from the back surface 12b may be combined to form a groove-type high resistance region.

FIG. 12 is a graph showing an example of a specific resistance distribution of a semiconductor substrate after ion irradiation, and shows a result of combining ion irradiation from the main surface and ion irradiation from the back surface. In the figure, ions of ³ He ²⁺ are irradiated at a depth of 40 μm and 140 μm from the main surface side of the semiconductor substrate at a dose of 10 ¹³ /cm ² , and a depth of 60 μm from the back side of the semiconductor substrate. Position, the result of the case of irradiating ions of ³ He ²⁺ at a dose of 10 ¹³ /cm ² . As shown, it can be seen that the resistivity of the substrate will be from about 3 Ω in the range from the main surface to a depth of about 150 μm. Cm increases to about 1kΩ. More than cm. Further, it can be seen that after heat treatment, in the field from the main surface to a depth of about 150 μm, the resistivity of the substrate becomes about 1 kΩ. High resistance area of cm. By thus changing the acceleration energy to illuminate the ion beam to different depth positions, and combining the irradiation of the ion beam from the back side, a groove-type high resistance field having a large depth d can be formed.

In the above-described embodiment, the case where the retainer or the triple-trap structure is used is shown as the first isolation structure of the conventional type. In the modification, other isolation techniques for forming an insulating layer such as STI (Shallow Trench Isolation) or DTI (Deep Trench Isolation) may be used. As the first isolation structure.

E1‧‧‧1st circuit area

E2‧‧‧2nd circuit area

E3‧‧‧Separation field

10‧‧‧Semiconductor device

12‧‧‧Semiconductor substrate

12a‧‧‧Main face

12b‧‧‧Back

12d‧‧‧ body area

14‧‧‧Three-well structure

16‧‧‧n trap

18‧‧‧p trap

20‧‧‧ analog component field

22‧‧‧p-type contact area

24‧‧‧ retaining ring

26‧‧‧ analog signal terminals

28‧‧‧ Grounding terminal

30‧‧‧Digital component field

32‧‧‧p-type contact area

36‧‧‧Digital Signal Terminals

40‧‧‧1st isolation structure

50‧‧‧2nd isolation structure

52‧‧‧Ditch type high resistance field

52d‧‧‧ bottom

W1, w2‧‧‧ width

Claims (9)

A semiconductor device characterized by comprising: a first circuit field provided on a main surface of a semiconductor substrate; and a second circuit field provided on a side of the first circuit region of the main surface; and a first isolation structure; The first circuit field is formed in the first circuit field, and the second isolation structure is formed between the first circuit field and the second circuit region, and has a higher resistance region than the semiconductor substrate. The isolation structure includes a trench type high resistance region, and the trench high resistance region is formed such that a width in a direction adjacent to the first circuit region and the second circuit region is wider as it leaves the main surface. The semiconductor device according to claim 1, wherein the first isolation structure includes at least one of a retainer and a triple well structure. The semiconductor device according to claim 1 or 2, wherein the trench type high resistance region is formed deeper than the impurity diffusion layer formed in the first circuit region. The semiconductor device according to claim 1 or 2, wherein the trench-type high-resistance field is formed deeper than the first isolation structure. The semiconductor device according to the first or second aspect of the invention, wherein the second isolation structure further includes a planar high resistance region formed at a position deeper than the impurity diffusion layer of the first circuit region, wherein the planar type is high The field of resistance is continuous with the aforementioned trench type high resistance field. A semiconductor device according to claim 5, wherein the foregoing The planar high resistance field is formed by avoiding the second circuit field described above. A method of manufacturing a semiconductor device, comprising: a step of preparing a semiconductor substrate having: a first circuit region provided on a main surface; and a side of the first circuit region provided on the main surface 2 circuit field; a step of disposing a mask on the main surface of the semiconductor substrate, the mask having an opening corresponding to a field between the first circuit region and the second circuit region; and a step of ion-irradiating the main surface on the cover, and forming a high-resistance field having a higher resistivity than the semiconductor substrate in the field between the first circuit field and the second circuit region, wherein the trench-type high-resistance field is The width in the direction in which the first circuit region and the second circuit region are adjacent is wider as it leaves the main surface. The method of manufacturing a semiconductor device according to claim 7, wherein the ion irradiation on the main surface includes irradiating an ion beam in a direction intersecting a normal line of the main surface. The method of manufacturing a semiconductor device according to the seventh or eighth aspect of the invention, further comprising: providing a mask having an opening at a position corresponding to the first circuit region on a back side opposite to a main surface of the semiconductor substrate And the step of performing ion irradiation on the back surface from the mask, and forming a high resistance region at a position closer to the back surface than the impurity diffusion layer in the first circuit region.