TWI602195B - Semiconductor memory device and memory system including the same - Google Patents

Description

Semiconductor memory device and memory system including the same Related application cross reference

The present application claims priority to Korean Patent Application No. 10-2013-0069152, filed on Jun. 17, 2013, which is hereby incorporated by reference.

Illustrative embodiments of the present invention relate to a semiconductor design technique, and more particularly to a semiconductor memory device for preventing degradation due to word line interference, a method of operating the semiconductor memory device, and an A memory system of the semiconductor memory device.

As the degree of integration of a memory increases, one of the spaces between the word lines contained in the memory (such as a DRAM) decreases. As the space between the word lines decreases, the coupling effect between adjacent word lines can increase.

At the same time, each time a data is input to a memory cell and a data is output from a memory cell, a word line is toggled between a start state and a deactivate state. Since the coupling effect between adjacent word lines can be increased as explained above, the data of one of the memory cells connected to one of the word lines adjacent to a frequently activated word line can be degraded. This phenomenon is called word line interference or word line hitting. Due to word line interference, the data of a memory cell can be used to renew the memory. One of the body cells is expected to be degraded during the retention time.

1 is a diagram for illustrating a portion of a cell array included in a DRAM illustrating the word line interference.

In FIG. 1, "WLL" corresponds to a frequently activated word line having a large number of starts (or a high start frequency). Further, "WLL-1" and "WLL+1" correspond to adjacent word lines which are adjacent to the frequently activated word line WLL. Further, "CL" indicates that one of the memory cells connected to the frequently activated word line WLL, "CL-1" indicates that one of the memory cells is connected to the adjacent word line WLL-1, and "CL+1" indicates the adjacent word. Line WLL+1 connects one of the memory cells. Memory cells CL, CL-1, and CL+1 include plasmonic crystals TL, TL-1, and TL+1, and cell capacitors CAPL, CAPL-1, and CAPL+1, respectively. For reference, "BL" and "BL+1" indicate bit lines.

When the frequently activated word line WLL is activated or deactivated, the voltages adjacent to the word lines WLL-1 and WLL+1 increase or decrease due to one of the word lines WLL, WLL-1 and WLL+1. . Therefore, the amount of charge charged in the cell capacitors CAPL-1 and CAPL+1 is affected, so that the data of the memory cells CL-1 and CL+1 can be degraded.

In addition, electrons are introduced into or discharged from the cell capacitors of the memory cells connected to the adjacent word lines due to electromagnetic waves (which are generated when the word lines are toggled between the activated state and the deactivated state), Therefore the information may be downgraded.

Various embodiments relate to: a semiconductor memory device renewably connectable to a memory cell adjacent to a word line having a large number of start times (or a high start frequency) word line; a semiconductor memory A method of operating a device; and a memory system including the semiconductor memory device.

Moreover, various embodiments are directed to a semiconductor memory device that can be reconnected adjacent to a word line having a large number of startup times (or a high startup frequency) without being applied with a separate address. Memory cell of word line; a semiconductor memory A method of operating a device; and a memory system including the semiconductor memory device.

In one embodiment, a semiconductor memory device can include: a plurality of word lines, each of which is coupled to a plurality of memory cells; and a column of control units adapted to sequentially activate and precharge during a target startup mode Corresponding to one of the target address word lines and the predetermined (N) number of adjacent word lines; and a mode exit control unit adapted to count the number of startup operations performed by the column control unit during the target startup mode to determine Whether to exit from the target startup mode.

In an embodiment, a memory system can include: a memory controller adapted to transmit a mode register set (MRS) setting signal or a target start command for entering a target startup mode, And performing a pre-charge and pre-charge command and a source address for selecting a word line, wherein the source address is classified as a start-precharge history satisfying a target condition of a predetermined condition and a start-precharge history that does not satisfy one of the predetermined conditions; and a semiconductor memory device adapted to enter the target start mode in response to the MRS set signal or the target start command, during the target start mode The sequence start and precharge correspond to one of the target address word lines and the predetermined (N) number of adjacent word lines, and exit from the target start mode by counting the number of start operations.

In one embodiment, a method for operating a semiconductor memory device having a plurality of word lines can include: entering a target startup mode by a mode register set (MRS) setting or a preset command; Sequentially initiating and pre-charging a target word line corresponding to one of the target addresses and a predetermined (N) number of adjacent word lines at a target address and an application of an action command; and counting by the target startup mode The target word line and the number of starts of the adjacent word lines exit from the target startup mode.

The method may further include: receiving a source address for selecting one of the word lines; classifying the source address as the target address and a normal address when entering the target startup mode; The normal address is applied after the target startup mode and the action command is started. And precharging corresponds to one of the normal address word lines; and when the source address and the action command are applied after exiting from the target startup mode, starting and precharging correspond to one of the source address word lines.

When a count number reaches N+1, the semiconductor memory device can exit from the target startup mode.

The method can further include: locking the target address after the categorization of the source address; and determining whether a value of the received source address corresponds to the locked target address after entering the target startup mode One of the values.

The sequential activation and pre-charging of the target word line may include: when the action command is applied after the entering action, the value corresponding to the source address applied through the receiving corresponds to the value of the target address And initiating and pre-charging a first start action corresponding to one of the word lines of the target address; at a time for performing the first start action, selecting the value from the value corresponding to the target address The value of the source address has the N number of addresses that are sequentially adjacent to each other when viewed in two directions; and the source that is applied through the reception when the action command is applied after the first activation action When the value of the address corresponds to the value of the target address, the second start action of one of the word lines corresponding to the N number of addresses selected in the selection is sequentially initiated and precharged.

The selecting may select at least two addresses corresponding to at least two of the plurality of word lines as the N number of addresses, the at least two word lines being adjacent to the one having the target address The two sides of the word line of the source address are physically disposed on the two sides.

According to the above embodiment, it is possible to reconnect to a memory cell adjacent to a word line having a large number of start times (or a high start frequency) word line, thereby substantially preventing the memory cells The data is degraded due to word line interference.

Furthermore, according to the above embodiment, the word line adjacent to one of the word lines having a large number of starts (or a high start frequency) is newly connected without being applied with a separate address. The memory cells may be possible, thereby shortening the time required to prevent the data of the memory cells from degrading due to word line interference.

70‧‧‧ memory controller

80‧‧‧Semiconductor memory device

300‧‧‧Mode setting unit

302‧‧‧Command mode setting section

304‧‧‧Mode register group mode setting section

310‧‧‧ address input unit

320‧‧‧ column control unit

322‧‧‧Address selection section

324‧‧‧ column drive section

330‧‧‧Target Address Latch

340‧‧‧ mode exit control unit

342‧‧‧Target Address Counter

344‧‧‧Mode Exit Signal Generator

350‧‧‧ Address Determination Unit

360‧‧‧New operation control unit

370‧‧‧ memory cell array

380‧‧‧Source Address Latch

710‧‧‧ address detection unit

730‧‧‧Command Generation Unit

750‧‧‧ address generation unit

800‧‧‧Mode setting unit

810‧‧‧ address input unit

820‧‧‧ column control unit

830‧‧‧Target Address Latch

840‧‧‧ mode exit control unit

850‧‧‧ address determination unit

860‧‧‧ new operation control unit

870‧‧‧ memory cell array

880‧‧‧Source Address Latch

1ST ACT_CMD‧‧‧First role command

2ND ACT_CMD‧‧‧Second action command

3RD ACT_CMD‧‧‧ Third Action Command

4TH ACT_CMD‧‧‧ fourth role command

ACT‧‧‧ function command / second action command / third action command

ACT_CMD‧‧‧ action order

ACT_TRR‧‧‧ Results / Output Signal / Signal

ADD‧‧‧ address

ADDR‧‧‧ address signal

BL‧‧‧ bit line

BL+1‧‧‧ bit line

CAPL‧‧‧cell capacitor

CAPL+1‧‧‧cell capacitor

CAPL-1‧‧‧cell capacitor

CL‧‧‧ memory cells

CL+1‧‧‧ memory cells

CL-1‧‧‧ memory cells

CMD‧‧‧ Command Signal/Command

CNT_TRR<0:3>‧‧‧Counting signal

CNT_TRR<0>‧‧‧ initialization bit

CNT_TRR<1>‧‧‧ first bit

CNT_TRR<2>‧‧‧ second bit

CNT_TRR<3>‧‧‧ remaining bits/third bits/last bits

DET‧‧‧Signal/Detection Information/Output Signal/Result

IN_ADDR‧‧‧ source address

INV‧‧‧Inverter

L‧‧‧ target address

L+1‧‧‧ adjacent address/address/selection address

L-1‧‧‧ adjacent address/address/selection address

NR‧‧‧"Anti-or" gate

PRE‧‧‧Precharge command

REF_CMD‧‧‧ new order

SEL_ADDR‧‧‧Select address

SETTING‧‧‧ mode register set code

TL‧‧‧cell crystal

TL+1‧‧‧cell crystal

TL-1‧‧‧cell crystal

TRR_ADDR‧‧‧target address

TRR_CMD‧‧‧ Target Startup Command

TRR_EN‧‧‧ mode enable signal

TRR_EXIT‧‧‧ mode exit signal

WL1‧‧‧ word line

WL2‧‧‧ word line

WLK‧‧‧ word line

WLL‧‧‧Frequently activated word line/word line/target word line

WLL+1‧‧‧adjacent word line/word line

WLL-1‧‧‧ adjacent word line/word line

WLNM‧‧‧ normal word line

1 is a diagram for illustrating a portion of a cell array included in a DRAM illustrating the word line interference.

Figure 2 is a timing diagram for illustrating one of the operations in a target startup mode.

3 is a block diagram illustrating a semiconductor memory device in accordance with an embodiment of the present invention.

4 is a detailed diagram illustrating one of the mode exit control units shown in FIG.

Figure 5 is a detailed diagram illustrating one of the address determination units shown in Figure 3.

Figure 6 is a detailed diagram illustrating one of the column control units shown in Figure 3.

Figure 7 is a block diagram illustrating a memory system in accordance with an embodiment of the present invention.

Figure 8 is a timing diagram illustrating a semiconductor memory device in accordance with one embodiment of the present invention.

Various embodiments are described in greater detail below with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and Throughout the invention, the various components in the various figures and embodiments of the invention correspond to the components of the same number. It should also be noted that in the present specification, "connected/coupled" means a component that not only directly couples another component but also indirectly couples another component through an intermediate component. In addition, a singular form may include a plural form as long as it is not specifically mentioned in a sentence.

Figure 2 is used to illustrate one of the operations in a target startup mode or a target startup operation One of the patterns. In the following description, the target startup mode means that one of adjacent word lines adjacent to a target word line having a large number of startup times (or a high startup frequency) or a frequently activated word line placement may be renewed or activated. Special re-new mode.

A semiconductor memory device includes a plurality of word lines and a memory controller (not shown in FIG. 2) applies various signals (such as command signals CMD, address ADD, and data (not shown in FIG. 2) to the semiconductor memory. The device controls the semiconductor memory device. Hereinafter, the value of one of the addresses corresponding to one of the word lines of the L-th word line (where L is greater than one of the natural numbers) will be represented by "L".

The semiconductor memory device or the memory controller detects a target address of one of the target word lines having a large number of startup times (or a high startup frequency) among the word lines in a predetermined manner.

When the target address is detected, the memory controller applies the command signal CMD and the address ADD to allow the semiconductor memory device to perform a target boot operation. The semiconductor memory device enters the target startup mode in response to the applied command CMD and the address ADD.

In the target boot operation, the memory controller applies the target address and the adjacent address corresponding to the word line adjacent to the target word line to the semiconductor memory device. Hereinafter, a description will be given of a case in which the target address system is "L".

In the target start operation, the target address L is applied to the semiconductor memory device together with an action command ACT, and after a predetermined time elapses, a precharge command PRE is applied to the semiconductor memory device. The semiconductor memory device activates and then precharges the target word line or deactivates the target word line.

Next, adjacent addresses L+1 and L-1 are sequentially applied. In FIG. 2, the adjacent address L+1 is applied together with a second action command ACT, and the adjacent address L-1 is applied together with a third action command ACT. Therefore, the adjacent word lines WLL+1 and WLL-1 corresponding to the adjacent address L+1 and L-1 are respectively activated, and the memory cells adjacent to the adjacent word lines WLL+1 and WLL-1 are newly connected. The order in which the adjacent addresses L+1 and L-1 are applied may be changed.

In the case of degrading the data due to word line interference in this way, since the memory controller should use the command CMD for the new target word line and the adjacent word line, respectively, and the address ADD L, L+1 And L-1 is directly input to the semiconductor memory device, so an operation time can be increased.

3 is a block diagram illustrating a semiconductor memory device in accordance with an embodiment of the present invention.

Referring to FIG. 3, the semiconductor memory device can include a memory cell array 370, a mode setting unit 300, an address input unit 310, a column control unit 320, a target address latch 330, and a mode exit control unit 340. The address determination unit 350, the new operation control unit 360, and a source address latch 380. Here, the mode setting unit 300 may include a command mode setting section 302 and/or an MRS mode setting section 304.

The mode setting unit 300 can set the semiconductor memory device to enter a target startup mode in response to an MRS setting or a preset command, and set the semiconductor memory device to start from the target in response to a mode exit signal TRR_EXIT. Mode exits. The mode setting unit 300 can set a value of a target address TRR_ADDR.

In detail, the mode setting unit 300 activates a mode enable signal TRR_EN in response to the MRS setting or the preset command to cause the semiconductor memory device to enter the target startup mode. Further, the mode setting unit 300 causes the semiconductor memory device to exit from the target startup mode by initiating the mode enable signal TRR_EN in response to activation of the mode exit signal TRR_EXIT. Further, the mode setting unit 300 can set the value of the target address TRR_ADDR by selecting a signal selected to represent one of the values of the target address TRR_ADDR. For example, the mode setting unit 300 can determine the value of the target address TRR_ADDR by being input with an MRS setting code SETTING corresponding to the external application from one of the semiconductor memory devices through the address input unit 310. One of the bits of the source address IN_ADDR.

That is, during the target startup mode, the mode enable signal TRR_EN is maintained for one start. status. In contrast, the mode enable signal TRR_EN maintains a de-start state after exiting from the target boot mode. The general operation of the semiconductor memory device can be performed even when entering the target startup mode. That is, the general operation of the semiconductor memory device, such as data reading/writing, can be performed without limitation even when entering the target startup mode. Since the source address IN_ADDR applied through the address input unit 310 does not have the value of the target address TRR_ADDR during the target startup mode, the column control unit 320 cannot perform the target startup operation.

The mode setting unit 300 includes a command mode setting section 302 and/or an MRS mode setting section 304. That is, the mode setting unit 300 may include only the command mode setting section 302, may include only the MRS mode setting section 304, or may include both the command mode setting section 302 and the MRS mode setting section 304. The command mode setting section 302 causes the semiconductor memory device to enter the target startup mode or exit from the target startup mode in response to the preset command. The MRS mode setting section 304 causes the semiconductor memory device to enter the target startup mode or exit from the target startup mode in response to the MRS setting.

The MRS setting means one of a mode register set (MRS) setting, and one of the MRS schemes for setting a general-purpose semiconductor memory device can be used as it is. That is, the MRS setting can be performed through the MRS setting code SETTING. The MRS setting code SETTING can be applied to the MRS mode setting section 304. Therefore, the MRS mode setting section 304 performs an operation of determining whether to activate one of the mode enable signals TRR_EN and one of the values of the MRS set code SETTING determination target address TRR_ADDR for controlling entry into the target startup mode. The MRS mode setting section 304 performs an operation of determining whether to activate the operation of the mode enable signal TRR_EN and the value of the determination target address TRR_ADDR in response to the MRS set code SETTING, and performs determination of whether to activate the mode enable signal in response to the mode exit signal TRR_EXIT. One of the TRR_EN operations.

The preset command applied to the mode setting unit 300 means that a single command is preset to control entry into the target startup mode, excluding the general application to the semiconductor memory device. Various commands, such as a read command and a write command. Of course, similar to the various commands generally applied to the semiconductor memory device, such as the read command and the write command, the preset command is applied to the mode setting unit 300 through a path through which the command is input. A preset command is applied to the command mode setting section 302 between the constituent elements of the mode setting unit 300. The command mode setting section 302 performs: determining whether to activate one of the mode enable signals TRR_EN for controlling entry into the target boot mode using a preset command applied from the outside; and determining the target address TRR_ADDR using the MRS set code SETTING One of the values of the operation. That is, the command mode setting section 302 performs an operation of determining whether to activate the mode enable signal TRR_EN in response to a preset command applied from the outside, performs an operation of determining the value of the target address using the MRS set code SETTING, and exits in response to the mode. The signal TRR_EXIT is executed to determine whether or not to initiate one of the mode enable signals TRR_EN.

The address input unit 310 can buffer the address signal ADDR applied from the outside and generate the source address IN_ADDR. For reference, the source address IN_ADDR may include a plurality of bits, and some of the bits of the source address IN_ADDR may be applied to the mode setting unit 300 as the MRS set code SETTING. The determination of the bits of the source address IN_ADDR to be used as certain bits of the MRS set code SETTING can be changed by a designer. The source address IN_ADDR applied to the address input unit 310 can be classified into a target address and a normal according to the value of the target address determined by the mode setting unit 300 at a time point when the entry to the target startup mode is made. Address. That is, after determining the value of the target address by the mode setting unit 300 at the time point when the entry to the target action mode is made, the source address IN_ADDR may correspond to one of the values of the target address and the target bit. The value of the address is not related to one of the addresses.

The memory cell array 370 includes a plurality of word lines WL1, WL2, ... WLK. The respective word lines WL1, WL2, ... WLK can be independently selected based on the value of the source address IN_ADDR. For reference, the memory cell array 370 can include a plurality of banks and a plurality of bank groups. In this situation The source address IN_ADDR may contain information for selecting a library and a library group.

The column control unit 320 may sequentially start and precharge the word line WLL corresponding to the target address TRR_ADDR and the word line WL1, WL2 ... WLK adjacent to the word line WLL corresponding to the target address TRR_ADDR during the target startup mode. N number of word lines (for example, WLL+1 and WLL-1). For reference, the number represented by N can be selected by a designer to be other numbers of natural numbers greater than two. Therefore, the word lines WLL+1 and WLL-1 adjacent to the word line WLL corresponding to the target address TRR_ADDR mean two adjacent word lines WLL+1 adjacent to the word line WLL entity corresponding to the target address TRR_ADDR and WLL-1. In addition, when N is "4", N number of word lines WLL+1 and WLL-1 adjacent to the word line WLL corresponding to the target address TRR_ADDR means adjacent to the word line WLL entity corresponding to the target address TRR_ADDR. The four adjacent word lines WLL+2, WLL+1, WLL-1 and WLL-2 are placed. The adjacent word lines WLL+1 and WLL-1 mean the following word lines: the data adjacent to the word line WLL entity corresponding to the target address TRR_ADDR and in which the memory cells connected to the word lines are subjected to the target word line WLL Repeat the start-precharge operation affected by the word line.

In detail, during the target startup mode, each time an action command ACT_CMD and a target address TRR_ADDR are applied, the column control unit 320 sequentially starts and precharges the target word line WLL' and the word line WL1 corresponding to the target address TRR_ADDR. Among the WL2...WLK, two adjacent word lines WLL+1 and WLL-1 are disposed adjacent to the target word line WLL. That is, when the address having the value of the target address TRR_ADDR in the source address IN_ADDR is input through the address input unit 310, the column control unit 320 not only activates and precharges the target word line WLL but also activates and precharges two adjacent Word lines WLL+1 and WLL-1.

The operation for sequentially starting and precharging the target word line WLL and the two adjacent word lines WLL+1 and WLL-1 may be performed in a predetermined order in response to repeated application of the action command ACT_CMD and the target address TRR_ADDR. For example, the operation can be performed in the following manner For example, in response to the first application of the action command ACT_CMD and the target address TRR_ADDR, the target word line WLL is first activated and precharged, and the adjacent word line WLL is activated and precharged in response to the second application of the action command ACT_CMD and the target address TRR_ADDR. -1, and initiating and pre-charging the adjacent word line WLL+1 in response to the third application of the action command ACT_CMD and the target address TRR_ADDR.

The sequential start and precharge target word line WLL and two adjacent word lines WLL+1 and WLL-1 may be sequentially executed in an automatic decision order after the action command ACT_CMD and the target address TRR_ADDR are applied from the outside for the first time. Operation. For example, the operation may be performed in the following manner: in response to the first application of the action command ACT_CMD and the target address TRR_ADDR, the target word line WLL is first activated and precharged, and is activated and pre-responsive in response to the precharge of the target word line WLL. Charging is adjacent to word line WLL-1 and is initiated and precharged adjacent word line WLL+1 in response to pre-charging of word line WLL-1.

During the target startup mode, the column control unit 320 activates and precharges one of the normal word lines WLNM corresponding to the normal address NM among the precharge word lines WL1, WL2, ... WLK whenever the action command ACT_CMD and the normal address NM are applied. That is, when the address applied through the address input unit 310 during the target startup mode is the normal address NM, the column control unit 320 activates and precharges the normal word line WLNM in addition to the target startup operation.

Whenever the action command ACT_CMD and the source address IN_ADDR are applied after exiting from the target startup mode, the column control unit 320 activates and precharges one of the word lines WL1, WL2, ..., WLK corresponding to the source address IN_ADDR. . That is, after exiting from the target boot mode, the column control unit 320 starts and precharges one of the word lines corresponding to the corresponding source address IN_ADDR regardless of whether the address applied through the address input unit 310 has the target address TRR_ADDR. value.

The mode exit control unit 340 may count the number of startup or start-precharge operations performed by the column control unit 320 during the target startup mode and determine whether to activate the mode exit signal TRR_EXIT. That is, when counting by the column control unit during the target startup mode When the number of startup operations performed by 320 reaches a predetermined number, the mode exit control unit 340 activates the mode exit signal TRR_EXIT, so that the mode setting unit 300 can deactivate the mode enable signal TRR_EN, thereby allowing the semiconductor memory device to self The target startup mode exits.

In detail, the mode exit control unit 340 does not count the number of all boot operations performed by the column control unit 320 during the target boot mode. That is, the mode exit control unit 340 counts only the number of operations initiated by the column control unit 320 and precharges the target word line WLL and the two adjacent word lines WLL+1 and WLL-1 and is not counted by the column control unit 320 and The number of operations to precharge the normal word line WLNM. Although the mode exit control unit 340 specifically counts the number of startup operations of the column control unit 320, when the number of counts reaches 3, the mode exit control unit 340 activates the mode exit signal TRR_EXIT. Since the column control unit 320 sequentially starts and precharges the target word line WLL and the two adjacent word lines WLL+1 and WLL-1, the mode exit control unit 340 detects whether the column control unit 320 has activated and precharged the target word line. The WLL and each of the two adjacent word lines WLL+1 and WLL-1, and determine whether to activate the mode exit signal TRR_EXIT.

The target address latch 330 can store the target address TRR_ADDR during the target boot mode. The target address TRR_ADDR stored in the target address latch 330 is the value of the target address, which is generated by the mode setting unit 300.

The address determining unit 350 may compare the value of the target address TRR_ADDR stored in the target address latch 330 with the value of the source address IN_ADDR during the target startup mode, and determine whether the source address IN_ADDR has the target address TRR_ADDR. value. The operation result exit control unit 340 is controlled by the address determining unit 350 by determining whether the source address IN_ADDR has the value of the target address TRR_ADDR.

The source address latch 380 can store the source address IN_ADDR applied from the address input unit 310. The source address IN_ADDR stored in the source address latch 380 is transferred to the address decision unit 350 and the column control unit 320.

The re-operation control unit 360 may control the column control unit 320 for general re-operation based on the re-new command REF_CMD and the mode enable signal TRR_EN. Depending on the operation or type of semiconductor memory device, it may be possible to use the source address IN_ADDR stored in source address latch 380 as a new address. In this case, if the source address IN_ADDR is not restricted from being used as a new address during the target startup mode, the target startup operation cannot be performed normally. For example, since the general re-operation can be set to have a higher priority than the target startup operation, the source address IN_ADDR stored in the source address latch 380 cannot be used in the target startup operation, but is available In the normal re-operation, the target startup operation cannot be performed normally.

Therefore, the new operation control unit 360 (as a component of the semiconductor memory device required to use the source address IN_ADDR stored in the source address latch 380 as one of the new addresses) can prevent the target from being activated. This general re-operation is performed during the mode. That is, the re-operation control unit 360 can be omitted in the semiconductor memory device without using the source address IN_ADDR stored in the source address latch 380 as one of the new addresses.

4 is a detailed diagram illustrating one of the mode exit control units 340 shown in FIG.

Referring to FIG. 4, the mode exit control unit 340 can include a target address counter 342 and a mode exit signal generator 344.

The target address counter 342 can count the number of times the value of the source address IN_ADDR has the value of the target address TRR_ADDR during the target boot mode. That is, during the period in which the mode enable signal TRR_EN is activated and enters the target start mode, when the output signal ACT_TRR of the address decision unit 350 is activated and it is determined that the source address IN_ADDR applied through the address input unit 310 has the target address When the value of TRR_ADDR is reached, the target address counter 342 performs a counting operation.

When the number of counts by the target address counter 342 reaches 3, the mode exit signal generator 344 can activate the mode exit signal TRR_EXIT. Can be seen, although the target is intended The address counter 342 counts only three times, but one of the count signals CNT_TRR<0:3> to be output from the target address counter 342 is a 4-bit signal. In order not to add a separate decoding circuit between the target address counter 342 and the mode exit control unit 340, the respective bits of the count signals CNT_TRR<0:3> may be sequentially activated one by one. For example, in the initialization operation of the target address counter 342 (which is performed in the target startup operation), one of the initialization bit signals CNT_TRR<0:3> is initialized to the bit CNT_TRR<0>, and the remaining bits CNT_TRR< 1:3> Keep it going. Next, only the first bit CNT_TRR<1> of the count signal CNT_TRR<0:3> is started, and the remaining bits CNT_TRR<0> and CNT_TRR<2:3> designate a de-start state. Next, only the second bit CNT_TRR<2> of the count signal CNT_TRR<0:3> is activated, and the remaining bits CNT_TRR<0:1> and CNT_TRR<3> are marked as a de-start state. Next, only the third bit CNT_TRR<3> of the count signal CNT_TRR<0:3> is activated, and the remaining bits CNT_TRR<0:2> are marked as a de-start state. In response to the activation of the third bit CNT_TRR<3> of the count signal CNT_TRR<0:3>, the start mode exit signal TRR_EXIT causes all bits of the count signal CNT_TRR<0:3> to be deactivated. In this case, the mode exit signal generator 344 may activate the mode exit signal TRR_EXIT only when the last bit CNT_TRR<3> of the count signal CNT_TRR<0:3> is activated.

If a separate decoding circuit is added between the target address counter 342 and the mode exit control unit 340, one of the signals to be output from the target address counter 342 may have a signal of a smaller number of bits.

FIG. 5 is a detailed diagram illustrating one of the address determining units 350 shown in FIG.

Referring to FIG. 5, the address determining unit 350 uses the values of the respective bit <0:15> of the one-to-one comparison source address IN_ADDR and the respective bits of the target address TRR_ADDR stored in the target address latch 330. One of the values of the element <0:15>.

In detail, the address determining unit 350 includes: a plurality of "mutually exclusive OR" gates XOR<0:15>, which are used to store the respective bits <0:15> of the source address IN_ADDR and Each bit <0:15> of the target address TRR_ADDR in the target address latch 330 performs a "mutual exclusion" operation; an "anti-OR" gate NR, which is used for "mutual exclusion" or XOR All the output signals of <0:15> are "reverse OR"; and a "reverse" gate NAND and an inverter INV are used for the period in which only the mode enable signal TRR_EN is activated to a logic high level. The output signal of the "reverse OR" gate NR is output as the output signal ACT_TRR of the address determining unit 350.

Observing the operation of the address determining unit 350, when all the individual bits <0:15> of the source address IN_ADDR and the target bit TRR_ADDR stored in the target address latch 330 are <0:15 > With exactly the same logic value, all output signals of "mutual or "gate XOR<0:15> become logic low and the output signal of "reverse" gate NR becomes a logic high level, correspondingly, address The output signal ACT_TRR of the decision unit 350 is activated to a logic high level. Conversely, when the respective bit <0:15> of the source address IN_ADDR and the target bit <TR:ADDR stored in the target address latch 330 are <0:15>, they are in any one of the bits. The logical values that do not correspond to each other, the signal of at least one of the "mutually exclusive or" gates XOR<0:15> becomes a logic high level and the output signal of the "reverse" gate NR When the logic level is changed to a logic low level, the corresponding output signal ACT_TRR of the address determining unit 350 is deactivated to a logic low level.

FIG. 6 is a detailed diagram illustrating one of the column control units 320 shown in FIG.

Referring to FIG. 6, column control unit 320 can include an address selection section 322 and a column of drive sections 324.

When the value of the source address IN_ADDR corresponds to the value L of the target address TRR_ADDR during the target startup mode, the address selection section 322 can select to have an adjacent value when the value L of the source address IN_ADDR is viewed along both sides. The two select addresses SEL_ADDR (ie, L+1 and L-1).

In detail, the address selection section 322 may perform an operation of selecting one of the addresses only during the target startup mode in which the mode enable signal TRR_EN is initiated.

In another embodiment, the address selection section 322 can directly apply the signal ACT_TRR from the address determination unit 350 and can determine whether the value of the source address IN_ADDR has the value of the target address TRR_ADDR. However, in FIG. 6, the address selection section 322 is applied with the count signal CNT_TRR<0:3> output from the target address counter 342, and it is determined whether the value of the source address IN_ADDR has the value of the target address TRR_ADDR. The value of the source address IN_ADDR is determined to have the value of the target address TRR_ADDR by the counting signal CNT_TRR<0:3> outputted from the target address counter 342 instead of being directly applied to the signal ACT_TRR from the address determining unit 350. It is possible. This is because the count signal CNT_TRR<0:3> output from the target address counter 342 generates a signal in response to the signal ACT_TRR of the address decision unit 350.

Since the address selection section 322 performs an operation of selecting an address only when the value of the source address IN_ADDR has the value of the target address TRR_ADDR (in response to the count signal CNT_TRR<0:3>), the section is selected in the address. The source address IN_ADDR applied at the time point when the operation of selecting the address of 322 is performed has the value L of the target address TRR_ADDR. Therefore, the address selection section 322 can sequentially select two selection addresses L+1 and L-1 having adjacent values when viewed from both sides of the value L of the source address IN_ADDR.

Column drive section 324 can be enabled and precharged in response to active command ACT_CMD corresponding to one of word lines WL1, WL2 ... WLK corresponding to one of source address IN_ADDR. Thus, one of the column drive sections 324 operates substantially, even during the target startup mode in which the address selection section 322 operates, in response to the action command ACT_CMD, the start and precharge correspond to values that do not have the target address TRR_ADDR. One of the source address IN_ADDR (ie, the normal word line WLNM), which is.

When the source address IN_ADDR having the value of the target address TRR_ADDR and the action command ACT_CMD are applied together during the target startup mode, the column drive section 324 not only activates and precharges the target word line WLL, but also starts and precharges two Adjacent to word lines WLL+1 and WLL-1, which correspond to two selected addresses selected by address selection section 322 L+1 and L-1.

In detail, column drive section 324 can initiate and precharge two adjacent word lines WLL+1 and WLL-1 during the target startup mode by using the following method: initiating and precharging it in response to the action command ACT_CMD. One method or one of the methods of starting and precharging it regardless of the action command ACT_CMD.

First, whenever the source address IN_ADDR having the value of the target address TRR_ADDR is applied together with the active command ACT_CMD, the column driving section 324 can start and precharge the target word line WLL and two adjacent word lines by using sequentially. One of the WLL+1 and WLL-1 methods initiates and precharges the target word line WLL and two adjacent word lines WLL+1 and WLL-1 during the target startup mode. For example, when the source address IN_ADDR having the value of the target address TRR_ADDR is applied for the first time together with the active command ACT_CMD, the column driving section 324 starts and precharges the target word line WLL. When column drive section 324 performs an operation to initiate and precharge target word line WLL, address selection section 322 selects two select addresses L+1 and L-1 based on the value L of source address IN_ADDR. When the source address IN_ADDR having the value of the target address TRR_ADDR is applied a second time together with the action command ACT_CMD after the target word line WLL is precharged, the column drive section 324 is activated and precharged corresponding to being selected by the address. Section 322 selects two of the address lines L+1 or L-1 between any of the addresses L+1 and L-1, or the word line WLL+1 or WLL-1. When the source address IN_ADDR having the value of the target address TRR_ADDR is applied immediately after the word line is precharged, the column drive section 324 is activated and precharged corresponding to being selected by the address. Section 322 selects the word line WLL+1 or WLL-1 between the two selected addresses L+1 and L-1 that have not been used in the start and precharge operations. In this method, the source unrelated to the value of the target address TRR_ADDR in the state in which the start and precharge of the two selected addresses L+1 and L-1 selected by the address selection section 322 are not completed is not completed. When the address IN_ADDR is applied together with the action command ACT_CMD, the instant start and precharge correspond to the source address IN_ADDR which is unrelated to the value of the target address TRR_ADDR. The normal word line WLNM can be possible.

Second, the column driving section 324 can be started by using and starting the pre-charging target word line WLL by using the source address IN_ADDR having the value of the target address TRR_ADDR together with the active command ACT_CMD. The method of sequentially starting and pre-charging two adjacent word lines WLL+1 and WLL-1, regardless of the action command ACT_CMD, starting and pre-charging the target word line WLL and two adjacent word lines WLL+1 during the target startup mode and WLL-1. For example, when the source address IN_ADDR having the value of the target address TRR_ADDR is applied for the first time together with the active command ACT_CMD, the column driving section 324 starts and precharges the target word line WLL. When column drive section 324 performs an operation to initiate and precharge target word line WLL, address selection section 322 selects two select addresses L+1 and L-1 based on the value L of source address IN_ADDR. Next, when the target word line WLL is precharged, the column drive section 324 is enabled and precharged to correspond to any one of the two selected addresses L+1 and L-1 selected by the address selection section 322. The word line L+1 or L-1 is WLL+1 or WLL-1. The column drive section 324 is continuously enabled and precharged to correspond to the two selected addresses L+1 and L-1 selected by the address selection section 322, immediately after the word line is precharged. The word line WLL+1 or WLL-1 of the address that has not been used in the startup and precharge operations. In this method, the source address IN_ADDR may not be in the middle of the state in which the start and precharge of the two selected addresses L+1 and L-1 selected by the address selection section 322 are not completed together with the action command ACT_CMD. Apply. That is, after entering the target startup mode, sufficient time to start and precharge the target word line WLL and all of the two adjacent word lines WLL+1 and WLL-1 should be continuously ensured.

In a semiconductor memory device in accordance with an embodiment of the present invention, a method for selecting one of word lines WL1, WL2, ... WLK using a target address TRR_ADDR is set forth. However, if the memory cell array 370 includes a plurality of banks and a plurality of bank groups, one of the methods for selecting one of the banks using the target address TRR_ADDR may be used. For example, it can be used by comparing the source address IN_ADDR The library selection information and the target address TRR_ADDR containing only the library selection information are used to select one of the target libraries. This is because when one of the banks in the access library has a high frequency, the probability that a target word line exists in the library becomes high. Therefore, even when a selection of any one of the banks having a high access frequency can be made, it may be possible to select a target word line having a large number of starts (or a high start frequency).

Figure 7 is a block diagram illustrating a memory system in accordance with an embodiment of the present invention.

Referring to FIG. 7, the memory system includes a semiconductor memory device 80 and a memory controller 70. The memory controller 70 can include a bit address detecting unit 710, a command generating unit 730, and an address generating unit 750. The semiconductor memory device 80 can include a memory cell array 870, a mode setting unit 800, an address input unit 810, a column control unit 820, a target address latch 830, a mode exit control unit 840, and a bit. The address determining unit 850, the new operating control unit 860 and a source address latch 880. The mode setting unit 800 includes a command mode setting section 802 and/or an MRS mode setting section 804.

For reference, although not shown in detail in FIG. 7, as shown in FIG. 3, memory cell array 870 includes a plurality of word lines WL1, WL2, ... WLK. Word lines WL1, WL2, ... WLK may be selected based on the value of a source address IN_ADDR, respectively. Additionally, memory cell array 870 can include a plurality of banks and a plurality of bank groups. In this case, the source address IN_ADDR may contain information for selecting a library and a library group.

The memory controller 70 can generate a command signal CMD and an address signal ADDR to control operation for activating and precharging the respective word lines WL1, WL2, ... WLK included in the semiconductor memory device 80. In detail, the memory controller 70 generates an MRS set code SETTING or a target start command TRR_CMD, and transmits the MRS set code SETTING or the target start command TRR_CMD to the semiconductor memory device 80 for entering a target startup mode. Acting and pre-charging commands, and the effects and pre-charging The command is transmitted to the semiconductor memory device 80 for performing a start-up or start-precharge operation, and the transfer source address IN_ADDR is used to select the word lines WL1, WL2, ... WLK, respectively. The source address IN_ADDR transmitted by the memory controller 70 to the semiconductor memory device 80 can be classified as its startup or start-precharge history, which satisfies one of the predetermined conditions, the target address TRR_ADDR, and its startup (or start-precharge) The history does not satisfy one of the predetermined conditions, the normal address NM. The source address IN_ADDR can be transferred to the semiconductor memory device 80 in the same manner regardless of whether the source address IN_ADDR is classified as the target address TRR_ADDR or the normal address NM. In this case, information about the value of the source address IN_ADDR classified as the target address TRR_ADDR is transmitted to the semiconductor memory device 80. The MRS setting code SETTING means a signal for setting a mode register group (MRS) of the semiconductor memory device 80, and is usually transmitted through one of its transmission source addresses IN_ADDR. Unlike the illustration of FIG. 7, a separate path for transmitting the MRS set code SETTING may be added between the memory controller 70 and the semiconductor memory device 80. The MRS setting code SETTING for setting the mode register group may contain information about the value of the source address IN_ADDR classified as the target address TRR_ADDR. That is, information about the value of the source address IN_ADDR classified as the target address TRR_ADDR is transmitted to the semiconductor memory device at a time point different from one of the time points at which the general source address IN_ADD is transmitted. 80.

Among the constituent elements of the memory controller 70, when the number of times the source address IN_ADDR is transmitted to the semiconductor memory device 80 together with the active command ACT_CMD is at least one reference number, the address detecting unit 710 can be based on a signal DET. The source address IN_ADDR is detected as the target address TRR_ADDR, and when the number of times the source address IN_ADDR is transmitted to the semiconductor memory device 80 together with the action command ACT_CMD is less than the reference number, the source address IN_ADDR is determined according to a signal DET. Detected as the normal address NM. The detection information DET about the source address IN_ADDR detected by the address detecting unit 710 is transmitted to the command generating unit 730 and the address generating unit 750 to affect the command generating unit 730 and the address generation The operation of unit 750.

The command generating unit 730 may generate not only the action command ACT_CMD and a precharge command PRE_CMD, but also generate a target start command TRR_CMD based on the output signal DET of the address detecting unit 710. The command generating unit 730 generates not only the action command ACT_CMD and the precharge command PRE_CMD for controlling the start-precharge operation of the semiconductor memory device 80, but also generates the target start command TRR_CMD for controlling to the result of the address detection unit 710. Entry in the target startup mode. For reference, the action command ACT_CMD and the precharge command PRE_CMD are generated by being bundled, for example, in a group. The precharge command PRE_CMD is automatically generated when a predetermined time elapses after the generation of the action command ACT_CMD. That is, control is performed in such a manner that pre-charging is started when a predetermined time elapses after any one of the word lines WL1, WL2, ... WLK included in the semiconductor memory device 80 is activated. Word line.

The address generating unit 750 can generate not only the source address IN_ADDR but also the MRS setting code SETTING based on the output signal DET of the address detecting unit 710. That is, the address generation unit 750 not only generates the source address IN_ADDR for selecting the respective word lines WL1, WL2, ... WLK included in the semiconductor memory device 80, but also based on the result of the address detection unit 710 DET. The MRS setting code SETTING is generated for controlling entry into the target startup mode. The source address IN_ADDR is typically generated at a time when the action command ACT_CMD is generated. The source address IN_ADDR is transmitted to the semiconductor memory device 80 along with the action command ACT_CMD. The MRS set code SETTING is generated at an independent time, which can be set by a designer regardless of the time at which the action command ACT_CMD is generated.

The semiconductor memory device 80 can enter the target startup mode in response to the MRS setting code SETTING or the target startup command TRR_CMD applied from the memory controller 70, sequentially starting and pre-charging a target word line WLL and two during the target startup mode. Adjacent to the word lines WLL+1 and WLL-1, and retired from the target startup mode by counting the number of startup operations Out.

In the semiconductor memory device 80, the mode setting unit 800 can set the semiconductor memory device 80 to enter the target startup mode in response to the MRS setting code SETTING or the target enable command TRR_CMD, and set the semiconductor in response to a mode exit signal TRR_EXIT. The memory device 80 is caused to exit from the target startup mode. The mode setting unit 800 sets the value of the target address TRR_ADDR.

In detail, the mode setting unit 800 activates a mode enable signal TRR_EN in response to the MRS set code SETTING or the target start command TRR_CMD to cause the semiconductor memory device 80 to enter the target boot mode. The mode setting unit 800 causes the semiconductor memory device 80 to exit from the target startup mode by initiating the mode enable signal TRR_EN in response to activation of the mode exit signal TRR_EXIT. Further, the mode setting unit 800 sets the value of the target address TRR_ADDR by inputting a signal selected to represent one of the values of the target address TRR_ADDR. For example, the mode setting unit 800 determines the value of the target address TRR_ADDR by being input to a partial setting code SETTING of the source address IN_ADDR applied from the memory controller 70 through the address input unit 810.

That is, the mode enable signal TRR_EN maintains an active state during the target startup mode. In contrast, the mode enable signal TRR_EN maintains a de-start state after exiting from the target boot mode. The general operation of the semiconductor memory device 80 can be performed even when entering the target startup mode. That is, the general operation of the semiconductor memory device 80, such as data reading/writing, can be performed without limitation even when entering the target startup mode. This is because when the source address IN_ADDR applied through the address input unit 810 does not have the value of the target address TRR_ADDR during the target startup mode, the column control unit 820 cannot perform the target startup operation.

The mode setting unit 800 includes a command mode setting section 802 and/or an MRS mode setting section 804. That is, the mode setting unit 800 may include only the command mode setting section 802, may only include the MRS mode setting section 804, or may include the command mode setting section 802 and The MRS mode sets both sections 804. The command mode setting section 802 causes the semiconductor memory device 80 to enter the target boot mode/exit from the target boot mode in response to the target boot command TRR_CMD. The MRS mode setting section 804 causes the semiconductor memory device 80 to enter or exit from the target startup mode in response to the MRS setting code SETTING.

The MRS mode setting section 804 performs an operation of determining whether to activate one of the mode enable signals TRR_EN and one of the values of the target address TRR_ADDR using the MRS set code SETTING for controlling entry into the target start mode, the MRS set code SETTING Corresponding to some of the bits of the source address IN_ADDR applied through the address input unit 810. The MRS mode setting section 804 performs an operation of determining whether to activate the operation of the mode enable signal TRR_EN and determining the value of the target address TRR_ADDR in response to the MRS set code SETTING of the source address IN_ADDR applied by the address input unit 810, and responds to The mode exit signal TRR_EXIT is executed to determine whether or not to initiate one of the mode enable signals TRR_EN.

The command mode setting section 802 performs: determining whether to activate one of the mode enable signals TRR_EN for controlling the entry into the target start mode using the target start command TRR_CMD applied from the memory controller 70; and determining using the MRS set code SETTING One of the values of the target address TRR_ADDR operates. That is, the command mode setting section 802 performs an operation of determining whether to activate the mode enable signal TRR_EN in response to the target start command TRR_CMD, performs an operation of determining the value of the target address TRR_ADDR using the MRS set code SETTING, and responds to the mode exit signal TRR_EXIT And the execution determines whether to activate one of the mode enable signals TRR_EN.

The address input unit 810 can buffer the address signal ADDR applied from the memory controller 70 and generate the source address IN_ADDR. For reference, the source address IN_ADDR may include a plurality of bits, and some of the bits of the source address IN_ADDR may be applied to the mode setting unit 800 as the MRS set code SETTING. The determination of some bits of the source address IN_ADDR to be used as the MRS setting code SETTING can be changed by a designer. change.

Column control unit 820 can sequentially initiate and precharge target word line WLL and two adjacent word lines WLL+1 and WLL-1 during the target startup mode.

In detail, during the target startup mode, each time the action command ACT_CMD and the target address TRR_ADDR are applied, the column control unit 820 sequentially starts and precharges the target word line WLL and two adjacent word lines WLL+1 and WLL-. 1. When the address having the value of the target address TRR_ADDR in the source address IN_ADDR is input through the address input unit 810, the column control unit 820 not only sequentially activates and precharges the target word line WLL but also activates and precharges two adjacent words. Lines WLL+1 and WLL-1.

In response to the repeated application of the action command ACT_CMD and the target address TRR_ADDR from the memory controller 70, the target word line WLL and the two adjacent word lines WLL+1 and WLL- are sequentially activated and precharged in a predetermined order. 1 operation. For example, the operation may be performed in the following manner: in response to the first application of the action command ACT_CMD and the target address TRR_ADDR, the target word line WLL is first activated and precharged, in response to the action command ACT_CMD and the second address of the target address TRR_ADDR. The adjacent word line WLL-1 is activated and precharged, and the adjacent word line WLL+1 is activated and precharged in response to a third application of the active command ACT_CMD and the target address TRR_ADDR.

The target word line WLL and the two adjacent word lines WLL+1 for sequentially starting and precharging may be performed in an automatic decision order after the action command ACT_CMD and the target address TRR_ADDR are first applied from the memory controller 70. And the operation of WLL-1. For example, the operation may be performed in the following manner: in response to the first application of the action command ACT_CMD and the target address TRR_ADDR, the target word line WLL is first activated and precharged, and is activated and pre-responsive in response to the precharge of the target word line WLL. Charging is adjacent to word line WLL-1 and is initiated and precharged adjacent word line WLL+1 in response to pre-charging of word line WLL-1.

During the target startup mode, the column control unit 820 activates and precharges the word lines WL1, WL2, ... WLK each time the action command ACT_CMD and the normal address NM are applied. A normal word line WLNM. When the address applied through the address input unit 810 during the target startup mode is the normal address NM, the column control unit 820 starts and precharges the normal word line WLNM. The target initiates the operation.

The column control unit 820 activates and precharges one of the word lines WL1, WL2, ... WLK corresponding to one of the source address IN_ADDR whenever the action command ACT_CMD and the source address IN_ADDR are applied after exiting from the target startup mode. After exiting from the target boot mode, the column control unit 820 starts and precharges one of the word lines corresponding to the corresponding source address IN_ADDR regardless of whether the address applied through the address input unit 810 has the value of the target address TRR_ADDR.

The mode exit control unit 840 may count the number of startup (or start-precharge) operations performed by the column control unit 820 during the target startup mode and determine whether to activate the mode exit signal TRR_EXIT. That is, when one of the number of start operations performed by the column control unit 820 is counted up to a predetermined number during the target start mode, the mode exit control unit 840 activates the mode exit control unit 840 such that the mode setting unit The 800 can be enabled to activate the mode enable signal TRR_EN, thereby allowing the semiconductor memory device 80 to exit from the target boot mode.

In detail, the mode exit control unit 840 does not count the number of all boot operations performed by the column control unit 820 during the target boot mode. That is, the mode exit control unit 840 counts only the number of operations initiated by the column control unit 820 and precharges the target word line WLL and the two adjacent word lines WLL+1 and WLL-1 and is not counted by the column control unit 820 and The number of operations to precharge the normal word line WLNM. Although the mode exit control unit 840 specifically counts the number of startup operations of the column control unit 820, when the number of counts reaches 3, the mode exit control unit 840 activates the mode exit signal TRR_EXIT. Since the column control unit 820 sequentially starts and precharges the target word line WLL and the two adjacent word lines WLL+1 and WLL-1, the mode exit control unit 840 detects whether the column control unit 820 has started and precharges the target word line. WLL and each of two adjacent word lines WLL+1 and WLL-1 And determine whether to activate the mode exit signal TRR_EXIT.

The target address latch 830 can store the target address TRR_ADDR during the target boot mode. The target address TRR_ADDR stored in the target address latch 830 is the value of the target address, which is generated by the mode setting unit 800.

The address determining unit 850 can compare the value of the target address TRR_ADDR stored in the target address latch 830 with the value of the source address IN_ADDR during the target startup mode, and determine whether the source address IN_ADDR has the target address TRR_ADDR. value. The operation result ACT_TRR can control the operation of the mode exit control unit 840 by determining whether the source address IN_ADDR has the value of the target address TRR_ADDR.

The source address latch 880 can store the source address IN_ADDR applied through the address input unit 810. The source address IN_ADDR stored in the source address latch 880 is transferred to the address decision unit 850 and the column control unit 820.

The re-operation control unit 860 can control the column control unit 820 for general re-operation based on a new command REF_CMD and a mode enable signal TRR_EN. Depending on the operation or type of semiconductor memory device 80, it may be possible to use the source address IN_ADDR stored in source address latch 880 as a new address. In this case, if the source address IN_ADDR is not restricted from being used as a new address during the target startup mode, the target startup operation cannot be performed normally. For example, since the general re-operation can be set to have a higher priority than the target startup operation, the source address IN_ADDR stored in the source address latch 880 cannot be used in the target startup operation, but is available In the normal re-operation, and therefore the target startup operation cannot be performed normally.

Therefore, the new operation control unit 860 (as one of the components required in the semiconductor memory device using one of the source address IN_ADDR stored in the source address latch 880 as a new address) can prevent the target from being activated. This general re-operation is performed during the mode. That is, the re-operation control unit 860 can be omitted in the semiconductor memory device without using the source address IN_ADDR stored in the source address latch 880 as one of the new addresses.

Figure 8 is a timing diagram illustrating a semiconductor memory device in accordance with one embodiment of the present invention.

Referring to FIG. 8, when the signal TRR_EN is enabled in a logic high level by the MRS setting or the preset command, the semiconductor memory device enters the target startup mode. When the target startup mode is entered, the initialization bit CNT_TRR<0> of the count signal CNT_TRR<0:3> output from the target address counter 342 is started at a logic high level.

After entering the target startup mode, whenever the source address IN_ADDR applied with the action command ACT_CMD has the value L of the target address TRR_ADDR, the output of the address determination units 350 and 850 is started from a logic low level by a logic high level. Signal ACT_TRR. When the output signals ACT_TRR of the address determining units 350 and 850 are activated to the logic high level, the first bit CNT_TRR<1> of the count signal CNT_TRR<0:3> output from the target address counter 342, and the second bit CNT_TRR <2> and the third bit CNT_TRR<3> are sequentially activated. When the first bit CNT_TRR<1>, the second bit CNT_TRR<2>, and the third bit CNT_TRR<3> of the count signal CNT_TRR<0:3> are sequentially activated, the target word line WLL and two adjacent The word lines WLL+1 and WLL-1 are sequentially activated and precharged.

In detail, since the source address IN_ADDR has the value L of the target address TRR_ADDR when a first action command 1ST ACT_CMD is applied, the target word line WLL is activated and precharged. During a period in which the target word line WLL is activated and precharged, the address selection section 322 selects two of the selected addresses SEL_ADDR (ie, L+1 and L-1) adjacent to the value L of the target address TRR_ADDR. One of the addresses L+1. In response to the source address IN_ADDR having the value L of the target address TRR_ADDR when the first action command 1ST ACT_CMD is applied, the output signals ACT_TRR of the address determining units 350 and 850 are correspondingly started from the logic low level to the logic high level, from the target The initialization bit CNT_TRR<0> of the count signal CNT_TRR<0:3> output by the address counter 342 is started with a logic low level and the first bit CNT_TRR<1> of the count signal CNT_TRR<0:3> is a logic high The level starts. The output signal ACT_TRR of the address determining units 350 and 850 that are activated to the logic high level is turned to the logic low level at the time point when the input of the first active command 1ST ACT_CMD ends.

Since the source address IN_ADDR has the value L of the target address TRR_ADDR when a second action command 2ND ACT_CMD is applied, corresponding to the address when starting and precharging the target address TRR_ADDR in response to the first action command 1ST ACT_CMD The adjacent word line WLL+1 of the selected address L+1 of the selected section 322 is enabled and precharged. During a period in which the first adjacent word line WLL+1 adjacent to the target word line WLL is activated and precharged, the address selection section 322 selects two selected addresses L+ adjacent to the value L of the target address TRR_ADDR. The remaining one of L1 and L-1 is not selected. In response to the source address IN_ADDR having the value L of the target address TRR_ADDR when the second action command 2ND ACT_CMD is applied, the output signals ACT_TRR of the address determining units 350 and 850 are correspondingly started from the logic low level to the logic high level, from the target The first bit CNT_TRR<1> of the count signal CNT_TRR<0:3> output by the address counter 342 is started with a logic low level and the second bit CNT_TRR<2> of the count signal CNT_TRR<0:3> is one. The logic high level starts. The output signal ACT_TRR of the address determining units 350 and 850 that are activated to the logic high level is turned to the logic low level at the time point when the input of the second active command 2ND ACT_CMD ends.

Since the source address IN_ADDR has the value L of the target address TRR_ADDR when a third action command 3RD ACT_CMD is applied, corresponding to the activation and pre-charging adjacent to the target address TRR_ADDR when responding to the second action command 2ND ACT_CMD The adjacent word line WLL-1 of the address L-1 selected by the address selection section 322 is activated and precharged adjacent to the word line WLL+1. During a period in which the second adjacent word line WLL-1 adjacent to the target word line WLL is activated and precharged, the address selection section 322 selects two selected addresses L+ adjacent to the value L of the target address TRR_ADDR. The remaining one of L1 and L-1 is not selected. For reference, although the address L+1 selected by the address selection section 322 can be seen. Corresponding to the address L+1, it has been selected in response to the first active command 1ST ACT_CMD target word line WLL being activated and precharged, but this occurs because of the address that can be selected by the address selection section 322. The number is only 2 and therefore there is no extra address to choose from. In this case, the selected location does not have a substantial meaning because it is not used to initiate and precharge a word line after exiting from the target boot mode. In response to the third address command 3RD ACT_CMD being applied, the source address IN_ADDR has the value L of the target address TRR_ADDR, and the output signals ACT_TRR of the address determining units 350 and 850 are correspondingly started from the logic low level to the logic high level, from the target. The second bit CNT_TRR<2> of the count signal CNT_TRR<0:3> output by the address counter 342 is started with a logic low level and the third bit CNT_TRR<3> of the count signal CNT_TRR<0:3> is one. The logic high level starts.

Since the third bit CNT_TRR<3> of the count signal CNT_TRR<0:3> outputted from the target address counter 342 to the logic high level starts to activate the mode exit signal TRR_EXIT, the mode enable signal TRR_EN is correspondingly started. To the logic low level, and the semiconductor device exits from the target startup mode.

Although the source address IN_ADDR has the value L of the target address TRR_ADDR when a fourth action command 4THACT_CMD is applied, since the mode enable signal TRR_EN is started to the logic low level to exit from the target startup mode, since the source address IN_ADDR has The value L of the target address TRR_ADDR does not perform an additional operation except that the start and precharge correspond to one of the source address IN_ADDR word lines WL.

According to the embodiments set forth above, it may be possible to reconnect to a memory cell adjacent to a word line having a large number of start times (or a high start frequency) word line, thereby substantially preventing the The data of the memory cells is degraded due to word line interference.

Moreover, in accordance with the embodiments, a memory cell that is reconnected to a word line adjacent to a word line having a large number of start times (or a high start frequency) without being applied to a separate address may be Possible, thereby shortening the prevention of the data of the memory cells due to word lines One of the time required to disrupt and degrade.

While the invention has been described with respect to the embodiments of the present invention, it is understood that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.

For example, the locations and types of logic gates and transistors illustrated in the embodiments set forth above should be implemented differently depending on the polarity of the signals input thereto.

300‧‧‧Mode setting unit

302‧‧‧Command mode setting section

304‧‧‧Mode register group mode setting section

310‧‧‧ address input unit

320‧‧‧ column control unit

330‧‧‧Target Address Latch

340‧‧‧ mode exit control unit

350‧‧‧ Address Determination Unit

360‧‧‧New operation control unit

370‧‧‧ memory cell array

380‧‧‧Source Address Latch

ACT_CMD‧‧‧ action order

ACT_TRR‧‧‧ Results / Output Signal / Signal

ADDR‧‧‧ address signal

CMD‧‧‧ Command Signal/Command

CNT_TRR<0:3>‧‧‧Counting signal

IN_ADDR‧‧‧ source address

REF_CMD‧‧‧ new order

TRR_ADDR‧‧‧target address

TRR_EN‧‧‧ mode enable signal

TRR_EXIT‧‧‧ mode exit signal

WL1‧‧‧ word line

WL2‧‧‧ word line

WLK‧‧‧ word line

WLL‧‧‧Frequently activated word line/word line/target word line

WLL+1‧‧‧adjacent word line/word line

WLL-1‧‧‧ adjacent word line/word line

WLNM‧‧‧ normal word line

Claims (21)

A semiconductor memory device comprising: a plurality of word lines, each of which is connected to a plurality of memory cells; a column of control units adapted to sequentially activate and precharge corresponding to a target bit during a target startup mode a word line and a predetermined (N) number of adjacent word lines; and a mode exit control unit adapted to count the number of start operations performed by the column control unit during the target start mode to determine whether the target is from the target The boot mode exits, wherein the source address for selecting one of the word lines is classified as a target address and a normal address, and the start-precharge history of the target address satisfies a predetermined condition, the normal address The start-precharge history does not satisfy the predetermined condition. The semiconductor memory device of claim 1, wherein the semiconductor memory device enters the target startup mode by a mode register set (MRS) setting or a preset command. The semiconductor memory device of claim 1, wherein the source address for selecting the word lines corresponds to the target address during the target mode of operation and corresponds to the normal address when entering the target mode of operation. The semiconductor memory device of claim 3, wherein, during the target startup mode, when the target address is applied together with an action command, the column control unit sequentially activates and precharges the target word line and the number of N An adjacent word line, wherein during the target startup mode, when the normal address is applied together with the action command, the column control unit starts and precharges a word line corresponding to the normal address, and wherein After the target startup mode exits, when the source address is applied together with the action command, the column control unit starts and precharges corresponding to the source address. One word line. The semiconductor memory device of claim 4, wherein during the target startup mode, the mode exit control unit counts a number of start operations of the target word line and the N number of adjacent word lines by the column control unit, and The number of start operations of the word line corresponding to the normal address by the column control unit is not counted, and when the number of counts reaches N+1, the semiconductor memory device is caused to exit from the target boot mode. The semiconductor memory device of claim 3, further comprising: an address input unit adapted to receive the source address, the source address being externally applied; a target address latch adapted to the target Storing the target address during the startup mode; and an address determination unit adapted to determine whether a value of the source address applied to the address input unit during the target startup mode corresponds to a value of the target address . The semiconductor memory device of claim 6, wherein the mode exit control unit comprises: a target address counter adapted to count the value of the source address based on an operation of the address determining unit during the target startup mode a number of times corresponding to the value of the target address; and a mode exit signal output section adapted to initiate a mode exit signal when the number of counts of one of the target address counters reaches N+1. The semiconductor memory device of claim 6, wherein the column control unit comprises: an address selection section adapted to determine, during the target startup mode, that the value of the source address corresponds to the target The value of the address is sequentially selected by having N number of addresses adjacent to the value of the target address; and a column of driving segments adapted to sequentially initiate and precharge word lines corresponding to the target address and the N number of addresses selected by the address selection segment during the target startup mode in response to the action command . The semiconductor memory device of claim 8, wherein during the target startup mode, when the source address first applied with the action command has the value of the target address, the address selection segment selection The N number of addresses, and the column driving section starts and precharges the word line corresponding to the target address, and wherein after the word line corresponding to the target address is activated and precharged, When the source address applied with the action command has the value of the target address, the column drive segment is sequentially activated and precharged corresponding to the N number of addresses selected by the address selection segment. The word lines. The semiconductor memory device of claim 6, further comprising: a source address latch adapted to store the source address applied from the address input unit; and a new operation control unit adapted to be stored in the source In the case where one of the source address latches is used as one of the re-new addresses in the general re-operation, the general re-operation is prevented from being performed during the target startup mode. The semiconductor memory device of claim 8, wherein the address selection section selects at least two addresses corresponding to at least two adjacent word lines as the N number of addresses, the at least two adjacent word lines are adjacent to each other Placed on two sides of the word line corresponding to the target address. A memory system includes: a memory controller adapted to transmit a mode register set (MRS) setting signal or a target start command for entering a target startup mode for performing startup and pre- The role of charging operation and pre-charge commands, as well as for selecting word lines a source address, wherein the source address is classified as a target address of a start-precharge history satisfying a predetermined condition, and a start-precharge history does not satisfy one of the predetermined conditions; and a semiconductor a memory device adapted to enter the target startup mode in response to the MRS setting signal or the target startup command, sequentially initiating and pre-charging corresponding to a target word line and a predetermined one of the target addresses during the target startup mode ( N) a number of adjacent word lines, and exiting from the target boot mode by counting the number of boot operations, wherein the memory controller includes: an address detection unit adapted to be at the source address and a function command When the number of times transmitted to the semiconductor memory device is at least one reference number, the source address is detected as the target address, and the source address is transmitted to the semiconductor memory device together with the action command When the number of times is less than the reference number, the source address is detected as the normal address; a command generating unit is adapted to generate the role and precharge command, and based on the address One unit outputs the target signal to generate a start command; and an address generation unit adapted to generate the source addresses, and based on the output signal of the address detecting means to generate the set signal MRS. The memory system of claim 12, wherein the semiconductor memory device comprises: a column of control units adapted to sequentially activate and precharge the word line and the N number corresponding to the target address during the target startup mode Adjacent to the word line; and a mode exit control unit adapted to count the number of startup operations performed by the column control unit during the target startup mode to determine whether to exit from the target startup mode. The memory system of claim 13, wherein during the target startup mode, when the target address is applied together with the action command, the column control unit sequentially starts and precharges the target word line and the N a plurality of adjacent word lines, wherein during the target startup mode, when the normal address is applied with the action command, the column control unit starts and precharges a word line corresponding to the normal address, and wherein After the target boot mode exits, when the source address is applied with the action command, the column control unit initiates and precharges a word line corresponding to the source address. The memory system of claim 14, wherein during the target startup mode, the mode exit control unit counts the number of start operations of the target word line and the N number of adjacent word lines by the column control unit, and Counting the number of start operations of the word line corresponding to the normal address by the column control unit, and causing the semiconductor memory device to exit from the target boot mode when the count number reaches N+1. The memory system of claim 13, wherein the semiconductor memory device further comprises: an address input unit adapted to receive the source address, the source address is transmitted from the memory controller; a target address lock a register adapted to store the target address during the target startup mode; and an address determination unit adapted to determine whether a value of the source address applied to the address input unit during the target startup mode corresponds to One of the values of the target address. The memory system of claim 16, wherein the mode exit control unit comprises: a target address counter adapted to count the value of the source address based on an operation of the address determining unit during the target startup mode. The number of times the value is at the target address; and A mode exit operation section adapted to cause the semiconductor memory device to exit from the target startup mode when the number of counts of one of the target address counters reaches N+1. The memory system of claim 16, wherein the column control unit comprises: an address selection section adapted to determine, during the target startup mode, the value of the source address corresponding to the address determination unit At the value of the target address, N number of addresses having adjacent values of the value of the target address are sequentially selected; and a column of driving segments adapted to respond to the action command during the target startup mode The sequence start and precharge correspond to the target address and the word line of the N number of addresses selected by the address selection section. The memory system of claim 18, wherein, during the target startup mode, when the source address first applied with the action command has the value of the target address, the address selection section selects the N number of addresses, and the column driving section starts and precharges the word line corresponding to the target address, and wherein after the word line corresponding to the target address is activated and precharged, When the source command is applied with the source address having the value of the target address, the column driving section is sequentially activated and precharged corresponding to the N number of addresses selected by the address selection section. The word lines. The memory system of claim 16, wherein the semiconductor memory device further comprises: a source address latch adapted to store the source address applied from the address input unit; and a new operation control unit It is suitable to prevent the normal re-operation from being performed during the target startup mode in the case where one of the addresses stored in the source address latch is used as one of the re-new addresses in the general re-operation. The memory system of claim 18, wherein the address selection section selects at least two addresses corresponding to at least two adjacent word lines as the N number of addresses, the at least two adjacent word lines are adjacent to each other. On both sides of the word line corresponding to the target address.