TWI698509B - Method for producing silicon carbide wafer - Google Patents

Abstract

A method for producing a silicon carbide wafer includes: providing a silicon carbide wafer having an unpolished surface; in which the unpolished surface has a first surface and a second surface; polishing one surface of the first surface and the second surface of the unpolished surface with a polisher in a first polishing solution; in which the polisher includes a polishing pad and a plurality of abrasive particles fixed to the polishing pad; and polishing another surface of the first surface and the second surface of the unpolished surface with the polisher in a second polishing solution; in which the pH value of the first polishing solution is not more than 7, and the pH value of the second polishing solution is not less than 7.

Description

Method for manufacturing silicon carbide wafer

The invention relates to a semiconductor wafer and a manufacturing method thereof, in particular to a silicon carbide wafer and a manufacturing method thereof.

As a wide band gap semiconductor, silicon carbide wafer has the characteristics of high thermal conductivity and high saturation electron drift rate. With the increasing demand for high-speed and high-frequency radio technology, wide band gap semiconductors have attracted more and more attention. Such semiconductor devices can meet many advantages that ordinary silicon-based semiconductors cannot satisfy, such as being able to operate at higher power levels and more Work under high temperature and harsher environment. In fact, metal semiconductor field effect transistors and metal oxide semiconductor field effect transistors manufactured on this basis have all been realized. Therefore, it is more and more important to obtain high-quality silicon carbide wafers (silicon carbide substrates). The high quality mentioned here not only refers to the quality of the silicon carbide wafer itself, but more importantly refers to the high quality (low defect rate) and excellent flatness parameters of the silicon carbide wafer surface. This is not only a requirement for device preparation, but also a requirement for epitaxial thin films. In fact, the epitaxial film has a strong dependence on the wafer (substrate). When the surface of the wafer fluctuates greatly, it will seriously affect the quality of the epitaxial film. The grown epitaxial layer will also be affected by wafer surface defects and flatness. All defects on the wafer will be transferred to the new epitaxial layer. Such defects not only cause leakage, but also significantly reduce electron mobility.

Therefore, the inventor believes that the above-mentioned shortcomings can be improved, and with great concentration of research and the application of scientific principles, we finally propose an invention with reasonable design and effective improvement of the above-mentioned shortcomings.

The embodiment of the present invention provides a silicon carbide wafer and a manufacturing method thereof, which can effectively improve the defects and poor flatness that may occur on the surface of the silicon carbide wafer in the prior art.

The embodiment of the present invention discloses a method for manufacturing a silicon carbide wafer, which includes: providing a silicon carbide wafer having a surface to be polished; wherein the surface to be polished has a first surface and a second surface; In a first polishing solution, polishing one of the first surface and the second surface of the surface to be polished; wherein the polisher includes a polishing pad and is fixed to the polishing pad And using the polisher in a second polishing solution to polish the other of the first surface and the second surface of the surface to be polished; wherein, the The pH value of the first polishing liquid is not greater than 7, and the pH value of the second polishing liquid is not less than 7.

The embodiment of the present invention further discloses a silicon carbide wafer, which includes two surfaces on opposite sides, and at least one of the two surfaces is a polished surface and includes: a reference surface, which is not formed with a length greater than 5 A scratch of micrometers; and a microstructure module formed on the reference surface, the microstructure module including a plurality of micro recesses recessed in the reference surface and a plurality of protruding from the reference surface Micro-protrusions, and the three-dimensional arithmetic mean deviation (Sa) of the microstructure module is less than 2.5 nanometers, and the three-dimensional contour height difference (Sz) of the microstructure module is less than 20 nanometers.

In summary, the method for manufacturing a silicon carbide wafer disclosed in the embodiment of the present invention can polish the first surface and the second surface of the surface to be polished by using the first polishing liquid and the second polishing liquid, and In combination, a plurality of the abrasive particles are fixed on the polishing pad, thereby effectively improving the surface flatness of the silicon carbide wafer, and reducing scratches or defects (micro-concavity, micro-protrusion) on the surface of the silicon carbide wafer.

Furthermore, the silicon carbide wafer disclosed in the embodiment of the present invention can provide a scratch-free polished surface, and has excellent flatness parameters (eg, Sa of the polished surface is less than 2.5 nm and Sz is less than 20 nm). In the subsequent application of silicon carbide wafers, it can effectively reduce the transmission of defects to the epitaxial layer and improve the quality of the epitaxial layer.

In order to further understand the features and technical content of the present invention, please refer to the following detailed descriptions and drawings about the present invention, but these descriptions and drawings are only used to illustrate the present invention, and do not make any claims about the protection scope of the present invention. limit.

100‧‧‧Silicon carbide wafer

1‧‧‧Polished surface

11‧‧‧Datum plane

12‧‧‧Microstructure module

121‧‧‧Micro depression

122‧‧‧Micro bump

FIG. 1 is a schematic flowchart of a method for manufacturing a silicon carbide wafer according to an embodiment of the present invention.

2 is a three-dimensional schematic diagram of a silicon carbide wafer according to an embodiment of the present invention.

Fig. 3 is a partial enlarged schematic view of the polishing surface of Fig. 2.

Please refer to Figures 1 to 3, which are embodiments of the present invention. It should be noted that the relevant quantities and appearances mentioned in the accompanying drawings in this embodiment are only used to specifically illustrate the implementation of the present invention, so that To understand the content of the present invention, not to limit the protection scope of the present invention.

[Method of manufacturing silicon carbide wafer]

As shown in Fig. 1, this embodiment discloses a method for manufacturing a silicon carbide wafer. The manufacturing method of the silicon carbide wafer includes step S110, step S120, and step S130. It must be noted that the order of the steps and the actual operation mode described in this embodiment can be adjusted according to requirements and are not limited to those described in this embodiment.

Step S110 is to provide a silicon carbide wafer. The silicon carbide wafer has at least one surface to be polished. In other words, the silicon carbide wafer has two surfaces on opposite sides, and may have the surface to be polished (single-side polishing) on the surface on one side thereof, or the silicon carbide wafer may also have two opposite surfaces. The surfaces on both sides have the surface to be polished (double-sided polishing).

Furthermore, the mask to be polished has a first surface and a second surface, and the crystal orientation of the first surface is different from the crystal orientation of the second surface. In more detail, the first surface of this embodiment is a carbon surface, and the second surface is a silicon surface, but the invention is not limited to this. The surface to be polished of the silicon carbide wafer referred to in this embodiment is a surface that has not been processed by a polishing process, and the size of the silicon carbide wafer is four inches, but the invention is not limited to this. For example, the size of the silicon carbide wafer can also be six inches or other larger or smaller sizes. Furthermore, when the silicon carbide wafer is undergoing incoming inspection, the linear roughness arithmetic average height (Ra) of the surface to be polished may be less than 7 nm, but is not limited thereto.

Step S120 is to perform a rough polishing process on the silicon carbide wafer. The rough polishing process includes polishing one of the first surface and the second surface of the surface to be polished in a first polishing liquid with a polisher. Then, the other of the first surface and the second surface of the surface to be polished is polished in a second polishing liquid using the polisher. Wherein, the polisher includes a polishing pad and a plurality of abrasive particles fixed on the polishing pad, and neither the first polishing liquid nor the second polishing liquid contains any abrasive particles. Furthermore, the pH value of the first polishing liquid is not greater than 7 (acid polishing liquid), and the pH value of the second polishing liquid is not less than 7 (alkaline polishing liquid).

Furthermore, in the rough polishing process of this embodiment, the polishing parameters of the polisher are polishing pressure greater than 20 g/cm ² , rotation speed not less than 25 rpm, and chemical mechanical polishing time between 0.5 and 2 hours. In the polisher, the average particle size of the plurality of abrasive particles fixed on the polishing pad is less than 20 μm, and the density of the plurality of abrasive particles distributed on the polishing pad is less than 50%. Furthermore, the plurality of abrasive particles are at least one selected from diamond (diamond), silicon carbide, aluminum oxide, boron carbide, and cubic boron nitride, and this embodiment uses diamond, but is not limited Here.

Preferably, the pH value of the first polishing liquid in this embodiment is not greater than 2 (acidic polishing liquid), and the polisher in the first polishing liquid is for the first surface (carbon surface) of the surface to be polished Perform polishing. And the pH value of the second polishing liquid is not less than 8 (alkaline polishing liquid), and the polisher is used in the second polishing liquid to perform processing on the second surface (silicon surface) of the surface to be polished. polishing. After the silicon carbide wafer undergoes a rough polishing process, the linear roughness (Ra) detected on the surface to be polished is between 0.5 nanometer (nm) and 1 nanometer.

In more detail, the first polishing liquid (such as acidic polishing liquid) contains an oxidizing agent, and the first polishing liquid is selected from permanganate, hydrogen peroxide, potassium hydrogen persulfate, cerium ammonium nitrate, At least one of periodate, iodate, persulfate, chlorate, chromate, bromate, perbromide, ferrite, perrhenate, and perruthenate, and This embodiment uses permanganate, but it is not limited to this. In addition, the second polishing liquid (such as alkaline polishing liquid) contains a metal salt, and the second polishing liquid is selected from sodium carbonate, potassium carbonate, sodium hydroxide, potassium hydroxide, ammonium hydroxide, At least one of tetramethyl ammonium hydroxide, and this embodiment uses potassium hydroxide, but it is not limited thereto.

It must be noted that in the rough polishing process of this embodiment, it is preferable to use the first polishing liquid to polish the first surface (carbon surface) of the surface to be polished, and then use the second polishing liquid to polish the surface. The second surface (silicon surface) of the surface to be polished is polished. The main reason is that the hardness of the first surface (carbon surface) is greater than that of the second surface (silicon surface), and the general industry has higher requirements for the surface processing quality of the second surface (silicon surface). It will increase the chance of damage to the surface of the wafer. In order to reduce the number of times of processing the second surface (silicon surface), the first surface (carbon surface) is processed first, but the invention is not limited to this. For example, in another embodiment of the present invention, the rough polishing process may also first use a first polishing solution to polish the second surface of the surface to be polished, and the first polishing solution may use Alkaline polishing liquid with pH not less than 8. Then, a second polishing liquid is used to polish the first surface of the surface to be polished, and the second polishing liquid can be an acidic polishing liquid with a pH value not greater than 2.

Step S130 is to perform a fine polishing process on the silicon carbide wafer. The fine polishing process includes polishing one of the first surface and the second surface of the surface to be polished in a third polishing liquid with the polisher. Next, use the polisher to polish the other of the first surface and the second surface of the surface to be polished in a fourth polishing solution, so that the surface to be polished forms a Polished surface. Wherein, the pH value of the third polishing liquid is not greater than 7 (acidic polishing liquid), and the pH value of the fourth polishing liquid is not less than 7 (alkaline polishing liquid), and the third polishing liquid and the fourth polishing liquid Preferably, the polishing liquid does not contain any abrasive particles.

Furthermore, in the fine polishing process of this embodiment, the polishing parameters of the polisher are polishing pressure greater than 15 g/cm ² , rotation speed not less than 15 rpm, and chemical mechanical polishing time between 0.5 and 2 hours. The specifications of the polisher used in the fine polishing process are the same or similar to the specifications of the polisher used in the rough polishing process, which will not be repeated here.

Preferably, the pH value of the third polishing liquid in this embodiment is not greater than 4 (acidic polishing liquid), and the polisher is used in the third polishing liquid to perform processing on the first surface of the surface to be polished. polishing. The pH value of the fourth polishing liquid is not less than 8 (alkaline polishing liquid), and the polisher polishes the second surface of the surface to be polished in the fourth polishing liquid. After the silicon carbide wafer undergoes the fine polishing process, the linear roughness (Ra) detected on the polished surface (the polished surface produced after the fine polishing process) is less than 0.5 nanometers. And the three-dimensional arithmetic mean deviation (Sa) of the polishing surface is less than 2.5 nanometers, the three-dimensional contour height difference (Sz) of the polishing surface is less than 20 nanometers, and the polishing surface is not formed with a length greater than 5 microns (μm) Of a scratch (scratch). In addition, the removal rate of the thickness of the polishing surface of the rough polishing process and the fine polishing process is greater than about 0.1 micrometers per hour.

In more detail, the third polishing liquid (for example, an acidic polishing liquid) is similar to the first polishing liquid in the rough polishing process (for example, the third polishing liquid contains an oxidizing agent). The fourth polishing liquid (for example, alkaline polishing liquid) is similar to the second polishing liquid in the rough polishing process (for example, the fourth polishing liquid contains metal salts).

It must be noted that, similar to the rough polishing process described above, in the fine polishing process of this embodiment, it is preferable to use a third polishing liquid to polish the first surface of the surface to be polished, and then use the fourth polishing solution. The polishing liquid polishes the second surface of the surface to be polished, but the present invention is not limited to this. For example, in another embodiment of the present invention, the fine polishing process may first use a third polishing solution to polish the second surface of the surface to be polished, and the third polishing solution may be Alkaline polishing liquid with pH not less than 8. Then, a fourth polishing liquid is used to polish the first surface of the surface to be polished, and the fourth polishing liquid may be an acidic polishing liquid with a pH value not greater than 4.

[Silicon carbide wafer polishing surface test]

2 and 3, for the polished surface 1 of the silicon carbide wafer 100 processed by the above-mentioned manufacturing method of the silicon carbide wafer, the detailed test method and test results are as follows. Among them, this embodiment uses a four-inch silicon carbide wafer for the polishing process, but the invention is not limited to this.

Wafer surface roughness (Sa, Sz) test: Take out the multiple silicon carbide wafers 100 processed by the above-mentioned silicon carbide wafer manufacturing method and take out three of them as wafer surface roughness test pieces (numbered 1, 2, 3) According to the white light interference measurement principle and the international standard ISO25178 for surface roughness, the white light interferometer is used for testing to obtain the three-dimensional arithmetic mean deviation (Sa) and three-dimensional of the microstructure module 12 as shown in FIG. Contour height difference (Sz). It must be noted that when the wafer surface roughness test is performed, 13 points evenly distributed on the polishing surface 1 of each test piece are selected for the test, and the test results of the 13 points are averaged, and the relevant The test results are shown in Table 1 (Table 1 only shows the average value of each test parameter).

It can be seen from Table 1 that the three-dimensional arithmetic mean deviation (Sa) of the three wafer surface roughness test pieces (numbered 1, 2, and 3) ranges from 1.07 nanometers to 2.27 nanometers (less than 2.5 nanometers). The three-dimensional contour height difference (Sz) ranges from 11.30 nm to 15.08 nm (less than 20 nm). The ratio of the three-dimensional arithmetic average deviation to the three-dimensional contour height difference (Sa/Sz) is between 0.09 and 0.15 (less than 0.25).

Wafer surface defect (scratch, pit defect, bump defect) test: Take out one of the multiple silicon carbide wafers 100 processed by the above-mentioned silicon carbide wafer manufacturing method as a wafer surface defect test piece, and target its polished surface 1 (including reference plane 11) for surface defect testing, the test items include the number of scratches, and the number of micro-structure modules 12 (pit defects) and micro-projections 122 (bump defects) ( As shown in Figure 3). Wherein, the scratch is defined as a surface defect with a length greater than 5 microns. Furthermore, in the wafer surface defect test, the number of various defects is tested for the entire polished surface 1, and then the number of various defects per square centimeter is calculated. The calculation method is the total number of various defects Divide the amount by the surface area of a four-inch chip (the surface area of a four-inch chip is approximately 71.5 cm²). Related test results are shown in Table 2.

It can be seen from Table 2 that the total number of scratches on the polished surface of the wafer surface defect test piece is 0, so the number of scratches per square centimeter area is also 0. The total number of micro recesses 121 of the microstructure module 12 is 69, so the number of micro recesses 121 per square centimeter area is only 0.96 (less than 1). The total number of micro protrusions 122 of the microstructure module 12 is 37, so the number of micro protrusions 122 per square centimeter is only 0.52 (less than 1). On the whole, the sum of the number of micro recesses 121 and micro protrusions 122 per square centimeter of the polishing surface 1 (including the reference surface 11) is less than 3, and any one of the microstructure modules 12 The micro recess 121 or any micro protrusion 122 is orthographically projected to a projection area of the reference surface 11, and its area is less than 100 square micrometers ( μ m ² ) (the values are not listed in Table 1). It is worth mentioning that in all the micro recesses 121 and the micro protrusions 122, the defect area is less than 25 microns square centimeters (μm ² ). That is to say, there are no micro depressions 121 or micro protrusions 122 larger than 25 micrometers square cm in the polishing surface 1 (including the aforementioned reference surface 11).

[Silicon Carbide Wafer]

As shown in FIGS. 2 and 3, this embodiment also discloses a silicon carbide wafer 100. The silicon carbide wafer 100 may be processed by the above-mentioned silicon carbide wafer manufacturing method, but the present invention is not limited thereto.

Specifically, the silicon carbide wafer 100 includes two surfaces on opposite sides, and at least one of the two surfaces is a polishing surface 1. The polishing surface 1 includes a reference surface 11 and a microstructure module 12. Wherein, the reference surface 11 is not formed with a scratch (not shown in the figure) with a length greater than 5 microns, that is, the silicon carbide wafer 100 in this embodiment includes polishing with or without scratches. Surface 1.

The microstructure module 12 is formed on the reference surface 11. The microstructure module 12 includes a plurality of micro depressions 121 (pit defects) recessed on the reference surface 11 and a plurality of micro bumps 122 (bump defects) protruding from the reference surface 11. In addition, the three-dimensional arithmetic mean deviation (Sa) of the microstructure module 12 is less than 2.5 nanometers (nm), and the three-dimensional contour height difference (Sz) of the microstructure module 12 is less than 20 nanometers. The ratio (Sa/Sz) of the three-dimensional arithmetic average deviation of the microstructure module 12 to the three-dimensional contour height difference (Sa/Sz) is less than 0.25.

Furthermore, the number of micro depressions 121 per square centimeter (cm ² ) of the reference surface 11 is less than one, and the number of micro protrusions 122 per square centimeter (cm ² ) of the reference surface 11 is The number is less than one. On the whole, the total number of micro depressions 121 and micro protrusions 122 per square centimeter of the reference plane 11 is less than three. And any one of the micro recesses 121 or any one of the micro protrusions 122 of the microstructure module 12 is orthographically projected to a projection area of the reference plane 11, and the area is less than 100 square microns (μm ² ).

[Technical effects of the embodiments of the present invention]

In summary, the method for manufacturing silicon carbide wafers disclosed in the embodiments of the present invention can first polish the first surface of the surface to be polished with a first polishing liquid in the rough polishing process, and then use The second polishing liquid polishes the second surface of the surface to be polished, and in the fine polishing process, first use a third polishing liquid to polish the first surface of the surface to be polished, and then use the fourth polishing The liquid polishes the second surface of the surface to be polished, and fixes a plurality of abrasive particles on the polishing pad, thereby effectively improving the flatness of the polishing surface 1 of the silicon carbide wafer 100 (Sa is less than 2.5 nanometers) , Sz is less than 20 nanometers), and reduce scratches or defects (micro-recesses 121, micro-protrusions 122) on the polishing surface 1 of the silicon carbide wafer 100.

Furthermore, if the polishing liquid contains a plurality of abrasive particles, the phenomenon of agglomeration of the plurality of abrasive particles will often occur, so that the plurality of abrasive particles cannot be uniformly dispersed in the polishing liquid. In this case, when polishing the silicon carbide wafer, a plurality of abrasive particles agglomerated with each other will easily form scratches on the surface of the silicon carbide wafer. In contrast to the above-mentioned deficiencies, in the embodiment of the present invention, a plurality of abrasive particles can be fixed on the polishing pad, thereby avoiding agglomeration of a plurality of abrasive particles, and effectively reducing scratches on the surface of the silicon carbide wafer.

In addition, the silicon carbide wafer 100 disclosed in the embodiment of the present invention can provide a scratch-free polished surface 1 and has excellent flatness parameters (for example, Sa of the polished surface is less than 2.5 nm and Sz is less than 20 nm). Therefore, in the subsequent application of the silicon carbide wafer 100, the transmission of defects to the epitaxial layer can be effectively reduced, and the quality of the epitaxial layer can be improved.

The foregoing descriptions are only preferred and feasible embodiments of the present invention, and are not used to limit the scope of protection of the present invention. All equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the protection scope of the claims of the present invention. .

Claims (4)

A method for manufacturing a silicon carbide wafer includes: providing a silicon carbide wafer having a surface to be polished; wherein the surface to be polished has a first surface and a second surface; wherein the first surface is a carbon Surface, and the second surface is a silicon surface; a polisher is used to polish the first surface of the surface to be polished in a first polishing liquid; wherein, the polisher includes a polishing pad And a plurality of abrasive particles fixed on the polishing pad; after the first surface is polished by the polisher in a first polishing solution, the polisher is used for polishing the first surface in a second polishing solution The second surface of the surface to be polished is polished; wherein the pH value of the first polishing liquid is not greater than 2, and the pH value of the second polishing liquid is not less than 8; After the second surface is polished in the second polishing solution, the first surface of the surface to be polished is polished by the polisher in a third polishing solution; and in the polishing After polishing the first surface in the third polishing solution, use the polisher to polish the second surface of the surface to be polished in a fourth polishing solution to make the The surface to be polished forms a polishing surface; wherein the pH value of the third polishing solution is not greater than 7, and the pH value of the fourth polishing solution is not less than 7. The method for manufacturing a silicon carbide wafer according to claim 1, wherein the first polishing liquid contains an oxidizing agent, and the second polishing liquid contains a metal salt. The method for manufacturing a silicon carbide wafer according to claim 1, wherein the pH value of the third polishing liquid is not greater than 4, and the polisher is used for the surface to be polished in the third polishing liquid. The first surface is polished; the pH value of the fourth polishing liquid is not less than 8, and the polisher is in the fourth polishing liquid to perform polishing on the second surface of the surface to be polished Polishing; wherein the three-dimensional arithmetic mean deviation (Sa) of the polishing surface is less than 2.5 nanometers, and the three-dimensional wheel of the polishing surface The profile height difference (Sz) is less than 20 nanometers, and the polished surface is not formed with a scratch with a length greater than 5 microns. The method for manufacturing a silicon carbide wafer according to claim 1, wherein neither the first polishing liquid nor the second polishing liquid contains any abrasive particles.

Images