TWI698084B - Oscillator and control method - Google Patents

Abstract

An oscillator includes a voltage controlled oscillating circuit and a processing circuit. The voltage controlled oscillating circuit generates an oscillating frequency according to a digital signal. When the digital signal has a first signal value, the oscillating frequency is a first oscillating frequency. The processing circuit determines a second signal value of the digital signal according to the first oscillating frequency and a target oscillating frequency, to adjust the oscillating frequency to a second oscillating frequency. The processing circuit further performs an interpolation according to a first frequency difference value between the target oscillating frequency and the first oscillating frequency and a second frequency difference value between the second oscillating frequency and the first oscillating frequency to determine a target signal value of the digital signal, in order to adjust the oscillating frequency to the destination oscillating frequency.

Description

Oscillator and control method

The contents of the embodiments described in this disclosure are related to an oscillator, and more particularly to a voltage-controlled oscillator circuit and a method for controlling its oscillation frequency.

The oscillation frequency of the oscillator is determined by the inductance and capacitance of the resonant tank. Generally speaking, the oscillation frequency of the oscillator can be adjusted by controlling the capacitance value. However, when environmental conditions (such as temperature, voltage) change, it takes a lot of time to determine the appropriate control signal to set the capacitance value so that the oscillator can operate at the expected oscillation frequency.

One embodiment of the present disclosure relates to an oscillator. The oscillator includes a voltage controlled oscillation circuit and a processing circuit. The voltage controlled oscillation circuit is used for generating an oscillation frequency according to a digital signal. When the digital signal is a first signal value, the oscillation frequency is a first oscillation frequency. The processing circuit is used for determining a second signal value of the digital signal according to the first oscillation frequency and a target oscillation frequency, so as to adjust the oscillation frequency to a second oscillation frequency. The processing circuit further uses a first frequency difference value and a second frequency difference value to perform an interpolation operation to determine a target signal value of the digital signal to adjust the oscillation frequency to the target oscillation frequency, wherein the first frequency The difference is the difference between the target oscillation frequency and the first oscillation frequency, and the second frequency difference is the difference between the second oscillation frequency and the first oscillation frequency.

One embodiment of the present disclosure relates to a control method. The control method includes: generating an oscillation frequency of a voltage-controlled oscillation circuit according to a digital signal, wherein when the digital signal is a first signal value, the oscillation frequency is a first oscillation frequency; according to the first oscillation frequency and a target oscillation frequency Determine a second signal value of the digital signal to adjust the oscillation frequency to a second oscillation frequency; and perform an interpolation operation based on a first frequency difference and a second frequency difference to determine a target signal of the digital signal Value to adjust the oscillation frequency to the target oscillation frequency, wherein the first frequency difference is the difference between the target oscillation frequency and the first oscillation frequency, and the second frequency difference is the second oscillation frequency and the The difference between the first oscillation frequency.

In summary, through at least one of the above embodiments, the processing circuit can quickly determine the target signal value to control the voltage-controlled oscillation circuit to operate at the target oscillation frequency.

100‧‧‧Oscillator

102‧‧‧Voltage controlled oscillation circuit

104‧‧‧Processing circuit

106‧‧‧register

202‧‧‧Variable Capacitor Array

500‧‧‧Control method

S520, S540, S560, S580‧‧‧Step

LUT‧‧‧Lookup table

C _VAR 1, C _VAR 2, C1, C2, C3, C4, C5, C6, C7‧‧‧Capacitor

N1, N2, N3‧‧‧node

M1, M2, M3, SW1, SW2, SW3‧‧‧Switch

V _SW ‧‧‧Digital signal

S _SW 1, S _SW 2‧‧‧Signal value

S _SW 3‧‧‧Target signal value

S[1], S[2], S[3]‧‧‧bit

V _TUNE 、V _B ‧‧‧Control voltage

V _DD ‧‧‧Supply voltage

F, F1, F2‧‧‧Oscillation frequency

F _DES ‧‧‧Target oscillation frequency

△F1, △F2‧‧‧frequency difference

L1‧‧‧Inductor

To make the above and other objectives, features, advantages and embodiments of the present disclosure more comprehensible, the description of the accompanying drawings is as follows: Figure 1 is a schematic diagram of an oscillator according to some embodiments of the present disclosure; FIG. 2 is a schematic diagram of the voltage-controlled oscillation circuit of FIG. 1 according to some embodiments of the present disclosure; FIG. 3 is a schematic diagram of the variable capacitor array of FIG. 2 according to some embodiments of the present disclosure; FIG. 4 is a schematic diagram of the relationship between the first oscillation frequency, the second oscillation frequency, and the target oscillation frequency according to some embodiments of the present disclosure; and FIG. 5 is a control method according to some embodiments of the present disclosure Flow chart.

The following is a detailed description of the embodiments with the accompanying drawings, but the provided embodiments are not used to limit the scope of this disclosure, and the description of the structure operation is not used to limit the order of its execution, any recombination of components The structure and the devices with equal effects are all within the scope of this disclosure. In addition, the drawings are for illustrative purposes only, and are not drawn according to the original dimensions. To facilitate understanding, the same or similar elements in the following description will be described with the same symbols.

The term "coupled" used in this article can also refer to "electrical coupling", and the term "connected" can also refer to "electrical connection". "Coupling" and "connection" can also refer to two or more components cooperating or interacting with each other.

FIG. 1 is a schematic diagram of an oscillator 100 according to some embodiments of the present disclosure. In some embodiments, the oscillator 100 includes a voltage-controlled oscillation circuit 102, a processing circuit 104, and a register 106. The processing circuit 104 is coupled to the voltage controlled oscillation circuit 102 and the register 106. The processing circuit 104 can provide a digital signal V _SW to the voltage controlled oscillation circuit 102. The voltage controlled oscillation circuit 102 generates a corresponding oscillation frequency F according to the digital signal V _SW . The processing circuit 104 can detect the oscillation frequency F when the voltage-controlled oscillation circuit 102 operates based on the digital signal V _SW . For example, in some embodiments, the processing circuit 104 includes a counter. The counter is used to count according to the signal with the oscillation frequency F generated by the voltage-controlled oscillation circuit 102 to generate different values. In this way, the processing circuit 104 can detect the oscillation frequency F according to this value.

The register 106 is used to record the correspondence between different signal values of the digital signal V _SW and the oscillation frequency F. For example, the above-mentioned correspondences can be implemented in the register 106 by means of look-up table (LUT). In some embodiments, when the processing circuit 104 detects the oscillation frequency F, the processing circuit 104 can read the signal value of the digital signal V _SW corresponding to the oscillation frequency F from the look-up table LUT. For example, the processing circuit 104 can read the signal value of the digital signal V _SW according to the value generated by the counter to the corresponding address of the look-up table LUT. The above configuration of the processing circuit 104 and the register 106 is only an example, and the content of this disclosure is not limited thereto.

FIG. 2 is a schematic diagram of the voltage-controlled oscillation circuit 102 of FIG. 1 according to some embodiments of the present disclosure. In some embodiments, the voltage controlled oscillation circuit 102 includes a variable capacitor array 202, an inductor L1, a capacitor C _VAR 1, a capacitor C _VAR 2, a switch M1, a switch M2, and a switch M3. The inductor L1 receives the supply voltage V _DD . The variable capacitor array 202 and the inductor L1 are coupled to the node N1 and the node N2. The variable capacitor array 202 receives the digital signal V _SW and determines the capacitance value of the variable capacitor array 202 according to the digital signal V _SW . The capacitor C _VAR 1 is coupled between the node N1 and the node N3. The capacitor C _VAR 2 is coupled between the node N3 and the node N2. The node N3 receives the control voltage V _TUNE to determine the capacitance values of the capacitor C _VAR 1 and the capacitor C _VAR 2. For example, in some embodiments, the capacitor C _VAR 1 and the capacitor C _VAR 2 may be implemented by varactors. In some embodiments, the varactor can be realized by a transistor. In this example, the gate of the transistor used to implement the varactor receives the control voltage V _TUNE . In this way, if the control voltage V _TUNE changes, the capacitance values of the capacitor C _VAR 1 and the capacitor C _VAR 2 will change accordingly. The foregoing implementation of the capacitor C _VAR 1 and the capacitor C _VAR 2 is only an example, and the content of the disclosure is not limited thereto.

The switches M1~M2 are cross-coupled. That is, the control end of the switch M1 and one end of the switch M2 are coupled to the node N2, and the control end of the switch M2 and one end of the switch M1 are coupled to the node N1. The switch M3 is coupled between the switch M1 and the ground, and is coupled between the switch M2 and the ground. The switch M3 receives the control voltage V _B and is used as a constant current source. In some embodiments, the variable capacitance array 202, the inductor L1, the capacitor C _VAR 1, and the capacitor C _VAR 2 are configured as a resonant circuit. The switches M1~M2 are set to generate a negative impedance to cancel the parasitic resistance of the resonance circuit. In this way, the voltage-controlled oscillation circuit 102 can start to generate a signal with an oscillation frequency F.

In some embodiments, the oscillation frequency F of the voltage-controlled oscillation circuit 102 can be obtained by the following formula (1):

Where C is the equivalent capacitance value of the variable capacitance array 202, the capacitor C _VAR 1 and the capacitor C _VAR 2, and L is the inductance value of the inductor L1.

As mentioned earlier, the capacitance value of the variable capacitor array 202 is determined according to the digital signal V _SW . When the capacitance value of the variable capacitor array 202 changes, C in the formula (1) will change accordingly, so as to change the oscillation frequency F of the voltage-controlled oscillator circuit 102 accordingly. In other words, the oscillation frequency F of the voltage controlled oscillation circuit 102 can be changed through the digital signal V _SW .

The above-mentioned voltage-controlled oscillation circuit 102 is only used as an example, and the arrangement of various other voltage-controlled oscillation circuits 102 is also covered by this disclosure.

FIG. 3 is a schematic diagram of the variable capacitor array 202 of FIG. 2 according to some embodiments of the present disclosure. In some embodiments, the variable capacitor array 202 is an N-bit variable capacitor array. N is a positive integer. The nth bit of the variable capacitance array 202 corresponds to 2 ^(n-1) capacitors. n is a positive integer and less than or equal to N.

In some embodiments, the signal value of the digital signal V _SW consists of a plurality of bits, which respectively correspond to the N-bit variable capacitor array. Taking the example in Figure 3, the first bit S[1] of the signal value of the digital signal V _SW corresponds to the capacitor C1. The second bit S[2] of the signal value of the digital signal V _SW corresponds to the capacitors C2~C3. The third bit S[3] of the signal value of the digital signal V _SW corresponds to the capacitors C4~C7.

Specifically, the capacitor C1 and the switch SW1 are connected in series between the node N1 and the node N2, and the switch SW1 is controlled by the first bit S[1] of the signal value of the digital signal V _SW . The capacitor C2 and the capacitor C3 are connected in parallel, and the capacitors C2 to C3 and the switch SW2 are connected in series between the node N1 and the node N2. The switch SW2 is controlled by the second bit S[2] of the signal value of the digital signal V _SW . The capacitors C4 to C7 are connected in parallel with each other, and the capacitors C4 to C7 and the switch SW3 are connected in series between the node N1 and the node N2. The switch SW3 is controlled by the third bit S[3] of the signal value of the digital signal V _SW . By analogy, the setting method between the N-bit variable capacitor array and the digital signal V _SW can be derived.

With the above configuration, the capacitance value of the variable capacitor array 202 can be changed by adjusting the digital signal V _SW . When the capacitance value of the variable capacitance array 202 changes, the equivalent capacitance values of the variable capacitance array 202, the capacitor C _VAR 1 and the capacitor C _VAR 2 will change accordingly. Based on the above formula (1), when the equivalent capacitance value changes, the oscillation frequency F of the voltage-controlled oscillation circuit 102 will change accordingly. The variable capacitor array 202 described above is only an example, and the arrangement of various other variable capacitor arrays 202 is also covered by this disclosure.

FIG. 4 is a schematic diagram illustrating the relationship between the oscillation frequency F1, the oscillation frequency F2, and the target oscillation frequency F _DES according to some embodiments of the present disclosure. Fig. 5 is a flowchart of a control method 500 according to some embodiments of the present disclosure. Please refer to Figures 1 to 5 together below.

In step S520, the processing circuit 104 detects the oscillation frequency F1 when the voltage-controlled oscillation circuit 102 operates based on the signal value S _SW 1 of the digital signal V _SW . In some embodiments, when the oscillator 100 is powered on, the voltage-controlled oscillation circuit 102 generates an initial oscillation frequency (for example, the oscillation frequency F1) according to the signal value S _SW 1 of the digital signal V _SW . In some embodiments, the processing circuit 104 reads the signal value S _SW 1 of the digital signal V _SW corresponding to the oscillation frequency F1 from the look-up table LUT in the register 106 according to the oscillation frequency F1.

In step S540, the processing circuit 104 adjusts the digital signal V _SW from the signal value S _SW 1 to the signal value S _SW 2 according to the oscillation frequency F1 and the target oscillation frequency F _DES . In some embodiments, the processing circuit 104 includes a frequency detector for comparing the oscillation frequency F1 with the target oscillation frequency F _DES . When the oscillation frequency F1 is different from the target oscillation frequency F _DES , the processing circuit 104 adjusts the signal value S _SW 1 to the signal value S _SW 2 according to a preset value M.

For example, when the oscillation frequency F1 is less than the target oscillation frequency F _DES , the processing circuit 104 generates the signal value S _SW 2 to reduce the capacitance value of the variable capacitor array 202. In this way, the oscillation frequency F1 can be raised to a higher oscillation frequency. Alternatively, when the oscillation frequency F1 is greater than the target oscillation frequency F _DES , the processing circuit 104 generates a signal value S _SW 2 to increase the capacitance value of the variable capacitor array 202. In this way, the oscillation frequency F1 can be reduced.

If the switches SW1 to SW3 of the variable capacitor array 202 are implemented by N-type transistors, when the oscillation frequency F1 is less than (greater than) the target oscillation frequency F _DES , the processing circuit 104 subtracts the signal value S _SW 1 from the preset value M (Add) to generate the signal value S _SW 2. Suppose the signal value S _SW 1 is 111 (that is, S[3]=1, S[2]=1, S[1]=1). In this case, the switches SW1 to SW3 are all turned on. At this time, the capacitors C1 to C7 are connected in parallel with each other. The capacitance value of the variable capacitance array 202 is substantially equal to the sum of the capacitance values of the capacitors C1 to C7. If the oscillation frequency F1 is less than the target oscillation frequency F _DES (as shown in Figure 4), the processing circuit 104 subtracts the preset value M from the digital signal V _SW 1 (for example, M=6, the corresponding bit is 110) to The generated signal value S _SW 2 is 001. In this case, the switch SW1 is turned on, but the switch SW2 and the switch SW3 are turned off. At this time, the capacitance value of the variable capacitance array 202 is substantially equal to the capacitance value of the capacitor C1. In other words, the capacitance value of the variable capacitor array 202 is reduced to increase the oscillation frequency F1 to the oscillation frequency F2.

Or, in other examples, if the switches SW1 to SW3 of the variable capacitor array 202 are implemented by P-type transistors, when the oscillation frequency F1 is less than (greater than) the target oscillation frequency F _DES , the processing circuit 104 sends the digital signal V _SW 1 is added (subtracted) to the preset value M to generate a digital signal V _SW 2. The operations here can be deduced based on the above paragraphs, so the description will not be repeated.

In some embodiments, the capacitance values of the capacitors C1 to C7 are the same or partially the same. In some embodiments, the aforementioned preset value M can be adjusted according to the capacitance values of the capacitors C1 to C7. For example, when the capacitance values of the capacitors C1 to C7 are the same and the capacitance value is larger, the preset value M can be set to be smaller. In some embodiments, the preset value M may also be determined according to the linearity requirement of the oscillator 100. By considering the linearity requirement of the oscillator to set the default value M, a more accurate oscillation frequency F2 can be obtained to improve the accuracy of the interpolation operation mentioned later.

In step S560, the processing circuit 104 detects the oscillation frequency F2 when the voltage controlled oscillation circuit 102 operates based on the signal value S _SW 2 of the digital signal V _SW . In some embodiments, after the signal value of the digital signal V _SW is adjusted from S _SW 1 to S _SW 2, the variable capacitor array 202 generates the oscillation frequency F2 based on the signal value S _SW 2 of the digital signal V _SW . The counter of the processing circuit 104 can detect the oscillation frequency F2 generated by the variable capacitor array 202 accordingly.

In step S580, the processing circuit 104 performs an interpolation operation based on the frequency difference ΔF2 and the frequency difference ΔF1 to determine a target signal value S _SW 3 corresponding to the target oscillation frequency F _DES .

In some embodiments, the processing circuit 104 calculates the difference between the oscillation frequency F2 and the oscillation frequency F1 to determine the frequency difference ΔF1, and calculates the difference between the target oscillation frequency F _DES and the oscillation frequency F1 to determine the frequency difference Δ F2. As shown in Figure 3, in some embodiments, the processing circuit 104 can perform interpolation operations based on the frequency difference ΔF1 and the frequency difference ΔF2 to efficiently determine the target signal value corresponding to the target oscillation frequency F _DES S _SW 3.

For example, the processing circuit 104 may calculate the target adjustment value P according to the frequency difference ΔF1, the frequency difference ΔF2, and the aforementioned preset value M. In some embodiments, the target adjustment value P can be obtained by the following formula (2):

Based on the above formula (2), the processing circuit 104 calculates the magnitude of the signal value of the digital signal V _SW to be adjusted according to the ratio between the frequency difference △F2 and the frequency difference △F1 and the preset value M (that is, the target adjustment What is the value P). Then, the processing circuit 104 generates the target signal value S _SW 3 according to the target adjustment value P and the signal value S _SW 1. In some embodiments, the target signal value S _SW 3 can be obtained by the following formula (3): S _SW 3=S _SW 1+P...(3)

For example, if the signal value S _SW 1 is 001 and P is 3 (the corresponding bit is 011), the target signal value S _SW 3 is 100. Accordingly, the processing circuit 104 transmits the digital signal V _SW having the target signal value S _SW 3 to the variable capacitor array 202 to determine the state of the switches in the variable capacitor array 202 (for example, on or off). By determining the states of the switches, the capacitance value of the variable capacitor array 202 can be adjusted. In this way, the equivalent capacitance values of the variable capacitance array 202, the capacitor C _VAR 1 and the capacitor C _VAR 2 can be adjusted to be substantially equal to the target capacitance value. Accordingly, the target capacitance value and the inductance value L of the inductor L1 can make the oscillation frequency of the voltage-controlled oscillation circuit 102 the target oscillation frequency F _DES .

In other words, according to the above equations (2) to (3), after obtaining two oscillation frequencies F1 and F2, the processing circuit 104 can use these oscillation frequencies F1 and F2 and their corresponding signal values S _sw 1 and S _sw 2 Quickly interpolate the target signal value S _SW 3. In some related technologies, when environmental conditions (such as operating temperature, voltage, etc.) change, the look-up table needs to be rebuilt. This will consume a lot of time. Compared with the above-mentioned related technology, the processing circuit 104 can quickly determine the target signal value S _SW 3. In some embodiments, the control method 500 may be repeated multiple times to increase the accuracy of the target signal value S _SW 3.

The multiple steps of the control method 500 described above are only examples, and are not limited to be executed in the order in this example. Without departing from the operation manner and scope of the embodiments of the present disclosure, various operations under the control method 500 may be appropriately added, replaced, omitted, or executed in a different order.

In summary, through at least one of the above embodiments, the processing circuit can quickly determine the target signal value to control the voltage-controlled oscillation circuit to operate at the target oscillation frequency.

Although the present disclosure has been disclosed in the above embodiments, it is not intended to limit the present disclosure. Anyone with ordinary knowledge in the field can make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, this disclosure The scope of protection shall be subject to the scope of the attached patent application.

500‧‧‧Control method

S520, S540, S560, S580‧‧‧Step

Claims (9)

An oscillator comprising: a voltage-controlled oscillation circuit for generating an oscillation frequency according to a digital signal, wherein when the digital signal is a first signal value, the oscillation frequency is a first oscillation frequency; and a processing circuit , For determining a second signal value of the digital signal according to the first oscillation frequency and a target oscillation frequency to adjust the oscillation frequency to a second oscillation frequency, wherein when the first oscillation frequency is different from the target oscillation frequency When, the processing circuit subtracts a preset value from the first signal value or adds the first signal value to the preset value to generate the second signal value, and adjusts the digital signal from the first signal value Is the second signal value, and the processing circuit is further used to perform an interpolation operation based on a first frequency difference and a second frequency difference to determine a target signal value of the digital signal to adjust the oscillation frequency to The target oscillation frequency, wherein the first frequency difference is the difference between the target oscillation frequency and the first oscillation frequency, and the second frequency difference is the difference between the second oscillation frequency and the first oscillation frequency difference. The oscillator described in claim 1, wherein the voltage-controlled oscillation circuit includes a variable capacitor array, the variable capacitor array is used to receive the digital signal, and a capacitance value of the variable capacitor array is based on the Digital signal decision. The oscillator described in item 2 of the scope of patent application, wherein the processing circuit is further used to compare the first oscillation frequency and the target oscillation Frequency to adjust the digital signal. For the oscillator described in item 2 of the scope of patent application, when the first oscillation frequency is less than the target oscillation frequency, a capacitance value of the variable capacitor array is reduced according to the second signal value, and when the first oscillation frequency is When the oscillation frequency is greater than the target oscillation frequency, the capacitance value of the variable capacitor array is increased according to the second signal value. For example, the oscillator described in claim 1, wherein when the first oscillation frequency is less than the target oscillation frequency, the processing circuit subtracts the preset value from the first signal value to generate the second signal value, And when the first oscillation frequency is greater than the target oscillation frequency, the processing circuit adds the first signal value to the predetermined value to generate the second signal value. For the oscillator described in claim 1, wherein the processing circuit is further used to determine a product based on a ratio between the first frequency difference and the second frequency difference and a product of the preset value Target adjustment value, and adding the first signal value and the target adjustment value to generate the target signal value. For example, the oscillator described in claim 1 further includes: a register for storing a look-up table, wherein the processing circuit is further used for reading the digit from the look-up table according to the first oscillation frequency The first signal value of the signal. A control method includes: generating an oscillation frequency of a voltage-controlled oscillation circuit according to a digital signal, wherein when the digital signal is a first signal value, the oscillation frequency is a first oscillation frequency; according to the first oscillation frequency And a target oscillation frequency determines a second signal value of the digital signal to adjust the oscillation frequency to a second oscillation frequency, wherein the second signal value that determines the digital signal includes: when the first oscillation frequency is different from the At the target oscillation frequency, subtract a preset value from the first signal value or add the first signal value to the preset value to generate the second signal value; and according to a first frequency difference and a second Two frequency difference values are subjected to an interpolation operation to determine a target signal value of the digital signal to adjust the oscillation frequency to the target oscillation frequency, wherein the first frequency difference is the difference between the target oscillation frequency and the first oscillation frequency And the second frequency difference is the difference between the second oscillation frequency and the first oscillation frequency. For the control method described in item 8 of the scope of patent application, wherein adjusting the digital signal includes: determining a target adjustment value according to a ratio between the first frequency difference value and the second frequency difference value and the preset value ; Add the first signal value and the target adjustment value to generate the target signal value; and adjust the digital signal to the target signal value to adjust the oscillation frequency to the target oscillation frequency.

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