TWI697839B - Method and computer program product and apparatus for adjusting operating frequencies - Google Patents

Abstract

A method for adjusting operating frequencies, performed by a processing unit of a device side, includes: collecting an interface-activity parameter; selecting one from multiple frequencies according to the interface-activity parameter; and driving a clock generator to output a clock signal at the selected frequency, thereby enabling a host access interface and/or a flash access interface to operate at a corresponding operating frequency.

Description

Operating frequency adjustment method and computer program product and device

The invention relates to a flash memory device, in particular to an operating frequency adjustment method and computer program products and devices.

Flash memory devices are generally divided into NOR flash memory devices and NAND flash memory devices. The NOR flash memory device is a random access device. The host can provide any address for accessing the NOR flash memory device on the address pin, and promptly retrieve it from the data pin of the NOR flash memory device Obtain the data stored at that address. On the contrary, NAND flash memory devices are not random access, but serial access. NAND flash memory devices cannot access any random address like NOR flash memory devices. Instead, the host side needs to write serial bytes (Bytes) into the NAND flash memory device to define the request The type of command (such as read, write, erase, etc.), and the address used for this command. The address can point to a page (the smallest data block for a write operation in the flash memory device) or a block (the smallest data block for an erase operation in the flash memory device).

Power saving is usually an important issue for flash memory devices. Traditionally, the host can control the flash memory device to work in different sleep modes to save power consumption when the flash memory device is not used to access data. The flash memory device selectively turns on or off all or part of the circuits according to different sleep modes to save power. However, such control does not apply to the Active Mode when transferring data between the host and the flash memory device. Therefore, the present invention provides an operating frequency adjustment method and computer Program products and devices can be used in active mode to achieve better power saving effects.

In view of this, how to reduce or eliminate the deficiencies in the above-mentioned related fields is indeed a problem to be solved.

The present invention provides an operating frequency adjustment method, a computer program product, and a device. The method is implemented by a processing unit on the device side when loading and executing firmware or software code, including: collecting interface activity parameters; Select one of the two frequencies; and drive the clock generator to output a clock signal of the selected frequency, so that the host access interface and/or the flash memory access interface run at the corresponding operating frequency.

The present invention also provides a computer program product for adjusting the operating frequency, which includes the following code: collecting interface activity parameters; selecting one from a plurality of frequencies according to the interface activity parameters; and driving a clock generator to output a clock of the selected frequency Signal to make the host access interface and/or flash memory access interface run at the corresponding operating frequency.

The present invention provides an operating frequency adjustment device, including: a clock generator and a processing unit. The processing unit collects interface activity parameters; selects one from multiple frequencies according to the interface activity parameters; and drives the clock generator to output a clock signal of the selected frequency, so that the host access interface and/or flash memory access interface runs in the corresponding Operating frequency.

The interface activity parameters include data transmission information of the host access interface and/or flash memory access interface.

One of the advantages of the above-mentioned embodiment is that the device side can actively activate the control mechanism for saving power consumption in Active Mode, without passively waiting for the command from the host side.

Another advantage of the above embodiment is that the device side can adjust the time generated by the clock generator to be provided to the processing unit and/or the access interface according to the data transmission state between the device side and the host side or between the device side and the storage unit. Pulse signal for finer power consumption control.

Other advantages of the present invention will be explained in more detail with the following description and drawings.

100: Flash memory system

110: host side

130: device side

131: physical layer

132: Data Link Layer

133: Flash memory controller

134: Processing Unit

135: Timer

136_1, 136_2: clock generator

137_1, 137_2, 138_1, 138_2: register

139: Flash memory access interface

150: storage unit

170: Universal flash memory storage interconnection layer

CLK1, CLK2: clock signal

139_0: Access sub-interface

150_0_0~150_0_i: storage subunit

210: data line

230_0~230_i: Chip enable control signal

S310~S350: method steps

S410~S460: method steps

500: Flash memory system

530: device side

535: Divider

610~650: program module

FIG. 1 is a schematic diagram of a system architecture of a flash memory according to an embodiment of the present invention.

2 is a schematic diagram of the connection between the access sub-interface and a plurality of storage sub-units.

FIG. 3 is a flowchart of a method for adjusting the operating frequency according to an embodiment of the present invention.

4 is a flowchart of a method for periodically adjusting the clock signal output by a clock generator according to an embodiment of the present invention.

FIG. 5 is a schematic diagram of a system architecture of a flash memory according to another embodiment of the present invention.

FIG. 6 is a schematic diagram of functional modules for adjusting operating frequency according to an embodiment of the present invention.

The following description is a preferred implementation manner for completing the invention, and its purpose is to describe the basic spirit of the invention, but not to limit the invention. The actual content of the invention must refer to the scope of the claims that follow.

It must be understood that the words "including" and "including" used in this specification are used to indicate the existence of specific technical features, values, method steps, operations, elements and/or components, but do not exclude the possibility of adding More technical features, values, method steps, job processing, components, components, or any combination of the above.

Words such as "first", "second", and "third" used in the claims are used to modify the elements in the claims, and are not used to indicate that there is a priority, prerequisite relationship, or an element Prior to another component, or the chronological order of execution of method steps, is only used to distinguish components with the same name.

It must be understood that when an element is described as being “connected” or “coupled” to another element, it can be directly connected or coupled to other elements, and intermediate elements may appear. Conversely, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intervening elements. Other terms used to describe the relationship between elements can also be interpreted in a similar manner, such as "between" and "directly between", or "adjacent" as opposed to "directly adjacent" and so on.

Refer to Figure 1. The flash memory system architecture 100 includes a host 110, a device 130, and a storage unit 150. This system architecture can be implemented in personal computers, laptop PCs, tablets, mobile phones, digital cameras, digital cameras and other electronics product. The device 130 may include a flash memory controller 133. The host 110 and the device 130 can communicate with each other with a flash memory communication protocol (for example, Universal Flash Storage UFS). The flash memory controller 133 is electrically connected (coupled) to the host terminal 110 through the data link layer 132 and the physical layer 131. The flash memory controller 133 can read the user data obtained from the storage unit 150 from the data buffer (not shown in FIG. 1) through the direct memory access controller (not shown in FIG. 1), and connect it through the drive data The layer 132 and the physical layer 131 are knocked out to the host 110 in sequence. The flash memory controller 133 can store the user data to be written by the host terminal 110 into the data buffer through a direct memory access controller (not shown in FIG. 1). The processing unit 134 can be implemented in a variety of ways, such as the use of general-purpose hardware, such as a single processor, multi-processors with parallel processing capabilities, graphics processors, lightweight general-purpose processors (Lightweight General-Purpose Processor) or other tools. A processor with arithmetic capability, and provides the functions described later when executing instructions, macrocodes or microcodes. The flash memory controller 133 may be a UFS controller, which communicates with the host terminal 110 through the UFS communication protocol. Although the UFS communication protocol is used as an example in the embodiment of the present invention, the present invention can also be applied to other communication protocols, such as Universal Serial Bus (USB), advanced technology attachment (ATA), advanced serial technology Attach (serial advanced technology attachment, SATA), rapid peripheral component interconnect express (PCI-E) or other interface communication protocols.

The device side 130 further includes a flash memory access interface 139, so that the processing unit 134 can communicate with the storage unit 150 through the flash memory access interface 139. In detail, a Double Data Rate (DDR) communication protocol can be used, for example, open NAND flash (Open NAND Flash Interface ONFI), double data rate switch (DDR Toggle) or other interfaces. The processing unit 134 writes user data to the designated address (destination address) in the storage unit 150 through the flash memory access interface 139, and reads the user data from the designated address (source address) in the storage unit 150. Flash memory access interface 139 uses several electronic signals to The data and command transmission between the coordinating processing unit 134 and the storage unit 150 includes a data line, a clock signal, and a control signal. The data line can be used to transfer commands, addresses, read and write data; the control signal line can be used to transfer Chip Enable CE, Address Latch Enable ALE, Command Extraction Enable ( Control signals such as Command Latch Enable CLE) and Write Enable WE.

The storage unit 150 may include a plurality of storage sub-units, each of which uses an associated access sub-interface to communicate with the processing unit 134. One or more storage sub-units can be packaged in a die. The flash memory access interface 139 may include j access sub-interfaces, and each access sub-interface is connected to i storage sub-units. The access sub-interface and the subsequent storage sub-units can also be collectively referred to as input and output channels, and can be identified by the logic unit number (Logic Unit Number LUN). In other words, i storage sub-units share one access sub-interface. For example, when the device 130 includes 4 I/Os and each I/O is connected to 4 storage sub-units, the device 130 can access 16 storage sub-units. The processing unit 134 can drive to access one of the sub-interfaces, read from the designated storage sub-unit, or write data to the designated storage sub-unit. Each storage sub-unit has an independent chip enable (CE) control signal. In other words, when data is to be read or written to a designated storage sub-unit, the associated access sub-interface needs to be driven to enable the chip enable control signal of this storage sub-unit. Refer to Figure 2. The processing unit 134 can use independent chip enable control signals 230_0_0 to 230_0_i to select one of the connected storage subunits 150_0_0 to 150_0_i through the access sub-interface 139_0, and then use the shared data line 210 from the selected storage Read data from the specified address of the subunit, or send user data to be written to the specified address to the selected storage subunit.

Refer to Figure 1. The device end 130 further includes a clock generator (Clock Generator) 136_1. The clock generator 136_1 is a circuit that generates a clock signal CLK1, and outputs the clock signal CLK1 to the processing unit 134 for synchronizing the extraction, decoding, execution, and writing of firmware commands, macrocode or microcode, etc. In some embodiments, when the host 110 is expected to be out of storage for a long time When the storage unit 150 is fetched, a command can be sent to the device terminal 130 to make the device terminal 130 enter the power saving mode. For example, the host terminal 110 may send the primitive DME_HIBERNATE_ENTER to enter the sleep mode (Sleep Mode) to the device terminal 130. When the flash memory controller 133 receives the primitive DME_HIBERNATE_ENTER, the clock generator 136_1 can be turned off to save power consumption. Alternatively, the host terminal 110 may send a Start Stop Unit (SSU) command to the device terminal 130 to force the device terminal 130 to enter the sleep state (Sleep State). When the flash memory controller 133 receives the start-stop unit command to enter the sleep state, it blocks the clock signal CLK1 generated by the clock generator 136_1, so that the clock signal CLK1 cannot be provided to the processing unit 134. For the data format and sending details of the primitive DME_HIBERNATE_ENTER and the start-stop unit command, please refer to the version 2.1 of the general flash memory storage standard published in June 2016. When the processing unit 134 is not driven by the clock signal CLK1, it cannot operate, so that power consumption can be saved. It should be noted here that when the processing unit 134 is not driven by the clock signal CLK1, it cannot execute any firmware or software commands, macrocode or microcode. However, in the Active Mode, the host 110 does not have any control mechanism that allows the device 130 to save power consumption.

To solve this defect, the embodiment of the present invention proposes a power saving mechanism in the operating mode, which is actively controlled by the device end 130, which can respond to the data transmission status between the device end 130 and the host end 110 or between the device end 130 and the storage unit 150 To adjust the clock signal generated by the clock generator to be provided to the processing unit and/or the access interface. For example, when only a lower transmission rate is required between two devices, the clock generator can be used to generate a lower frequency clock signal to save power consumption.

Refer to Figure 1. The device end 130 further includes a clock generator 136_2. The clock generator 136_2 is a circuit that generates the clock signal CLK2, and outputs the clock signal CLK2 to the universal flash memory storage interconnect layer 170 (UFS InterConnect Layer-UIC, which includes the physical layer 131, the data link layer 132 and the flash memory). The controller 133) and the flash memory access interface 139 are used to synchronize data transmission and reception operations. The universal flash memory storage interconnection layer 170 can be called host access interface. The clock generators 136_1 and 136_2 adjust the frequency of the output clock signals CLK1 and CLK2 according to the settings of the registers 138_1 and 138_2, respectively.

In order to provide a better power saving effect, the device 130 can preset multiple frequencies for the processing unit 134 and the flash memory access interface 139 respectively. For example, the frequency of the clock signal CLK1 output to the processing unit 134 can be 500, 250, 125 MHz, etc., and the clock signal output to the access interface (including the general flash memory storage interconnection layer 170 and the flash memory access interface 139) The frequency of CLK2 can be 300, 150, 75 MHz and so on. Refer to Figure 3. The method shown in FIG. 3 can be implemented by the processing unit 134 when loading and executing specific firmware or software commands, macrocodes or microcodes. The processing unit 134 first collects interface activity parameters, including data transmission related information of the universal flash memory storage interconnection layer 170 and/or the flash memory access interface 139 (step S310). For example, the interface activity parameters can indicate whether the device 130 enters an idle state, whether the flash memory access interface 139 is used for background operations, and the data transmission mode of the general flash memory storage interconnect layer 170. The processing unit 134 selects one of the above-mentioned frequencies for the processing unit 134 and the access interface according to the interface activity parameters (step S330), and drives the clock generator 136_1 to output the clock signal CLK1 to the processing unit 134 at the selected frequency And the clock generator 136_2 is driven to output the clock signal CLK2 to the access interface at the selected frequency, so that the processing unit 134, the universal flash memory storage interconnection layer 170, and the flash memory access interface 139 can run at a specified operating frequency (step S350) . In some embodiments of step S350, the processing unit 134 may only adjust the frequency of the clock signal CLK2 output by the clock generator 136_2, and fix the frequency of the clock signal CLK1 output by the pulse generator 136_1 at a higher level .

Refer to Figure 4. The method shown in FIG. 4 can be implemented by the processing unit 134 when loading and executing specific firmware or software commands, macrocodes or microcodes. The processing unit 134 may periodically execute a loop (steps S410 to S460), and in each round, collect interface activity parameters, and determine the clock signals CLK1 and CLK2 output by the clock generators 136_1 and 136_2 according to the interface activity parameters And drive the clock generators 136_1 and 136_2 to output clock signals CLK1 and CLK2 at the determined frequency.

The device end 130 further includes a timer 135. The processing unit 134 can set the timer 135 to restart counting for a specified period of time, such as 2, 3, or 5 milliseconds (milliseconds ms), at the beginning or at the end of each round. Whenever the timer 135 counts to the designated time, an interrupt is issued to the processing unit 134, so that the processing unit 134 can start a new round of operation frequency adjustment (step S410).

In some embodiments, the frequencies of the clock signals CLK1 and CLK2 can be adjusted to meet one of the three levels according to the collected interface activity parameters. The frequency range of the example is shown in Table 1:

When the processing unit 134 determines that the device terminal 130 needs to run at a high speed, it can drive the clock generator 136_1 to output the clock signal CLK1 at a frequency between 400 and 600 MHz and drive the clock generator 136_2 to output at a frequency between 250 and 350 MHz The clock signal CLK2. When it is determined that the device terminal 130 needs to run at a medium speed, the clock generator 136_1 can be driven to output the clock signal CLK1 at a frequency between 200 and 300 MHz and the clock generator 136_2 can be driven to output the clock at a frequency between 125 and 175 MHz. The signal CLK2. When it is determined that the device terminal 130 needs to run at a low speed, the clock generator 136_1 can be driven to output the clock signal CLK1 at a frequency between 100 and 150 MHz and the clock generator 136_2 can be driven to output the clock at a frequency between 62.5 and 87.5 MHz. The signal CLK2. The manufacturer of the device 130 can store the three-level preset frequencies of the clock signals CLK1 and CLK2 in a non-volatile memory (not shown in FIG. 1) before leaving the factory, so that the processing unit 134 can perform operating frequency adjustment Method to use.

When the processing unit 134 detects the interrupt issued by the timer 135 (step S410), it can first determine whether the device 130 needs to perform a background operation (step S420). Register 137_2 can be 1 The bit latch device 130 needs to perform background operation information, for example, "1" means required; "0" means not required. The processing unit 134 can read the value of the register 137_2 to determine whether the device terminal 130 needs to perform a background operation. The background operation is not initiated by the instruction of the host side 110, but the data access initiated by the device side 130, which can be garbage collection process (garbage collection GC process), wear leveling process (wear leveling process), read recovery process ( read reclaim process) or read update process (read reflash process).

For example, after multiple accesses, a physical page may contain valid and invalid sections (also called expired sections), where the valid section stores valid user data, and the invalid section stores invalid (old ) User data. When it is detected that the available space of the storage unit 150 is insufficient, the processing unit 134 can set a register (which can be referred to as a background-operation register) 137_2 to indicate that the device side 130 needs to perform a background operation (such as a garbage collection procedure). In the garbage collection process, the processing unit 134 drives the flash memory access interface 139 to rewrite the collected valid user data to the idle block or the empty physical page of the active block, so that these data contain invalid user data Blocks can be changed to idle blocks, and after erasing, they can be provided to other users for data storage.

For another example, due to a certain number of erasing (for example, 500, 1000, or 5000 times), the physical blocks in the storage unit 150 will be classified as bad blocks due to poor data retention capabilities. No longer use. In order to extend the service life of the physical block, the processing unit 134 continuously monitors the number of erasures of each physical block. When the number of erasures of a data block exceeds the erasure threshold, the processing unit 134 can set the register 137_2 to indicate that the device end 130 needs to perform a background operation (such as a loss averaging procedure). In the wear averaging process, the processing unit 134 drives the flash memory access interface 139 to read the user data in this data block (source block). Then, the processing unit 134 selects an idle block with the least number of erasures as the target block, and drives the flash access interface 139 to write the previously read user data to the available physical page in the selected target block.

In addition, when the start condition of the read recovery program or read update program is met, the processing unit 134 can also set the register 137_2 to indicate that the device end 130 needs to perform background operations (such as reading the recovery program or read the update program).

Since background operations need to execute a series of commands to read data from the storage unit 150 and write data to the storage unit 150, the processing unit 134, the flash memory access interface 139, and the storage unit 150 should run at a faster operating frequency. When it is determined that the device terminal 130 needs to perform a background operation (the "yes" path in step S420), the clock generator 136_1 is driven to output the clock signal CLK1 to the processing unit 134 at the highest selectable frequency and the clock generator 136_2 is driven to The selectable highest frequency output clock signal CLK2 is sent to the universal flash memory storage interconnection layer 170 and the flash memory access interface 139, so that the processing unit 134, the universal flash memory storage interconnection layer 170 and the flash memory access interface 139 can operate at the highest Operating frequency (step S430). For example, the processing unit 134 may set the register 138_1 to a value that meets the third level of CLK1 (that is, between 400 and 600 MHz) as shown in Table 1, so that the clock generator 136_1 outputs the clock signal CLK1 at a corresponding frequency according to the set value To the processing unit 134; and set the register 138_2 to a value that meets the third level of CLK2 (that is, between 250 and 350 MHz) as shown in Table 1, so that the clock generator 136_2 outputs the clock signal CLK2 to the general purpose at the corresponding frequency according to the set value The flash memory storage interconnection layer 170 and the flash memory access interface 139. It should be noted that during the background operation, the access command issued by the host terminal 110 can also be interspersed.

For situations where background operations are not required, the processing unit 134 can make the processing unit 134, the flash memory access interface 139, and the storage unit 150 run at a matching operating frequency in response to the data transmission mode between the device 130 and the host 110. When it is determined that the device end 130 does not need to perform background operations (the "No" path in step S420), the processing unit 134 obtains the running status of the device end 130 and the data transmission mode between the device end 130 and the host end 110 (step S440).

The UFS interface can run in pulse width modulation gear (PWM, Pulse-Width Modulation gear) or high-speed gear (HS, High-Speed gear). The pulse width modulation gear can be 0.5Gbps (Gigabits per second) or lower, and the high-speed gear can be 1.4Gbps or higher. The pulse width modulation gear can be called the low-speed gear. For example, Table 2 lists the data rates of different high-speed gears (HS-GEARs) defined by the UFS specification:

The high-speed HS-G1 has a Class A rate of 1248Mbps, while the high-speed HS-G1 has a Class B rate of 1248Mbps, the high-speed HS-G2 has a Class A rate of 2496Mbps, and the high-speed HS-G2 has a Class B rate of 2915.2Mbps. ,So on and so forth. Table 3 lists the data rates of different pulse width modulation files (PWMS-GEARs) defined by the UFS specification:

The data rate of low-speed PWM-G0 is between 0.01 and 3Mbps, the data rate of low-speed PWM-G1 is between 3 and 9Mbps, and the data rate of low-speed PWM-G2 is between 6 and 18Mbps, and so on analogy.

The device 130 can be configured with a register 137_1 to store the data transmission mode between the device 130 and the host 110. The register 137_1 can latch the value of at least 5 bits, of which 2 bits (also known as the mode register) represent the transmission mode (transmission mode), and the other 3 bits (also known as the gear register) represent the gear Bit (gear). For example, the mode register stores "0b00", "0b01", "0b10" and "0b11" respectively representing that the UFS interface is operating in pulse width modulation gear, PWM-auto gear, high-speed gear and HS-auto gear. The gear register stores one of "0b000" to "0b111" respectively representing the corresponding one of the 0th to 7th gears. The host terminal 110 may send a mode change command to the device terminal 130 to configure the data transmission mode between the device terminal 130 and the host terminal 110. When the flash memory controller 133 receives the mode change command, it sets the mode register and the gear register according to the instructions of the mode change command. Table 4 describes the setting examples of the mode register and gear register of different data transmission modes:

When the mode change command instructs the device terminal 130 to operate in the 0th gear of pulse width modulation, the flash memory controller 133 sets the mode register and gear register to "0b00" and "0b000" respectively. When the mode change command instructs the device terminal 130 to operate in the 0th gear from the arterial wave width modulation, the flash memory controller 133 sets the mode register and the gear register to "0b01" and "0b000" respectively. Pulse wave width modulation or other gears from arterial wave width modulation The settings can be deduced by analogy, and will not be repeated for the sake of brevity. When the mode change command instructs the device terminal 130 to operate in the first high-speed gear, the flash memory controller 133 sets the mode register and gear register to "0b10" and "0b001" respectively. When the mode change command instructs the device terminal 130 to operate in the first gear of the automatic high speed, the flash memory controller 133 sets the mode register and the gear register to "0b11" and "0b001" respectively. The rest of the gear settings for high-speed or auto-high-speed can be deduced by analogy and will not be repeated for the sake of simplicity.

When the device 130 is running at the auto-arterial wave width modulation gear or automatic high-speed gear, and there is no data transmission with the host 110 for a preset period of time, the device 130 will automatically enter the idle state. , Used to close some circuits and save power consumption. The device terminal 130 may further be provided with a register (not shown in FIG. 1), coupled to the processing unit 134, for latching information on whether the device terminal 130 enters the idle state.

After the processing unit 134 obtains the operating status of the device 130 and the data transmission mode between the device 130 and the host 110 (step S440), it selects one of multiple frequencies accordingly (step S450). Refer to the division of frequency levels shown in Table 1. The processing unit 134 can determine the frequency of the processing unit 134, the flash access interface 139, and the storage unit 150 according to the contents of the register 137_1 using the following rules: (1) When the device 130 enters the idle state, regardless of the data transmission mode, select the A horizontal frequency; (2) When the device 130 is not in an idle state and the data transmission mode is pulse wave width modulation or auto-arterial wave width modulation, select the frequency that meets the first level regardless of the gear position; (3) When the device 130 does not enter the idle state and the data transmission mode is high-speed or automatic high-speed first gear, select the frequency that meets the second level; and (4) when the device 130 does not enter the idle state and the data transmission mode is high-speed or automatic For high-speed second gear or third gear, select the frequency that meets the third level.

After the processing unit 134 selects one of the multiple frequencies according to the data transmission mode (step S450), the clock generator 136_1 is driven to output the clock signal CLK1 to the processing unit 134 at the selected frequency and the clock generator 136_2 is driven to select the frequency Output clock signal CLK2 gives the universal flash memory storage interconnection layer 170 and the flash memory access interface 139 so that the processing unit 134, the universal flash memory storage interconnection layer 170 and the flash memory access interface 139 can run at a specified operating frequency (step S460). For example, when the data transmission mode is high-speed or automatic high-speed first gear, the processing unit 134 can set the register 138_1 to a value that meets the second level of CLK1 (that is, between 200 and 300 MHz) as shown in Table 1, so that the clock The generator 136_1 outputs the clock signal CLK1 to the processing unit 134 at the corresponding frequency according to the set value; and sets the register 138_2 to a value corresponding to the second level of CLK2 (that is, between 125 and 175 MHz) as shown in Table 1, so that the clock generator 136_2 outputs a clock signal CLK2 to the general flash memory storage interconnection layer 170 and the flash memory access interface 139 at a corresponding frequency according to the set value. In some embodiments of step S460, the processing unit 134 may only adjust the frequency of the clock signal CLK2 output by the clock generator 136_2, while keeping the frequency of the clock signal CLK1 output by the pulse generator 136_1 at a specific level.

The interface activity parameters described in step S310 in FIG. 3 may include all or part of the values in the registers 137_1 and 137_2.

The device end 130 of the flash memory system architecture 100 shown in FIG. 1 can be further modified to allow the processing unit 134 to control only one clock generator to allow the processor 134 and the access interface (including the general flash memory storage interconnection layer) 170 and flash memory access interface 139) run at different operating frequencies. Refer to Figure 5. The modified device end 530 can be provided with a frequency divider 535, which is coupled between the clock generator 136_1, the universal flash memory storage interconnection layer 170 and the flash memory access interface 139 for inputting a frequency from the clock generator 136_1 The clock signal CLK1 generates a clock signal CLK2 with a frequency of 1/2, 3/5 or 2/3, and outputs the clock signal CLK2 to the general flash memory storage interconnection layer 170 and the flash memory access interface 139. In response to the modified device end 530, as shown in FIG. 4, step S430 can be modified to: the processing unit 134 sets the register 138_1 to a value corresponding to the third level of CLK1 (that is, between 400 and 600 MHz) as shown in Table 1, and drives the clock The generator 136_1 outputs the clock signal CLK1 to the processing unit 134 and the frequency divider 535 at a corresponding frequency according to the set value, so that the frequency divider 535 generates and outputs a clock signal CLK2 with a frequency of 2/5, 1/2 or 2/3 to Universal flash memory storage interconnection layer 170 and flash Deposit and access interface 139. In addition, as shown in FIG. 4, step S460 can be modified to drive the clock generator 136_1 to output the clock signal CLK1 to the processing unit 134 and the frequency divider 535 at the selected frequency, so that the frequency divider 535 generates and outputs 1/2, 3 The clock signal CLK2 with the selected frequency of /5 or 2/3 is sent to the universal flash memory storage interconnection layer 170 and the flash memory access interface 139.

It should be noted here that when the processing unit 134 further includes a circuit for adjusting the clock signal CLK1, the frequency of the clock signal CLK1 is not necessarily equal to the operating frequency of the processing unit 134 during operation. When the host access interface 170 or the flash memory access interface 139 further includes a circuit for adjusting the clock signal CLK2, the output frequency of the clock signal CLK2 is not necessarily equal to the operation of the host access interface 170 or the flash memory access interface 139 during operation frequency. However, those skilled in the art can understand that an increase in the output frequency of the clock signal CLK1 will result in an increase in the operating frequency of the processing unit 134 during operation, and vice versa. The faster output frequency of the clock signal CLK2 will result in faster operating frequencies of the host access interface 170 and the flash memory access interface 139, and vice versa.

Several use cases are presented below to illustrate how to apply the above-mentioned operating frequency adjustment device and method.

In the first use case, it is assumed that the device terminal 130 does not perform background operations: at the beginning, the host terminal 110 sends a mode change command to the device terminal 130, instructing the device terminal 130 to operate in a specific gear of automatic high speed. When the flash memory controller 133 receives the mode change command, the register 137_1 is set to latch the information of the data transmission mode. At this time, the device end 130 enters an active state. Then, the processing unit 134 reads the register 137_1 (step S440), and drives the clock generator 136_1 according to the data transmission mode to output the clock signal CLK1 to the processing unit 134 at a corresponding frequency (for example, a frequency that matches the second or third level of CLK1) In addition, the clock generator 136_2 is driven to output the clock signal CLK2 to the access interface at a corresponding frequency (for example, a frequency corresponding to the second or third level of CLK2), so that the processing unit 134, the general flash memory storage interconnection layer 170 and the flash memory are accessed The interface 139 can run at a desired operating frequency (steps S450 to S460). Then, if there is no data transmission with the host 110 for a preset period of time, the device 130 automatically enters the idle state. state. The processing unit 134 detects that it enters the idle state (step S440), drives the clock generator 136_1 to output the clock signal CLK1 to the processing unit 134 at a frequency that matches the first level of CLK1, and drives the clock generator 136_2 to meet the first level of CLK2 The clock signal CLK2 is output to the access interface, so that the processing unit 134, the universal flash memory storage interconnection layer 170, and the flash memory access interface 139 can run at a slower operating frequency, thereby saving power consumption (steps S450 to S460) .

In the second use case, it is assumed that the device terminal 130 does not perform background operations: at the beginning, the host terminal 110 sends a mode change command to the device terminal 130, instructing the device terminal 130 to operate in a specific gear of high speed or automatic high speed. When the flash memory controller 133 receives the mode change command, the register 137_1 is set to latch the information of the data transmission mode. Next, the processing unit 134 reads the register 137_1 (step S440), and drives the clock generator 136_1 according to the data transmission mode to output the clock signal CLK1 to the processing unit 134 at a corresponding frequency (for example, a frequency that matches the second or third level of CLK1). The driving clock generator 136_2 outputs the clock signal CLK2 to the access interface at a corresponding frequency (for example, a frequency that corresponds to the second or third level of CLK2), so that the processing unit 134, the universal flash memory storage interconnection layer 170, and the flash memory access interface 139 can run at the desired operating frequency (steps S450 to S460). Then, the host terminal 110 sends a mode change command to the device terminal 130, instructing the device terminal 130 to operate in a specific gear of pulse wave width modulation or self-arterial wave width modulation (that is, the changed data transmission mode). When the flash memory controller 133 receives the mode change command, the register 137_1 is set to latch the information of the data transmission mode after the change. Next, the processing unit 134 reads the register 137_1 (step S440), and drives the clock generator 136_1 according to the changed data transmission mode to output the clock signal CLK1 to the processing unit 134 and drives the clock generator 136_2 at a frequency consistent with the first level of CLK1 The clock signal CLK2 is output to the access interface at a frequency consistent with the first level of CLK2, so that the processing unit 134, the universal flash memory storage interconnection layer 170, and the flash memory access interface 139 can run at a slower operating frequency, thereby saving power consumption (Steps S450 to S460).

In the third use case, assume that the device 130 does not perform background operations: in the beginning, the main The machine terminal 110 sends a mode change command to the device terminal 130, instructing the device terminal 130 to operate in the second or third gear of high speed or automatic high speed. When the flash memory controller 133 receives the mode change command, the register 137_1 is set to latch the information of the data transmission mode. Next, the processing unit 134 reads the register 137_1 (step S440), drives the clock generator 136_1 according to the data transmission mode to output the clock signal CLK1 to the processing unit 134 at a frequency that matches the third level of CLK1, and drives the clock generator 136_2 to match The third level frequency of CLK2 outputs the clock signal CLK2 to the access interface, so that the processing unit 134, the universal flash memory storage interconnection layer 170 and the flash memory access interface 139 can run at the desired operating frequency (steps S450 to S460). Then, the host terminal 110 sends a mode change command to the device terminal 130, instructing the device terminal 130 to operate in the first gear of high speed or automatic high speed (that is, the changed data transmission mode). When the flash memory controller 133 receives the mode change command, the register 137_1 is set to latch the information of the data transmission mode after the change. Next, the processing unit 134 reads the register 137_1 (step S440), and drives the clock generator 136_1 according to the changed data transmission mode to output the clock signal CLK1 to the processing unit 134 and drives the clock generator 136_2 at a frequency that matches the second level of CLK1 The clock signal CLK2 is output to the access interface at a frequency that matches the second level of CLK2, so that the processing unit 134, the universal flash memory storage interconnection layer 170, and the flash memory access interface 139 can run at a slower operating frequency, thereby saving power consumption (Steps S450 to S460).

The method steps for adjusting the operating frequency performed by the processing unit 134 can be implemented by a computer program product composed of one or more functional modules. These functional modules are stored in a non-volatile storage device, and can be loaded and executed by the processing unit 134 at a specific time. Refer to Figure 6. The processing unit 134 executes the Interrupt Handler Module (Interrupt Handler Module) 610 to complete part of the operation of step S310 and the operation of step S410, executes the background operation detection module 620 to complete the operation of step S420, and executes device-side operation status and data transmission mode detection The test module 630 is to complete part of the operation of step S310 and the operation of step S440, the frequency selection module 640 is executed to complete the operations of step S330 and step S450, and the clock generator driving module 650 is executed to complete the operations of steps S350, S430 and S460. operating. The background operation detection module 620 can call one of the operating state of the device and the data transmission mode detection module 630 and the clock generator driving module 650 according to the detection result. The background operation detection module 620 and the frequency selection module 640 can use parameters to transmit the selected frequency to the clock generator driving module 650.

All or part of the steps in the method of the present invention can be implemented by a computer program, such as a computer operating system, a specific hardware driver in the computer, or a software application program. In addition, it can also be implemented in other types of programs as shown above. Those with ordinary knowledge in the technical field can write the method of the embodiments of the present invention into a computer program, which will not be described for brevity. The computer program implemented according to the method of the embodiment of the present invention can be stored in an appropriate computer readable data carrier, such as DVD, CD-ROM, USB disk, hard disk, and can also be placed on the Internet (for example, the Internet Or other appropriate vehicle).

Although FIGS. 1 and 5 include the above-described components, it is not excluded that, without violating the spirit of the invention, more other additional components can be used to achieve better technical effects. In addition, although the flowcharts in Figures 3 and 4 are executed in the specified order, those skilled in the art can modify the order of these steps under the premise of achieving the same effect without violating the spirit of the invention. Therefore, this The invention is not limited to using only the sequence described above. In addition, those skilled in the art can also integrate several steps into one step, or in addition to these steps, perform more steps sequentially or in parallel, and the present invention is not limited thereby.

Although the present invention is described using the above embodiments, it should be noted that these descriptions are not intended to limit the present invention. On the contrary, this invention covers modifications and similar arrangements that are obvious to those skilled in the art. Therefore, the scope of applied claims must be interpreted in the broadest way to include all obvious modifications and similar settings.

S310~S350: method steps

Claims (19)

A computer program product, which is loaded and executed by a processing unit on a device side, and includes the following code: collecting an interface activity parameter, wherein the interface activity parameter includes a host access interface and/or a flash memory access interface Data transmission information; select one from a plurality of first frequencies according to the interface activity parameters; and drive a first clock generator to output a first clock signal of the selected first frequency, so that the host stores The fetch interface and/or the flash memory access interface runs at a first operating frequency, wherein, when the interface activity parameter indicates that the device side needs to perform a background operation, the selected first frequency is the largest of the first frequencies By. The computer program product according to claim 1, comprising the following code: selecting one from a plurality of second frequencies according to the interface activity parameter; and driving a second clock generator to output the selected second frequency A second clock signal of, so that the processing unit runs at a second operating frequency. The computer program product of claim 1, wherein the first clock signal of the selected first frequency is output to the processing unit, so that the processing unit runs at a second operating frequency: the selected first frequency The first clock signal of the frequency is output to a frequency divider; and the frequency divider outputs a second clock signal of a second frequency to the host access interface and/or the flash memory access interface, so that the The host access interface and/or the flash memory access interface run at the first operating frequency. The computer program product according to claim 1, wherein the background operation is not initiated by an instruction from a host, but data access initiated by the device. The computer program product according to claim 1, wherein, when the interface activity parameter indicates that the device side does not need to perform background operations and the device side enters an idle state, the selected first frequency is the first frequency The smallest. The computer program product of claim 1, wherein when the interface activity parameter indicates that the device side does not need to perform background operations, the device side does not enter an idle state, and the data transmission mode of a host side and the device side is pulse In the case of wave width modulation or self-arterial wave width modulation, the selected first frequency is the smallest one of the first frequencies. The computer program product of claim 1, wherein, when the interface activity parameter indicates that the device side does not need to perform background operations, the device side does not enter an idle state, and the data transmission mode of a host side and the device side is high-speed Or in the second or third gear of automatic high speed, the selected first frequency is the largest of the first frequencies. The computer program product of claim 1, wherein, when the interface activity parameter indicates that the device side does not need to perform background operations, the device side does not enter an idle state, and the data transmission mode of a host side and the device side is high-speed Or in the first gear of automatic high speed, the selected first frequency is lower than the largest of the first frequencies. An operating frequency adjustment method, executed by a processing unit on a device side, includes: collecting an interface activity parameter, wherein the interface activity parameter includes data transmission information of a host access interface and/or a flash memory access interface; according to the interface The activity parameter selects one from a plurality of first frequencies; and drives a first clock generator to output a first clock signal of the selected first frequency, so that the host access interface and/or the flash memory The interface is selected to run at a first operating frequency, wherein when the interface activity parameter indicates that the device needs to perform a background operation, the selected first frequency is the largest of the first frequencies. An operating frequency adjustment device, comprising: a first clock generator; and a processing unit coupled to the first clock generator to collect an interface activity parameter, wherein the interface activity parameter includes a host access interface and/ Or data transmission information of a flash memory access interface; select one from a plurality of first frequencies according to the interface activity parameter; and drive the first clock generator to output a selected first frequency The first clock signal causes the host access interface and/or the flash memory access interface to run at a first operating frequency, wherein when the interface activity parameter indicates that the device needs to perform a background operation, the selected second A frequency is the largest of the first frequencies. The operating frequency adjusting device according to claim 10, comprising: a second clock generator coupled to the processing unit, wherein the processing unit selects one of a plurality of second frequencies according to the interface activity parameter; and drives The second clock generator outputs a second clock signal of the selected second frequency, so that the processing unit runs at a second operating frequency. The operating frequency adjustment device according to claim 10, comprising: a frequency divider coupled to the first clock generator, wherein the first clock signal of the selected first frequency is output to the processing unit , Making the processing unit run at a second operating frequency: the first clock signal of the selected first frequency is output to the frequency divider; and the frequency divider outputs a second clock of a second frequency Signals are given to the host access interface and/or the flash memory access interface, so that the host access interface and/or the flash memory access interface operate at the first operating frequency according to the second clock signal of the second frequency. The operating frequency adjustment device according to claim 12, wherein the second frequency is 1/2, 3/5 or 2/3 of the first frequency. The operating frequency adjustment device according to claim 10, wherein the selected first frequency is between 250 and 350 MHz. The operating frequency adjustment device according to claim 14, wherein the background operation is a garbage collection process, a wear leveling process, a read recovery process, or a read update process. The operating frequency adjustment device of claim 10, wherein, when the interface activity parameter indicates that the device side does not need to perform background operations and the device side enters an idle state, the selected first frequency is the first frequency The smallest one, and between 62.5~87.5MHz. The operating frequency adjustment device of claim 10, wherein when the interface activity parameter indicates that the device side does not need to perform background operations, the device side does not enter an idle state, and the data transmission mode of a host side and the device side is In pulse wave width modulation or auto-arterial wave width modulation, the selected first frequency is the smallest one of the first frequencies. The operating frequency adjustment device of claim 10, wherein when the interface activity parameter indicates that the device side does not need to perform background operations, the device side does not enter an idle state, and the data transmission mode of a host side and the device side is In high-speed or automatic high-speed second gear or third gear, the selected first frequency is the largest of the first frequencies and is between 250-350 MHz. The operating frequency adjustment device of claim 10, wherein when the interface activity parameter indicates that the device side does not need to perform background operations, the device side does not enter an idle state, and the data transmission mode of a host side and the device side is In the first gear of high-speed or automatic high-speed, the selected first frequency is lower than the largest of the first frequencies and is between 125 and 175 MHz.

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