TWI697005B - Testing device and testing method - Google Patents

Abstract

A testing device includes a transfer interface, a tester, a first socket group and a second socket group. The first socket group includes a plurality of tested devices coupled in series and the second socket group includes a plurality of tested devices coupled in series. The tester is electrically connected to the socket group via the transfer interface. The transfer interface is configured to merge a first testing signal with a second testing signal to generate a double frequency testing signal. The double-frequency testing signal and a plurality of control signals are provided to the tested devices in the first socket group and the second socket group to perform the testing procedure on the tested devices of a same tested device pair simultaneously, and performing the testing procedure on the tested device pairs sequentially.

Description

Test device and test method

The invention relates to a testing device and a testing method, and in particular to a testing device and a testing method which can improve the testing efficiency and productivity during the testing process.

After IC manufacturing, wafer acceptance test (WAT), chip probing (CP), and package assembly, an appropriate tester should be used to perform final tests on the electronic functions of the memory device (final tests, FT). In general, the maximum test frequency provided by the tester is fixed. However, the operating frequency of memory devices continues to increase, which makes existing testers unable to test high-frequency memory devices in the next generation. The traditional frequency doubling method by changing the circuit board interface or the so-called Device Specific Adapter (DSA) is proposed. Therefore, the two input/output (I/O) terminals of the tester are connected to one pin of the circuit board interface to achieve the purpose of frequency doubling. However, test efficiency and production capacity may be greatly reduced. In addition, when a single high-frequency test signal is compared with a frequency-doubled test signal, the test accuracy will be greatly reduced and errors may occur.

Therefore, there is a need for a test device and test method with high test frequency and high productivity, thereby improving the test efficiency of the test program.

The invention provides a testing device and a testing method which can improve the testing efficiency and the productivity during the testing process.

The invention provides a testing device. Test device tester, transmission interface, first socket group and second socket group. The tester has a first input/output terminal and a second input/output terminal, wherein the first input/output terminal is configured to provide a first test signal and the second input/output terminal is configured to provide a second test signal. The transmission interface is coupled to the tester. The transmission interface is configured to combine the first test signal and the second test signal received by the tester to generate a multiplier test signal. The first socket set has a plurality of first devices under test coupled in series and is coupled to the transmission interface to receive the frequency-doubled test signal. The second socket set has a plurality of second devices under test coupled in series and is coupled to the transmission interface to receive the frequency-doubled test signal.

In an embodiment of the present invention, the plurality of first devices to be tested respectively correspond to the plurality of second devices to be tested, and the plurality of first devices to be tested respectively form corresponding to the plurality of second devices to be tested A pair of devices under test, wherein the first device under test and the second device under test of the same pair of devices under test simultaneously receive the frequency-doubled test signal.

The invention provides a test method. The test method includes the following steps: receiving the first test signal from the first input/output terminal and receiving the second test signal from the second input/output terminal; combining the first test signal and the second test signal to generate a multiplied test signal ; Grouping multiple first devices under test in series into a first socket group, and grouping multiple second devices under test in a second socket group; and performing a first test procedure in which the multiplier test signal And the multiple control signals are provided to the multiple devices under test via the first socket group and the second socket group.

Based on the above, by combining multiple test signals into a frequency-doubled test signal and using the frequency-multiplied test signal to execute a test procedure, the tester can test the device under test at a high frequency. In addition, by coupling the devices under test of the first socket group and the second socket group in series and forming a plurality of pairs of devices under test, the tester can perform parallel tests on multiple devices under test at high frequencies. Therefore, the efficiency of the test procedure and the test productivity can be improved.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below and described in detail in conjunction with the accompanying drawings.

The present invention can be more easily understood by the description of the following embodiments by referring to the drawings. Among them, the drawings are simplified for describing the structure or method of the present invention. Therefore, the actual parts, actual shapes, actual dimensions, and actual proportions are not used for the parts shown in the figures. Some sizes or size ratios have been enlarged or simplified to provide a better description. The actual number, actual shape or actual size ratio can be selectively designed and arranged, and the detailed component layout may be more complicated.

Please refer to FIG. 1, the test device 100 includes a tester 120 and a socket board (SB). The socket board (SB) includes a transmission interface 110 and a socket board 130. The transmission interface 110 is included in the Hi-Fix socket board, and is connected between the tester 120 and the socket board 130.

The tester 120 includes a first input/output terminal IO1 and a second input/output terminal IO2. The first input/output terminal IO1 is configured to provide a first test signal to the transmission interface 110; the second input/output terminal IO2 is configured to provide a second test signal to the transmission interface 110. The frequency of the first test signal and the frequency of the second test signal may be the same or different. In one embodiment, the first test signal and the second test signal have the same frequency, but there is a difference in transmission time when the first test signal and the second test signal are transmitted by the tester 120. It should be noted that the present invention is not limited to the number of input/output terminals of the tester 120.

The transmission interface 110 includes a signal intersection 111, a first bus 112, a second bus 113, a third bus 114, and a fourth bus 115. The first input/output terminal IO1 is coupled to the signal crossing point 111 through the first bus 112, so that the first test signal from the first input/output terminal IO1 is transmitted to the signal crossing point 111 through the first bus 112. The second input/output terminal IO2 is coupled to the signal cross point 111 via the second bus 113, so that the second test signal from the second input/output terminal IO2 is transmitted to the signal cross point 111 via the second bus 113. After the transmission interface 110 receives the first test signal and the second test signal, the signal intersection 111 merges the first test signal and the second test signal to generate a multiplied test signal. The frequency of the frequency-doubled test signal may be the frequency of the first test signal or twice the frequency of the second test signal.

The transmission path of the first bus 112 and the transmission path of the second bus 113 may be as shown in FIG. 1, respectively, which allows the signal cross point 111 to receive the first test signal and the second test signal without time delay and Avoid merge errors caused by delayed transmission times.

As shown in FIG. 1, the socket board 130 may further include a first socket group 131 and a second socket group 132. The first socket group 131 and the second socket group 132 are configured to accommodate a plurality of devices to be tested. Each socket of the first socket group 131 and the second socket group 132 may be one of a plurality of devices to be tested, and each device to be tested includes one or more chips assembled therein ( Not shown).

The first socket group 131 may include a plurality of sockets accommodating a plurality of devices under test 1311~131n coupled in series. The second socket group 132 may include a plurality of sockets that accommodate a plurality of devices under test 1321˜132n coupled in series. The devices under test 1311~131n of the first socket group 131 respectively correspond to the devices under test 1321~132n of the second socket group 132. The devices under test 1311 to 131n of the first socket group 131 and the corresponding devices under test 1321 to 132n of the second socket group 132 respectively form a plurality of pairs of devices 133 to be tested. In the same device under test pair, the device under test in the first socket group 131 and the device under test in the second socket group 132 simultaneously receive the frequency-doubled test signal, so as to simultaneously execute the test procedure.

In an embodiment of the invention, the tester 120 provides a plurality of control signals CS0~CSn to the first socket group 131 and the second socket group 132. The same control signal is provided to the device under test in the same device under test pair to enable the test procedure of the device under test. As shown in FIG. 1, the device under test 1311 and the device under test 1321 located in the device under test pair 133 receive the same control signal CS0 so that the devices under test 1311 and 1321 can simultaneously execute the test procedure. By analogy, the devices under test 131n and 132n belong to the same pair of devices under test and receive the same control signal CSn so that the devices under test 131n and 132n simultaneously execute the test procedure. Where n is an integer greater than 1.

The frequency-doubled test signal and the control signals CS0~CSn are also transmitted to the multiple devices under test in the first socket group 131 and the second socket group 132 to perform the test procedure. The device under test can output multiple feedback signals. Here, the devices under test 1311 to 131n of the first socket group 131 transmit at least one first feedback signal to the signal intersection 111. The devices under test 1321~132n of the second socket group 132 transmit at least one second feedback signal to the signal cross point 111. The transmission interface 110 duplicates the first feedback signal or the second feedback signal to generate multiple identical feedback signals. Part of the same feedback signal is transmitted from the signal cross point 111 to the first input/output terminal IO1 through the first bus 112, and another part of the same feedback signal is transmitted from the signal cross point 111 to the second through the second bus 113 Input/output terminal IO2. The tester 120 receives the same feedback signal from the device under test at different input/output terminals IO1 and IO2 and correlates the first test signal and the second test signal to complete the test of the device under test.

As shown in FIG. 1, the transmission path of the third bus 114 and the transmission path of the fourth bus 115 are basically the same, which enables the signal cross point 111 to transmit the combined multiple of the first test signal and the second test signal Test signals without any time delay. Since the transmission path of the first bus 112 and the transmission path of the second bus 113 are basically the same, the input/output terminal IO1 and the input/output terminal IO2 can simultaneously receive the same feedback signal transmitted by the signal crosspoint 111 to Time delay on test results. In FIG. 1, the first socket group 131 is coupled to the first termination line 134, and the second socket group 132 is coupled to the second termination line 135. The termination lines 134 and 135 each have a resistance value Rterm and a voltage value Vterm. The voltage value Vterm can be changed according to the type of test device being tested. For example, when the device under test is Double Data Rate (DDR) memory DDR1, DDR2, DDR3 or lower power double data rate (LPDDR) memory LPDDR1, LPDDR2, In LPDDR, the voltage value Vterm can be set to half of the power supply voltage value VDDQ provided to the output buffer of the memory chip (1/2*VDDQ). When the device under test is DDR4, the voltage value Vterm can be set equal to VDDQ. When the device under test is LPDDR4, the voltage value Vterm can be set to 0V.

In order to execute the test procedure of the device under test pair 133, the device under test 1311, 1321 in the device under test pair 133 is provided with the control signal CS0 from the tester 120 and the frequency multiplier provided by the transmission interface via the bus 114, 115 Test signal. The control signal CS0 causes the same device under test to simultaneously execute the test procedure of the frequency-doubled test signal to the devices under test 1311 and 1321 in 133.

The test procedure is sequentially executed on the pair of devices under test. That is to say, after the test program execution is completed on the device pair under test including the devices under test 1311, 1321, the test program is executed on the next device pair under test including the devices under test 1312, 1322. In this way, the test procedure is sequentially executed on the pair of devices under test.

Taking the test device 100 having 8 input/output terminals as an example, the tester 120 of the test device 100 may include 8 first input/output terminals IO1_0~IO1_7 (not shown) that are independent of each other, and 8 second terminals that are independent of each other Input/output terminals IO2_0~IO2_7 (not shown). The transmission interface 110 of the test device 100 may include eight independent signal crosspoints 111_0~111_7 (not shown), eight mutually independent first busbars 112_0~112_7 (not shown) to represent, and eight mutually independent Of the second bus 113_0~113_7 (not shown), eight independent third bus 114_0~114_7 (not shown), and eight independent fourth bus 115_0~115_7 (not shown) . The socket board 130 of the testing device 100 includes a pair of independent device pairs 133 and eight independent termination lines 134_0~134_7, 135_0~135_7. The pair of devices under test 133 includes devices under test 1311 and 1321. The device under test 1311 will correspond to the first input/output terminals IO1_0~IO1_7 and the second input/output terminals IO2_0~IO2_7. The device under test 1321 will correspond to the first input/output terminals IO1_0~IO1_7 and the second input/output terminals IO2_0~IO2_7. In this example, the first input/output terminal IO1_0, the second input/output terminal IO2_0, the signal cross point 111_0, the first bus 112_0, the second bus 113_0, the third bus 114_0, the fourth bus 115_0, The devices under test 1311, 1321 and the termination lines 134_0, 135_0 of the device under test pair 133 can be independently constructed to form the 0th test group of the test device 100. First input/output terminal IO1_1, second input/output terminal IO2_1, signal cross point 111_1, first bus 112_1, second bus 113_1, third bus 114_1, fourth bus 115_1, device under test pair 133 The devices under test 1311, 1321 and the termination lines 134_1, 135_1 can be independently constructed as the first test group of the test device 100, and so on. In this way, the test device 100 with 8 sets of input/output pins connected to each other can be constructed to form 8 IO test groups with input/output pins connected independently of each other.

Please refer to FIG. 2, the testing device 200 includes a tester 220 and a socket board (SB). The socket board (SB) includes a transmission interface 210 and a socket board 230. The tester 220 and the transmission interface 210 are similar to the tester 120 and the transmission interface 110 in FIG. 1, so detailed descriptions of these elements are omitted here. The socket board 230 includes a first socket group 231 and a second socket group 232. The first socket group 231 includes a plurality of devices under test 2311~231n coupled in series, and the second socket group 232 includes a plurality of devices under test coupled in series 2321~232n. The devices under test 2311 to 231n of the first socket group 231 and the devices under test 2321 to 232n of the second socket group 232 form a plurality of pairs of devices to be tested 233, wherein the test procedure is simultaneously executed on the devices of the same pair And it is executed in sequence on multiple pairs of devices under test. The first socket group 231 and the second socket group 232 are coupled to the same termination line 234.

Taking a test device 200 having 8 input/output terminals as an example, the tester 220 of the test device 200 may include 8 first input/output terminals IO1_0~IO1_7 (not shown) that are independent of each other, and 8 second terminals that are independent of each other Input/output terminals IO2_0~IO2_7 (not shown). The transmission interface 210 of the testing device 200 may include eight independent signal cross points 211_0~211_7 (not shown). The socket board 230 of the test device 200 includes a pair of independent device-to-be-tested pairs 233 and eight independent termination lines 234_0~234_7 (not shown). The pair of devices under test 233 includes devices under test 2311, 2321. The device under test 2311 corresponds to the first input/output terminal IO1_0~IO1_7 and the second input/output terminal IO2_0~IO2_7. The device under test 2321 will correspond to the first input/output terminals IO1_0~IO1_7 and the second input/output terminals IO2_0~IO2_7. In this example, the first input/output terminal IO1_0, the second input/output terminal IO2_0, the signal cross point 211_0, the device under test 2311, 2321 of the device under test pair 233, and the termination line 234_0 can be independently constructed as the test device 200 The 0th test group. The first input/output terminal IO1_1, the second input/output terminal IO2_1, the signal cross point 211_1, the device under test 2311, 2321 of the device under test pair 233, and the termination line 234_1 can be independently constructed as the first test group of the test device 200 ,So on and so forth. In this way, the test device 200 having 8 sets of input/output pins connected to each other can be constructed to form 8 test groups whose input/output pins are independently connected to each other.

Please refer to FIG. 3A to FIG. 3D. FIG. 3A to FIG. 3D are timing diagrams illustrating the first test signal, the second test signal, and the multiplier test signal during the test procedure (writing procedure) according to different embodiments. The first test signal and the second test signal may include a plurality of pulses with different levels (such as high level pulses and low level pulses). The frequency of the frequency-doubled test signal may be twice the frequency of the first test signal or twice the frequency of the second test signal.

Please refer to FIG. 1 and FIG. 3A to FIG. 3D. The test method using the test device 100 will be described below. The tester 120 provides the first test signal and the second test signal to the transmission interface 110 via the bus bars 112 and 113, respectively. The signal cross point 111 of the transmission interface 110 merges the first test signal and the second test signal to generate a multiplied test signal and provides the multiplied test signal to the first socket group 131 and the second socket group 132. At the same time, the tester 120 provides the control signals CS0~CSn to the devices under test of the first socket group 131 and the second socket group 132. The devices under test in the same pair of devices under test simultaneously receive the frequency-doubled test signal, and the devices under test in the same pair of devices under test simultaneously receive the same control signal. Therefore, the device under test of the same device under test pair will simultaneously execute the test procedure. The control signals CS0~CSn are configured to sequentially execute the test procedure on the device under test. In this example, the control signals CS0~CSn are delayed from each other, so that the control signals CS0~CSn can sequentially cause the device under test to execute the test procedure. However, the invention is not limited to this, the control signals CS0~CSn can enable the device-under-test pair in different ways.

In FIG. 3A, each first test signal may include a high-level pulse followed by a low-level pulse. The present invention does not limit the first test signal and the second test signal to any specific waveform or level. The first test signal and the second test signal can be provided according to test requirements.

For example, in FIG. 3B, the first test signal may include a low-level pulse followed by a high-level pulse, and the second test signal may include a high-level pulse followed by a low-level pulse. Alternatively, in FIG. 3C, the first test signal includes a pulse formed by two low-level pulses, then the third state voltage level, and the second test signal may include the third state voltage level, and then The pulse formed by the other two high-level pulses. In FIG. 3D, the first test signal may include a third state voltage level, then a pulse formed by two high level pulses, and the second test signal may include a pulse formed by two high level pulses, Then comes the third state voltage level. The multiplier test signal is generated based on the first test signal and the second test signal. The frequency of the multiplier test signal may be the frequency of the first test signal or twice the frequency of the second test signal.

FIG. 3E shows a timing diagram of the same feedback signal detected by the device under test at different input/output terminals during the reading procedure. Here, the detected timing is shown by the upward arrow in FIG. 3E. It should be noted that the waveforms of the same feedback signal shown in FIG. 3E are for illustration purposes only, and different waveforms of the same feedback signal also fall within the scope of the present application.

Referring to FIGS. 1 and 3E, the first feedback signal transmitted by the device under test provided in the first socket group 131 is transmitted to the signal cross point 111 via the third bus 114. The transmission interface 110 duplicates and shares the first feedback signal to generate multiple identical first feedback signals. One of the same first feedback signal is transmitted to the input/output terminal IO1 through the signal cross point 111 and the first bus 112, and the other of the same first feedback signal passes through the signal cross point 111 and the second bus 113 is transferred to the input/output terminal IO2. The tester 120 receives a plurality of the same first feedback signals from different input/output terminals IO1, IO2 and associates the same first feedback signal with the first test signal and the second test signal to complete the test setting on the first The reading procedure of one of the devices under test in the socket group 131. During the synchronous or asynchronous reading procedure for one of the devices under test in the first socket group 131, the second feedback signal transmitted by the other device under test in the second socket group 132 passes through the fourth bus 115 It is transmitted to the signal cross point 111. The transmission interface 110 duplicates the second feedback signal to generate a plurality of identical second feedback signals, wherein one of the same second feedback signals is transmitted to the input/output terminal IO1 via the signal intersection 111 and the first bus 112. The other of the same second feedback signal is transmitted to the input/output terminal IO2 via the signal cross point 111 and the second bus 113. The tester 120 can receive a plurality of the same second feedback signals from different input/output terminals, and associate the same second feedback signal with the first test signal and the second test signal to complete the test and set it on the second socket The reading procedure of another device under test in group 132.

4 is a test method according to an embodiment of the invention. In step S401, the first test signal from the first input/output terminal is received, and the second test signal from the second input/output terminal is received. In step S403, the first test signal and the second test signal are combined to generate a frequency-doubled test signal. In step S405, multiple devices under test are grouped into a first socket group and a second socket group. The first socket group includes a plurality of first devices to be tested connected in series. The second socket group includes a plurality of second devices to be tested connected in series. In step S407, the first test procedure is executed, in which the multiplier test signal and the plurality of control signals are provided to the device under test through the first socket group and the second socket group.

In the embodiment of the present invention, the test signal is combined by the signal cross point of the transmission interface to generate a frequency-doubled test signal. The generated frequency doubling test signal and the corresponding feedback signal are copied and shared for high frequency writing and reading. Therefore, the tester can simultaneously execute the test procedure at a high frequency. In addition, there is a first socket group including a plurality of devices under test coupled in series and a second socket group including a plurality of devices under test coupled in series. The device under test in the first socket group and the corresponding device under test in the second socket group form a plurality of pairs of devices under test, and each pair of devices under test simultaneously receives the frequency-doubled test signal and receives the same control signal. In the above manner, the test devices of the same test device pair simultaneously execute the test procedure. In addition, by simultaneously executing the test procedure on the device-under-test of the same device-under-test pair and sequentially executing the test procedure on a plurality of device-under-test pairs, the test efficiency and test productivity of the test procedure can be improved.

Although the present invention has been disclosed as above by the embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

100、200‧‧‧Test device 110、210‧‧‧Transmission interface 111, 211‧‧‧ signal intersection 112‧‧‧First bus 113‧‧‧Second bus 114‧‧‧The third bus 115‧‧‧The fourth bus 120、220‧‧‧Tester 130、230‧‧‧Socket board 131、231‧‧‧First socket group 1311~131n, 1321~132n, 2311~231n, 2321~232n 132、232‧‧‧Second socket group 133, 233‧‧‧ Pair of devices to be tested 134, 135, 234 CS0~CSn‧‧‧Control signal IO1‧‧‧First input/output IO2‧‧‧Second input/output Rterm‧‧‧Resistance S401, S403, S405, S407 SB‧‧‧Socket board Vterm‧‧‧Voltage value

FIG. 1 is a schematic diagram of a testing device according to an embodiment of the invention. 2 is a schematic diagram of a testing device according to another embodiment of the invention. FIGS. 3A to 3D are examples of timing diagrams of the first test signal, the second test signal, and the frequency-doubled test signal during the first test procedure according to an embodiment of the present invention. FIG. 3E is shown in the second test according to the embodiment of the invention Timing diagram of the same feedback signal detected at different input/output terminals during the program. FIG. 4 is a flowchart of a testing method according to an embodiment of the invention.

100‧‧‧Test device

110‧‧‧Transmission interface

111‧‧‧signal intersection

112‧‧‧First bus

113‧‧‧Second bus

114‧‧‧The third bus

115‧‧‧The fourth bus

120‧‧‧Tester

130‧‧‧Socket board

131‧‧‧First socket group

1311~131n, 1321~132n‧‧‧ device under test

132‧‧‧Second socket group

133‧‧‧ Pair of devices under test

134, 135‧‧‧ Termination line

CS0~CSn‧‧‧Control signal

IO1‧‧‧First input/output

IO2‧‧‧Second input/output

Rterm‧‧‧Resistance

SB‧‧‧Socket board

Vterm‧‧‧Voltage value

Claims (10)

A test device includes: a tester having a first input/output terminal and a second input/output terminal, wherein the first input/output terminal is configured to provide a first test signal and the second input/ The output terminal is configured to provide a second test signal; a transmission interface, coupled to the tester, is configured to combine the first test signal and the second test signal received from the tester to generate a frequency multiplier A test signal; a first socket group having a plurality of sockets, the sockets of the first socket group accommodating a plurality of first devices to be tested connected in series, coupled to the transmission interface to receive the frequency-doubled test signal; and A second socket set has a plurality of sockets. The sockets of the second socket set accommodate a plurality of second devices to be tested connected in series, and are coupled to the transmission interface to receive the frequency-doubled test signal. The test device as described in item 1 of the patent application scope, wherein the first devices to be tested correspond to the second devices to be tested and the first devices to be tested respectively correspond to the second devices to be tested A plurality of pairs of devices under test are formed, wherein the first device under test and the second device under test that are the same pair of devices under test simultaneously receive the frequency-doubled test signal. The test device as described in item 2 of the patent application scope, wherein the tester provides a plurality of control signals to the pairs of devices under test, wherein the first device under test and the second device under test in the same pair of devices under test The test device receives an identical control signal. The test device as described in item 3 of the patent application scope, wherein the device-under-test pairs are sequentially provided with the frequency-multiplied test signal to sequentially execute a test procedure, and wherein the control signals are sequentially received according to the test procedure Enable. The test device as described in item 1 of the patent application range, wherein the frequency of the frequency-doubled test signal is twice the frequency of the first test signal or twice the frequency of the second test signal. The test device as described in item 1 of the patent application scope, wherein the frequency of the first test signal and the frequency of the second test signal are substantially the same. The test device as described in item 1 of the patent application scope, wherein the first socket group is electrically coupled to a first termination line, the second socket group is electrically coupled to a second termination line, and the first The end line is different from this second end line. The test device as described in item 1 of the patent application scope, wherein the first socket group and the second socket group are electrically coupled to a same termination line. The test device according to item 1 of the patent application scope, wherein the transmission interface includes: a first bus, coupled to the first input/output end, for receiving the first test signal; and a second bus , Coupled to the second input/output end, for receiving the second test signal; a third bus, coupled to the first socket group, for providing the frequency-multiplied test signal to the first socket group A fourth bus, coupled to the second socket group, used to provide the frequency multiplier test A signal to the second socket set; and a signal crosspoint configured to receive the first test signal through the first bus, the second bus receives the second test signal, and merges the first test signal and the The second test signal is used to generate the frequency multiplied test signal, and the frequency multiplied test signal is provided to the first socket group and the second socket group through the third bus and the fourth bus, respectively. A test method suitable for a test device includes: receiving a first test signal from a first input/output terminal and receiving a second test signal from a second input/output terminal; combining the first test signal and The second test signal generates a frequency-doubled test signal; grouping a plurality of serially connected first devices under test into a plurality of sockets of a first socket group, and grouping a plurality of serially connected second devices under test into A plurality of sockets of a second socket set; and executing a first test procedure, wherein the frequency-multiplied test signal and the plurality of control signals are provided to each socket of the first socket set and each socket of the second socket set to The devices under test.

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