TWI694433B - Pixel circuit - Google Patents

Abstract

A pixel circuit includes an inputting circuit, a LED, a driving circuit, and a compensating circuit. The inputting circuit is electrically coupled to a data line, a first node and a second node, and configured to receive a scanning signal and a data voltage. The LED is electrically coupled to the second node, and configured to receive a first voltage. The driving circuit is electrically coupled to the first node, the second node and a grounding end. The compensating circuit is electrically coupled to the inputting circuit and a grounding end. The compensating circuit is configured to receive a control signal, the first voltage and a reference voltage and output a compensating voltage to the inputting circuit.

Description

Pixel circuit

This disclosure relates to a pixel circuit, especially a pixel circuit that can compensate for the variation of the critical voltage of the driving transistor.

Low temperature poly-silicon thin-film transistors (LTPS TFT) have the characteristics of high carrier mobility and small size, and are suitable for display panels with high resolution, narrow bezels and low power consumption. At present, excimer laser annealing (ELA) technology is widely used in the industry to form polycrystalline silicon thin films of low-temperature polycrystalline silicon thin film transistors. However, since the scanning power of each shot of the excimer laser is not stable, the polycrystalline silicon films in different regions will have differences in grain size and number. Therefore, the characteristics of the low-temperature polysilicon thin film transistor will be different in different areas of the display panel.

For example, low-temperature polysilicon thin film transistors in different regions will have different threshold voltages. Different threshold voltages will cause differences in driving currents, resulting in inconsistent luminous brightness of low-temperature polysilicon thin film transistors. In this case, the display panel will face the problem of uneven brightness of the display screen when displaying images.

The invention provides a pixel circuit, which mainly uses an external compensation circuit and a buffer circuit to transmit the compensation voltage to the pixel circuit for compensation, solve the current unevenness caused by the critical voltage variation, and prevent the display panel from displaying a black screen The effect of the flicker phenomenon.

The first aspect of this case is to provide a pixel circuit. The pixel circuit includes a data writing circuit, a light emitting diode, a driving circuit and a compensation circuit. The write circuit is electrically coupled to the data line, the first node and the second node, and is used to receive the scanning signal and the data voltage. The light emitting diode is electrically coupled to the second node for receiving the first voltage. The driving circuit is electrically coupled to the first node and the second node and used to receive the second voltage. The compensation circuit is electrically coupled to the writing circuit and the ground, and is used to receive the control signal, the first voltage and the reference voltage, and output the compensation voltage to the writing circuit.

The second aspect of this case is to provide a pixel circuit. The pixel circuit includes a data writing circuit, a driving circuit, a light emitting diode and a compensation circuit. The write circuit is electrically coupled to the data line and the first node to receive the scanning signal. The driving circuit is electrically coupled to the first node and the second node for receiving the first voltage. The light emitting diode is electrically coupled to the driving circuit and used to receive the second voltage. The compensation circuit is electrically coupled to the writing circuit and the ground, and is used to receive the control signal and the first voltage, and output the compensation voltage to the writing circuit.

The third aspect of this case is to provide a pixel circuit. The pixel circuit includes a data writing circuit, a driving circuit, a light emitting diode and a compensation circuit. The write circuit is electrically coupled to the data line and the first node to receive the scan signal and the data voltage. The driving circuit is electrically coupled to the writing circuit and the second node for receiving the first voltage. The light emitting diode is electrically coupled to the driving circuit and used to receive the second voltage. The compensation circuit is electrically coupled to the current source and the write circuit for receiving the current source and the first voltage and outputting the data voltage to the write circuit.

The pixel circuit of the present invention can utilize an external compensation circuit and a buffer circuit to transmit the compensation voltage generated by the external compensation circuit to the interior of the pixel circuit for compensation, solve the current unevenness caused by the critical voltage variation, and prevent the display panel from displaying a black screen The effect of the flashing phenomenon at the time.

100, 200, 300 ‧‧‧ pixel circuit

110, 210, 310‧‧‧ write circuit

120, 220, 320 ‧‧‧ LED

130, 230, 330 ‧‧‧ drive circuit

140, 240, 340‧‧‧ Compensation circuit

141,341‧‧‧Operational amplifier

241‧‧‧Adder

DL‧‧‧Data cable

V _DATA ‧‧‧Data voltage

I _DATA ‧‧‧Data source

SCAN[n]‧‧‧scanning signal

N1, N2, N3, N4, N5, N6, N7, N8, N9

VDD‧‧‧Working voltage

VSS‧‧‧System low voltage

Vref‧‧‧Reference voltage

CTL‧‧‧Control signal

PH‧‧‧High level

PL‧‧‧Low level

Id1, Id2, Id3 ‧‧‧ drive current

T1~T12‧‧‧Transistor

C1~C6‧‧‧Capacitance

TP1‧‧‧Reset phase

TP2‧‧‧ compensation stage

TP3‧‧‧ Writing stage

TP4‧‧‧Lighting stage

In order to make the above and other objects, features, advantages and embodiments of the disclosure document more obvious and understandable, the drawings are described as follows: FIG. 1 is a circuit diagram of a pixel circuit according to an embodiment of the disclosure document; section 2 FIG. 3 is a circuit diagram of a pixel circuit according to an embodiment of the present disclosure; FIG. 3 is a circuit diagram of a pixel circuit according to an embodiment of the present disclosure; FIG. 4 is a pixel according to an embodiment of the present disclosure The operation timing diagram of the circuit; FIG. 5 is a circuit diagram of a pixel circuit according to an embodiment of the present disclosure; and FIG. 6 is an operation timing diagram of a pixel circuit according to an embodiment of the present disclosure.

The embodiments of the present invention will be described below in conjunction with related drawings. In the drawings, the same reference numerals indicate the same or similar elements or method flows.

Please refer to Figure 1. FIG. 1 is a circuit diagram of a pixel circuit 100 according to an embodiment of the present disclosure. As shown in FIG. 1, the pixel circuit 100 includes a data writing circuit 110, a light-emitting diode 120, a driving circuit 130 and a compensation circuit 140. The pixel circuit 100 can control the magnitude of the driving current Id1 flowing through the light-emitting diode 120, so that the light-emitting diode 120 generates different gray-scale brightness.

According to the above, the writing circuit 110 is electrically coupled to the data line DL, the nodes N1 and N2, and is used to receive the scan signal SCAN[n] and the data voltage V _DATA input from the data line DL. The first end of the light-emitting diode 120 is electrically coupled to the node N2, and the second end of the light-emitting diode 120 is used to receive the operating voltage VDD. The driving circuit 130 is electrically coupled to the nodes N1 and N2 and used to receive the system low voltage VSS. The compensation circuit 140 is electrically coupled to the writing circuit 110 and the ground, and is used to receive the control signal CTL, the operating voltage VDD, and the reference voltage Vref, and output the compensation voltage to the writing circuit 110.

The writing circuit 110 includes transistors T1 and T2, the first end of the transistor T1 is electrically coupled to the data line DL, the second end of the transistor T1 is electrically coupled to the node N1, and the control end of the transistor T1 is electrically Coupling to scan signal SCAN[n]. The first end of the transistor T2 is electrically coupled to the node N2, the second end of the transistor T2 is electrically coupled to the compensation circuit 140, and the control end of the transistor T2 is electrically coupled to the scan signal SCAN[n]. The writing circuit 110 is used for determining the voltage level of the node N1 according to the scan signal SCAN[n] and the data voltage V _DATA , and determining the voltage of the node N2 according to the compensation voltage input by the compensation circuit 140.

The driving circuit 130 includes a transistor T3 and a capacitor C1. The first terminal of the transistor T3 is used to receive the system low voltage VSS, the second terminal of the transistor T3 is electrically coupled to the node N2, and the control terminal of the transistor T3 is electrically coupled Connect to node N1. The first end of the capacitor C1 is electrically coupled to the node N1, and the second end of the capacitor C1 is electrically coupled to the node N2. The driving circuit 130 is used to generate a driving current Id1 to the light emitting diode 120.

The compensation circuit 140 includes transistors T4 and T5, a capacitor C2, and an operational amplifier 141. The first end of the transistor T4 is electrically coupled to the operating voltage VDD, and the second end of the transistor T4 is electrically coupled to the node N3. The control terminal of T4 is electrically coupled to the control signal CTL. The first terminal of the transistor T5 is electrically coupled to the ground terminal, the second terminal of the transistor T5 is electrically coupled to the node N3, and the control terminal of the transistor T5 is electrically coupled to the reference voltage Vref. The first end of the capacitor C2 is electrically coupled to the node N3, and the second end of the capacitor C2 is electrically coupled to the ground. The first input terminal of the operational amplifier 141 is electrically coupled to the node N3, the second input terminal of the operational amplifier 141 is electrically coupled to the output terminal of the operational amplifier 141, and the output terminal of the operational amplifier 141 is electrically coupled to the data line DL And the writing circuit 110, the operational amplifier 141 is used to output the compensation voltage.

In practice, the transistors T1 to T5 can be implemented with P-type low-temperature polycrystalline silicon thin film transistors, but this embodiment is not limited thereto. For example, the transistors T1 to T5 can also be implemented with P-type amorphous silicon thin-film transistors or other types of thin-film transistors.

The operation mode of the pixel circuit 100 will be further described below in conjunction with FIGS. 1 and 2. FIG. 2 is an operation timing diagram of the pixel circuit 100 according to an embodiment of the present disclosure. As shown in FIG. 2, during the operation of the pixel circuit 100, the operating voltage VDD operates at a high level V _HIGH (higher than the reference voltage Vref), and the control signal CTL and the scanning signal SCAN[n] will be at a high level Switch between PH and low level PL.

In this embodiment, since the direction of the laser scanning is parallel to the direction of the data line DL, if the energy emitted by the laser is the same, it can be assumed that the characteristics (eg, critical voltage) of the transistor T5 in the compensation circuit 140 and the transistor The characteristics of T3 are similar, so the voltage of node N3 can be used to compensate the pixel circuits of the same row.

According to the above, in the reset phase TP1, the control signal CTL is at the low level PL, so that the transistor T4 is turned on, and resets the voltage level of the node N3 to the high level V _HIGH . Then, in the compensation stage TP2, the control signal CTL is at the high level PH, so that the transistor T4 is switched from the on state to the off state, so the voltage of the node N3 will be discharged through the transistor T5 to be originally at the high level V _HIGH The voltage is discharged to the compensation voltage Vref+|V _TH5 |. Then, due to the characteristics of virtual ground, the operational amplifier 141 will make the positive and negative voltages of the operational amplifier 141 the same, and the negative terminal of the operational amplifier 141 is coupled to the output, so the operational amplifier 141 will compensate The voltage Vref+|V _TH5 | is output to the transistor T2 of the writing circuit 110.

According to the above, in the writing stage TP3, the scanning signal SCAN[n] is at the low level PL, so that the transistors T1 and T2 are in the conducting state, the data voltage V _DATA is input from the data line DL to the node N1, and the compensation voltage Vref+|V _TH5 | is input to the node N2 by the compensation circuit 140. Next, in the light-emitting phase TP4, the scanning signal SCAN[n] is at a high level PH, so that the transistors T1 and T2 are turned off, due to the node N1 data voltage V _DATA and the node N2 compensation voltage Vref+|V _TH5 | The voltage difference of makes the transistor T3 in the on state, so that the driving current Id1 generated by the transistor T3 can be obtained from "Formula 1". Furthermore, because the characteristics of transistor T3 are assumed to be similar to transistor T5, the critical voltage of transistor T3 |V _TH3 | is the same as the critical voltage of transistor T5 |V _TH5 |, the two can cancel each other, "Formula 1" As follows: Id=K(Vref+|V _TH5 |-V _DATA -|V _TH3 |) ² =K(Vref-V _DATA ) ² "Formula 1"

In this embodiment, it can be known from “Formula 1” that the driving current Id1 has nothing to do with the threshold voltage of the driving circuit 130. Therefore, even if the driving transistors 130 in different regions of the display panel have different characteristics (for example, different threshold voltages), the driving current Id1 and the data voltage V _DATA still maintain a fixed correspondence.

In another embodiment, please refer to FIG. 3. FIG. 3 is a circuit diagram of the pixel circuit 200 according to an embodiment of the present disclosure. As shown in FIG. 3, the pixel circuit 200 includes a data writing circuit 210, a light-emitting diode 220, a driving circuit 230, and a compensation circuit 240. The pixel circuit 200 can control the magnitude of the driving current Id2 flowing through the light-emitting diode 220, so that the light-emitting diode 220 generates different gray-scale brightness.

According to the above, the writing circuit 210 is electrically coupled to the data line DL and the node N1 to receive the scan signal SCAN[n] and the data voltage V _DATA and the compensation voltage input from the data line DL. The driving circuit 230 is electrically coupled to the nodes N1 and N2 for receiving the working voltage VDD. The light-emitting diode 220 is electrically coupled to the driving circuit 230 and used to receive the system low voltage VSS. The compensation circuit 240 is electrically coupled to the writing circuit 210 and the ground, and is used to receive the control signal CTL and the operating voltage VDD, and output the compensation voltage to the writing circuit 210.

The writing circuit 210 includes a transistor T6, a first end of the transistor T6 is electrically coupled to the data line DL, a second end of the transistor T6 is electrically coupled to the node N4, and a control end of the transistor T6 is electrically coupled To scan signal SCAN[n]. The writing circuit 210 is used to determine the voltage level of the node N4 according to the scan signal SCAN[n] and the sum of the data voltage V _DATA and the compensation voltage.

The driving circuit 230 includes a transistor T7 and a capacitor C3. The first end of the transistor T7 is electrically coupled to the node N5, the second end of the transistor T7 is electrically coupled to the light-emitting diode 220, and the control end of the transistor T7 It is electrically coupled to the node N4. The first end of the capacitor C3 is electrically coupled to the node N4, and the second end of the capacitor C3 is electrically coupled to the node N5. The driving circuit 230 is used to generate a driving current Id2 to the light emitting diode 220.

The compensation circuit 240 includes transistors T8 and T9, a capacitor C4, and an adder 241. The first end of the transistor T8 is electrically coupled to the ground, and the second end of the transistor T8 is electrically coupled to the node N6, the transistor T8 The control terminal of is electrically coupled to the control signal CTL. The first terminal of the transistor T9 is electrically coupled to the operating voltage VDD, the second terminal of the transistor T5 is electrically coupled to the node N6, and the control terminal of the transistor T9 is electrically coupled to the node N6. The first end of the capacitor C4 is electrically coupled to the node N6. The adder 241 is electrically coupled to the second end of the capacitor C4, the data line DL, and the write circuit 210. After receiving the data voltage V _DATA input from the source integrated circuit (Source IC), the adder 241 converts the data voltage V _DATA and compensation voltage are combined and output.

In practice, the transistors T6~T9 can be implemented with P-type low-temperature polycrystalline silicon thin film transistors, but this embodiment is not limited thereto. For example, the transistors T6 to T9 can also be implemented with P-type amorphous silicon thin-film transistors or other types of thin-film transistors.

The operation mode of the pixel circuit 200 will be further described below with reference to FIGS. 3 and 4. FIG. 4 is an operation timing diagram of the pixel circuit 200 according to an embodiment of the present disclosure. As shown in FIG. 4, during the operation of the pixel circuit 200, the operating voltage VDD operates at a high level V _HIGH (higher than the reference voltage Vref), and the control signal CTL and the scanning signal SCAN[n] will be at a high level Switch between PH and low level PL.

In this embodiment, the characteristics (eg, critical voltage) of the transistor T9 in the compensation circuit 240 are similar to the characteristics of the transistor T7, and the transistor T9 and the transistor T7 are located in the same row, so the voltage of the node N6 can be used for Compensate for pixel circuits in the same row.

According to the above, in the reset phase TP1, the control signal CTL is at the low level PL, so that the transistor T8 is turned on, and the voltage level of the node N6 is pulled down to the low level V _LOW . Then, in the compensation stage TP2, the control signal CTL is at the high level PH, so that the transistor T8 is switched from the on state to the off state, so the voltage of the node N6 will be discharged through the transistor T9 to be originally at the low level V _LOW The voltage is charged to the compensation voltage VDD-|V _TH9 |. The adder 241 then adds the compensation voltage VDD-|V _TH9 | to the data voltage V _DATA and outputs it to the transistor T6 of the writing circuit 210.

According to the above, in the writing stage TP3, the scanning signal SCAN[n] is at the low level PL, so that the transistor T6 is in an on state, the compensation voltage VDD-|V _TH9 | and the data voltage V _DATA are input to the node from the data line DL N4. Next, in the light-emitting phase TP4, the scanning signal SCAN[n] is at the high level PH, so that the transistor T6 is turned off, because the voltage of the node N4 is V _DATA +VDD-|V _TH9 | and the operation of the node N5 The voltage difference of the voltage VDD makes the transistor T7 in an on state, so that the driving current Id2 generated by the transistor T7 can be known from "Formula 2". Furthermore, because the characteristics of transistor T9 are assumed to be similar to transistor T7, the critical voltage of transistor T9 |V _TH9 | is the same as the critical voltage of transistor T7 |V _TH7 |, the two can cancel each other, "Equation 2" As follows: Id=K(V _SG -|V _TH7 |) ² =K(VDD-V _DATA -VDD+|V _TH9 |-|V _TH7 |) ² =k(-V _DATA ) ² "Formula 2"

In this embodiment, it can be known from "Formula 2" that the driving current Id2 has nothing to do with the threshold voltage of the driving circuit 230. Therefore, even if the driving transistors 230 in different regions of the display panel have different characteristics (for example, different threshold voltages), the driving current Id2 and the data voltage V _DATA still maintain a fixed correspondence.

In another embodiment, please refer to FIG. 5. FIG. 5 is a circuit diagram of a pixel circuit 300 according to an embodiment of the present disclosure. As shown in FIG. 5, the pixel circuit 300 includes a data writing circuit 310, a light-emitting diode 320, a driving circuit 330 and a compensation circuit 340. The pixel circuit 300 can control the magnitude of the driving current Id3 flowing through the light-emitting diode 320, so that the light-emitting diode 320 generates different gray-scale brightness.

According to the above, the writing circuit 310 is electrically coupled to the data line DL and the node N1 for receiving the scan signal SCAN[n] and the current source I _DATA input from the data line DL. The driving circuit 330 is electrically coupled to the nodes N7 and N8 for receiving the operating voltage VDD. The light emitting diode 320 is electrically coupled to the driving circuit 330 and used to receive the system low voltage VSS. The compensation circuit 340 is electrically coupled to the writing circuit 310 and the ground, and is used to determine the data voltage V _DATA according to the current source I _DATA and output the data voltage V _DATA to the writing circuit 310.

The writing circuit 310 includes a transistor T10, a first end of the transistor T10 is electrically coupled to the data line DL, a second end of the transistor T10 is electrically coupled to the node N7, and a control end of the transistor T10 is electrically coupled To scan signal SCAN[n]. The writing circuit 310 is used to determine the voltage level of the node N7 according to the scan signal SCAN[n] and the current source I _DATA .

The driving circuit 330 includes a transistor T11 and a capacitor C5. The first end of the transistor T11 is electrically coupled to the node N8, the second end of the transistor T11 is electrically coupled to the light emitting diode 320, and the control end of the transistor T11 It is electrically coupled to the node N7. The first end of the capacitor C5 is electrically coupled to the node N7, and the second end of the capacitor C5 is electrically coupled to the node N8. The driving circuit 330 is used to generate a driving current Id3 to the light emitting diode 320.

The compensation circuit 340 includes a transistor T12, a capacitor C6, and an operational amplifier 341. The first terminal of the transistor T12 is electrically coupled to the operating voltage VDD, and the second terminal of the transistor T12 is electrically coupled to the current source I _DATA , the transistor The control terminal of T4 is electrically coupled to the node N9. The first end of the capacitor C6 is electrically coupled to the first end of the transistor T12, and the second end of the capacitor C6 is electrically coupled to the node N9. The first input terminal of the operational amplifier 341 is electrically coupled to the node N9, the second input terminal of the operational amplifier 341 is electrically coupled to the output terminal of the operational amplifier 341, and the output terminal of the operational amplifier 341 is electrically coupled to the data line DL And the writing circuit 310, the operational amplifier 341 is used to output the data voltage V _DATA .

In practice, the transistors T10 to T12 can be implemented with P-type low-temperature polycrystalline silicon thin film transistors, but this embodiment is not limited thereto. For example, the transistors T10 to T12 can also be implemented with P-type amorphous silicon thin-film transistors or other types of thin-film transistors.

The operation mode of the pixel circuit 300 will be further described below in conjunction with FIGS. 5 and 6. FIG. 5 is an operation timing diagram of the pixel circuit 300 according to an embodiment of the present disclosure. As shown in FIG. 6, during the operation of the pixel circuit 300, the operating voltage VDD operates at the high level V _HIGH and the scan signal SCAN[n] switches between the high level PH and the low level PL.

In this embodiment, the characteristics (eg, critical voltage) of the transistor T12 in the compensation circuit 340 are similar to the characteristics of the transistor T11, and the transistor T11 and the transistor T12 are located in the same row, so the voltage of the node N9 can be used to The pixel circuits on the same line compensate.

In the writing stage TP3, the current source I _DATA provided by the source integrated circuit (Source IC) flows through the transistor T12, which can determine the voltage of the node N9. The voltage of the node N9 can be obtained from "Formula 3", and then the node The voltage of N9 is regarded as the data voltage V _DATA . Then, due to the characteristics of virtual ground, the operational amplifier 341 will make the positive and negative terminals of the operational amplifier 341 have the same voltage value, and the negative terminal of the operational amplifier 341 is coupled to the output terminal, so the operational amplifier 341 will The data voltage V _{DATA is} output to the transistor T10 of the writing circuit 310, and the scan signal SCAN[n] is at a low level PL at this time, so that the transistor T10 is turned on, and the data voltage V _DATA is input from the data line DL to the node N7 . "Formula 3" is as follows:

Next, in the light-emitting phase TP4, the scanning signal SCAN[n] is at the high level PH, so that the transistor T10 transitions to the off state. The voltage difference between the data voltage V _{DATA of the} node N7 and the working voltage VDD of the node N8 makes the The transistor T11 is in an on-state, so that the driving current Id3 generated by the transistor T11 is known from "Formula 4". Further, since it is assumed the transistor T11 and the transistor T12 of similar characteristics, and therefore the threshold voltage of transistor T11 is | V _TH11 | threshold voltage of transistor T12 is | V _TH12 | same, both can be canceled each other, "Formula 4" As follows:

In this embodiment, it can be known from "Formula 4" that the driving current Id3 has nothing to do with the threshold voltage of the driving circuit 330. Therefore, even if the driving transistors 330 in different regions of the display panel have different characteristics (for example, different threshold voltages), the driving current Id3 and the data source I _DATA still maintain a fixed correspondence.

In summary, the pixel circuit of the present invention can utilize the circuit architecture of an external compensation circuit, a buffer circuit or an adder to transmit the compensation voltage generated by the external compensation circuit to the interior of the pixel circuit for compensation to solve the criticality The current non-uniformity caused by the voltage variation can prevent the flicker phenomenon when the display panel displays a black screen, thereby increasing the contrast of the display screen.

Certain words are used in the specification and patent application scope to refer to specific elements. However, those of ordinary skill in the art should understand that the same elements may be referred to by different nouns. The specification and the scope of patent application do not use the difference in names as a way to distinguish the components, but the difference in the functions of the components as the basis for distinguishing. "Inclusion" mentioned in the description and the scope of patent application is an open term, so it should be interpreted as "including but not limited to." In addition, "coupling" here includes any direct and indirect connection means. Therefore, if it is described that the first element is coupled to the second element, it means that the first element can be directly connected to the second element through electrical connection, wireless transmission, optical transmission, or other signal connection, or through other elements or connections The means is indirectly electrically or signally connected to the second element.

In addition, unless otherwise specified in the description, any singular case also includes the meaning of the plural case.

The above are only preferred embodiments of the present invention, and any equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

100‧‧‧Pixel circuit

110‧‧‧ Writing circuit

120‧‧‧ LED

130‧‧‧Drive circuit

140‧‧‧ Compensation circuit

141‧‧‧Operational amplifier

DL‧‧‧Data cable

V _DATA ‧‧‧Data voltage

SCAN[n]‧‧‧scanning signal

N1, N2, N3 ‧‧‧ node

VDD‧‧‧Working voltage

Vref‧‧‧Reference voltage

CTL‧‧‧Control signal

Id1‧‧‧ drive current

T1~T5‧‧‧Transistor

C1~C2‧‧‧Capacitance

Claims (15)

A pixel circuit, including: a writing circuit, electrically coupled to a data line, a first node and a second node, for receiving a scanning signal and a data voltage; a light emitting diode, electrical Coupled to the second node for receiving a first voltage; a driving circuit electrically coupled to the first node and the second node for receiving a second voltage; and a compensation circuit electrically coupled Connected to the write circuit and a ground terminal, for receiving a control signal, the first voltage and a reference voltage, and outputting a compensation voltage to the write circuit; wherein, when the write circuit is turned on, the The compensation circuit is used to output the compensation voltage to the second node. The pixel circuit of claim 1, wherein the write circuit includes: a first transistor having a first terminal, a second terminal, and a first control terminal, the first terminal is electrically coupled to the A data line, the second terminal is electrically coupled to the first node, the first control terminal is electrically coupled to the scan signal; and a second transistor having a third terminal, a fourth terminal and a In the second control terminal, the third terminal is electrically coupled to the second node, the fourth terminal is electrically coupled to the compensation circuit, and the second control terminal is electrically coupled to the scan signal. The pixel circuit according to claim 1, wherein the driving circuit comprises: a third transistor having a first terminal, a second terminal and a control terminal, the first terminal is used to receive the second voltage, the The second terminal is electrically coupled to the second node, the control terminal is electrically coupled to the first node; and a first capacitor has a third terminal and a fourth terminal, the third terminal is electrically coupled Connected to the first node, the fourth terminal is electrically coupled to the second node. The pixel circuit of claim 1, wherein the compensation circuit comprises: a fourth transistor having a first terminal, a second terminal and a first control terminal, the first terminal is used to receive the first voltage , The first control terminal is electrically coupled to the control signal; a fifth transistor has a third terminal, a fourth terminal, and a second control terminal, the third terminal is electrically coupled to the ground terminal , The fourth terminal is electrically coupled to the second terminal, the second control terminal is used to receive the reference voltage; a second capacitor has a fifth terminal and a sixth terminal, the fifth terminal is electrically coupled Connected to the second terminal and the fourth terminal, the sixth terminal is electrically coupled to the ground terminal; and an operational amplifier has a first input terminal, a second input terminal and an output terminal, the first The input end is electrically coupled to the second end, the fourth end and the fifth end, the second input end is electrically coupled to the output end, the input The output terminal is electrically coupled to the write circuit for outputting the compensation voltage. As in the pixel circuit of claim 1, wherein the control signal is a first level during the reset phase, the scan signal is a fourth level, and the control signal is a second level during the compensation phase, the The scanning signal is the fourth level, the control signal is the second level during the data input stage, the scanning signal is a third level, and the control signal is the second level during the light emitting stage, the scanning The signal is the fourth level. A pixel circuit includes: a writing circuit electrically coupled to a data line and a first node for receiving a scanning signal; a driving circuit electrically coupled to the first node and a second node A node for receiving a first voltage; a light emitting diode, electrically coupled to the driving circuit and for receiving a second voltage; and a compensation circuit, electrically coupled to the writing circuit and a ground For receiving a control signal and the first voltage and outputting a compensation voltage to the write circuit; wherein, when the write circuit is turned on, the compensation circuit is used to output the compensation voltage to the first node . The pixel circuit of claim 6, wherein the writing circuit includes: A first transistor has a first end, a second end and a control end, the first end is electrically coupled to the data line, the second end is electrically coupled to the first node, the control The terminal is electrically coupled to the scanning signal. The pixel circuit of claim 6, wherein the driving circuit includes: a second transistor having a first terminal, a second terminal and a control terminal, the first terminal is electrically coupled to the second node , The second terminal is electrically coupled to the light emitting diode, the control terminal is electrically coupled to the first node; and a first capacitor has a third terminal and a fourth terminal, the third terminal It is electrically coupled to the first node, and the fourth terminal is electrically coupled to the second node. The pixel circuit of claim 6, wherein the compensation circuit includes: a third transistor having a first terminal, a second terminal, and a first control terminal, the first terminal is electrically coupled to the ground terminal , The first control terminal is electrically coupled to the control signal; a fourth transistor has a third terminal, a fourth terminal, and a second control terminal, the third terminal is used to receive the first voltage, The fourth terminal is electrically coupled to the second terminal, the second control terminal is electrically coupled to the fourth terminal; a second capacitor has a fifth terminal and a sixth terminal, and the fifth terminal is electrically Is sexually coupled to the second end and the fourth end, and the sixth end is electrically coupled to the ground end; and An adder electrically coupled to the second capacitor and the writing circuit is used to output the compensation voltage according to a data voltage. As in the pixel circuit of claim 6, wherein the control signal is a first level during the reset phase, the scan signal is a fourth level, and the control signal is a second level during the compensation phase, the The scanning signal is the fourth level, the control signal is the second level during the data input stage, the scanning signal is a third level, and the control signal is the second level during the light emitting stage, the scanning The signal is the fourth level. A pixel circuit includes: a write circuit electrically coupled to a data line and a first node for receiving a scanning signal and a data voltage; a driving circuit electrically coupled to the write circuit And a second node for receiving a first voltage; a light emitting diode, electrically coupled to the driving circuit and for receiving a second voltage; and a compensation circuit, electrically coupled to a current source and The write circuit is used to receive the current source and the first voltage, and output the data voltage to the write circuit. The pixel circuit according to claim 11, wherein the writing circuit comprises: a first transistor having a first terminal, a second terminal and a control terminal, the first terminal is electrically coupled to the data Line, the second end is electrically coupled to In the first node, the control terminal is electrically coupled to the scan signal. The pixel circuit according to claim 11, wherein the driving circuit comprises: a second transistor having a first terminal, a second terminal and a control terminal, the first terminal is electrically coupled to the second Node, the second terminal is electrically coupled to the light emitting diode, the control terminal is electrically coupled to the first node; and a first capacitor has a third terminal and a fourth terminal, the third The terminal is electrically coupled to the first node, and the fourth terminal is electrically coupled to the second node. The pixel circuit according to claim 11, wherein the compensation circuit comprises: a third transistor having a first terminal, a second terminal and a control terminal, the first terminal is used to receive the first voltage, The second terminal is electrically coupled to the current source, the control terminal is electrically coupled to a third node; a second capacitor has a third terminal and a fourth terminal, and the third terminal is electrically coupled To the first end, the fourth end is electrically coupled to the third node; and an operational amplifier having a first input end, a second input end, and an output end, the first input end is electrically coupled Connected to the third node, the second input terminal is electrically coupled to the output terminal, and the output terminal is electrically coupled to the write circuit for outputting the data voltage determined according to the current source. The pixel circuit as described in claim 11, in which The scan signal is at a first level in the material input stage, and the scan signal is at a second level in the light emitting stage.

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