TWI694428B - Driving circuit - Google Patents

Abstract

The present invention discloses a driving circuit including a plurality of first bus lines and a plurality of first signal lines. The plurality of first bus lines is disposed on a first side of a display area and configured to receive clock signals. Each first signal line corresponds to each first bus line respectively. The first bus lines situated between the first side and the first bus line that is farthest from the first side are provided with a transmission section and an extension section. The transmission section is connected between the corresponding first bus line and the display area so as to transmit the clock signal received by the corresponding first bus line to the display area. One end of the extension section is connected to the corresponding first bud line, the other end of the extension section being connected to

Description

Drive circuit

The invention relates to a driving circuit, in particular to a driving circuit for driving a display panel.

In the prior art, the gate driver of the liquid crystal display panel includes a multi-level shift register, which is used to provide a gate driving signal to the display area to control the turning on and off of the pixel transistor. Generally speaking, there is a bus bar on the side of the shift register away from the display panel to receive the clock signal from the timing controller or an external connector to the shift register to control the output of the shift register The timing and pulse width of the gate drive signal.

In the conventional gate driver, the signal coupling phenomenon is easily generated between two adjacent bus bars, and the number of bus bars crossed by the inner bus bar near the display area and the outer bus bar far from the display area are different. , Making the capacitance value of the inner and outer busbars inconsistent, resulting in a gap in coupling effect. This phenomenon will make the inner busbars near the display area and the busbar counties near the outer side drive the gate lines inconsistently, resulting in uneven brightness in the display screen.

Based on the above, the present invention provides a driving circuit in which the transmission line between the bus bar and the shift register has an extension section for matching the capacitance value of the inner bus bar and the outer bus bar, thereby reducing The drive capability of the inner and outer busbars to the gate line is different.

An embodiment of the present invention provides a driving circuit for transmitting a plurality of clock signals to a display area of a display device. The driving circuit includes a plurality of first bus lines and a plurality of first signal lines. A plurality of first signal lines are arranged on the first side of the display area, and are respectively used to receive clock signals. The plurality of first signal lines respectively correspond to each first bus bar and are coupled between the first signal line and the first side of the display area. Among the plurality of first bus bars, at least one first signal line between the first bus bar farthest from the first side and the first side has a transmission section and an extension section, and the transmission section is connected to the corresponding Between the first bus line and the display area, for transmitting the clock signal received by the corresponding first bus line to the display area, one end of the extension section is connected to the corresponding first bus line, the extension section The other end extends away from the first side to bridge at least one first bus bar.

Another embodiment of the present invention provides a driving circuit for transmitting a plurality of clock signals to a display area of a display device. The driving circuit includes a plurality of first bus bars and a plurality of first signal lines. A plurality of first bus bars are disposed on a first side of the display area, and each first bus bar is used to receive a clock signal. The plurality of first signal lines respectively correspond to each first bus bar and are coupled between the first signal line and the first side of the display area. Among the plurality of first bus lines, the first signal line corresponding to each first bus line between the first bus line furthest from the first side and the first side has a transmission section and an extension section , The transmission section is connected between its corresponding first bus line and the display area, one end of the extension section is connected to its corresponding first bus line, and the other end of the extension section faces away from the first side The extension extends across at least one non-corresponding first bus bar, wherein the number of first bus bars across at least two extension sections is different from each other.

To further understand the features and technical content of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are for reference and description only, and are not intended to limit the present invention.

Z: display device

A: Display area

S1: First side

S2: Second side

1: Drive circuit

B1, B11, B12, B13,...B116: the first bus

B2, B21, B22, B23,...B216: second bus

S11, S12, S13...S116: the first signal line

S21, S22, S23...S216: second signal line

S11_T, S12_T...S116_T: transmission section

S11_C, S12_C...S116_C: extended section

G1, G2...G16: gate line

2: Mobile register circuit

SR1, SR2, SR3...SR16: shift register

C1, C2...C16: clock signal

T: substrate

FIG. 1 shows a schematic diagram of a driving circuit used in a display device according to a first embodiment of the invention.

FIG. 2 shows a schematic diagram of the driving circuit of the first embodiment of the present invention.

FIG. 3 shows a modified embodiment of the driving circuit of the first embodiment of the present invention.

FIG. 4 shows another modified embodiment of the driving circuit of the first embodiment of the present invention.

FIG. 5 shows a schematic diagram of a driving circuit used in a display device according to a second embodiment of the invention.

6 is a partially enlarged schematic diagram of the display device of FIG. 5.

7A and 7B show a modified embodiment of the driving circuit of the second embodiment of the present invention.

FIG. 8A shows the discharge rate of each first bus bar under different cross-wire numbers of its corresponding extension section and the highest discharge rate and the lowest discharge under the same cross-wire number in the driving circuit of the second embodiment of the invention Rate ratio.

FIG. 8B shows the discharge rate of each second bus bar under different cross-wire numbers of its corresponding extended section and the highest discharge rate and the lowest discharge under the same cross-wire number in the driving circuit of the second embodiment of the present invention. Rate ratio.

The following describes the implementation of the driving circuit disclosed by the present invention through specific embodiments and FIG. 1 to FIG. 8B. Those skilled in the art can understand the advantages and effects of the present invention from the content disclosed in this specification. However, the content disclosed below is not intended to limit the protection scope of the present invention. Without departing from the spirit of the inventive concept, those skilled in the art can implement the present invention in other different embodiments based on different viewpoints and applications.

In the drawings, for the sake of clarity, all shown are simplified schematic diagrams to illustrate the basic architecture of the present invention. Therefore, the structure shown in the drawings is not based on the actual implementation of the shape and size ratio. For example, for convenience of explanation, the size of a specific element is exaggerated. In addition, it should be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “connected to” another element, it can be directly on or connected to the other element , Or intermediate elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to physical and/or electrical connections. Furthermore, the "electrically connected" or "coupled" system may be that there are other elements between the two elements.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant technology and the present invention, and will not be interpreted as idealized or excessive Formal meaning unless explicitly defined as such in this article.

In addition, it should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, And/or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Accordingly, the "first element", "component", "region", "layer" or "portion" discussed below may be referred to as the second element, component, region, layer or section without departing from the teachings herein.

First embodiment

The driving circuit 1 of the first embodiment of the present invention will be described below with reference to FIGS. 1 to 4. First, please refer to FIG. 1, which shows a schematic diagram of the driving circuit 1 of the first embodiment of the present invention used in the display device Z. The display device Z has a substrate T, a display area A, and a driving circuit 1 located on the first side S1 of the display area A and coupled to the display area A. In this embodiment, the display device Z is a thin-film transistor liquid crystal display panel, and the drive circuit 1 is a gate drive circuit for transmitting clock signals to the display area A of the display device Z. In practical applications, a shift register circuit may also be included between the driving circuit 1 and the first side S1 of the display area A to receive the clock signal from the driving circuit 1 and output the gate driving signal to Display area A to turn on the pixel transistor.

The embodiment shown in FIG. 1 takes the structure of a gate on array (GOA) as an example, that is, the driving circuit 1 for driving the gate is integrated on the substrate T. However, the invention is not limited to this. In other embodiments, the gate driving circuit may be coupled to the display area A in an external manner, for example. In addition, in practical applications, the display device Z may further include a source driving circuit, which may be coupled to other sides of the display area A by an external connection or an integrated method on the substrate T. The display device Z is not limited to that shown in FIG. 1. It should be understood that, for the sake of clarity, the display device Z of FIG. 1 only displays the substrate T, the drive circuit 1 and the display area A, and other elements are omitted.

FIG. 2 is a partial schematic diagram of the display device Z of FIG. 1, which shows a schematic diagram of the driving circuit 1 of this embodiment. In this embodiment, there is a shift register circuit 2 between the driving circuit 1 and the display area A, which together with the driving circuit 1 constitutes the gate driver 3 of the display device Z. The driving circuit 1 includes a plurality of first bus lines B1 and a plurality of first signal lines (S11, S12, S13, S14). As shown in FIG. 1, the first bus line B1 is disposed on the first side S1 of the display area A, and each first signal line (S11, S12, S13, S14) corresponds to each first bus line (B11 , B12, B13, B14) and coupled to the first bus bar (B11, B12, B13, B14) and the display area Between A. Specifically, the first signal line S11 is coupled between the first bus line B11 and the shift register SR1 of the shift register circuit 2; the first signal line S12 is coupled to the first bus line B12 Between the shift register SR2 of the shift register circuit 2; the first signal line S13 is coupled between the first bus line B13 and the shift register SR3 of the shift register circuit 2; The first signal line S14 is coupled between the first bus line B14 and the shift register SR4 of the shift register circuit 2.

As shown in FIG. 2, the first bus wires (B11, B12, B13, B14) are used to receive clock signals (C1, C2, C3, C4) respectively, and pass through the first signal wires (S11, S12, S13, S14) Transmit the clock signals (C1, C2, C3, C4) to the shift register circuit 2. The shift register circuit 2 is connected to the display area A through gate lines (G1, G2, G3, G4) for receiving clock signals (C1, C1, B1, B12, B13, B14) from the first bus bar C2, C3, C4), and output the gate drive signal to the gate line (G1, G2, G3, G4) according to the clock signal (C1, C2, C3, C4) to control each gate line (G1 G2, G3, G4) Turn on and off the pixel transistors. In this embodiment, the serial numbers of the clock signals (C1, C2, C3, C4) represent the time sequence, that is, the first bus line B11 first receives the clock signal C1, and then, the first bus line B12 receives the time Pulse signal C2, and so on. However, the present invention is not limited to this. In other embodiments, the clock signals (C1, C2, C3, C4) can also pass through the first bus line B14, the first bus line B13, the first bus line B12 and the first bus line B11 in sequence receive.

Please refer to FIG. 2, in this embodiment, the first bus bar (B11, B12, B13) between the first bus bar B14 farthest from the first side S1 and the first side S1 in the first bus bar B1 Among them, the first signal line S13 corresponding to at least one of the first bus wires (in the embodiment of FIG. 2, taking the first bus wire B13 as an example) has a transmission section S13_T and an extension section S13_C. The transmission section S13_T is coupled between its corresponding first bus line B13 and the display area A, and is used to connect the corresponding first bus line The clock signal C3 received by B13 is transmitted to the display area A. One end of the extension section S13_C is connected to the corresponding first bus line B13, and the other end of the extension section S13_C extends away from the first side S1 to bridge across at least one first bus line (implementation of FIG. 2 In the example, it is connected across the first bus line S14). It should be noted that, for the sake of clarity, the extended section S13_C in FIG. 2 is drawn with a thicker line than the transmission section S13_T to distinguish it from the transmission section S13_T. However, the difference in size ratio between the transmission section S13_T and the extension section S13_C in the figure does not represent the difference in size ratio between the two line segments in practical applications.

In the embodiment of FIG. 2, taking the first signal line S13 of a first bus line B13 having an extended section S13_C as an example, the rest is located on the first bus line between the first bus line B14 and the first side S1 Lines (B11, B12) only have transmission sections (S11_T, S12_T) for transmitting clock signals (C1, C2), and no extension sections. However, the present invention is not limited to this. In other embodiments, as shown in the embodiment shown in FIG. 3, among the plurality of first bus bars (B11, B12, B13, B14), the first bus bar B14 and the first side S1 that are farthest from the first side S1 The first signal line (S11, S12, S13) corresponding to each first bus bar (B11, B12, B13) has an extended section (S11_C, S12_C, S13_C).

In detail, in the embodiment of the present invention, the extension section is arranged so that the first busbar closer to the first side S1 can have a similar span than the first busbar farther away from the first side S1 The number of lines, thereby reducing the difference in capacitance between the first signal lines (S11, S12, S13, S14) to reduce the pair of first busbars (B11, B12, B13, B14) of the drive circuit 1 The difference in the driving degree of each gate line (G1, G2, G3, G4). Specifically, for the present embodiment, the aforementioned “driving” refers to transmitting the received clock signals (C1, C2, C3, C4) to the shift register circuit 2 to make the shift register Circuit 2 outputs the gate drive signal to the gate line. For example, when two first bus lines each drive a gate line, and the corresponding first signal line has a capacitance value difference, the two first bus lines will be on the clock signal transmission path. The equivalent capacitance value is different. In this case, wait for the signal transmission path For the first bus with a larger effective capacitance value, the fall time of the output clock signal waveform is longer; for the first bus with a smaller equivalent capacitance value on the signal transmission path, In other words, the fall time (Fall time) of the output clock signal waveform is shorter. At this time, the difference in the falling time of the pulse signal waveform will cause different on-time lengths for the pixel transistors on different gate lines. Therefore, the difference in capacitance between the first signal lines (S11, S12, S13, S14) may cause uneven brightness and darkness in the horizontal direction of the display screen. In this embodiment, by extending the sections (S11_C, S12_C, S13_C) on the first signal lines (S11, S12, S13), by reducing the distance between the first signal lines (S11, S12, S13, S14) The capacitance value difference further reduces the capacitance value difference of each first bus bar B1 on the signal transmission path. In this way, this embodiment can solve the problem of uneven brightness in the display screen caused by the above-mentioned difference in driving degree.

Further, in the embodiments of FIGS. 2 and 3, the extended section (S11_C, S12_C, S13_C) of the first signal line (S11, S12, S13) corresponding to the first bus bar (B11, B12, B13) All are connected to a first bus bar. Specifically, the extension section S13_C corresponding to the first bus line B13 in FIG. 3 is connected across the adjacent first bus line B14; the extension section S12_C corresponding to the first bus line B12 is connected across the adjacent The first bus bar B13; the extension S11_C corresponding to the first bus bar B11 is connected across the adjacent first bus bar B12. However, the present invention is not limited to the above; in other embodiments, the extension section may extend away from the first side S1 and span across two or more first bus bars. In addition, in the embodiments of FIG. 2 and FIG. 3, the display devices Z of four first bus bars (B11, B12, B13, B14) are taken as examples. However, the present invention is not limited to this. In practical applications, depending on the resolution of the display device Z, the first bus line B1 may include, for example, 8 or 16 bus lines; the present invention does not limit the number of the first bus line B1. In the following, a variation embodiment in which the extension section is connected across two or more first bus bars will be described with FIG. 4.

The main difference between the modified embodiment shown in FIG. 4 and the embodiments of FIGS. 2 and 3 is that: in the embodiments of FIGS. 2 and 3, the number of the first bus bar B1 is four, and each extended section (S11_C, S12_C, S13_C) is connected across a first bus bar; the number of the first bus bar B1 in FIG. 4 is 8 and partially extends the section (S11_C, S12_C, S13_C, S14_C, S15_C, S16_C) Connected to more than two first busbars. In detail, in the embodiment illustrated in FIG. 4, the number of the first bus bar connected by each extended section (S11_C, S12_C, S13_C, S14_C, S15_C, S16_C, S17_C) follows the following rules: if the first bus The number of cables is N, and one of the plurality of first bus cables (B11, B12...B1N) has M first bus cables on the side away from the first side S1, when M<N /2, the extension section corresponding to one of the above first bus bars spans M first bus bars; when M≧N/2, the extension area corresponding to one of the above first bus bars The number of the first bus bar connected by the segment is N/2.

For example, in the embodiment shown in FIG. 4, the number of the first bus bar B1 is 8, so N/2 is 4. As far as the first bus bar B15 is concerned, there are three first bus bars (B16, B17, B18) on the side away from the first side S1, so M=3. Since M=3 conforms to M<N/2, the number of the first bus line spanned by the extension section S15_C of the first signal line S15 corresponding to the first bus line B15 should be 3 (M=3), That is, it is connected across the first bus bar (B16, B17, B18). As far as the first bus bar B12 is concerned, there are six first bus bars (B13, B14, B15, B16, B17, B18) on the side away from the first side S1, so M=6. Since M=6 conforms to M≧N/2, the number of first bus wires spanned by the extended section S12_C of the first signal wire S12 corresponding to the first bus wire B12 is 4 (N/2=4) , That is, across the first bus bar (B13, B14, B15, B16).

Please refer to FIG. 4, in this embodiment, the first signal lines (S14, S15, S16, S17, S18) corresponding to the first bus bars (B14, B15, B16, B17, B18) each span eight first exchange Since the current cables (B11, B12...B18), the signal transmission paths of the five first bus cables (B14, B15, B16, B17, B18) will have the same equivalent capacitance value. Since the capacitance values of the signal transmission paths are the same, the five first bus bars (B14, B15, B16, B17, B18) will also have their corresponding gate lines (G4, G5, G6, G7, G8) The same degree of driving. In the conventional technology, in the gate driving circuit having eight bus bars as in this embodiment, only one bus bar has a signal line that spans the eight bus bars at the same time. Therefore, compared to the bus bar of the conventional gate drive circuit, the drive circuit 1 of this embodiment includes more bus bars having the same equivalent capacitance value. In this way, the difference in the driving degree of the gate line between the bus bars can be reduced.

Further, if the first side S1 is defined as being inward and the first side S1 as being outboard, then the total number of three first bus bars (B11, B12, B13) in FIG. 4 is five in total. , Six, and seven. Compared with the bus bar in the same position of the gate drive circuit that also has eight bus bars in the conventional technology, the first bus bar (B11, B12, B13) in this embodiment has a larger number of crossover wires. Therefore, it is possible to reduce the difference in the equivalent capacitance value with the outer first bus bar (B14, B15, B16, B17, B18). Through the above technical solution, in this embodiment, by setting the extension sections (S11_C, S12_C, S13_C, S14_C, S15_C, S16_C, and S17_C) and the number of the first busbars connected across them, each first busbar The lines (B11, B12, B13, B14, B15, B16, B17, B18) have a smaller difference in capacitance between the bus lines than the conventional gate drive circuit bus lines. In this way, the difference in the driving degree of the gate lines (G1, G2...G8) between the first bus bars B1 can be effectively reduced, and the brightness caused by the difference in driving degree in the screen output by the display device Z can be further improved Dark uneven.

Specifically, the rule of the number of cross-lines described in the embodiment of FIG. 4 can be understood as: For the driving circuit 1 of N first bus bars B1, the first signal lines (S11, S12...S1N) Extended section (S11_C, S12_C...S1N_C) The maximum value of the number of the first bus bar crossing in the direction away from the first side S1 is half of the total number of the first bus bar B1, that is, N/2. Taking the first bus line B17 and the first bus line B11 as an example, since the extension section S17_C corresponding to the first bus line B17 can only be bridged to the first bus line B18 from the outside at most, so only one bridge is connected The first bus line B18; and the extension section S11_C corresponding to the first bus line B11 can have at most 7 first bus lines that are bridged to the outside, that is, the first bus line (B12, B13, B14, B15 , B16, B17, B18), however, according to the rule of the number of crossover wires in this embodiment, under the architecture of eight first bus bars B1, the maximum number of crossover wires of the extended section is 4, so the first bus bar The extension section S11_C corresponding to B11 is connected to the four first bus bars (B12, B13, B14, B15) outward.

It should be noted that the above cross-line quantity rule is only one of the preferred embodiments of the present invention, and the present invention is not limited thereto. Further, as can be seen from the above rules, the higher the number of cross-over lines of the extension section, the more the difference in the equivalent capacitance value of the signal transmission path of the first bus bar B1 can be reduced. However, the higher the number of crossover lines, the higher the capacitance value of the overall driving circuit 1, and the excessively high capacitance value will reduce the driving efficiency of the driving circuit 1. Therefore, in the embodiment of FIG. 4, half of the total number of first bus bars B1 (N/2) is used as the maximum number of first bus bars extended across (S11_C, S12_C...S18_C) , Is one of the preferred embodiments of the present invention. However, in other embodiments, as long as the extending section extends away from the first side S1 and crosses at least one first bus bar, it falls within the scope of the present invention.

In summary, in the driving circuit 1 provided in this embodiment, by the first signal line corresponding to at least one first bus line between the first bus line furthest from the first side S1 and the first side S1 An extension section is provided to reduce the gap in the capacitance value of the signal transmission path between the first bus bars B1, thereby reducing the difference in the driving degree of the gate lines by the first bus bars B1. In this way, this embodiment can improve the problem of uneven brightness of the display image caused by the above-mentioned driving degree difference in the conventional technology.

Second embodiment

The driving circuit 1 of the second embodiment of the present invention will be described below with reference to FIGS. 5 to 8B. Referring to FIG. 5, the driving circuit 1 provided in this embodiment is applied to a display device Z driven by both sides. Specifically, the driving circuit 1 of this embodiment is respectively located on the first side S1 and the second side S2 opposite to the display area A and is coupled to the display area A, so as to clock from the first side S1 and the second side S2, respectively. The signal is transmitted to the display area A. In this embodiment, the driving circuit 1 also uses the structure of the gate integrated driving circuit (GOA) as an example, that is, the driving circuit 1 is formed on the substrate T, however, the invention is not limited thereto.

FIG. 6 is a partially enlarged schematic diagram of the display device Z of FIG. 5. For convenience of illustration, only the gate driver 3, the gate lines (G1, G2...G8) of the display device Z, and a part of the display area A are shown in FIG. 6, and other elements are omitted. As shown in FIG. 6, in this embodiment, the driving circuit 1 has a plurality of second bus lines B2 on the second side S2 of the display panel A, and second signal lines corresponding to each second bus line B2 (S21, S22...S28). The second bus line B2 is used to receive the clock signal (C1, C2...C8), and the second signal line (S21, S22...S28) is used to receive the clock of the corresponding second bus line The signal is transmitted to the display area A through the shift register circuit 2. In this embodiment, the number of the second bus line B2 is the same as the number of the first bus line B1, so the number of the second signal lines (S21, S22...S28) corresponds to eight, however, The present invention is not limited to this. In other embodiments, the number of the first bus bar B1 and the second bus bar B2 may be the same as 12, 16, etc.

In the embodiment of FIG. 6, a plurality of first bus lines B1 and corresponding first signal lines (S11, S12...S18) and a plurality of first bus lines B1 of the first embodiment and corresponding The first signal lines (S11, S12...S18) have the same structure, and the plurality of second bus lines B2 and the corresponding second signal lines (S21, S22...S28) have the same number of first The bus bar B1 and the corresponding first signal lines (S11, S12...S18) have corresponding structures, so that a plurality of second bus lines B2 and a plurality of The second signal lines (S21, S22...S28) are mirror-symmetrical to the plurality of first bus bars B1 and the plurality of first signal lines (S11, S12...S18) with respect to the display area A.

Specifically, in this embodiment, among the plurality of second bus bars B2, at least one second bus bar between the second bus bar B28 farthest from the second side S2 and the second side S2 corresponds to the first The two signal lines have a transmission section and an extension section, the transmission section is coupled between the corresponding second bus line and the display area A, and is used to connect the clock received by the corresponding second bus line The signal is transmitted to the display area A. One end of the extension section is connected to the corresponding second bus bar, and the other end of the extension section extends away from the second side S2 to bridge across at least one second bus bar. Taking the embodiment of FIG. 6 as an example, each second bus line (B11, B12...B18) corresponding to the second signal line (S21, S22...S28) has a transmission section (S21_T, S22_T ...S28_T) and an extended section (S21_C, S22_C...S28_C), however, the invention is not limited to this. In other embodiments, as long as the second signal line corresponding to at least one second bus bar B2 has an extended section, it falls within the scope of the present invention.

Further, in FIG. 6, the number of the second busbars across the extended sections (S21_C, S22_C..S28_C) located on the second side S2 in a direction away from the second side S2 and the corresponding first side The number of extension sections of S1 (S11_C, S12_C...S18_C) connected to the first bus bar is the same. In other words, in this embodiment, the number of extension sections of the second signal lines (S21, S22...S28) that cross the second bus line follows the same rules as the embodiment of FIG. 4: if the second The number of busbars is N, and one of the plurality of second busbars (B21, B22...B2N) has M second busbars on the side away from the second side S2, when M< N/2, the extension section corresponding to one of the above second busbars spans over M second busbars; when M≧N/2, the extension corresponding to one of the above second busbars The number of the second bus bar connected by the section is N/2.

For example, in FIG. 6, one side of the second bus bar B26 away from the second side S2 has two second bus bars (B27, B28), that is, M=2. Since N/2=4, M=2 meets M<N/2, so the extended section S26_C of the second signal line S26 corresponding to the second bus bar B26 is connected across two (M=2) second bus lines Flat cable (B27, B28). Taking the second bus bar B23 as an example, the second bus bar B23 has five second bus bars (B24, B25, B26, B27, B28) on one side away from the second side S2, that is, M=5. Since N/2=4, M=5 meets M≧N/2, so the extension section S23_C of the second signal line S23 corresponding to the second bus bar B23 extends away from the second side S2 to bridge over Four (N/2=4) second bus bars (B24, B25, B26, B27).

It should be emphasized that the above rule for the number of crossing lines of the extended section is only one of the preferred embodiments of the present invention, and the present invention is not limited thereto. Since the number of the second bus bars across the extended sections (S21_C, S22_C..S28_C) is greater, the smaller the difference in capacitance between the second signal lines (S21, S22...S28), so To achieve "reducing the difference in the capacitance of the signal transmission path between the second busbars", the more the number of crossovers, the better the effect of reducing the difference in capacitance. However, the higher the number of crossover lines, the higher the capacitance value of the overall driving circuit 1, and the excessively high capacitance value will reduce the driving efficiency of the driving circuit 1. Therefore, in this embodiment, half of the total number of second bus wires B2 (N/2) is also used as the maximum number of second bus wires connected to the extended section (S21_C, S22_C...S28_C), This is one of the preferred embodiments of the present invention. However, in other embodiments, as long as the extending section extends away from the first side S1 and spans at least one first bus bar, it falls within the scope of the present invention.

With the above-mentioned technical means, in this embodiment, an extension section is provided on each second signal line (S21, S22...S28) to reduce the distance between each second signal line (S21, S22...S28) Capacitance gap. In this way, the difference in the equivalent capacitance value on the signal transmission path between each second bus bar (B21, B22...B28) can be reduced, thereby reducing each second bus bar (B21, B22... B28) For each The driving degree difference of the gate lines (G1, G2...G8). In this way, the driving circuit 1 of this embodiment can improve the problem of uneven brightness of the display screen due to the above-mentioned driving degree difference in the conventional technology.

In addition, in the embodiment of FIG. 6, the order of receiving the clock signal by each second bus line B2 is spatially the same as that of each first bus line B1, all from the rightmost bus line to the left bus line The line receives clock signals in sequence. In other words, the first bus line B11 closest to the first side S1 and the second bus line B28 farthest from the second side S2 receive the clock signal C1 at the same time, and then, sequentially, the first bus line B12 and the second bus line B27 receive the clock signal C2 at the same time, the first bus line B13 and the second bus line B26 receive the clock signal C3 at the same time... and so on. However, the present invention is not limited to this. For example, in other embodiments, both the first bus line B1 and the second bus line B2 may receive clock signals from the inside to the outside, and the details will be described below in conjunction with FIGS. 7A, 7B, 8A, and 8B. Example description.

Please refer to FIGS. 7A and 7B, which show a modified embodiment of the second embodiment of the present invention, wherein FIG. 7A shows the driving circuit 1 on the first side S1 of the display area A; FIG. 7B shows the same modified embodiment, located at The driving circuit 1 of the second side S2 of the display area A. For the sake of clarity, the extended sections of the first signal lines (S11, S12...S116) and the second signal lines (S21, S22...S216) in FIGS. 7A and 7B are represented by thicker partial line segments, The transmission section is represented by a thinner line segment to separate the two; however, this difference in thickness is for illustrative purposes only, and does not represent the actual difference in thickness of the line segment. The difference between this modified embodiment and the embodiment of FIG. 6 is that: first, in the driving circuit 1 used in this modified embodiment, the number of the first bus bar B1 and the second bus bar B2 are both 16; second, FIG. 6 In the middle, the second bus line B2 receives the clock signals (C1, C2...C16) from the outside to the inside, that is, it receives the clock signal first through the second bus line B28 farthest from the second side S2 C1, and then the clock signals (C2, C3...C8) are received through the second bus line (B27, B26, B25...B21) in the direction close to the second side S2 in sequence. In the embodiment, the second bus bar B2 receives the clock signal in the opposite direction in space. In other words, as shown in FIG. 7B, the order of receiving the clock signal by the second bus line B2 is to first receive the clock signal C1 through the second bus line B21 closest to the second side S2, and then, toward the second side S2 The direction of is to receive the clock signal (C2, C3...C16) through the second bus line (B22, B23, B24...B216) in sequence.

With the above-mentioned technical means, this embodiment can further reduce the difference in the equivalent capacitance value on the signal transmission path between the second bus bars B2, so as to reduce the second bus bars B2 for the gate lines (G1, G2 ...G16) difference in driving ability. In addition, the above technical means can make the first bus bar B1 and the second bus bar B2 of this embodiment have the same driving capacity for the gate lines (G1, G2...G16). In detail, since each first signal line (S11, S12...S116) and each second signal line (S21, S22...S216) are mirror-symmetrical with respect to the display area A, the The first bus bar and the second bus bar with the same distance have the same equivalent capacitance value. For example, the first signal line S11 of the first bus line B11 and the second signal line S21 of the second bus line B21 have the same number of crossovers, so the first bus line B11 and the second bus line B21 are in time The capacitance values on the transmission path of the pulse signal are equal. Therefore, by making the first bus line B1 and the second bus line B2 receive clock signals (C1, C2...C16) from the inside to the outside, the embodiment of FIGS. 7A and 7B can reach the first bus The line B1 and the second bus bar B2 have the same driving capacity for the gate line. The following will further illustrate the rule of the number of crossover lines of the extended section according to the embodiment of the present invention and the first and second bus bars (B1, B2 from inside to outside) in FIGS. 7A and 7B according to the data in FIGS. 8A and 8B. ) Technical means for receiving clock signals.

Please refer to FIGS. 8A and 8B. FIG. 8A shows the discharge rate of each first bus bar B1 in its corresponding extended section under different number of cross-over lines, and the highest discharge rate and lowest under the same number of cross-over lines in the driving circuit 1 of this embodiment. The ratio of the discharge rate; Figure 8B shows the discharge rate of each second bus bar under different cross-wire numbers in its corresponding extended section, and the highest discharge under the same cross-wire number The ratio of the rate to the lowest discharge rate. The above "discharge rate" refers to the fall time (Fall time) of the clock signal output from each first bus bar B1 and each second bus bar B2 to the gate lines (G1, G2, G3...G16) In a common reference value, the percentage values shown in FIGS. 8A and 8B are shown. In FIGS. 8A and 8B, the "0 crossovers, 1 crossovers...15 crossovers" shown in this embodiment refer to the extension section located on the first side S1 facing away from the first side S1 in this embodiment The number of the first busbars connected across the extension, and the number of the second busbars connected across the extension section on the second side S2 extending away from the second side S2. In addition, the "discharge rate ratio" shown in FIGS. 8A and 8B represents the highest discharge of each of the first and second bus bars (B1, B2) under the same number of crossover lines in each extended section in this embodiment. The ratio of the rate to the lowest discharge rate.

As can be seen from FIG. 8A, in this embodiment, for the driving circuit 1 having 16 first and second bus bars (B1, B2), the number of crossover lines of the first bus bar B1 in the extended section is the first bus When the number of cables is about half (8), the discharge rate ratio becomes saturated gradually. Observing FIG. 8B, it can be seen that for the second bus bar B2, the number of cross-over lines of the extended section also has the same effect when the number of the second bus bar B2 is about half. When the number of crossover wires is 15, that is, the extension sections located on the first side S1 and the second side S2 respectively extend and cross over to the first bus line B116 farthest from the first side S1 and farthest from the second side When the second bus line B216 of S2 is used, the total number of crossovers of the first signal line (S11, S12...S116) and the second signal line (S21, S22...S216) is the same, that is, the transmission section is added The number of crossover lines of the upper extension section is the same, so the equivalent capacitance values of the transmission paths of the clock signals (C1, C2...C116) on the first side S1 and the second side S2 are equal, so the discharge rate ratio is 100% .

The experimental data of FIGS. 8A and 8B can support the rule of the number of cross-lines in the embodiment shown in FIG. 4 of the first embodiment, FIG. 6, FIG. 7A and FIG. 7B of the second embodiment. To be clear, in terms of achieving the effect of "reducing the difference in equivalent capacitance between busbars", the higher the number of crossovers, the smaller the discharge rate ratio is to achieve "reducing the difference in capacitance between busbars" "The better the effect, so in Figures 8A and 8B It can be seen that the discharge rate ratio decreases sequentially in different situations of "1 crossover", "2 crossovers", "3 crossovers" to "6 crossovers". However, as mentioned above, the higher the number of crossovers, the larger the overall capacitance of the drive circuit 1 and the worse the efficiency of the drive circuit 1. In addition, from the experimental data of FIGS. 8A and 8B, it can be seen that after the number of cross-lines gradually increases to reach “half of the total number of bus bars”, the discharge rate ratio decreases gradually and tends to saturation. Therefore, the embodiment shown in FIG. 4 of the first embodiment, FIG. 6, FIG. 7A and FIG. 7B of the second embodiment adopts “the maximum number of crossover wires is half of the total number of busbars” as one of the preferred embodiments. It should be emphasized that the present invention is not limited to this. In other embodiments, it is within the scope of the present invention as long as the extension section of the first side S1 spans at least one first bus bar, and the extension section of the second side S2 spans at least one second bus bar. .

Further, the data of FIGS. 8A and 8B can also support the technical means of the embodiments of FIGS. 7A and 7B. Specifically, when defining the area near the display area A as the inside and the area far from the display area A as the outside, the data in FIG. 8A sequentially makes the first bus line B11 to the first bus line B116 receive clock signals from the inside to the outside C1, the clock signal C2...the clock signal C16 is measured; the data of FIG. 8B is the sequence from the outside to the inside of the second bus line B216 furthest away from the second side S2 to the closest to the second side S2 The first bus bar B21 receives clock signal C1, clock signal C2...clock signal C16, respectively. Comparing FIGS. 8A and 8B, it can be seen that the discharge rate ratio (168.74%) in FIG. 8A is lower than the discharge in FIG. 8B when the extended sections respectively reach half of the total number of busbars (that is, "8 crossovers") Rate ratio (240.58%). It can be seen that the sequence of the clock signals (C1, C2...C16) received by the busbars is from the inner busbar to the outer busbar, and the effect of reducing the discharge rate difference between the busbars is better .

Therefore, in the embodiments of FIGS. 7A and 7B, the clock signals are received from the inner bus bars (B11, B21) to the outer bus bars (B116, B216). Specifically, the first bus line B11 and the second bus line B21 are used to first receive the clock signal C1 in timing, and then, sequentially, The first bus line B12 and the second bus line B22 are used to receive the clock signal C2 at the same time point, the first bus line B13 and the second bus line B23 are used to receive the clock signal C3 at the same time point. .. and so on. It should be emphasized that the above is only one of the preferred embodiments of the present invention, and the present invention is not limited thereto. In this way, the drive circuit 1 of the second side S1 can have a lower discharge rate ratio, and the drive capability of the drive circuit 1 of the first side S1 and the second side S2 for the gate lines (G1, G2...G16) the same. In this way, the problem of uneven horizontal brightness of the display screen caused by the difference in the equivalent capacitance value of the signal transmission path between each first bus line B1 or each second bus line B2 can be improved.

In summary, the driving circuit provided by the embodiment of the present invention can be determined by "corresponding to at least one first bus bar between the first bus bar farthest from the first side and the first side among the plurality of first bus bars The first signal line has a transmission section and an extension section" and "one end of the extension section is connected to the corresponding first bus bar, and the other end of the extension section extends away from the first side to bridge over "At least one first bus bar" technical means to reduce the difference in equivalent capacitance values between the first bus bars on the signal transmission path.

The content disclosed above is only a preferred and feasible embodiment of the present invention, and therefore does not limit the scope of the patent application of the present invention, so any equivalent technical changes made by using the description of the present invention and the content of the drawings fall into the application of the present invention. Within the scope of the patent.

Z: display device

A: Display area

S1: First side

1: Drive circuit

B1, B11, B12, B13, B14: the first bus

S11, S12, S13, S14: the first signal line

S11_T, S12_T, S13_T, S14_T: transmission section

S11_C, S12_C, S13_C, S14_C: extended section

G1, G2...G4: gate line

2: Mobile register circuit

SR1, SR2, SR3, SR4: shift register

C1, C2, C3, C4: clock signal

Claims (8)

A driving circuit for transmitting a plurality of clock signals to a display area of a display device, including: A plurality of first bus bars are provided on a first side of the display area, and each of the first bus bars is used to receive the clock signal; and A plurality of first signal lines, each of the first signal lines corresponds to each of the first bus bars and is coupled between the first signal line and the first side of the display area, Among the plurality of first bus bars, the first signal line corresponding to at least one first bus bar between the first bus bar furthest from the first side and the first side has a A transmission section and an extension section, the transmission section is coupled between the corresponding first bus line and the display area for transmitting the clock signal received by the corresponding first bus line To the display area, one end of the extension section is connected to the corresponding first bus bar, and the other end of the extension section extends away from the first side to bridge across at least one of the first bus bar . The driving circuit according to claim 1, wherein each of the first bus bars farthest from the first side among the plurality of first bus bars and the first side is the first bus bar The corresponding first signal line has the transmission section and the extension section. The driving circuit according to claim 2, wherein the total number of the plurality of first bus bars is N, and one of the plurality of first bus bars has M on the side far from the first side The first bus bar, when M<N/2, the extension section corresponding to one of the first bus bars crosses over the M first bus bars; when M≧N/2, Then, the number of the first bus bar across the extended section corresponding to one of the first bus bars is N/2. The driving circuit described in claim 1 further includes: A plurality of second bus bars are disposed on a second side of the display area relative to the first side, for transmitting the plurality of clock signals to the display area of the display panel; and A plurality of second signal lines, each second signal line corresponding to each second bus line respectively, for transmitting the clock signal received by the corresponding second bus line to the display area, Wherein, the plurality of second bus bars and the plurality of second signal lines are mirror-symmetrical to the plurality of first bus bars and the plurality of first signal lines with respect to the display area. The driving circuit described in claim 1 further includes: A plurality of second bus bars are disposed on a second side of the display area relative to the first side, for transmitting the plurality of clock signals to the display area of the display panel; and A plurality of second signal lines, each second signal line corresponding to each second bus line, Among the plurality of second bus bars, the second signal line corresponding to at least one second bus bar between the second bus bar and the second side furthest away from the second side has a A transmission section and an extension section, the transmission section is coupled between the corresponding second bus line and the display area for transmitting the clock signal received by the corresponding second bus line To the display area, one end of the extension section is connected to the corresponding second bus bar, and the other end of the extension section extends away from the second side to bridge across at least one second bus bar . The drive circuit according to claim 5, wherein the first bus bar closest to the first side among the plurality of first bus bars and the second side closest to the second side among the plurality of second bus bars The second bus bar is used to receive the same clock signal at the same time point. The driving circuit according to claim 5, wherein the first bus bar closest to the first side among the plurality of first bus bars and the second bus bar farthest from the second side among the plurality of second bus bars The second bus bar is used to receive the same clock signal at the same time. A driving circuit for transmitting a plurality of clock signals to a display area of a display device, including: A plurality of first bus bars are provided on a first side of the display area, and each of the first bus bars is used to receive the clock signal; and A plurality of first signal lines, each of the first signal lines corresponds to each of the first bus bars and is coupled between the first signal line and the first side of the display area, Among the plurality of first bus lines, the first signal line corresponding to each first bus line between the first bus line furthest from the first side and the first side has a A transmission section and an extension section, the transmission section is connected between the corresponding first bus line and the display area, and one end of the extension section is connected to the corresponding first bus line, The other end of the extension section extends away from the first side to bridge at least one of the first busbars that does not correspond to it, wherein at least two of the first sections connected by the extension section The number of bus bars is different from each other.

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