TWI693825B - Display method for reducing a double image effect and display system thereof - Google Patents

Abstract

A display method for reducing a double image effect includes changing a first transmission rate of a panel data clock to a second transmission rate, changing a first vertical synchronization period of a vertical synchronization signal to a second vertical synchronization period including a vertical pixel active synchronization interval and a blank interval according to at least the second transmission rate of the panel data clock, and enabling a backlight device only during a time interval of any length within the blank interval. The second transmission rate is greater than the first transmission rate. The second vertical synchronization period is greater than the first vertical synchronization period.

Description

Display method and system for reducing dual image effect

The present invention describes a display method and display system for reducing dual image effects, in particular to a display method and display system for maximizing the length of a vertical synchronization period to reduce double image effects.

Liquid crystal display (LCD) and organic light emitting diode (OLED) display devices have been widely used in multimedia players due to their advantages of light and thin appearance, power saving and no radiation. , Mobile phones, personal digital assistants, computer monitors, or flat-screen TVs and other electronic products.

Conventional monitors use pulse width modulation signals to drive the backlight when displaying images. And continuously turn on or turn off the backlight, so users can easily feel the screen flicker when viewing the screen and reduce the visual quality. Especially when the frequency demand is high or when displaying high-speed dynamic images, Motion Blur is prone to occur and the picture quality is reduced. Moreover, since the time when the backlight is turned on overlaps with the update time of the screen image, the user may see a transient phenomenon in the update of the screen image. Therefore, for the user, the display with the backlight constantly turned on is prone to double images. Moreover, even if the user does not notice the flickering phenomenon under the high-speed screen flickering, it will still cause the user's eyes to fatigue or even be visually injured after watching for a period of time. In order to reduce the viewing time when the screen image is updated, improve The LCD device uses the principle of pulse type backlight (Pulse Type Backlight), the backlight is turned on for as long as possible to avoid the screen image update time. In theory, if the backlight is turned on only when the liquid crystal of the display is in a steady state, the effect of dynamic blur can be avoided.

However, in order to maintain the average backlight brightness of the display and also have the function of eliminating motion blur, the duty cycle of the Pulse Width Modulation (PWM) signal driving the backlight must be optimized ( For example 16%). However, the optimized pulse modulation signal may not be supported by the display. For example, when the vertical sync signal of the display only supports a smaller blank space duty cycle (for example, 4%), the optimized interval for turning on the backlight will inevitably overlap with the vertical pixel active sync interval in the vertical sync signal. . Therefore, in the screen displayed by the human eye, there are still some areas where the double image caused by the motion blur will appear, which will lead to a decrease in visual quality.

An embodiment of the present invention proposes a display method for reducing the effect of dual images, including changing the first transmission rate of the panel data clock signal to a second transmission rate, and synchronizing the vertical synchronization according to at least the second transmission rate of the panel data clock signal The first vertical synchronization period of the signal is changed to the second vertical synchronization period, where the second vertical synchronization period includes the vertical pixel active synchronization interval and the blank interval, and the backlight device is turned on only during a time interval of any length within the blank interval . The second transmission rate is greater than the first transmission rate. The second vertical synchronization period is greater than the first vertical synchronization period.

Another embodiment of the present invention provides a display method for reducing dual image effects, including obtaining a vertical synchronization period of a vertical synchronization signal of a display panel, wherein the vertical synchronization period includes a vertical pixel active synchronization interval and a blank interval, and only within the blank interval Within any length of time, turn on the backlight. The vertical pixel active synchronization interval and the time interval during which the backlight device is turned on do not overlap, and the blank interval divided by the vertical synchronization period is greater than 5%.

Another embodiment of the present invention provides a display system including a display panel and a gate drive circuit Road, data drive circuit, timing controller, backlight device and processor. The display panel contains multiple pixels for displaying images. The gate driving circuit is coupled to the pixels. The data driving circuit is coupled to the pixels. The timing controller is coupled to the gate drive circuit and the data drive circuit, and is used to control the gate drive circuit and the data drive circuit. The processor is coupled to the timing controller and the backlight device to control the timing controller and the backlight device. After receiving the image data signal, the processor generates the panel data clock signal, and changes the first transmission rate of the panel data clock signal to the second transmission rate. The processor changes the first vertical synchronization period of the vertical synchronization signal to the second vertical synchronization period according to at least the second transmission rate of the data clock signal of the panel. The second vertical synchronization period includes a vertical pixel active synchronization interval and a blank interval. The timing controller controls the gate drive circuit and the data drive circuit to drive the pixels in the vertical pixel active synchronization interval to generate an image. The processor only turns on the backlight device in a time interval of any length in the blank interval. The second transmission rate is greater than the first transmission rate. The second vertical synchronization period is greater than the first vertical synchronization period.

100: display system

10: Display panel

11: Gate drive circuit

12: data drive circuit

13: Timing controller

14: Backlight device

15: processor

16: signal source

Vsync and Vsync’: vertical sync signal

BL and BL’: backlight drive signal

V _TOTAL : the first vertical synchronization period

ACT: the first vertical pixel active synchronization interval

BLK: first blank interval

BLE: the first backlight on interval

BLD: the first backlight off interval

F0: First-person visual area

V _TOTAL ': second vertical sync period

ACT’: Active synchronization interval of the second vertical pixel

BLK’: Second blank interval

BLE’: Second backlight on interval

BLD’: Second backlight off interval

F0’: Second human eye viewable area

S401 to S403: Steps

Figure 1 is a block diagram of an embodiment of the display system of the present invention.

Figure 2 is a waveform diagram of the vertical synchronization signal and the backlight driving signal under the initial settings in the display system of Figure 1.

Figure 3 is a waveform diagram of the vertical synchronization signal and the backlight driving signal under the updated settings in the display system of Figure 1.

FIG. 4 is a flowchart of a display method performed by the display system of FIG. 1 to reduce dual image effects.

FIG. 1 is a block diagram of an embodiment of the display system 100 of the present invention. The display system 100 includes a display panel 10, a gate driving circuit 11, a data driving circuit 12, a timing controller 13, a backlight device 14, and a processor 15. The display panel 10 may be any kind of display panel, such as a liquid crystal display (LCD) display panel or an organic light emitting diode (OLED) display device. The display panel 10 includes a plurality of pixels P for displaying images. A plurality of pixels P can be arranged in a pixel array to display a rectangular image. The gate driving circuit 11 is coupled to the pixels P, and the gate voltage can be used to control the control terminals of the pixels P row by row, thereby controlling the on or off state of the pixels P. The data driving circuit 12 is coupled to the pixels P, and can transmit the data voltage to the pixels P row by row, so that the pixels P display different colors and grayscale values. The timing controller 13 is coupled to the gate driving circuit 11 and the data driving circuit 12 and is used to control the gate driving circuit 11 and the data driving circuit 12. The timing controller 13 may be a logic board (T-CON), which may be regarded as a core circuit that controls the timing operation of the display panel 10, and is used to control the driving timing of the gate driving circuit 11 and the data driving circuit 12 to scan the pixels P. The timing controller 13 can also convert the input video signal (for example, low voltage differential signal, LVDS) into the data signal form used by the data driving circuit (for example, low swing differential signal, RSDS). The backlight device 14 is used to provide a backlight light source. The backlight device 14 may be a device composed of any controllable luminous body, for example, the backlight device 14 may be a light-emitting diode array (Light-Emitting Diode Array), an incandescent light bulb, an electroluminescent panel (ELP) or a cold cathode Fluorescent lamp (Cold Cathode Fluorescent Lamp, CCFL) and other devices. The processor 15 is coupled to the timing controller 13 and the backlight device 14 for controlling the timing controller 13 and the backlight device 14. The processor 15 may be any form of logical operation element. For example, the processor 15 may be a processing chip (Scaler) in the display system 100, or may be a microprocessor having logic processing capabilities. Multiple sets of timing control parameters (Timing Parameters) may also be stored in the processor 15. The communication method between the processor 15 and the timing controller 13 can be signal transmission via an integrated circuit bus (I ² C). Moreover, the processor 15 can receive the image data signal generated by the signal source 16. The video data signal generated by the signal source 16 may be a video data stream generated by a display card of an external computer, or a video data stream generated by a video player (such as a DVD Player). Any reasonable hardware changes are within the scope disclosed by the present invention.

In the display system 100, after the processor 15 receives the image data signal, it can generate a panel data clock (Panel Data Clock) signal, and change the first transmission rate of the panel data clock signal to the second transmission rate. Then, the processor 15 can change the first vertical synchronization period of the vertical synchronization signal to the second vertical synchronization period according to at least the second transmission rate of the data clock signal of the panel. Moreover, the second vertical synchronization period includes a vertical pixel active synchronization interval and a blank interval. The timing controller 13 can control the gate driving circuit 11 and the data driving circuit 12 to drive the pixels in a vertical pixel active synchronization interval to generate images. In order to avoid the occurrence of double images, the processor 15 only turns on the backlight device 14 within a time interval of any length within the blank interval. The second transmission rate is greater than the first transmission rate, and the second vertical synchronization period is greater than the first vertical synchronization period. The display method performed by the display system 100 to reduce the dual image effect and the details thereof will be described later.

FIG. 2 is a waveform diagram of the vertical synchronization signal Vsync and the backlight driving signal BL in the initial setting in the display system 100. In FIG. 2, for more specific description, the number of vertical pixels of the display panel 10 can be set to 1080. The vertical synchronization signal Vsync may be a periodic signal. In Figure 2, the period of the vertical sync signal Vsync is 1130 pixel scan time. Therefore, in FIG. 2, the first vertical synchronization period V _TOTAL can be defined as the time of 1130 pixel scans, represented by 1130p. Moreover, the first vertical synchronization period V _TOTAL includes a first vertical pixel active synchronization interval (or simply referred to as Active interval) ACT, and a first blank interval (or referred to as Blank Time Interval) BLK. The first vertical pixel active synchronization interval ACT must correspond to the number of vertical pixels of the display panel 10. Therefore, the length of the first vertical pixel active synchronization interval ACT is equal to the time of 1080 pixel scans, expressed as 1080p. Moreover, the length of the first blank interval BLK is equal to the first vertical synchronization period V _TOTAL minus the length of the first vertical pixel active synchronization interval ACT. Therefore, the length of the first blank interval BLK is equal to the scanning time of 1130-1080 pixels, which is represented by 50p. It should be understood that since the number of vertical pixels of the display panel 10 is 1080, the first vertical synchronization period V _TOTAL (1130 pixel scan time) includes the time to scan 1080 physical pixels (first vertical pixel Active synchronization interval (ACT), and the time to scan 50 virtual pixels (the first blank interval BLK). In other words, the plurality of pixels P of the display panel 10 will operate in a transient state (update state) within the first vertical pixel active synchronization interval ACT. In the first blank interval BLK, it will operate in a steady state. The pixel is transiently defined as the liquid crystal molecules in the pixel are rotating and unstable. The definition of a pixel in a stable state means that the liquid crystal molecules in the pixel have been rotated to a stable state. In order to avoid double images caused by Motion Blur, the backlight driving signal BL can turn on the backlight device 14 only during a period of time in the first blank interval BLK. For example, the backlight driving signal BL may turn on the backlight device 14 in the first backlight turning-on interval BLE. The first backlight-on interval BLE is within the first blank interval BLK. Moreover, the backlight driving signal BL can turn off the backlight device 14 in the first backlight off interval BLD. Therefore, for the viewer, the display screen seen by the visible area F0 of the first human eye operates in a steady state, and in theory, double images will not occur.

Unfortunately, in Figure 2, the length of the first blank interval BLK is equal to the time of 50 pixel scans. This means that in the initial setting of the display system 100, the vertical sync signal Vsync only supports a smaller duty cycle of the first blank interval BLK, which is 50/1130=4.4%. In other words, unless the duty ratio of the backlight driving signal BL is less than 4.4%, the display system 100 will not be able to provide the function of dual image elimination. Moreover, even if the duty ratio of the backlight driving signal BL is less than 4.4%, since the backlight driving signal BL is a Pulse Width Modulation (PWM) signal, an excessively small duty ratio will cause the energy of the pulse modulation signal to decrease, Therefore, the problem of insufficient screen brightness may also occur. In view of this, the display system 100 will use the calculation formula of the panel data clock signal to adjust the first blank interval BLK to a larger second blank interval BLK' (as shown in FIG. 3) to make the backlight drive signal BL can be optimized to achieve both the function of double image elimination and the function of maintaining the brightness of the screen, as explained below.

FIG. 3 is a waveform diagram of the vertical synchronization signal Vsync′ and the backlight driving signal BL′ in the display system 100 under the updated settings. It should be understood that in the display system 100, the transmission rate of the panel data clock signal, the horizontal synchronization period of the horizontal synchronization signal, and the vertical synchronization period of the vertical synchronization signal conform to the following formula: P _DATA = H _TOTAL × V _TOTAL × FR

P _DATA is the transmission rate of the clock signal of the panel data, H _TOTAL is the horizontal synchronization period, V _TOTAL is the vertical synchronization period, and FR is the frame rate (Frame Rate) constant. Therefore, in the case where the first vertical synchronization period V _TOTAL is 1130 pixel scans, if the first horizontal synchronization period H _TOTAL is set to 525 pixel scans and the frame rate constant FR is set to 144 Hertz (Hz), the transmission rate of the clock signal of the panel data of the display system 100 is 525×1130×144. In order to make a first vertical synchronization period V _TOTAL increases, the aforementioned equation based, may increase the data transmission rate when the panel P _DATA clock signals, or data transfer rate clock signal to the panel P _DATA may increase and the horizontal synchronization period H _TOTAL decreases. For example, the first transmission rate (eg 75 MHz) of the clock signal of the panel data of the display system 100 can be changed to a larger second transmission rate (eg 99 MHz). In addition, the first horizontal synchronization period of the horizontal synchronization signal (for example, 560 pixel scan time) can be changed to a smaller second horizontal synchronization period (for example, 525 pixel scan time). According to the formula of P _DATA =H _TOTAL ×V _TOTAL ×FR, when the frame rate constant FR is set to 144 Hz, the corresponding first vertical synchronization period V _TOTAL can be derived as follows: V _TOTAL =P _DATA /(H _TOTAL ×FR)=99000000/(525×144)=1309.52

Therefore, when the transmission rate of the pulse signal P _{DATA of the} panel data clock increases and the horizontal synchronization period H _TOTAL decreases, the corresponding first vertical synchronization period V _TOTAL can be deduced from the formula in a time of approximately 1309 pixel scans. However, in order to avoid confusion, in Figure 3, the vertical synchronization period corresponding to the time of 1309 pixel scans is called "second vertical synchronization period V _TOTAL '". The vertical sync signal in Figure 3 is called "Vertical Sync Signal Vsync'". The backlight driving signal in FIG. 3 is called "backlight driving signal BL'". In other words, the second vertical synchronization period V _TOTAL 'can be defined as the time of 1309 pixel scans, denoted by 1309p. In addition, the second vertical synchronization period V _TOTAL 'includes a second vertical pixel active synchronization interval ACT' and a second blank interval BLK'. The second vertical pixel active synchronization interval ACT' must correspond to the number of vertical pixels of the display panel 10. Therefore, the length of the first vertical pixel active synchronization interval ACT is equal to the length of the second vertical pixel active synchronization interval ACT', which is equal to the time of 1080 pixel scans, expressed in 1080p. When the first vertical synchronization period V _TOTAL (1130p) of the vertical synchronization signal Vsync is changed to the second vertical synchronization period V _TOTAL '(1309p) of the vertical synchronization signal Vsync', the first time length (50p) of the first blank interval BLK Will change to the second blank interval BLK' second time length (229p). In other words, the length of the second blank interval BLK' is equal to the second vertical synchronization period V _TOTAL ', minus the length of the second vertical pixel active synchronization interval ACT'. Therefore, the length of the second blank interval BLK' is equal to the time of 1309-1080=229 pixel scans, expressed as 229p. Similarly, in order to avoid double images caused by Motion Blur, the backlight driving signal BL' may turn on the backlight device 14 only during a period of time in the second blank interval BLK'. For example, the backlight driving signal BL' may turn on the backlight device 14 in the second backlight turning-on interval BLE'. The second backlight-on interval BLE' is within the second blank interval BLK'. In addition, the backlight driving signal BL' can turn off the backlight device 14 in the second backlight off interval BLD'. Since the backlight device 14 is turned off outside the second blank interval BLK', the second vertical pixel active synchronization interval ACT' does not overlap with the second backlight on interval BLE' where the backlight device 14 is turned on. Therefore, for the viewer, the display screen seen by the second human eye's viewable area F0' operates in a steady state, and theoretically no double image will occur.

Compared with FIG. 2 in FIG. 3, since the second vertical synchronization period V _TOTAL 'is greater than the first vertical synchronization period V _TOTAL , the second blank interval BLK' will also be greater than the first blank interval BLK. In other words, after the first vertical sync period V _{TOTAL is} changed to the second vertical sync period V _TOTAL ', the duty cycle (4.4%) of the first blank interval BLK supported by the vertical sync signal Vsync will be increased to the vertical sync signal Vsync 'Duty cycle of the supported second blank interval BLK (229/1309=17.4%). The increase is about 13%. However, as mentioned above, in order to maintain the average backlight brightness of the display and also have the function of eliminating motion blur, the duty cycle of the pulse modulation signal driving the backlight source must be optimized. Therefore, when the optimized duty ratio of the backlight driving signal BL' is 16%, since the duty ratio of the second blank interval BLK supported by the vertical sync signal Vsync' is greater than 16%, the display system 100 can support the backlight driving signal The optimized duty cycle of BL'. In other words, since the second time length (229p) of the second blank interval BLK' is greater than the first time length (50p) of the first blank interval BLK, the display system 100 can provide better design flexibility of the backlight driving signal BL' . Even, the second vertical synchronization period V _TOTAL ′ can approach the maximum vertical synchronization period supported by the display panel 10. Therefore, with such a design, the display system 100 can still maintain the brightness of the screen with the function of dual image elimination.

However, the method of setting the duty cycle of the second blank interval BLK supported by the vertical sync signal Vsync' to be greater than the optimized duty cycle of the backlight driving signal BL' in the present invention is not limited by the above steps. For example, the user can directly select the second vertical synchronization period V _TOTAL 'that is greater than the first vertical synchronization period V _TOTAL among the plurality of vertical synchronization periods supported by the display panel 10. Or, the user can directly select the display panel supported by the larger second vertical synchronization period V _TOTAL ', so that the second blank interval BLK' corresponding to the selected display panel is long enough to support driving the backlight device. Optimized pulse modulation signal BL'. In addition, the user can also change the first transmission rate of the panel data clock signal to a larger second transmission rate to maximize the second vertical synchronization period V _TOTAL '. As mentioned above, if you want to completely eliminate the double image caused by motion blur, in the display panel that supports a larger second vertical synchronization period V _TOTAL ', the second vertical pixel active synchronization interval ACT' and the time when the backlight device is turned on The intervals (the second backlight-on interval BLE') cannot overlap. In addition, the display system 100 may also select a “suboptimal” pulse modulation signal used to drive the backlight device 14. For example, the display system 100 may also select a pulse modulation signal with a duty ratio of 5% used by the backlight device 14. Therefore, the second blank interval BLK' of the display system 100 divided by the second vertical synchronization period V _TOTAL 'must be greater than 5%. Under this design, although the screen brightness of the display panel 10 is slightly reduced, the display system 100 can still completely eliminate the double image caused by the motion blur.

As mentioned above, the processor 15 of the display system 100 can receive the image data signal generated by the signal source 16. The image data signal generated by the signal source 16 may be an audio-visual data stream generated by a display card of an external computer, or an audio-visual data stream generated by an audio-visual player. For example, the display card of an external computer can generate an image data signal with a transmission rate of 144M (pixels per second), and the processor 15 can also generate panel data clock signals of different transmission speeds P _DATA according to the image data signal for use Choose. For example, when the user wants to increase the second vertical sync period V _TOTAL 'to the maximum vertical sync period supported by the display system 100, he can select the appropriate panel data clock signal transmission speed P _DATA . The transmission speed P _{DATA of the} selected clock signal of the panel data may be the second transmission rate higher than the original transmission rate (first transmission rate) as described above. The transmission rate of the image data signal (such as 144M pixels/sec) can be different from the second transmission rate of the panel data clock signal. In other words, the processor 15 has a modulation function and can optimally generate the transmission speed P _DATA of the panel data clock signal used by the display panel 10.

FIG. 4 is a flowchart of a display method performed by the display system 100 to reduce the dual image effect. The display method performed by the display system 100 to reduce the dual image effect includes steps S401 to S403. Any reasonable technical changes belong to the scope disclosed by the present invention. Steps S401 to S403 are described below.

Step S401: Change the first transmission rate of the panel data clock signal to the second transmission rate; Step S402: Change the first vertical synchronization period V _{TOTAL of the} vertical synchronization signal according to at least the second transmission rate of the panel data clock signal Is a second vertical synchronization period V _TOTAL 'larger than the first vertical synchronization period V _TOTAL ', wherein the second vertical synchronization period V _TOTAL ' includes a second vertical pixel active synchronization interval ACT' and a second blank interval BLK'; step S403 : The backlight device 14 is turned on only during a time interval of any length within the second blank interval BLK'.

The principles and details of steps S401 to S403 have been described in the foregoing, so they will not be repeated here. In the display system 100, when the second vertical synchronization period V _TOTAL 'is large enough, the second blank interval BLK' can support an optimized backlight driving signal with a high duty ratio. Therefore, the on/off interval of the backlight device 14 of the display system 100 can be optimized, so that the double image caused by the motion blur can be avoided, and the visual experience quality can also be improved.

In summary, the present invention describes a display method and display system for reducing the effect of dual images. The display system can increase the transmission speed of the clock signal of the panel data and/or reduce the horizontal synchronization period to maximize the vertical synchronization period. Or, the user can directly select a display system that supports a larger vertical synchronization period. Since the vertical synchronization period is large, the length of the blank interval in the vertical synchronization period will also be large. When the length of the blank interval is large enough, it means that the duty cycle of the blank interval supported by the vertical synchronization signal will be greater than the optimized duty cycle of the backlight driving signal. Therefore, the vertical synchronization signal can be matched with the optimized backlight driving signal to reduce or even eliminate the double image caused by the motion blur. In other words, since the length of the blank interval is large enough, the display system of the present invention can set the optimized start interval of the backlight device to fall within the blank interval, thereby avoiding the transient state when the human eye sees the pixel update The image can increase the quality of the visual experience under the condition that the image brightness and image quality can be maintained.

The above are only the preferred embodiments of the present invention, and all changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

Vsync’: vertical sync signal

BL’: backlight drive signal

V _TOTAL ': second vertical sync period

ACT’: Active synchronization interval of the second vertical pixel

BLK’: Second blank interval

BLE’: Second backlight on interval

BLD’: Second backlight off interval

F0’: Second human eye viewable area

Claims (20)

A display method for reducing dual image effects, including: changing a first transmission rate of a panel data clock signal to a second transmission rate; based on at least the second transmission of the panel data clock signal Rate, changing a first vertical synchronization period of a vertical synchronization signal to a second vertical synchronization period, where the second vertical synchronization period includes a vertical pixel active synchronization interval and a blank interval; and only within the blank interval Within a time interval of any length, a backlight device is turned on; wherein the second transmission rate is greater than the first transmission rate, and the second vertical synchronization period is greater than the first vertical synchronization period. The method according to claim 1, further comprising: changing a first horizontal synchronization period of a horizontal synchronization signal to a second horizontal synchronization period; wherein the second horizontal synchronization period is smaller than the first horizontal synchronization period. The method according to claim 1, wherein the vertical pixel active synchronization interval is a constant, and when the first vertical synchronization period of the vertical synchronization signal is changed to the second vertical synchronization period, the blank interval is changed from a first A time length is changed to a second time length, and the second time length is greater than the first time length. The method of claim 1, wherein when the second transmission rate is greater than the first transmission rate, the second vertical synchronization period approaches a maximum vertical synchronization period supported by a display panel. The method according to claim 1, wherein the first vertical synchronization cycle of the vertical synchronization signal The period is changed to the second vertical synchronization period, which is directly selecting the second vertical synchronization period larger than the first vertical synchronization period among the plurality of vertical synchronization periods supported by a display panel. The method according to claim 1, further comprising: turning off the backlight device outside the blank interval, so that the vertical pixel active synchronization interval does not overlap the time interval when the backlight device is turned on. The method according to claim 1, wherein a transmission rate of the data clock signal of the panel, a horizontal synchronization period of a horizontal synchronization signal, and a vertical synchronization period of the vertical synchronization signal conform to P _DATA = H _TOTAL × V _TOTAL ×FR, P _{DATA is} the transmission rate, H _{TOTAL is} the horizontal synchronization period, V _{TOTAL is} the vertical synchronization period, and FR is a frame rate (Frame Rate) constant. The method according to claim 1, further comprising: receiving an image data signal generated by a signal source; and generating the panel data clock signal according to the image data signal; wherein a transmission rate of the image data signal and the The second transmission rate of the panel data clock signal is different. The method according to claim 1, wherein the backlight device is driven by a backlight pulse modulation signal, and after the first vertical synchronization period of the vertical synchronization signal is changed to the second vertical synchronization period, the backlight pulse A duty cycle of the modulation signal is smaller than a duty cycle of the vertical synchronization signal. A display method for reducing dual image effects, including: Obtain a vertical synchronization period of a vertical synchronization signal of a display panel, wherein the vertical synchronization period includes a vertical pixel active synchronization interval and a blank interval; change a first horizontal synchronization period of a horizontal synchronization signal of the display panel Is a second horizontal synchronization period; and only turns on a backlight device within a time interval of any length within the blank interval; wherein the vertical pixel active synchronization interval does not overlap the time interval during which the backlight device is turned on , The second horizontal synchronization period is less than the first horizontal synchronization period, and the blank interval divided by the vertical synchronization period is greater than five percent. The method according to claim 10, further comprising: changing a first transmission rate of a Panel Data Clock signal to a second transmission rate to maximize the vertical synchronization period; wherein the The second transmission rate is greater than the first transmission rate. A display system includes: a display panel including a plurality of pixels for displaying an image; a gate driving circuit coupled to the pixels; a data driving circuit coupled to the pixels; A sequence controller, coupled to the gate drive circuit and the data drive circuit, for controlling the gate drive circuit and the data drive circuit; a backlight device; and a processor, coupled to the timing controller and the A backlight device for controlling the timing controller and the backlight device; After the processor receives an image data signal, it generates a Panel Data Clock signal, and changes a first transmission rate of the panel data clock signal to a second transmission rate, based on at least the panel The second transmission rate of the data clock signal changes a first vertical synchronization period of a vertical synchronization signal to a second vertical synchronization period. The second vertical synchronization period includes a vertical pixel active synchronization interval and a blank interval , And the timing controller controls the gate drive circuit and the data drive circuit to drive the pixels in the vertical pixel active synchronization interval to generate the image; and the processor is only in any of the blank intervals Within a length of time, when the backlight device is turned on, the second transmission rate is greater than the first transmission rate, and the second vertical synchronization period is greater than the first vertical synchronization period. The system according to claim 12, wherein the processor changes a first horizontal synchronization period of a horizontal synchronization signal to a second horizontal synchronization period, and the second horizontal synchronization period is smaller than the first horizontal synchronization period. The system of claim 12, wherein the vertical pixel active synchronization interval is a constant, and when the first vertical synchronization period of the vertical synchronization signal is changed to the second vertical synchronization period, the blank interval is changed from a first A time length is changed to a second time length, and the second time length is greater than the first time length. The system of claim 12, wherein when the second transmission rate is greater than the first transmission rate, the second vertical synchronization period approaches a maximum vertical synchronization period supported by the display panel. The system according to claim 12, wherein the processor sets the backlight device in the blank interval It is turned off so that the vertical pixel active synchronization interval does not overlap with the time interval during which the backlight device is turned on. The system of claim 12, wherein a transmission rate of the panel data clock signal, a horizontal synchronization period of a horizontal synchronization signal, and a vertical synchronization period of the vertical synchronization signal conform to P _DATA = H _TOTAL × V _TOTAL ×FR, P _{DATA is} the transmission rate, H _{TOTAL is} the horizontal synchronization period, V _{TOTAL is} the vertical synchronization period, and FR is a frame rate (Frame Rate) constant. The system according to claim 12, wherein a transmission rate of the image data signal received by the processor is different from the second transmission rate of the panel data clock signal. The system according to claim 12, wherein the backlight device is driven by a backlight pulse modulation signal, and after the first vertical synchronization period of the vertical synchronization signal is changed to the second vertical synchronization period, the backlight pulse A duty cycle of the modulation signal is smaller than a duty cycle of the vertical synchronization signal. The system according to claim 12, wherein the processor directly selects the second vertical synchronization period larger than the first vertical synchronization period among the plurality of vertical synchronization periods supported by the display panel.

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