TWI691240B - Method for manufacturing integrated circuit board and conductive film circuit - Google Patents
Method for manufacturing integrated circuit board and conductive film circuit Download PDFInfo
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- TWI691240B TWI691240B TW107141340A TW107141340A TWI691240B TW I691240 B TWI691240 B TW I691240B TW 107141340 A TW107141340 A TW 107141340A TW 107141340 A TW107141340 A TW 107141340A TW I691240 B TWI691240 B TW I691240B
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- 238000000034 method Methods 0.000 title claims description 15
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 238000005530 etching Methods 0.000 claims abstract description 34
- 239000000919 ceramic Substances 0.000 claims description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 11
- 238000007747 plating Methods 0.000 claims description 6
- 230000004907 flux Effects 0.000 claims description 5
- 229910000679 solder Inorganic materials 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims description 4
- 239000011889 copper foil Substances 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 239000010410 layer Substances 0.000 claims 12
- 239000011247 coating layer Substances 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 6
- 230000002457 bidirectional effect Effects 0.000 abstract description 4
- 230000010354 integration Effects 0.000 abstract description 3
- 229910052802 copper Inorganic materials 0.000 description 7
- 239000010949 copper Substances 0.000 description 7
- 239000000463 material Substances 0.000 description 7
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 230000003139 buffering effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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Abstract
本發明之集成電路板,係具有一絕緣載板,至少於絕緣載板其中一面設有一導電膜線路,於導電膜線路之部分區域覆設有至少一層之堆疊線路;以及,透過雙向分次蝕刻之於絕緣載板上所建置之導電膜線路或堆疊之線路,其線路厚度可相對大於其線路間距,有助於將小功率之控制電路及大功率之電子元件集成於同一電路板,以及使大功率之電子元件亦能縮小電性腳位之間距,藉由集成之效應來降低整體結構成本。The integrated circuit board of the present invention has an insulating carrier board, at least one side of the insulating carrier board is provided with a conductive film circuit, and at least one layer of stacked circuit is covered in a part of the conductive film circuit; and, through bidirectional partial etching For conductive film circuits or stacked circuits built on an insulating carrier board, the circuit thickness can be relatively greater than the circuit spacing, which helps to integrate low-power control circuits and high-power electronic components on the same circuit board, and The high-power electronic components can also reduce the distance between the electrical pins, and reduce the overall structural cost through the effect of integration.
Description
本發明係有關於一種集成電路板,特別是指一種具有高精準度細微線路與大電流線高線路的集成電路板,以及與其相關的導電膜線路製造方法。The invention relates to an integrated circuit board, in particular to an integrated circuit board with fine lines with high precision and high lines with high current lines, and a method for manufacturing a conductive film circuit related thereto.
陶瓷覆銅板是高壓大功率IGBT模組的重要組成部件,其具有陶瓷的高導熱、高電絕緣、高機械強度、低膨脹等特性,又兼具無氧銅的高導電性和優異焊接性能,且能像PCB線路板一樣刻蝕出各種線路圖形。Ceramic copper clad laminate is an important component of high-voltage high-power IGBT modules. It has the characteristics of high thermal conductivity, high electrical insulation, high mechanical strength and low expansion of ceramics. It also has the high conductivity of oxygen-free copper and excellent welding performance. And can etch various circuit patterns like PCB circuit board.
已知一種在陶瓷基板上進行選擇性金屬化的方法,係利用直接銅接合(direct bonded copper , 簡稱DBC)技術,在高溫下將陶瓷層與例如銅層的金屬層燒結接合,燒結後,該陶瓷層與銅層之間的結合力強且可靠度高。A method for selective metallization on a ceramic substrate is known, which uses direct bonded copper (DBC) technology to sinter the ceramic layer to a metal layer such as a copper layer at high temperature. After sintering, the The bonding force between the ceramic layer and the copper layer is strong and the reliability is high.
但在大面積陶瓷層介面與大面積銅層介面之間,容易存在有內應力及接面孔洞率之問題,進而產生俗稱貝殼紋的材料缺陷,且其僅能使用單向蝕刻來形成線路,故其最小線距只能等同線高,亦因此而侷限了將不同功率元件集成之特性。However, between the large-area ceramic layer interface and the large-area copper layer interface, it is easy to have the problems of internal stress and hole rate of the interface, which in turn produces material defects commonly known as shell patterns, and it can only use unidirectional etching to form circuits. Therefore, the minimum line distance can only be equal to the line height, which also limits the characteristics of integrating different power components.
本發明即在提供一種將厚度較低的低電流線路,及厚度較高的大電流線路集成於絕緣載板之同一面的集成電路板,以及與其相關的導電膜線路製造方法,為其主要目的者。The present invention is to provide an integrated circuit board that integrates a low-current circuit with a relatively low thickness and a large-current circuit with a relatively high thickness on the same side of an insulating carrier board, and a method for manufacturing a conductive film circuit related thereto, for its main purpose By.
本發明之集成電路板,係具有一絕緣載板,至少於該絕緣載板其中一面設有一導電膜線路,於該導電膜線路之部分區域覆設有至少一層之堆疊線路。The integrated circuit board of the present invention has an insulating carrier board. At least one side of the insulating carrier board is provided with a conductive film circuit, and at least one layer of stacked circuits is covered in a part of the conductive film circuit.
依據上述技術特徵,該集成電路板,係於該絕緣載板之兩面皆設有一導電膜線路,於該絕緣載板上設有至少一個以上之通孔,於該至少一通孔中填覆有供用以構成該絕緣載板兩面之導電膜線路電氣連接及增加流通電流量的導電件。According to the above technical features, the integrated circuit board is provided with a conductive film circuit on both sides of the insulating carrier board, at least one through hole is provided on the insulating carrier board, and the at least one through hole is filled for use Conducting members that electrically connect the conductive film lines on both sides of the insulating carrier board and increase the amount of circulating current.
依據上述技術特徵,該集成電路板,係於該導電膜線路上設有一層堆疊線路,於該導電膜線路與該堆疊線路之間設有一由導電材料構成的接合層。According to the above technical feature, the integrated circuit board is provided with a layer of stacked circuits on the conductive film circuit, and a bonding layer made of conductive material is provided between the conductive film circuit and the stacked circuit.
依據上述技術特徵,該集成電路板,係於該導電膜線路上設有複數層堆疊線路,於該導電膜線路與該複數層堆疊線路之間,及各該堆疊線路之間分別設有一由導電材料構成的接合層,藉由堆疊線路間之接合層來達到二次緩衝,以降低貝殼紋效應及與異質材料接合之應力問題。According to the above technical features, the integrated circuit board is provided with a plurality of stacked circuits on the conductive film circuit, a conductive layer is provided between the conductive film circuit and the plurality of stacked circuits, and between each of the stacked circuits The bonding layer composed of materials achieves secondary buffering through the bonding layer between stacked lines to reduce the shell effect and the stress problem of bonding with heterogeneous materials.
依據上述技術特徵,該集成電路板,係於該導電膜線路及各該堆疊線路之外露部位覆設一鍍膜層。According to the above technical features, the integrated circuit board is covered with a plating layer on the exposed portions of the conductive film circuit and each of the stacked circuits.
各該接合層係可以選擇為焊料、助焊劑、鍍膜其中之一或其組合者。Each of the bonding layer systems can be selected from one of solder, flux, and plating film or a combination thereof.
該導電膜線路上層之堆疊線路具有至少一橫跨連接於該導電膜線路所屬相鄰區塊之間的第一架橋區塊。The stacked circuit on the upper layer of the conductive film circuit has at least one first bridge block connected between adjacent blocks to which the conductive film circuit belongs.
該導電膜線路上層之堆疊線路具有至少一橫跨連接於該導電膜線路所屬相鄰區塊之間的第一架橋區塊;以及,該至少其中一堆疊線路上層之堆疊線路具有至少一橫跨連接於其下層堆疊線路所屬相鄰區塊之間的第二架橋區塊。The stacked circuit on the upper layer of the conductive film circuit has at least one first bridging block connected between adjacent blocks to which the conductive film circuit belongs; and, the stacked circuit on the upper layer of the at least one stacked circuit has at least one span The second bridge block is connected between adjacent blocks to which the lower layer stacked circuit belongs.
本發明之導電膜線路製造方法,係包括下列步驟:(a)建置第一次蝕刻架構,提供一暫時性載板,於該暫時性載板之板面上覆設一導電膜,由該導電膜未與該暫時性載板接觸之一面做為第一蝕刻面;(b)第一次線路蝕刻,以蝕刻方式將該導電膜之第一蝕刻面非線路圖形部分移除至預先設定之深度;(c)建置第二次蝕刻架構,提供一絕緣載板,以該完成第一線路蝕刻的導電膜之第一蝕刻面與該絕緣載板接觸的方式,將該導電膜連同該暫時性載板固設於該絕緣載板上;(d)產生第二面蝕刻面,待該導電膜確實固設於該絕緣載板之後,將該導電膜上方之暫時性載板移除,使該導電膜原本與該暫時性載板接觸之一面外露成為第二線路蝕刻面;(e)第二次線路蝕刻,以蝕刻方式將該導電膜之第二蝕刻面與該第一蝕刻面相對應之非線路圖形部分完全移除,即可於該絕緣載板上建構出線路厚度相對大於線路間距的導電膜線路。The method for manufacturing a conductive film circuit of the present invention includes the following steps: (a) constructing a first etching structure, providing a temporary carrier board, and covering the board surface of the temporary carrier board with a conductive film, by which The surface of the conductive film that is not in contact with the temporary carrier is used as the first etched surface; (b) The first line etching, the non-circuit pattern part of the first etched surface of the conductive film is removed to the preset by etching Depth; (c) build a second etching structure to provide an insulating carrier board, the first etching surface of the conductive film that completed the first line etching is in contact with the insulating carrier board, the conductive film together with the temporary The fixed carrier is fixed on the insulating carrier; (d) A second etching surface is generated. After the conductive film is fixed on the insulating carrier, the temporary carrier above the conductive film is removed, so that The surface of the conductive film that was originally in contact with the temporary carrier board is exposed as a second circuit etching surface; (e) The second circuit etching, corresponding to the second etching surface of the conductive film and the first etching surface by etching If the non-circuit pattern part is completely removed, a conductive film circuit with a circuit thickness relatively greater than the circuit spacing can be constructed on the insulating carrier.
該暫時性載板係可以為石英玻璃或陶瓷載板。The temporary carrier board may be a quartz glass or ceramic carrier board.
該導電膜係可以為一銅箔。The conductive film can be a copper foil.
該絕緣載板係可以為一陶瓷載板。The insulating carrier board may be a ceramic carrier board.
本發明主要利用於絕緣載板其中一面設有一導電膜線路,於導電膜線路之部分區域覆設有至少一層之堆疊線路之設計,可將小功率之控制電路及大功率之電子元件集成於同一電路板,以及使大功率之電子元件亦能縮小電性腳位之間距,藉由集成之效應來降低整體結構成本;尤其,透過雙向分次蝕刻之方式,有效解決傳統線路使用單向蝕刻其最小線距只能等同線高之限制,以及有效解決內應力及接面孔洞率之問題,避免產生俗稱貝殼紋的材料缺陷。The present invention is mainly used in the design of a conductive film circuit on one side of the insulating carrier board, and a part of the conductive film circuit is covered with at least one layer of stacked circuit design, which can integrate a low-power control circuit and a high-power electronic component in the same The circuit board and the high-power electronic components can also reduce the distance between the electrical pins, and the overall structure cost is reduced by the effect of integration; in particular, the bidirectional fractional etching method is used to effectively solve the problem of traditional circuits using unidirectional etching The minimum line distance can only be equal to the limit of line height, as well as effectively solve the problems of internal stress and hole rate of the joint, to avoid the material defects commonly known as shell patterns.
本發明主要提供一種可具有高精準度細微線路與大電流線高線路的集成電路板,以及與其相關的導電膜線路製造方法,如第1圖所示,本發明之集成電路板,係具有一絕緣載板10,至少於該絕緣載板10其中一面設有一導電膜線路12,於該導電膜線路12之部分區域覆設有至少一層之堆疊線路20。The present invention mainly provides an integrated circuit board with fine lines and high current lines with high accuracy, and a method for manufacturing a conductive film circuit related thereto. As shown in FIG. 1, the integrated circuit board of the present invention has a The
據以,整體集成電路板係可在絕緣載板10之同一面形成由導電膜線路12所構成之厚度較低的低電流電路,以及由導電膜線路12結合堆疊線路20所構成之厚度較高的大電流電路,可將小功率之控制電路及大功率之電子元件集成於同一電路板,以及使大功率之電子元件亦能縮小電性腳位之間距,藉由集成之效應來降低整體結構成本。Accordingly, the integrated circuit board can be formed on the same surface of the
本發明之集成電路板,於實施時,係可將預先製作好之堆疊線路20利用焊料、助焊劑或堆疊線路20上之接合鍍膜來形成接合於導電膜線路12上之接合層22,利用接合層22接合該導電膜線路12及該堆疊線路20,並且可以利用同樣的工法,如第2圖所示,堆疊第二層以上的堆疊線路20,藉由堆疊線路20間之接合層22來達到二次緩衝,以降低貝殼紋效應及與異質材料接合之應力問題。In the implementation of the integrated circuit board of the present invention, the prefabricated
再者,該導電膜線路12上層之堆疊線路20具有至少一橫跨連接於該導電膜線路12所屬相鄰區塊之間的第一架橋區塊211(如第6圖所示);甚至,在集成電路板堆疊有第二層以上的堆疊線路20之實施樣態下,該至少其中一堆疊線路20上層之堆疊線路20亦可具有至少一橫跨連接於其下層堆疊線路20所屬相鄰區塊之間的第二架橋區塊212(如第6圖所示),至少透過第一架橋區塊211(或者第一架橋區塊211及第二架橋區塊212)之線路設計,將原一整面之電路層區隔成多個立體堆疊之連通區塊電路層,藉此將膨脹應力導引至高度方向及利用架橋區塊之彎曲來緩衝水平方向之應力,以相對更為積極、可靠之手段降低貝殼紋效應及與異質材料接合之應力問題,更值得一提的是藉由將應力導引至高度方向可有效改善載板與承載元件間之應力問題及提高承載元件及電路之可靠度。Furthermore, the
甚至可進一步利用例如電鍍或化鍍之工法於該導電膜線路12及各該堆疊線路20之外露部位覆設一鍍膜層30,可透過該鍍膜層30之增設,達到縮小線距以及保護堆疊線路20之目的。Even a method such as electroplating or chemical plating can be further used to coat a
當然,本發明之集成電路板,於實施時,亦可將預先製作好之複數個堆疊線路20利用焊料、助焊劑或各有覆設接合鍍膜之堆疊線路20堆疊接合至預先設定的厚度之後,再將已預先完成接合複數之複數個堆疊線路20覆設於該導電膜線路12上;當然,各該接合層22係可以選擇為焊料、助焊劑、鍍膜其中之一或其組合者。Of course, in the implementation of the integrated circuit board of the present invention, a plurality of pre-fabricated
如第3圖所示,本發明之集成電路板,於實施時,整體集成電路板亦可依線路設計之需求,於該絕緣載板10兩面皆設有一導電膜線路12,於該絕緣載板10上設有至少一個以上之通孔11,並且對應於不同電流密度於該至少一通孔11中填覆有供用以構成該絕緣載板10面之導電膜線路12電氣連接及增加流通電流量的導電件13,以達到於該絕緣載板10兩面佈置大電流線路之目的。As shown in FIG. 3, when the integrated circuit board of the present invention is implemented, the overall integrated circuit board can also be provided with a
本發明之集成電路板,係可進一步透過將絕緣載板10上之導電膜線路12或堆疊線路20採用雙向分次蝕刻之製造方法,使導電膜線路12或堆疊線路20之線路厚度相對大於線路間距,甚至其線路厚度可以為線路間距之兩倍,相同線路厚度的條件下,可實現更小線路間距之線路設計,再者,本發明之集成電路板之絕緣載板10上之導電膜線路12,可以為鍍膜線路或者銅箔線路。The integrated circuit board of the present invention can further make the circuit thickness of the
請同時配合參照第4圖及第5圖所示,本發明之導電膜線路製造方法,係包括下列步驟:Please also refer to Figure 4 and Figure 5 together, the conductive film circuit manufacturing method of the present invention includes the following steps:
(a)建置第一次蝕刻架構,提供一暫時性載板40,於該暫時性載板40之板面上覆設一導電膜12A,由該導電膜12A未與該暫時性載板40接觸之一面做為第一蝕刻面;於實施時,該暫時性載板40係可以為石英玻璃或陶瓷載板;該導電膜12A係可以為一銅箔。(a) Build the first etching structure to provide a
(b)第一次線路蝕刻,以蝕刻方式將該導電膜12A之第一蝕刻面非線路圖形部分移除至預先設定之深度。(b) For the first circuit etching, the non-circuit pattern portion of the first etched surface of the
(c)建置第二次蝕刻架構,提供一絕緣載板10,以該完成第一線路蝕刻的導電膜12A之第一蝕刻面與該絕緣載板10接觸的方式,將該導電膜12A連同該暫時性載板40固設於該絕緣載板10上;於實施時,該絕緣載板10係可以為一陶瓷載板。(c) Build a second etching structure to provide an
(d)產生第二面蝕刻面,待該導電膜12A確實固設於該絕緣載板10之後,將該導電膜12A上方之暫時性載板40移除,使該導電膜12A原本與該暫時性載板40接觸之一面外露成為第二線路蝕刻面。(d) A second etched surface is created. After the
(e)第二次線路蝕刻,以蝕刻方式將該導電膜12A之第二蝕刻面與該導電膜12A之第一蝕刻面相對應之非線路圖形部分完全移除,即可於該絕緣載板10上建構出線路厚度相對大於線路間距的導電膜線路12。(e) The second circuit etching, the non-circuit pattern portion corresponding to the second etched surface of the
由於本發明係透過雙向分次蝕刻之於絕緣載板10上建置一線路厚度相對大於線路間距的導電膜線路12,不但有效解決傳統線路使用單向蝕刻其最小線距只能等同線高之限制。Since the present invention constructs a
尤其,在將已完成第一次蝕刻之導電膜12A固定於絕緣載板10時,由於導電膜12A與絕緣載板10接觸之面積,已遠小於導電膜12A原先尚未蝕刻之面積或使用鍍膜線路替代,可以有效解決直接銅接合(direct bonded copper , 簡稱DBC)技術所產生之內應力及接面孔洞率之問題,避免產生俗稱貝殼紋的材料缺陷。In particular, when the
以上所述之實施例僅係為說明本發明之技術思想及特點,其目的在使熟習此項技藝之人士能夠瞭解本發明之內容並據以實施,當不能以之限定本發明之專利範圍,即大凡依本發明所揭示之精神所作之均等變化或修飾,仍應涵蓋在本發明之專利範圍內。The above-mentioned embodiments are only to illustrate the technical ideas and features of the present invention, and its purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly, but cannot limit the patent scope of the present invention, That is to say, any equivalent changes or modifications made in accordance with the spirit disclosed by the present invention should still be covered by the patent scope of the present invention.
10:絕緣載板10: Insulated carrier board
11:通孔11: through hole
12A:導電膜12A: conductive film
12:導電膜線路12: Conductive film circuit
13:導電件13: conductive parts
20:堆疊線路20: Stacked line
211:第一架橋區塊211: The first bridge block
212:第二架橋區塊212: The second bridge block
22:接合層22: junction layer
30:鍍膜層30: coating
40:暫時性載板40: Temporary carrier board
第1圖係本發明第一實施例之集成電路板結構剖視圖。 第2圖係本發明第二實施例之集成電路板結構剖視圖。 第3圖係本發明第三實施例之集成電路板結構剖視圖。 第4圖係本發明之導電膜線路製造流程圖。 第5圖係本發明之導電膜線路於製造流程當中各步驟之成型狀態示意圖。 第6圖係本發明第四實施例之集成電路板結構剖視圖。Figure 1 is a cross-sectional view of the structure of an integrated circuit board according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view of an integrated circuit board structure according to a second embodiment of the invention. FIG. 3 is a cross-sectional view of an integrated circuit board structure according to a third embodiment of the invention. FIG. 4 is a manufacturing flowchart of the conductive film circuit of the present invention. FIG. 5 is a schematic diagram of the forming state of each step of the conductive film circuit of the present invention in the manufacturing process. FIG. 6 is a cross-sectional view of an integrated circuit board structure according to a fourth embodiment of the invention.
10:絕緣載板 10: Insulated carrier board
12:導電膜線路 12: Conductive film circuit
20:堆疊線路 20: Stacked line
22:接合層 22: junction layer
30:鍍膜層 30: coating
Claims (11)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW107141340A TWI691240B (en) | 2018-11-20 | 2018-11-20 | Method for manufacturing integrated circuit board and conductive film circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW107141340A TWI691240B (en) | 2018-11-20 | 2018-11-20 | Method for manufacturing integrated circuit board and conductive film circuit |
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| Publication Number | Publication Date |
|---|---|
| TWI691240B true TWI691240B (en) | 2020-04-11 |
| TW202021435A TW202021435A (en) | 2020-06-01 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080122079A1 (en) * | 2006-08-16 | 2008-05-29 | Phoenix Precision Technology Corporation | Package substrate and manufacturing method thereof |
| US10128194B1 (en) * | 2010-01-20 | 2018-11-13 | Amkor Technology, Inc. | Trace stacking structure and method |
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- 2018-11-20 TW TW107141340A patent/TWI691240B/en active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080122079A1 (en) * | 2006-08-16 | 2008-05-29 | Phoenix Precision Technology Corporation | Package substrate and manufacturing method thereof |
| US10128194B1 (en) * | 2010-01-20 | 2018-11-13 | Amkor Technology, Inc. | Trace stacking structure and method |
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| TW202021435A (en) | 2020-06-01 |
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