TWI690158B - Circuits and techniques for mesochronous processing - Google Patents

Abstract

Circuits and techniques for mesochronous processing are provided. A communication method for a mesochronously clocked system may include synchronizing processing of first and second processing units to first and second mesochronous clock signals, respectively. The first and second mesochronous clock signals may have a same frequency and different phases, respectively. The method may further include sending data from the first processing unit to the second processing unit, and enabling or disabling receipt of the data by the second processing unit based, at least in part, on states of the first and second mesochronous clock signals.

Description

Circuits and technologies for processing in-frequency and out-of-phase

The present invention generally relates to circuits and techniques for co-frequency and out-of-phase processing. In particular, some embodiments relate to transferring data between processing units with clock signals (which have different phases).

Clock signals can be used to coordinate data between components in an electronic system (such as between circuits in an integrated circuit (“IC” or “chip”) or between chips on a printed circuit board (PCB)) transmission. In a synchronous system, the components of the system are synchronized to a system-wide clock. The component performs data processing and transmission consistent with the system-wide clock pacing within a specific time period during the clock cycle of the system-wide clock. For example, the component may be synchronized with the system-wide clock when the clock signal is in a "high state" (for example, with a supply voltage) or when the clock signal is in a "low state" (for example, with a reference voltage). As another example, a component may be at the “edge” of a clock (for example, when the clock signal changes from a low state to a high state (“rising edge”) or from a high state to a low state (“falling edge”)) and full The system clock is synchronized.

A latch circuit can be used to store data. For example, a latch can store a single bit ("0" or "1") or multiple bits. The data can be provided to an input of a latch to be stored in the latch. The data stored in a latch can be read from an output of the latch. Some latches can be selectively operated in an enabled ("passthrough") state or a disabled ("hold") state based on the state of a control signal. When the latch is in the transparent state At this time, the latch is ready to receive new data at the input, and the output of the latch is operable to reflect the input of the latch. When in the transparent state, the latch may not be ready to provide (transmit) data to another circuit, because the output of the latch may be unstable (eg, depending on the state of the input data). When the latch is in the hold state, the data previously stored in the latch is stable (eg, ready to be read) and can be transferred to another circuit coupled to the output of the latch. If a latch enters the hold state when the enable signal is high, the latch performs "positive latch". If a latch enters the hold state when the enable signal is low, the latch performs "negative latch".

According to one aspect of the present invention, an integrated circuit including a plurality of processing units is provided. The processing units are operable to synchronize their processing with a plurality of clock signals of the same frequency and out of phase. The equivalent frequency out-of-phase clock signal includes a first clock signal and a second clock signal. The first clock signal and the second clock signal have the same frequency and different phases. The processing units include a first processing unit operable to synchronize processing with the first clock signal and a second processing unit operable to synchronize processing with the second clock signal. The second processing unit includes a latch circuit coupled to receive data from the first processing unit. The latch circuit is configured to operate based on the state of the first clock signal and the second clock signal.

In some embodiments, the first processing unit includes a latch circuit coupled to provide the data to the latch circuit of the second processing unit. In some embodiments, the latch circuit of the second processing unit is configured to operate in a transparent state based at least in part on the latch circuit of the first processing unit being in a holding state. In some embodiments, the latch circuit of the second processing unit is configured to be based at least in part on that the latch circuit of the first processing unit is in a holding state and the second clock signal represents a specific logic value And operate in a transparent state. In some embodiments, the latch circuit of the second processing unit is configured to be based at least in part on the latch circuit of the first processing unit In the transparent state and/or the second clock signal indicates a logic value different from the specific logic value and operates in a holding state.

In some embodiments, the latch circuit of the first processing unit is configured to operate in a hold state based on the first clock signal representing a specific logic value, and the latch of the second processing unit The circuit is configured to operate in a transparent state based at least in part on the first clock signal representing the specific logic value. In some embodiments, the latch circuit of the first processing unit is configured to operate in a hold state based on the first clock signal representing a first logic value, and the latch of the second processing unit The memory circuit is configured to operate in a transparent state based at least in part on the first clock signal representing the first logic value and the second clock signal representing a second logic value. In some embodiments, the latch circuit of the second processing unit is configured to represent a logic value different from the first logic value and/or the second clock signal based at least in part on the first clock signal It means that a logic value different from the second logic value operates in a holding state.

In some embodiments, the first clock signal is a first single-ended clock signal, and the second clock signal is a second single-ended clock signal. In some embodiments, the latch circuit includes a gated latch having an input data terminal, an enable terminal, and one or more output terminals, wherein the input data terminal is configured to be removed from the first processing unit Receiving data, and wherein the enable terminal is configured to receive a logical AND of an inverse of one of the first single-ended clock signal and the second single-ended clock signal.

In some embodiments, the first clock signal includes a first differential clock signal of a first differential signal pair, and the second clock signal includes a first differential signal of a second differential signal pair Two differential clock signals. In some embodiments, the latch circuit includes an input circuit and a buffer circuit, and the input circuit includes a plurality of first field effect transistors (FETs) of a first type, etc. The first FET, the second FET, and the third FET of the diffusion terminal between the first power supply rail and an input node of the buffer circuit. In some embodiments, the latch circuit further includes a plurality of second fields of a second type An effective transistor (FET), etc., includes a fourth FET, a fifth FET, and a sixth FET having a diffusion terminal coupled in series between a second power supply rail and the input node of the buffer circuit. In some embodiments, the gates of the first FET and the fourth FET are coupled to receive the data from the first processing circuit. In some embodiments, the gates of the second FET and the fifth FET are coupled to receive the first signal and the second signal of the first differential signal pair, respectively. In some embodiments, the gates of the third FET and the sixth FET are coupled to receive the first signal and the second signal of the second differential signal pair, respectively. In some embodiments, the buffer circuit includes at least one inverter having an input terminal coupled to the input node of the buffer circuit and an output terminal coupled to an output terminal of the latch circuit.

In some embodiments, the integrated circuit further includes a differential clock buffer having an input terminal of the first differential signal pair coupled to receive the first differential clock signal, wherein the differential The clock buffer is operable to provide the second differential signal pair of the second differential clock signal, and wherein the differential clock buffer is operable in response to a first of the first differential signal pair A signal transition and a complementary transition of a second signal of the first differential signal pair set a logical value of the second differential signal pair to match a logical value of the first differential signal pair.

In some embodiments, the integrated circuit includes a processing node, wherein the processing node includes the plurality of processing units, a control unit, and a bus, and wherein the processing units are communicatively coupled to the bus by the bus The control unit. In some embodiments, the control unit is operable to transmit arithmetic data to the processing units via the bus. In some embodiments, the processing units are operable to transmit the result data to the control unit via the bus. In some embodiments, the integrated circuit includes a plurality of processing nodes, and the like includes the processing node. In some embodiments, the processing nodes perform bitcoin exploration operations.

According to another aspect of the present invention, a latch circuit including a buffer circuit and an input circuit is provided. The buffer circuit has an input node and an output node. The input The road has: an output node, which is coupled to the input node of the buffer circuit; a data node, which is coupled to receive an input data signal; and a first enabling node and a second enabling node, which are coupled to receive separately The respective first in-frequency out-of-phase clock signal and second in-frequency out-of-phase clock signal of the first processing unit and the second processing unit. The first clock signal and the second clock signal have the same frequency and different phases. The input circuit is operable to activate the latch circuit based on the state of the first in-frequency out-of-phase clock signal and the second in-frequency out-of-phase clock signal.

In some embodiments, the data node is coupled to receive the input data signal from an output latch of the first processing unit. In some embodiments, the input circuit is configured to enable the latch circuit based at least in part on the output latch being in a disabled state. In some embodiments, the input circuit is configured to enable the latch circuit based at least in part on the output latch being in a disabled state and the second clock signal representing a specific logic value. In some embodiments, the input circuit is configured to deactivate the input latch based at least in part on the output latch being in an enabled state and/or the second clock signal representing a logic value different from the specific logic value Latch the circuit.

In some embodiments, the output latch is configured to operate in a disabled state based on the first clock signal representing a specific logic value, and the input circuit is configured to be based at least in part on the first The clock signal indicates the specific logic value and enables the latch circuit. In some embodiments, the output latch is configured to operate in a disabled state based on the first clock signal representing a first logic value, and the input circuit is configured to be based at least in part on the first A clock signal indicates the first logic value and the second clock signal indicates a second logic value to enable the latch circuit. In some embodiments, the input circuit is configured to represent a logic value different from the first logic value based on the first clock signal and/or the second clock signal represents a different logic from the second logic A logic value of the value disables the latch circuit.

In some embodiments, the first clock signal includes a first differential signal pair A first differential clock signal, and the second clock signal includes a second differential clock signal of a second differential signal pair. In some embodiments, the input circuit includes a plurality of first field effect transistors (FETs) of a first type, etc., which include an input node coupled in series to a first power supply rail and the buffer circuit The first FET, the second FET and the third FET of the diffusion terminal between them. In some embodiments, the input circuit further includes a plurality of second field effect transistors (FETs) of a second type, which includes the input node having a second power supply rail and the buffer circuit coupled in series The fourth FET, the fifth FET and the sixth FET of the diffusion terminal between. In some embodiments, the gates of the first FET and the fourth FET are coupled to receive the input data signal. In some embodiments, the gates of the second FET and the fifth FET are coupled to receive the first signal and the second signal of the first differential signal pair, respectively. In some embodiments, the gates of the third FET and the sixth FET are coupled to receive the first signal and the second signal of the second differential signal pair, respectively. In some embodiments, the buffer circuit includes at least one inverter having an input terminal coupled to the input node of the buffer circuit and an output terminal coupled to the output node of the buffer circuit.

According to yet another aspect of the present invention, a communication method for a co-frequency out-of-phase time control system is provided. The method includes: synchronizing the processing of the first processing unit and the second processing unit to the first in-frequency out-of-phase clock signal and the second in-frequency out-of-phase clock signal, the first in-frequency out-of-phase clock signal and the second The same frequency and different phase clock signals have the same frequency and different phases. The method further includes sending data from the first processing unit to the second processing unit. The method further includes: enabling or disabling the second processing unit to receive the data based at least in part on the status of the first in-frequency out-of-phase clock signal and the second in-frequency out-of-phase clock signal.

In some embodiments, enabling or disabling receipt of the data by the second processing unit based on the states of the first in-frequency out-of-phase clock signal and the second in-frequency out-of-phase clock signal includes: based at least in part on the first One of the output latches of the processing unit is disabled and enabled by the The second processing unit receives the data. In some embodiments, enabling or disabling receipt of the data by the second processing unit based on the states of the first in-frequency out-of-phase clock signal and the second in-frequency out-of-phase clock signal includes: based at least in part on the first One of the output latches of the processing unit is disabled and the second clock signal represents a specific logic value to enable the second processing unit to receive the data. In some embodiments, enabling or disabling receiving the data by the second processing unit based on the states of the first in-frequency out-of-phase clock signal and the second in-frequency out-of-phase clock signal further includes: based at least in part on the first The output latch of a processing unit is in an enabled state and/or the second clock signal indicates a logic value different from the specific logic value to disable reception of the data by the second processing unit.

In some embodiments, the method further includes disabling an output latch of the first processing unit based on the first clock signal representing a specific logic value, wherein based on the first in-frequency out-of-phase clock signal and the Enabling or disabling the second processing unit to receive the data by the state of the second in-phase out-of-phase clock signal includes: enabling the second processing unit to receive the data based at least in part on the first clock signal representing the specific logic value data. In some embodiments, the method further includes disabling an output latch of the first processing unit based on the first clock signal representing a first logic value, wherein based on the first in-frequency out-of-phase clock signal and Enabling or disabling the state of the second in-phase out-of-phase clock signal to enable or disable receiving the data by the second processing unit includes: at least partially based on the first clock signal representing the first logical value and the second clock signal representing A second logic value enables the second processing unit to receive the data. In some embodiments, enabling or disabling receiving the data by the second processing unit based on the states of the first in-frequency out-of-phase clock signal and the second in-frequency out-of-phase clock signal further includes: based at least in part on the first A clock signal indicates a logical value different from the first logical value and/or the second clock signal indicates a logical value different from the second logical value to disable reception of the data by the second processing unit.

In some embodiments, the first in-frequency out-of-phase clock signal includes a first differential clock signal of a first differential signal pair, and the second in-frequency out-of-phase clock signal includes a One of the second differential signal pair is the second differential clock signal. In some embodiments, the method further includes generating the second differential signal pair of the second differential clock signal, which includes: in response to a transition of a first signal of one of the first differential signal pair and the A complementary transition of one of the second differential signal pair and a second signal sets a logical value of the second differential signal pair to match a logical value of the first differential signal pair.

According to another aspect of the present invention, a computer-implemented electronic design automation method is provided. The method includes: synthesizing a circuit schematic diagram of a part of the same frequency out-of-phase system. The in-frequency out-of-phase system includes a plurality of processing units operable to synchronize respective processing with a plurality of out-of-phase clock signals in the same frequency. The equivalent frequency out-of-phase clock signal includes a first clock signal and a second clock signal having the same frequency and different phases. The processing units include a first processing unit operable to synchronize processing with the first clock signal and a second processing unit operable to synchronize processing with the second clock signal. The second processing unit is coupled to receive data from the first processing unit. Synthesizing the circuit schematic diagram includes generating a schematic diagram of a latch circuit of the second processing unit. The latch circuit is coupled to receive data from the first processing unit and is configured to operate based on the state of the first clock signal and the second clock signal.

In some embodiments, the method further includes simulating the operation of the circuit diagram by a computer, which includes simulating the operation of the latch circuit. In some embodiments, the method further includes: generating a physical layout of the circuit diagram from a computer. In some embodiments, the method further includes: generating, by a computer, a plurality of mask patterns for manufacturing an integrated circuit including the latch circuit.

Other aspects and advantages of some embodiments will be understood from the following drawings, detailed descriptions, and technical solutions. The drawings, detailed descriptions, and technical solutions all illustrate the principles of some embodiments by way of example only.

100‧‧‧ same frequency out of phase system

101‧‧‧Input data terminal

105‧‧‧Output data terminal

110a‧‧‧Transmission processing unit

110b‧‧‧Reception processing unit

120a‧‧‧clock signal

120b‧‧‧clock signal

130‧‧‧input latch

130a‧‧‧input latch

130b‧‧‧input latch

130c‧‧‧input latch

130d‧‧‧input latch

130s‧‧‧input latch

132‧‧‧Input data terminal

134‧‧‧Output data terminal

136‧‧‧Enable terminal

138‧‧‧Enable terminal

140a‧‧‧processing circuit

140b‧‧‧processing circuit

140c‧‧‧processing circuit

150‧‧‧Output latch

150a‧‧‧output latch

150b‧‧‧output latch

150c‧‧‧output latch

152‧‧‧Input data terminal

154‧‧‧Output data terminal

156‧‧‧Enable terminal

200‧‧‧Timing chart

201‧‧‧ period

202‧‧‧ period

203‧‧‧ period

204‧‧‧ Delay

250‧‧‧Timing chart

251‧‧‧ period

252‧‧‧ period

253‧‧‧ period

254‧‧‧delay/phase difference

310‧‧‧Data input terminal

312‧‧‧Enable terminal

321‧‧‧ "Reverse OR" gate

322‧‧‧ "Reverse OR" gate

330‧‧‧Data output terminal

332‧‧‧Data output terminal

440‧‧‧ input node/internal node

500‧‧‧Differential signal repeater

502‧‧‧Input terminal

504‧‧‧Input terminal

506a‧‧‧Output terminal

506b‧‧‧Output terminal

600‧‧‧Processing unit chain

601a‧‧‧processed data/output data

603‧‧‧Enter data

610‧‧‧ processing unit

610a‧‧‧First processing unit

610b‧‧‧second processing unit

610c‧‧‧ processing unit

620a‧‧‧clock signal

620b‧‧‧clock signal

620c‧‧‧clock signal

623‧‧‧clock signal

630a‧‧‧clock buffer

630b‧‧‧clock buffer

630c‧‧‧clock buffer

700‧‧‧ same frequency out of phase system

701‧‧‧Enter data

702‧‧‧clock signal

703‧‧‧ Output data

710‧‧‧Control unit

720a‧‧‧processing node

720b‧‧‧processing node

720c‧‧‧processing node

720x‧‧‧ processing node

730a‧‧‧Communication unit

730b‧‧‧Communication unit

730c‧‧‧Communication unit

730x‧‧‧Communication unit

800‧‧‧ Electronic Design Automation (EDA) tool

810‧‧‧Design Module

820‧‧‧Verification module

830‧‧‧Manufacture module

900‧‧‧Computer

902‧‧‧ processor

904‧‧‧Memory device

D‧‧‧Enter data

E‧‧‧Signal

M1‧‧‧p-type metal oxide semiconductor field effect transistor (MOSFET)

M2‧‧‧p-type metal oxide semiconductor field effect transistor (MOSFET)

M3‧‧‧p-type metal oxide semiconductor field effect transistor (MOSFET)

M4‧‧‧n-type metal oxide semiconductor field effect transistor (MOSFET)

M5‧‧‧n-type metal oxide semiconductor field effect transistor (MOSFET)

M6‧‧‧n-type metal oxide semiconductor field effect transistor (MOSFET)

M11‧‧‧Field Effect Transistor (FET)

M12‧‧‧Field Effect Transistor (FET)

Q‧‧‧Data output

Some advantages of some embodiments can be understood by referring to the following description in conjunction with the accompanying drawings point. In the drawings, the same element symbols generally refer to the same parts in all different views. In addition, the drawings are not necessarily drawn to scale, but generally focus on illustrating the principles of some embodiments of the present invention.

FIG. 1 is a block diagram of an in-frequency out-of-phase system according to some embodiments.

2A is an example of a timing diagram of an in-frequency out-of-phase system with a single-ended clock signal according to some embodiments.

2B is an example of a timing diagram of an in-frequency out-of-phase system with a differential clock signal according to some embodiments.

3 is a schematic diagram of an input latch of a processing unit of a system with a single-end clock signal of the same frequency and out of phase according to some embodiments.

4 is a schematic diagram of an input latch of a processing unit of a system having a differential clock signal of the same frequency but out of phase according to some embodiments.

FIG. 5 is a block diagram of a differential signal repeater according to some embodiments.

6 is a block diagram of a chain of processing units according to some embodiments.

7 is a block diagram of another co-frequency out-of-phase system according to some embodiments.

8 is a block diagram of an electronic design automation (EDA) tool according to some embodiments.

9 is a block diagram of a computer according to some embodiments.

In some cases, in-frequency out-of-phase processing may provide advantages over synchronous processing. As described above, synchronizing the processing units in a synchronous system to a system-wide clock allows the processing units to perform data processing and transmission operations consistent with the clock pace. Since different processing units are synchronized to the same clock signal, the processing unit can generally use conventional latches synchronized to a common clock to exchange data. However, the current drawn by a synchronous system will be very fast at certain points during the clock cycle of the whole system clock (for example, for a system synchronized to the rising clock edge, at the rising edge of each clock cycle) To increase. This rapid change in current drawn by the system ("current spike") can cause electromagnetic interference and/or power supply noise, which can affect synchronous systems (especially systems with high clock frequencies and/or low power supply voltages) ) Operation has adverse effects. In addition, the amplitude of the current drawn during a current spike can be significantly higher than the average current load of the synchronous system, which means that the maximum load on the power supply of the system can be much larger than the average load on the power supply. Since the design of the power supply of a synchronous system is generally determined by the maximum load rather than the average load, adapting to these current spikes will significantly increase the size and cost of the power supply of a synchronous system.

In contrast, the processing units in the same-frequency out-of-phase system are synchronized to the same-frequency out-of-phase clock signals with the same frequency and different phases. For example, in a system with frequency in-phase, allows the processing unit P _A and P _B, respectively, in synchronization with the rising edge of the clock signal of the C _A and C _B, wherein the clock signal C _A and C _B has substantially the same frequency, but the rising edge of the clock signal C _A offset rising edge of clock signal C _B respect. Since the processing unit P _A and P _B performs processing of data transmission and the synchronized operation to occur at different times, the processing unit of the peak current loads may occur at different times, rather than simultaneously. Therefore, the current load in the out-of-phase system of the same frequency can be more evenly distributed over the entire clock cycle than the current load of a synchronous system for comparison, and the adverse side effects (such as electromagnetic interference, Power supply noise, etc.) can be significantly smaller in the same frequency out of phase system. In addition, the maximum load on the power supply of the same frequency out-of-phase system can be significantly lower than the maximum load on a power supply for the comparison synchronous system, thereby allowing the use of a smaller and/or cheaper power supply in the same-frequency out-of-phase system Device.

The potential advantages of the same frequency out of phase system are not limited to reducing the side effects of current spikes. For example, in a synchronous system, the signal of the whole system clock can be degraded and/or deviated at different parts of the system due to changes in clock path parasitics (such as resistance and capacitance) and delay and changes in the delay of the clock signal oblique. Synchronizing the processing unit of the system to a degraded or skewed system-wide clock signal reduces the margin of components of the system synchronized with the clock. To ease the clock drop For level and skew problems, stronger drivers and transponders can be used for the entire system clock. However, the use of strong clock signal drivers and transponders can increase the power consumption of the system and/or cause electrical interference with other signals in the system. In contrast, since systems of the same frequency and different phases do not need to distribute a whole system of clock signals, these systems are generally not affected by problems caused by clock skew and degradation. Therefore, it is generally possible to implement the clock distribution of the in-frequency and out-of-phase system with higher efficiency and lower power consumption than the clock distribution of the synchronous system.

On the other hand, it is more difficult to transfer data between processing units synchronized to different clock signals. In-frequency out-of-phase circuits generally use dedicated data transceivers to transmit data between processing units in different clock domains. These data transceivers can be larger, more complex, inefficient, and/or an important source of power consumption. Therefore, efficient techniques are needed to transfer data between processing units in different clock domains of the same frequency out-of-phase system.

The present invention describes techniques for efficiently transmitting data between processing units in different clock domains of a common frequency out-of-phase system. The on-band out-of-phase system may include a processing unit P _TX that uses an output latch L _TX to transmit data to another processing unit P _RX , and the processing unit P _RX uses an input latch L _RX to receive the data. Synchronize the operation of the transmission processing unit P _TX with a clock signal C _TX (such as the rising edge of C _TX ), and synchronize the operation of the reception processing unit P _RX with a clock signal C _RX (such as the rising edge of C _RX ). The clock signals have substantially the same frequency and different phases. Based on the clock signal C _TX control (enabling / disabling) the transmission processing unit P _TX of the output latch L _TX, and a logical combination of signals and clock one clock signal C _RX C _TX control based on the reception processing unit P _RX The input latch L _RX .

Some embodiments of the above technology are effective because the receiver P _RX can determine whether the incoming data from the transmitter P _TX is stable based on the state of the transmitter clock signal C _TX because the transmitter clock signal C _TX controls the output latch L _{TX of the} transmitter. For example, if the output latch L _TX is a positive latch, the receiver P _RX can determine that when the transmitter's clock signal C _TX is high, the incoming data from the latch L _TX is stable of. In addition, in some embodiments, the above technique can be implemented efficiently and with low complexity by transmitting the clock signal C _TX of the transmitter together with the transmission data from the transmission unit P _TX to the reception unit P _RX . In some embodiments, the receiving processing unit P _RX not only uses the transmitter's clock signal C _TX to determine when the incoming data from the transmitting unit P _TX is stable, _{but also} generates its own time based on the transmitter's clock signal C _TX Pulse signal C _RX .

Particular embodiments of the subject matter described in this disclosure can be implemented to achieve one or more of the above-mentioned advantages.

FIG. 1 is a block diagram of the same-frequency out-of-phase system 100. The same-frequency out-of-phase system 100 includes an input data terminal 101 and an output data terminal 105. The in-frequency out-of-phase system 100 includes a transmission processing unit 110a and a reception processing unit 110b. The transmission processing unit 110a includes a processing circuit 140a. The reception processing unit 110b includes a processing circuit 140b. The processing circuit 140a is synchronized with a clock signal 120a (eg, the rising edge of the clock signal 120a). The processing circuit 140b is synchronized with a clock signal 120b (eg, the rising edge of the clock signal 120b). The clock signals 120a and 120b may have substantially the same frequency (eg, equal frequencies or frequencies within 10% of each other) and different phases, as will be described further below. In some embodiments, the frequency of the clock signal 120 may be between about 1 MHz and about 15 GHz or between about 10 GHz and about 15 GHz.

A processing circuit 140 may be a circuit for processing data and/or instructions, such as an adder, a multiplier, a pre-fetcher, a decoder, or a microprocessor core. Other types of processing units are feasible. In some embodiments, a processing circuit performs a hash or a hash function (eg, a cryptographic function). Examples of cryptographic hash functions include SHA-2 (conservative hash algorithm 2) functions, which include (but are not limited to) SHA-256 and SHA-512. The processing circuit 140a (of the transmission processing unit 110a) and the processing unit circuit 140b (of the reception processing unit 110b) may be two examples of the same processing circuit or different types of processing circuits.

Since the processing units 110a and 110b are synchronized with clock signals having different phases, the in-frequency out-of-phase system 100 uses a multi-phase technique to transfer data from the transmission processing unit 110a Sent to the reception processing unit 110b. The multi-phase communication technology is implemented by the output latch 150 of the transmission processing unit 110a and the input latch 130 of the reception processing unit 110b. Some embodiments of multi-phase communication technology are described below with reference to FIGS. 2A-2B.

The output latch 150 includes: an input data terminal 152, which is coupled to an output data terminal of the processing circuit 140a; an output data terminal 154, which is coupled to the reception processing unit 110b; and an enable terminal 156, which is coupled to the clock Signal 120a. The input latch 130 includes: an input data terminal 132 coupled to the output data terminal 154 of the output data latch 150 (of the transmission processing unit 110a); and an output data terminal 134 coupled to a data of the processing circuit 140b An input terminal; an enable terminal 136, which is coupled to the clock signal 120a; and another enable terminal 138, which is coupled to the clock signal 120b.

In the in-frequency out-of-phase system 100, when the output latch 150 is in a holding state (which is determined based on the state of the clock signal 120a that controls the output latch 150), the reception processing unit 110b receives data from the transmission processing unit 110a . As will be described below with reference to FIGS. 2A and 2B, unless the output latch 150 (of the transmission processing unit 110a) is in the holding state, the input latch 130 of the reception processing unit 110b cannot be enabled (from the transmission processing unit 110a ) Receive information.

FIG. 2A is an example of a timing diagram 200 of the same-frequency out-of-phase system 100, in which the clock signals 120a and 120b are single-ended signals having substantially the same frequency and different phases. In the example of FIG. 2A, the rising edge of the clock signal 120b occurs at about three-quarters of one clock period after the previous rising edge of the clock signal 120a. Therefore, in the example of FIG. 2A, the phase difference between the clock signal 120b and the clock signal 120a is approximately three quarters of a clock cycle.

As described above, the in-frequency out-of-phase system 100 includes a processing circuit 140a synchronized with the clock signal 120a and a processing circuit 140b synchronized with the clock signal 120b. In some embodiments, the processing circuit 140a is synchronized with the rising edge of the clock signal 120a, so that the processing circuit 140a and the rising edge of the clock signal 120a transmit the output data to the output in accordance with the pace The input data terminal 152 of the latch 150. In some embodiments, the output latch 150 performs positive latching, such that when the clock signal 120a is in a high state (eg period 201), the output latch is in a holding state and the clock signal 120a is in a low state (eg At time 202), the output latch is in the transparent state.

In some embodiments, the processing circuit 140b is synchronized with the rising edge of the clock signal 120b, so that the processing circuit 140b and the rising edge of the clock signal 120b transmit the output data on the output terminal 105 (e.g., to another lock) Memory). In some embodiments, the input latch 130 performs negative latching, so that when the enable condition of the latch is "true", the input latch 130 is in a transparent state, and when the enable condition of the latch is When "false", the input latch 130 is in a holding state. In some embodiments, when the clock signal 120a is high and the clock signal 120b is low (eg, period 203), the enable condition of the input latch 130 is "true" (and the latch is in the transparent state ). In some embodiments, when the clock signal 120a is low or the clock signal 120b is high, the enable condition of the input latch 130 is "false" (and the latch 130 is in a hold state). In this way, the clock signal 120b is low (which indicates that the input latch 130 has provided the previous data to the processing circuit 140b and is ready to receive new data) and the clock signal 120a is high (which indicates: the output lock When the register 150 is in a holding state and thus transmits new data to the input latch 130), the above-described embodiment of the input latch 130 is in a transparent state (ready to receive new data). In contrast, the clock signal 120b is high (which indicates that the input latch 130 is still providing the previous data to the processing circuit 140b and is therefore not ready to receive new data) or the clock signal 120a is low (which indicates : When the output latch 150 is in the transparent state and therefore is not ready to transmit new data), the above embodiment of the input latch 130 is in the holding state (not ready to receive new data).

In some embodiments, the clock signal 120b (eg, using an inverter) is generated as the inverse of the clock signal 120a with a delay 204. For example, the delay may be a propagation delay from the clock input of the processing circuit 140a to the enable input 138 of the input latch 130 (e.g. For example, a 16nm process is used to fabricate 50 picoseconds to 100 picoseconds in a wafer) (which includes the delay through the inverter). In this way, when the output latch 150 is in a hold state (eg, period 201), the input latch 130 is at the rising edge of the clock signal 120a that has been output by the output latch 150 (eg, before period 201 ) After the data is latched, the data is received from the output latch 150 (for example, during the period 203).

2B is an example of a timing diagram 250 of the same-frequency out-of-phase system 100, in which the clock signals 120a and 120b are differential clock signals having substantially the same frequency and different phases. As can be seen in FIG. 2B, the differential clock signal 120a includes a differential signal pair CLKP and CLKN, and the differential clock signal 120b includes a differential signal pair CLKNQ and CLKPQ. In the example of FIG. 2B, the rising edge of the signal CLKPQ occurs approximately one quarter of a clock period after the rising edge before the signal CLKP. Therefore, in the example of FIG. 2B, the phase difference between the clock signal 120b and the clock signal 120a is approximately a quarter of a clock cycle.

As described above, the in-frequency out-of-phase system 100 includes a processing circuit 140a synchronized with the clock signal 120a and a processing circuit 140b synchronized with the clock signal 120b. In some embodiments, the processing circuit 140a is synchronized to the rising edge of the signal CLKP, so that the processing circuit 140a transmits the output data to the input data terminal 152 of the output latch 150 in step with the rising edge of the signal CLKP. In some embodiments, the output latch 150 performs positive latching, such that when the signal CLKP is high and the signal CLKN is low (eg, period 251), the output latch is in a holding state, and when the signal CLKP is When the signal CLKN is low and the signal CLKN is high (for example, period 252), the output latch is in the transparent state.

In some embodiments, the processing circuit 140b is synchronized to the rising edge of the signal CLKPQ, so that the processing circuit 140b transmits the output data on the output data terminal 105 in synchronization with the rising edge of the signal CLKPQ (eg, to another latch) . In some embodiments, the input latch 130 performs negative latching, so that when the enable condition of the latch is "true", the input latch 130 is in a transparent state, and when the enable condition of the latch is When "false", the input latch 130 is in a holding state. In some embodiments, when the signal CLKP is high and the signal CLKPQ is low (eg, period 253), the enable condition of the input latch 130 is "true" (and the latch is in the transparent state). In some embodiments, when the signal CLKP is low or the signal CLKPQ is high, the enable condition of the input latch 130 is "false" (and the latch 130 is in the hold state). In this way, when the signal CLKPQ is low (which indicates that the input latch 130 has provided the previous data to the processing circuit 140b and is ready to receive new data) and the signal CLKP is high (which indicates that the output latch 150 is on hold While in the state and therefore transmitting new data to the input latch 130), the above-described embodiment of the input latch 130 is in a transparent state (ready to receive new data). In contrast, when the signal CLKPQ is high (which indicates that the input latch 130 is still providing the previous data to the processing circuit 140b and is therefore not ready to receive new data) or the signal CLKP is low (which indicates: the output latch When the memory 150 is in the transparent state and therefore is not ready to transmit new data), the above-described embodiment of the input latch 130 is in the holding state (not ready to receive new data).

As will be described further below with reference to FIG. 5, a differential clock signal 120b (eg, using a differential signal transponder) can be generated as the inverse of the differential clock signal 120a. The switching of the differential clock signal 120b (eg, the switching of the signals CLKNQ and CLKPQ) may occur after a delay 254 relative to the switching of the differential clock signal 120a (eg, the switching of the signal CLKN and/or signal CLKP). For example, the delay 254 may include a propagation delay from the clock input of the processing circuit 140a to the enable input 138 of the input latch 130 (e.g., using a 16nm process to manufacture 50 picoseconds to 100 picoseconds in a wafer ) (Which includes the delay through the differential signal transponder). In this way, when the output latch 150 is in the holding state (eg period 251), the input latch 130 is at the rising edge of the clock signal 120a that has been output by the output latch 150 (eg, before the period 251 ) After the data is latched, the data is received from the output latch 150 (for example, during the period 253).

An example has been described herein in which the positive edge trigger processing circuit (140a, 140b), the output latch 150 performs positive latching, and the input latch 130 performs negative latching. In some implementations For example, other timing and latching schemes can be used. For example, the processing circuit (140a, 140b) may be triggered by a negative edge, the output latch 150 may perform negative latching, and the input latch 130 may perform positive latching. Any suitable combination of positive/negative edge trigger processing unit, positive/negative output latch, and/or positive/negative input latch can be used.

In some embodiments, if the set time and/or hold time restrictions on the input data are not met, the input latch 130 may incorrectly latch the input data. The set time is only a period of time before the input latch 130 enters the hold state. The hold time is only a period of time after the input latch 130 enters the hold state. Set time and hold time restrictions: Unless the input data is stable during the set time period and hold time period, the proper latch of the input data cannot be guaranteed. In some embodiments, the phase difference between the clock signals 120a and 120b may be adjusted to ensure that the set time limit and/or hold time limit are met. The phase difference can be adjusted, for example, by increasing or decreasing the delay 204 (or 254). In some embodiments, the delay 204 (or 254) can be increased by inserting an additional delay element between the clock input of the processing unit 140a and the enable input 138 of the input latch 130.

FIG. 3 shows an embodiment of an input latch 130s, which is used in a receiving and processing unit 110b of a system 100 having a single-ended clock signal of the same frequency and out of phase. In the example of FIG. 3, the input latch 130s is a gated D latch, which has: a data input terminal 310; an enable input terminal 312; and a data output terminal 330, which provides matching and is stored by the latch One of the values is the data output Q; and a data output terminal 332, which provides a data output Q', which is the inverse of the value stored by the latch. When the signal (E) at the enable terminal 312 is high, the latch 130s is in the transparent state, so that the input data D is provided to the SR latch ("OR" gates 321 and 322 and the coupling between them ), the SR latch stores the input data D at the output data terminal 330 and stores the inverse of the input data D at the output terminal 332. When the signal (E) at the enable terminal is in a low state, the latch 130s is in a hold state, so that even if the input data D changes, the values on the data output terminals 330 and 332 are maintained. hold. In the example of FIG. 3, the "SR" gate is used to implement the SR latch. In some embodiments, "SR" gates and/or any other suitable circuit components are used to implement the SR latch.

In some embodiments, the data input terminal 310 of the D latch is coupled to the data input terminal 132 of the input latch 130s, and the non-inverting data output terminal 330 of the D latch is coupled to the data output of the input latch 130s Terminal 134, and the enable terminal 312 of the D latch is coupled to receive a signal which is the reverse of the clock signal 120a (provided at the enable terminal 136) and the clock signal 120b (provided at the enable terminal 138) The logical "and". In this way, when the clock signal 120a is in a high state and the clock signal 120b is in a low state, the input latch 130s is in a transparent state (eg, period 203 shown in FIG. 2A).

FIG. 4 shows an embodiment of an input latch 130d, which is used in a receiving processing unit 110b of a system 100 having a differential clock signal of the same frequency but out of phase. Other implementations of input latch 130 are possible. In the example of FIG. 4, the input latch 130d includes p-type metal oxide semiconductor (p-type MOS or PMOS) field-effect transistors (FETs) M1, M2, and M3, which are coupled in series to a power supply node A diffusion terminal between one input node 440 and a buffer circuit. The buffer circuit includes an inverter (FETs M11 and M12) that has its input coupled to the input node 440 and its output coupled to the output terminal 134 of the latch. The input latch 130d also includes n-type MOSFETs M4, M5, and M6, which have diffusion terminals coupled in series between the input node 440 and a reference (ground) node.

In the example of FIG. 4, the gate terminals of the n-type FET M4 and the p-type FET M1 are coupled to receive data from the output latch 150 of the transmission processing unit 110a (at the input data terminal 132). The gate terminals of n-type FET M5 and p-type FET M2 are coupled (at enable terminal 136) to receive the components of differential clock signal 120a (eg, signals CLKP and CLKN, respectively). The gate terminals of n-type FET M6 and p-type FET M3 are coupled (at enable terminal 138) to receive the components of differential clock signal 120b (eg, signals CLKNQ and CLKPQ, respectively).

The input latch 130d operates to implement the above-described functions of the input latch 130. E.g, When CLKN and CLKPQ are low and CLKP and CLKNQ are high (for example, period 253 in FIG. 2B), M2, M3, M5, and M6 are turned on, thereby putting the input latch 130d in the transparent state . In this case, M1 and M4 together act as an inverter, and the internal node 440 has the inverted value of the input data terminal 132, and the output terminal 134 has the same value as the input data terminal 132, that is, the input latch 130d It is in the transparent state, and a data value (the value inverted to the input terminal 132) is locked at the internal node 440.

At the end of the period 253 shown in FIG. 2B, CLKP transitions to a low value and CLKN transitions to a high value, thus turning off M5 and M2 (for example, in a high impedance state), thereby placing the input latch 130d Remaining. In this case, the internal node 440 is tri-stated, and regardless of the change of the input data on the input data terminal 132, the data value previously stored at the internal node 440 (eg, the potential of the internal node 440) is maintained. Therefore, regardless of the change of the input data on the input data terminal 132, the output terminal 134 maintains the same value it maintained at the end of the period 253.

Although not shown in the example of FIG. 2B, in the case where the in-frequency out-of-phase difference 254 is greater than one half of the period of the clock signal 120, when CLKPQ transitions to a high value and CLKNQ transitions to a low value, the input latch 130d From the transparent state to the holding state, M3 and M6 are cut off. In this case, the internal node 440 is tri-stated, regardless of changes in the input data on the input data terminal 132, the data value previously stored at the internal node 440 is maintained, and the data value of the output terminal 134 is maintained.

In the example of FIG. 4, the input latch 130 is implemented as one of the C ² MOS D latches with modified enable logic. Other implementations of input latch 130 are possible. In some embodiments, the input latch 130 is implemented as a dynamic transmission gate edge-triggered latch with one of modified enable logic, a double-edge latch with one of modified enable logic, and/or any other suitable latch Circuit.

In the examples of FIGS. 3 and 4, the input latch 130 and the output latch 150 are described as unit cell latches that store, receive, and transmit one unit of data. In some embodiments In this case, the input latch 130 and the output latch 150 are N-bit latches that store, receive, and transmit N-bit data. In some embodiments, an N-bit latch is constructed by copying components of the unit latch N times, wherein the enable terminal of each unit latch is coupled to the same control signal, and the unit latch The input data terminals of each are coupled to different input data signals.

In some embodiments, it is possible to use a differential signal repeater (for example, the US patent application named "System and Techniques for Repeating Differential Signals" filed on January 5, 2016 according to the agency case number BFY-002 The differential signal repeater described in case No. 14/988,371, which is incorporated by reference to the maximum extent permitted by applicable law) and the differential clock signal 120b is generated from the differential clock signal 120a . FIG. 5 shows a block diagram of a differential signal repeater 500 according to some embodiments. The differential signal repeater receives a signal pair on input terminals 502 and 504 as input, and provides a signal pair on output terminals 506a and 506b as output. In some embodiments, input terminals 502 and 504 are coupled to receive components of differential clock signal 120a (eg, differential signal pairs CLKP and CLKN), and signal repeater 500 is configured to be on output terminals 506a and 506b The components of the differential clock signal 120b are provided (eg, differential signal pairs CLKPQ and CLKNQ).

When CLKP and CLKN have complementary values, the differential signal repeater 500 operates to provide a pair of output differential signals CLKPQ and CLKNQ having complementary values at the output terminals 506a and 506b. In some embodiments, when CLKP and CLKN have complementary values, the values of CLKPQ and CLKNQ are inverses of the values of CLKP and CLKN, respectively. When the input signals (CLKP and CLKN) represent non-complementary values, the differential signal repeater 500 places the output terminals (506a, 506b) in a high impedance state. As described in US Patent Application No. 14/988,371, in some embodiments, the differential signal repeater 500 may only switch after the two components (CLKP, CLKN) of the input differential signal (clock signal 120a) are switched The components (CLKPQ, CLPNQ) of the differential signal (clock signal 120b) are switched and output.

Since the differential signal repeater 500 can adapt to a situation in which the input differential signals CLKP and CLKN are not switched simultaneously (or within a specified time window), the differential signal repeater 500 can tolerate any of the input differential signals The change (eg, process change) of the switch at a time later than its complementary counterpart or at a prescribed time window relative to the switch of its counterpart. Even when one of the input differential signals is switched later than the other input differential signal (for example, outside a prescribed time window with respect to the switching of the other input differential signal), the differential signal repeater 500 may be simultaneously or almost At the same time (for example, within one of the specified time windows of each other), the output of the differential signal is switched. Therefore, the output differential signal of the differential signal repeater 500 may have less skew than the input differential signal of the signal repeater, because the time period between the complementary transitions of the output differential signal of the differential signal repeater may be shorter The time period between the complementary transitions of the input differential signal of the differential signal repeater. As will be discussed below with reference to FIG. 6, a set of differential signal repeaters 500 can be used to propagate differential clock signals among all multiple components of a common frequency out-of-phase system, thereby preventing, canceling, or correcting differential clock signals Skewed. Preventing, canceling or correcting the skew shift of a differential signal may be referred to herein as a "skew limit" differential signal.

6 shows a chain 600 of processing units 610 according to some embodiments. The chain 600 includes a plurality of processing units 610a, 610b, 610c, and so on. In some embodiments, the processing units 610 in the chain 600 may be arranged in a column or a row. Any suitable number of processing units may be included in the chain 600, such as two or more processing units, or between 2 processing units to 300 processing units, or between 20 processing units to 30 processing units , Or 25 processing units, etc. Each processing unit includes a processing circuit (eg 140a, 140b or 140c). As described earlier, each processing circuit may be a circuit that processes data and/or instructions. The processing circuits in the chain 600 may be the same or different types of processing circuits. In some embodiments, each processing unit includes an input latch (such as 130a to 130c), an output latch (such as 150a to 150c), and a clock buffer (such as 630a to 630c).

In the example of FIG. 6, input data 603 (such as one unit of data or multiple bits Data) and a clock signal 623 (such as a differential clock signal) are provided to the input terminal of the first processing unit 610a. The clock buffer 630a buffers the clock signal 623 to generate a clock signal 620a that is phase shifted relative to the clock signal 623. The input latch 130a latches input data based on the state of the input clock signal 623 and the state of the phase shifted clock signal 620a, as described above. The processing circuit 140a processes the latched input data in step with the clock signal 620a. The output latch 150a also latches the processed data in step with the clock signal 620a and transmits the processed data 601a to the input terminal of the second processing unit 610b. The clock buffer 630a also provides the clock signal 620a to an input terminal of the processing unit 610b. Those of ordinary skill should understand that the latches and signal repeaters of the processing units 610b and 610c can operate in the same manner as the corresponding latches and signal repeaters of the processing unit 610a.

As described above, the operations of each input latch 130, processing circuit 140, and output latch 150 may be synchronized with one or more clock signals. In some embodiments, the clock signals 623 and 620a to 620c may be single-ended clock signals, and the clock buffers 630a to 630c may be inverters. In some embodiments, the clock signals 623 and 620a to 620c may be differential clock signals, and the clock buffers 620a to 620c may be differential signal repeaters 500. In some embodiments, the processing circuit 140a and the output latch 150a of the first processing unit 610a of the chain 600 are synchronized to the clock signal 620a, and the processing circuit 140b and the output latch 150b of the processing unit 610b are synchronized to the clock Signal 620b, and synchronizes the processing circuit 140c and the output latch 150c of the processing unit 610c with the clock signal 620c. In some embodiments, the input latch 130a is synchronized to a logical combination of clock signals 623 and 620a, the input latch 130b is synchronized to a logical combination of clock signals 620a and 620b, and the input latch 130c is synchronized with a logical combination of clock signals 620b and 620c.

As just one example of the communication between the processing units 610 in the chain 600, the output latch 150a is coupled to the input latch 130b. After the clock signal 620a switches (for example, at the beginning of the period 251 in FIG. 2B), the clock signal 620b also switches (for example, at the beginning of the period 253 in FIG. 2B). When the signal CLKP of the differential clock signal 620a is high and the differential During the period when the signal CLKPQ of the pulse signal 620b is in the low state, the input latch 130b may be in the transparent state (and thus may be ready to receive the output data 610a from the output latch 150a), and the output latch 150a may be in the hold In state (and therefore the output data 601a can be transferred to the input latch 130b).

In some embodiments, as a special case, the first processing unit 610a in the chain 600 may omit the input latch 130a and the clock buffer 630a. The first processing unit 610a may include a conventional input latch instead of the input latch 130a, and as an alternative to the clock buffer 630a, the first processing unit 610a may input the clock signal without forwarding the signal 623 is provided to the second processing unit 610b. This embodiment has the advantage of reducing the size of the first processing unit 610a in the chain, and can be implemented when the input data 603 and the clock signal 623 are provided to the circuit of the first processing unit 610a at the same time as the first processing unit 610a Time in the pulse domain.

7 shows another in-frequency out-of-phase system 700 according to some embodiments. The system 700 includes a control unit 710 and multiple processing nodes (720a, 720b, 720c, etc.). For example, each processing node 720 may include a chain 600 of processing units 610. In some embodiments, each processing node 720 includes a communication unit 730 that transfers data between the processing node 720 and the control unit 710. In the example of FIG. 7, the communication unit 730 sends the output data 703 from the processing node 720 to the control unit 710. Alternatively or additionally, the communication unit 730 may send the input data 701 and/or the clock signal 702 from the control unit 710 to the processing node 720. In some embodiments, the communication unit 730 implements a bus (eg, a series of buses) between the control unit 710 and the processing node 720. The busbar can be unidirectional or bidirectional. In some embodiments, each processing unit in a processing node 720 may be coupled to the communication unit 730 of the processing node through one or more data lines, and the output data may be directly transmitted to the data line(s) through the data line(s). Communication unit 730.

In the example of FIG. 7, the control unit provides input data 701 and a clock signal 702 to each processing node 720 (eg, the first processing unit in the processing unit chain of the processing node 610). In some implementations, each processing node 720 may include a data latch to buffer input data from the control unit.

The control unit 710 and the processing node 720 can be organized according to any suitable topology. For example, the communication units 730 may be placed in a row at the center of the wafer, where a chain of processing units forms a column on both sides of each busbar unit. Control units and other organizations of processing nodes are feasible.

The same frequency out of phase system 700 can perform any suitable computing task. For example, the in-frequency out-of-phase system 700 can perform a bitcoin exploration task. In some embodiments, each processing node uses a random number ("temporary random number") to perform a hash operation to determine whether the hash value matches a given number. Each processing unit in the processing node uses the output data from the previous processing unit in the processing node to perform the part of the hash operation. Other processing tasks are feasible. Each processing unit in a processing node can operate based on data and clock signals provided by previous processing units in the processing node, making the system-wide clock unnecessary. Since the clock signal of each processing unit is automatically generated from the clock signal of the previous processing unit (for example, using one of the inverters or differential clock repeaters described above), the clock signal can be at a different rate (for example , Due to process changes) spread through different processing nodes.

Electronic Design Automation (EDA) tools

In some embodiments, an electronic design automation (EDA) tool can be configured to use the techniques described herein to facilitate the design, simulation, verification, and manufacture of in-phase out-of-phase circuits. Generally speaking, EDA tools are used to design, simulate, verify, and/or prepare the manufacture of electronic systems (eg, integrated circuits, printed circuit boards, etc.).

As shown in FIG. 8, some embodiments of an EDA tool 800 may include one or more modules, such as a design module 810, a verification module 820, and/or a manufacturing module 830. The design module 810 is operable to perform one or more design steps, including (but not limited to) a system design step, a logic design step, a circuit synthesis step, a plane planning step, and/or a physical implementation step. In the system design step, the design module 810 may (for example, from a The user) receives a description of one of the functions to be implemented by the system and can perform hardware-software architecture separation of the described functions. Examples of EDA software tools purchased from Synopsys that can be used to perform system design steps include model architecture, Saber, system studio, and DesignWare® products.

In the logic design step, the design module 810 can obtain a high-level logic description of the system (for example, a description of the system in a hardware design language (HDL) (which includes (but is not limited to) Verilog or VHDL)). In some embodiments, the design module 810 generates a logical description of the system (or part thereof) based on the functional description of the system. In some embodiments, the design module 810 receives a logical description of the system (or part of it) from a user. Examples of EDA software tools purchased from Synopsys that can be used to perform logical design steps include VCS, VERA, DesignWare®, Magellan, Formality, ESP, and LEDA products.

In the synthesis step, the design module 810 can convert the high-level logic description of the system into a circuit diagram that can be represented by a wiring table or a component of a circuit and any other suitable description of the connection between the components. In some embodiments, this synthesis step may include selecting one or more library units to perform the logic functions specified in the high-level logic description of the circuit. In some embodiments, the schematic diagram can be customized according to a specific IC technology (eg, the IC technology to be used to implement the system). Examples of EDA software tools purchased from Synopsys that can be used to perform synthesis steps include Design Compiler®, Physical Compiler, DFT Compiler, Power Compiler, FPGA Compiler, TetraMAX, and DesignWare® products.

In the plan planning step, the design module 810 may generate a plan view of an IC that will implement the system or one of its parts. Examples of EDA tools purchased from Synopsys that can be used to perform the planning steps include Astro and custom designer products.

In the physical implementation step, the design module 810 can generate a representation of a physical implementation of the system (eg, a physical layout of components of a system on an IC). The representation of the physical implementation of the production system may include: "place" the components of the circuit (determine that the components of the circuit are on the IC Position); and route the connection of the circuit (determine the position of the electrical conductor of the component of the coupling circuit on the IC). In some embodiments, this physical implementation step may include selecting one or more library units to implement the circuit components included in the circuit schematic. Examples of EDA tools purchased from Synopsys that can be used to perform physical implementation steps include Astro, IC Compiler, and custom designer products.

Returning to FIG. 8, the verification module 820 is operable to perform one or more verification steps, including (but not limited to) a simulation step, a functional verification step, a schematic verification (eg, wiring comparison table verification) step, a power Crystal level verification step, a plan verification step and/or a physical verification step. In the simulation step, the verification module 820 can simulate the operation of a representation of the system (such as a high-level logic description, circuit schematic, plan view, or layout of one of the systems).

In the function verification step, the verification module 820 checks the functional accuracy of the high-level logic description of the system. For example, the verification module 820 can simulate the operation of a high-level logic description of a circuit in response to a specific input to determine whether the logic description of the circuit produces a correct output in response to the inputs. Examples of EDA tools purchased from Synopsys that can be used in the functional verification steps include VCS, VERA, DesignWare®, Magellan, Formality, ESP, and LEDA products.

In the schematic verification step, the verification module 820 checks the compliance of the system schematic (eg, system wiring pair table) with the applicable timing restrictions and the correspondence with the high-level logic description of the circuit. Exemplary EDA tools purchased from Synopsys in the verification step include Formality, PrimeTime, and VCS products.

In the transistor-level verification step, the verification module 820 checks the compliance of one of the transistor-level representations of the system with the applicable timing restrictions and the correspondence with the high-level logic description of the circuit. Examples of EDA tools purchased from Synopsys that can be used in transistor-level verification steps include AstroRail, PrimeRail, PrimeTime, and Star-RCXT products.

In the floor plan verification step, the verification module 820 checks the compliance of the system floor plan with applicable restrictions (such as timing, top-level routing, etc.).

In the physical verification step, the verification module 820 checks the conformity of the representation of the physical implementation of the system (for example, the physical layout of one of the system components on an IC) with manufacturing restrictions, electrical restrictions, lithography restrictions, and/or schematic restrictions. The Hercules product purchased from Synopsys is an example of an EDA tool that can be used in the physical verification step.

Returning to FIG. 8, the manufacturing module 830 is operable to perform one or more steps to prepare the manufacturing system, including (but not limited to) a design finalization step and/or a resolution enhancement step. In the design finalization step, the manufacturing module 830 generates (eg, after applying lithography enhancement) design finalization data for generating a mask (which is used to perform lithographic manufacturing of the system's IC). Examples of EDA tools purchased from Synopsys that can be used in the design finalization process include IC Compiler and custom designer series of tools.

In the resolution enhancement step, the manufacturing module 830 can perform the geometric adjustment of the physical layout of the system to improve the manufacturability of the IC. Examples of EDA software products purchased from Synopsys that can be used in this resolution enhancement step include Proteus, ProteusAF, and PSMGen tools.

An EDA tool can perform an EDA method that includes one or more (eg, all) of the above design, verification, and/or manufacturing steps in any suitable order. In some embodiments, one or more of the design, verification, and/or manufacturing steps may be performed iteratively (eg, until the tool determines that the system meets certain limits and/or passes certain tests).

In some embodiments, one or more EDA tools may be used to design, verify, and/or manufacture the co-frequency out-of-phase system 100 or a portion thereof. For example, an EDA tool can be used to synthesize a schematic circuit diagram of a co-frequency out-of-phase system (or part thereof) (eg, based on a logical description of the system or part thereof). In some embodiments, the synthesis diagram may include an output latch 150 in the first processing unit and an input latch 130 in the second processing unit, wherein the output data terminal of the output latch is coupled to the input latch The input data terminal of the device. As another example, an EDA tool can generate a representation of a physical implementation of a system (eg, a physical layout of components of the system on an IC), which includes an output latch of a first processing unit 150 and the input latch 130 of the second processing unit. As another example, an EDA tool can generate a lithography mask suitable for manufacturing physical implementations of the same frequency out-of-phase system, which includes the output latch 150 and the input latch 130. In some embodiments, these lithography masks can be used with one or more process technologies to fabricate an IC that implements the same frequency out of phase system.

Further description of some embodiments

Some embodiments of an EDA tool 800 (or its modules, or methods, steps, or operations performed by an EDA tool 800 or its modules) can be implemented in digital electronic circuits, or in computer software, firmware, or hardware Body (which includes the structures disclosed herein and their structural equivalents), or implemented in a combination of one or more of the above. The subject implementation described in the present invention may be implemented as one or more computer programs encoded on a computer storage medium to be executed by or controlled by the data processing device, ie, one of the computer program instructions or Multiple modules.

Alternatively or additionally, the program instructions may be encoded on an artificial propagation signal (such as a machine-generated electrical, optical, or electromagnetic signal) that is generated to encode for transmission to a suitable receiver device for processing by a data Information on equipment implementation. A computer storage medium can be or can be included in the following: a computer readable storage device, a computer readable storage substrate, a random or serial access memory array or device, or one of these Or one of the combinations. Furthermore, when a computer storage medium is not a propagated signal, a computer storage medium may be a source or destination of computer program instructions encoded in an artificial propagated signal. Computer storage media may also be one or more separate physical components or media (such as multiple CDs, disks, or other storage devices) or contained in one or more separate physical components or media (such as multiple CDs, disks, or other Storage device).

Some embodiments of the methods, steps, and tools described in the present invention may be implemented as operations performed by a data processing device on data stored on one or more computer-readable storage devices or received from other sources.

The term "data processing equipment" covers all types of equipment used to process data, Devices and machines, including, for example, a programmable processor, a computer, a single-chip system, or more or a combination of the foregoing. The device may include dedicated logic circuits, such as an FPGA (field programmable gate array) or an ASIC (dedicated integrated circuit). In addition to the hardware, the device can also include codes that generate one of the execution environments of the computer program in question, such as codes that make up the following: processor firmware, a protocol stack, a database management system, and an operation A system, a cross-platform runtime environment, a virtual machine, or a combination of one or more of them. The device and execution environment can implement a variety of different computing model infrastructures, such as network services, distributed computing, and grid computing infrastructures.

It can be written into a computer program (also known as a program, software, software application, script, or code) in any form of programming language (including compiled or interpreted languages, descriptive or procedural languages), and The computer program is deployed in any form, including as a stand-alone program or as a module, component, subroutine, target, or other unit suitable for use in a computing environment. A computer program may (but is not required) correspond to a file in a file system. A program can be stored in a part of a file that holds other programs or data (such as one or more scripts in a markup language resource), in a single file dedicated to the program in question, or in In multiple coordination files (such as files that store one or more modules, subprograms, or coded parts). A computer program can be deployed to be executed on one computer or on multiple computers that are located at one location or distributed across multiple locations and interconnected by a communications network.

Some embodiments of the procedures and logic flows described in the present invention can be executed by one or more programmable processors that execute one or more computer programs to input data by operation and Generate output and perform actions. Some embodiments of the procedures and logic flows described in this document can be performed by dedicated logic circuits (such as an FPGA (field programmable gate array) or an ASIC (dedicated integrated circuit)), and the devices described in this document Some embodiments may be implemented as dedicated logic circuits, such as an FPGA (field programmable gate array) or an ASIC (dedicated integrated circuit).

Processors suitable for executing a computer program include, for example, both general and special microprocessors and any one or more processors of any kind of digital computer. Generally speaking, a processor will receive commands and data from a read-only memory or a random access memory or both.

9 shows a block diagram of a computer 900. The elements of the computer 900 include one or more processors 902 for performing actions according to instructions and one or more memory devices 904 for storing instructions and data. In some embodiments, the computer 900 executes an EDA tool 800. Different versions of EDA tool 800 can be stored, distributed or installed. Some versions of the software can only implement some embodiments of the methods described herein.

In general, a computer 900 will also include one or more mass storage devices (such as magnetic disks, magneto-optical disks, or optical disks) for storing data, or will be operatively coupled to remove the one or more large capacity The storage device receives the data or transfers the data to the one or more mass storage devices, or both. However, a computer need not have such devices. Furthermore, a computer can be embedded in another device (for example, to name a few) a mobile phone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a global positioning system (GPS) receiver Device or a portable storage device (such as a universal serial bus (USB) flash drive). Devices suitable for storing computer program instructions and data include all forms of non-volatile memory, media, and memory devices, including (for example): semiconductor memory devices, such as EPROM, EEPROM, and flash memory devices; magnetic Disks, such as internal hard disks or removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks. The processor and memory can be supplemented by or incorporated into dedicated logic circuits.

A computer (which has: a display device for displaying information to a user, such as a CRT (cathode ray tube) or LCD (liquid crystal display) monitor; and the user can use it to provide input to A keyboard of a computer and a pointing device, such as a mouse or a trackball, implement the subject implementation described in the present invention to provide interaction with the user. Other types of devices can also be used to provide interaction with a user; for example, to The user's feedback can be any form of sensory feedback, such as visual feedback, auditory feedback, or tactile feedback; and input from the user can be received in any form (including sound, voice, or tactile input). In addition, a computer can send resources to or receive resources from a device for use by a user (eg, by responding to a request received from a web browser on a user's client device Send the webpage to the web browser) to interact with the user.

Some embodiments may be implemented in a computing system that includes a back-end component (for example) as a data server, or includes an intermediate software component (for example an application server), or includes a front-end component (for example A client computer with a graphical user interface or a web browser through which a user can interact with one of the subject implementations described in the present invention), or including one or more of these backends Any combination of components, middleware components or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (such as a communication network). Examples of communication networks include a local area network ("LAN") and a wide area network ("WAN"), a global network (such as the Internet), and peer-to-peer networks (such as special peer-to-peer networks) .

The computing system may include a client and a server. A client and server are generally remote from each other and usually interact through a communication network. The relationship between the client and the server results from the computer programs running on the respective computers and having a client-server relationship with each other. In some implementations, a server transmits data (eg, an HTML page) to a client device (eg, to display data to and receive user input from a user interacting with the client device). The data generated at the client device (such as a result of user interaction) can be received from the client device at the server.

A system of one or more computers can be configured to perform specific operations or actions by installing software, firmware, hardware, or a combination thereof on the system, which causes or causes the system to perform actions in operation . One or more computer programs can be configured to perform specific operations by including instructions that cause the device to perform actions when executed by the data processing device or action.

Although the present invention contains many specific implementation details, these should not be construed as limitations on the scope of any invention or what can be claimed, but should be interpreted as descriptions of features specific to specific embodiments of specific inventions. Certain features described in the context of separate implementations of the invention may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation can also be implemented in multiple implementations individually or in any suitable sub-combination. Furthermore, although features may have been described above as functioning in certain combinations and even originally claimed, in some cases, one or more features from a claimed combination may be removed from the combination and the The claim combination can be directed to a sub-combination or a variation of a sub-combination.

Similarly, although operations can be described in a specific order in the present invention or depicted in a specific order in the drawings, this should not be understood as a need to perform these operations in the specific order shown or in sequential order , Or perform all the operations shown to achieve the desired result. In certain situations, multitasking and parallel processing may be advantageous.

Furthermore, the separation of the various system components in the implementations described above should not be understood as requiring this separation in all implementations, and it should be understood that the program components and systems described can generally be integrated together in a single In software products or packaged into multiple software products.

Therefore, specific embodiments of the subject matter have been described herein. Other implementations are within the scope of the following patent applications. In some cases, the actions stated in the scope of the patent application can be performed in a different order and still achieve the desired result. In addition, the procedures depicted in the drawings do not necessarily require the particular order shown, or sequential order, to achieve the desired result. In certain embodiments, multitasking and parallel processing may be advantageous.

the term

The phrases and terms used herein are for description and should not be regarded as limiting.

As used in this specification and the scope of patent applications, the terms "approximately" and the phrase "nearly "Likely equal" and other similar phrases (such as "X has a value approximately equal to Y" or "X is approximately equal to Y") should be understood to mean that one value (X) is predetermined in one of the other values (Y) Within range. Unless otherwise indicated, the predetermined range may be ±20%, ±10%, ±5%, ±3%, ±1%, ±0.1% or less than ±0.1%.

As used in this specification and the scope of patent applications, unless clearly indicated to the contrary, the indefinite article "a" should be understood to mean "at least one". As used in this specification and the scope of patent applications, the phrase "and/or" should be understood to mean "any or both" of the combined elements, ie, in some cases coexist and in other cases Components that exist alone. Multiple components listed using "and/or" should be interpreted in the same way, that is, "one or more" of the combined components. There may be elements other than those explicitly identified by the "and/or" clause, regardless of whether these elements are related or unrelated to the clearly identified elements. Therefore, as a non-limiting example, when used with open language (such as "including"), the content of "A and/or B" in one embodiment may refer to A only (including the exception of B as appropriate) Other components), in another embodiment it may only refer to B (including elements other than A as appropriate), in yet another embodiment may refer to both A and B (including other elements as appropriate), and many more.

As used in this specification and the scope of patent applications, "or" should be understood to have the same meaning as "and/or" as defined above. For example, when separating items in a list, "or" or "and/or" should be interpreted to be inclusive, that is, not only include several elements or at least one of the elements of a list, but also include Elements or more than one of the elements of a list, and optionally include additional unlisted items. Only the terms clearly indicating the opposite (such as "the only one of..." or "the exactly one of...") or the term "composed of" used in the scope of the patent application will mean including Several components or a list of components are exactly one component. Generally speaking, when exclusive terms are added to the front (such as "any one", "one of...", "the only one of..." or "the exactly one of..."), The term "or" used should only be interpreted as indicating that no substitutes are included (ie, "one or the other but not both By"). "Essentially composed of" used in the scope of patent application shall have its usual meaning as used in the field of patent law.

As used in this specification and in the scope of patent application, the phrase "at least one" with respect to one or more elements of a list should be understood to mean any one or more of the elements selected from the elements of the list At least one element of, but does not necessarily include at least one of each element explicitly listed in the elements of the list and does not exclude any combination of elements in the elements of the list. This definition also allows: There may be elements other than those clearly identified in the elements of the list referred to by the phrase "at least one", regardless of whether these elements are related or unrelated to the clearly identified elements. Therefore, as a non-limiting example, "at least one of A and B" (or equivalently, "at least one of A or B", or equivalently, "at least one of A and/or B") : In one embodiment, it may refer to at least one (optionally including more than one) A, but there is no B (and optionally including elements other than B); in another embodiment, it may refer to at least one ( (Contains more than one as appropriate) B, but does not exist A (and optionally includes elements other than A); In yet another embodiment, it can refer to at least one (optionally includes more than one) A and at least one (visual The case includes more than one) B (and optionally other elements); etc.

The use of variations of "contains", "includes", "has", "contains", "involves" and the like means covering the items listed below and additional items.

The ordinal terms used to modify a claimed element (such as "first", "second", "third", etc.) in the scope of patent application do not imply any priority order, priority order, or a claimed element precedes another. A claim to the order of components or the chronological order in which the actions of a method are performed. The ordinal term is only used as a mark to distinguish one claimed element with a certain name from another element with the same name (but using ordinal terms) to distinguish the claimed element.

Equivalent

Therefore, although several aspects of at least one embodiment of the present invention have been described, it should be understood that those skilled in the art will readily think of various changes, modifications, and improvements. Such changes, Modifications and improvements are intended to be part of the invention, and are intended to fall within the spirit and scope of the invention. Accordingly, the [embodiment] and drawings are for illustration only.

100‧‧‧ same frequency out of phase system

101‧‧‧Input data terminal

105‧‧‧Output data terminal

110a‧‧‧Transmission processing unit

110b‧‧‧Reception processing unit

120a‧‧‧clock signal

120b‧‧‧clock signal

130‧‧‧input latch

132‧‧‧Input data terminal

134‧‧‧Output data terminal

136‧‧‧Enable terminal

138‧‧‧Enable terminal

140a‧‧‧processing circuit

140b‧‧‧processing circuit

150‧‧‧Output latch

152‧‧‧Input data terminal

154‧‧‧Output data terminal

156‧‧‧Enable terminal

Claims (35)

An integrated circuit includes: a plurality of processing units, which are operable to synchronize their processing with a plurality of respective out-of-phase clock signals of the same frequency. The equivalent-frequency out-of-phase clock signal includes a first clock signal and a first Two clock signals, the first clock signal and the second clock signal have a same frequency and different phases, and the processing units include a first process operable to synchronize processing with the first clock signal Unit and a second processing unit operable to synchronize processing with the second clock signal, wherein the second processing unit includes a latch circuit coupled to receive data from the first processing unit, and wherein the lock The memory circuit is configured to operate based on the states of the first clock signal and the second clock signal, and wherein the second processing unit further includes a clock buffer, the clock buffer is operable to A processing unit receives the first clock signal and generates the second clock signal by shifting a phase of the first clock signal by less than an amount of a clock cycle of the first clock signal. The integrated circuit of claim 1, wherein the first processing unit includes a latch circuit coupled to provide the data to the latch circuit of the second processing unit. The integrated circuit of claim 2, wherein the latch circuit of the second processing unit is configured to operate in a transparent state based at least in part on the latch circuit of the first processing unit being in a holding state . The integrated circuit of claim 2, wherein the latch circuit of the second processing unit is configured to be at least partially based on that the latch circuit of the first processing unit is in a holding state and the second clock signal indicates A specific logic value operates in a transparent state. The integrated circuit according to claim 4, wherein the latch circuit of the second processing unit is assembled The state is operated in a holding state based at least in part on the latch circuit of the first processing unit being in a transparent state and/or the second clock signal representing a logic value different from the specific logic value. The integrated circuit of claim 2, wherein the latch circuit of the first processing unit is configured to operate in a holding state based on the first clock signal representing a specific logic value, and wherein the second processing The latch circuit of the cell is configured to operate in a transparent state based at least in part on the first clock signal representing the specific logic value. The integrated circuit of claim 2, wherein the latch circuit of the first processing unit is configured to operate in a hold state based on the first clock signal representing a first logic value, and wherein the second The latch circuit of the processing unit is configured to operate in a transparent state based at least in part on the first clock signal representing the first logic value and the second clock signal representing a second logic value. The integrated circuit of claim 7, wherein the latch circuit of the second processing unit is configured to indicate a logic value different from the first logic value and/or the first logic value based at least in part on the first clock signal The two clock signal represents a logic value different from the second logic value and operates in a holding state. An integrated circuit according to claim 1, wherein the first clock signal is a first single-ended clock signal, and the second clock signal is a second single-ended clock signal. The integrated circuit of claim 9, wherein the latch circuit includes a gated latch having an input data terminal, an enable terminal, and one or more output terminals, wherein the input data terminal is configured to The first processing unit receives data, and wherein the enable terminal is configured to receive a logical AND of an inverse of one of the first single-ended clock signal and the second single-ended clock signal. The integrated circuit according to claim 1, wherein the first clock signal includes a first differential signal of a first differential signal pair, and wherein the second clock signal includes A second differential signal pair of a second differential signal. The integrated circuit according to claim 11, wherein the latch circuit includes an input circuit and a buffer circuit, and wherein the input circuit includes: a plurality of first field effect transistors (FETs) of a first type, etc. A first FET, a second FET, and a third FET having a diffusion terminal coupled in series between a first power supply rail and an input node of the buffer circuit; and a plurality of second field effect power of a second type A crystal (FET), which includes a fourth FET, a fifth FET, and a sixth FET having a diffusion terminal coupled in series between a second power supply rail and the input node of the buffer circuit, wherein the first FET And the gate of the fourth FET is coupled to receive the data from the first processing circuit, wherein the gates of the second FET and the fifth FET are coupled to receive the first signal of the first differential signal pair, respectively And a second signal, and wherein the gates of the third FET and the sixth FET are coupled to receive the first signal and the second signal of the second differential signal pair, respectively. The integrated circuit of claim 11, wherein the clock buffer is a differential clock buffer, the differential clock buffer has the first differential coupled to receive the first differential clock signal An input terminal of a signal pair, wherein generating the second clock signal includes providing the second differential signal pair of the second differential clock signal, and wherein the phase shift of the first clock signal is less than the The amount of one clock period of the first clock signal includes setting the response in response to a transition of a first signal of the first differential signal pair and a complementary transition of a second signal of the first differential signal pair A logical value of the second differential signal pair matches a logical value of the first differential signal pair. An integrated circuit comprising: a plurality of processing units which are operable to synchronize their processing with a plurality of respective out-of-phase clock signals of the same frequency, the equivalent-frequency out-of-phase clock signal including a first clock Signal and a second clock signal, the first clock signal and the second clock signal have a same frequency and different phases, and the processing units include an operable device to synchronize processing with the first clock signal A first processing unit and a second processing unit operable to synchronize processing with the second clock signal, wherein the second processing unit includes a latch circuit coupled to receive data from the first processing unit, And wherein the latch circuit is configured to operate based on the states of the first clock signal and the second clock signal, and wherein the latch circuit includes an input data terminal, an enable terminal, and one or more A gated latch of one of the output terminals, wherein the input data terminal is configured to receive data from the first processing unit, and wherein the enable terminal is configured to receive the first single-ended clock signal and the second A logical AND of the inverse of one of the single-ended clock signals. An integrated circuit includes: a plurality of processing units, which are operable to synchronize their processing with a plurality of respective out-of-phase clock signals of the same frequency. The equivalent-frequency out-of-phase clock signal includes a first clock signal and a first Two clock signals, the first clock signal and the second clock signal have a same frequency and different phases, and the processing units include a first process operable to synchronize processing with the first clock signal Unit and a second processing unit operable to synchronize processing with the second clock signal, wherein the second processing unit includes a latch circuit coupled to receive data from the first processing unit, and wherein the lock The memory circuit is configured to operate based on the states of the first clock signal and the second clock signal, where the first clock signal includes a first differential clock signal of a first differential signal pair , And wherein the second clock signal includes a second differential clock signal of a second differential signal pair, wherein the latch circuit includes an input circuit and a buffer circuit, and wherein the input circuit includes: A plurality of first field effect transistors (FETs) of a first type, etc., including a first FET having a diffusion terminal coupled in series between a first power supply rail and an input node of the buffer circuit, a first Two FETs and a third FET; and a plurality of second field effect transistors (FETs) of the second type, which include a series coupling between a second power supply rail and the input node of the buffer circuit The fourth FET, the fifth FET, and the sixth FET of the diffusion terminal, wherein the gates of the first FET and the fourth FET are coupled to receive the data from the first processing circuit, wherein the second FET and the fifth FET The gates of the FETs are coupled to receive the first and second signals of the first differential signal pair, respectively, and wherein the gates of the third FET and the sixth FET are coupled to receive the second differential signals, respectively The first signal and the second signal. An integrated circuit includes: a plurality of processing units, which are operable to synchronize their processing with a plurality of respective out-of-phase clock signals of the same frequency. The equivalent-frequency out-of-phase clock signal includes a first clock signal and a first Two clock signals, the first clock signal and the second clock signal have a same frequency and different phases, and the processing units include a first process operable to synchronize processing with the first clock signal Unit and a second processing unit operable to synchronize processing with the second clock signal, wherein the second processing unit includes a latch circuit coupled to receive data from the first processing unit, and wherein the lock The memory circuit is configured to operate based on the states of the first clock signal and the second clock signal, where the first clock signal includes a first differential clock signal of a first differential signal pair , And wherein the second clock signal includes a second differential clock signal of a second differential signal pair; and a differential clock buffer, the differential clock buffer is coupled to receive the The input terminal of the first differential signal pair of the first differential clock signal, wherein the difference The dynamic clock buffer is operable to provide the second differential signal pair of the second differential clock signal, and wherein the differential clock buffer is operable to respond to a first difference of the first differential signal pair A transition of a signal and a complementary transition of a second signal of the first differential signal pair set a logical value of the second differential signal pair to match a logical value of the first differential signal pair. A latch circuit includes: a buffer circuit having an input node and an output node; an input circuit having: an output node that is coupled to the input node of the buffer circuit; and a data node Coupled to receive an input data signal; and a first enabled node and a second enabled node, which are coupled to receive the respective first in-frequency and out-of-phase clock signals and second in-frequency of the first processing unit and the second processing unit, respectively Out-of-phase clock signal, the first clock signal and the second clock signal have a same frequency and different phases, wherein the input circuit is operable to be based on the first in-frequency out-of-phase clock signal and the second in-frequency signal The state of the out-of-phase clock signal enables the latch circuit, and the second processing unit further includes a clock buffer, the clock buffer is operable to receive the first clock signal from the first processing unit and borrow The second clock signal is generated by phase shifting one of the first clock signals by less than an amount of one clock cycle of the first clock signal. The latch circuit of claim 17, wherein the data node is coupled to receive the input data signal from an output latch of the first processing unit. The latch circuit of claim 18, wherein the input circuit is configured to enable the latch circuit based at least in part on the output latch being in a disabled state. The latch circuit of claim 18, wherein the input circuit is configured to enable the latch circuit based at least in part on the output latch being in a disabled state and the second clock signal representing a specific logic value. The latch circuit of claim 20, wherein the input circuit is configured to be based at least in part on the output latch being in an enabled state and/or the second clock signal representing a logical value different from the specific logical value The latch circuit is disabled. The latch circuit of claim 18, wherein the output latch is configured to operate in a disabled state based on the first clock signal representing a specific logic value, and wherein the input circuit is configured to at least The latch circuit is enabled based in part on the first clock signal representing the specific logic value. The latch circuit of claim 17, wherein the first clock signal includes a first differential clock signal of a first differential signal pair, and wherein the second clock signal includes a second differential signal One of the signal pairs is the second differential clock signal. The latch circuit of claim 23, wherein the input circuit includes: a plurality of first field effect transistors (FETs) of a first type, etc., which include a series connection with a first power supply rail and the buffer circuit The first FET, the second FET, and the third FET of the diffusion terminal between the input nodes; and a plurality of second field effect transistors (FETs) of the second type, which include having a series coupling to a first The fourth FET, the fifth FET and the sixth FET of the diffusion terminal between the two power supply rails and the input node of the buffer circuit, wherein the gates of the first FET and the fourth FET are coupled to receive the input data Signal, wherein the gates of the second FET and the fifth FET are coupled to receive the first signal and the second signal of the first differential signal pair, respectively, and wherein the gates of the third FET and the sixth FET It is coupled to receive the first signal and the second signal of the second differential signal pair, respectively. A latch circuit includes: a buffer circuit having an input node and an output node; an input circuit having: an output node which is coupled to the buffer circuit The input node; a data node, which is coupled to receive an input data signal; and a first enablement node and a second enablement node, which are coupled to receive the respective first coherence of the first processing unit and the second processing unit, respectively Frequency out-of-phase clock signal and second in-frequency out-of-phase clock signal, the first clock signal and the second clock signal have a same frequency and different phases, wherein the input circuit is operable to be based on the first in-frequency The state of the out-of-phase clock signal and the second in-frequency out-of-phase clock signal enable the latch circuit, and the first clock signal includes a first differential clock signal of a first differential signal pair, And wherein the second clock signal includes a second differential signal pair of a second differential signal pair, wherein the input circuit includes: a plurality of first field effect transistors (FETs) of a first type, They include a first FET, a second FET, and a third FET having a diffusion terminal coupled in series between a first power supply rail and the input node of the buffer circuit; and a plurality of second types of a second type A field effect transistor (FET), etc., includes a fourth FET, a fifth FET, and a sixth FET having a diffusion terminal coupled in series between a second power supply rail and the input node of the buffer circuit, wherein the The gates of the first FET and the fourth FET are coupled to receive the input data signal, wherein the gates of the second FET and the fifth FET are coupled to receive the first signal of the first differential signal pair and The second signal, and wherein the gates of the third FET and the sixth FET are coupled to receive the first signal and the second signal of the second differential signal pair, respectively. A communication method for a co-frequency out-of-phase time control system includes: synchronizing the processing of the first processing unit and the second processing unit to the first in-frequency out-of-phase clock signal and the second in-frequency out-of-phase clock signal, respectively, the First same frequency out of phase clock The signal and the second in-frequency out-of-phase clock signal have the same frequency and different phases, and the data and the first clock signal are sent from the first processing unit to the second processing unit, by the first time A phase shift of a pulse signal is less than an amount of a clock cycle of the first clock signal to generate the second clock signal in the second processing unit, and based at least in part on the first in-frequency out-of-phase clock The signal and the state of the second in-phase out-of-phase clock signal enable or disable the second processing unit to receive the data. The method of claim 26, wherein enabling or disabling receiving the data by the second processing unit based on the states of the first in-frequency out-of-phase clock signal and the second in-frequency out-of-phase clock signal includes: at least partially based on the One of the output latches of the first processing unit is disabled to enable the second processing unit to receive the data. The method of claim 26, wherein enabling or disabling receiving the data by the second processing unit based on the states of the first in-frequency out-of-phase clock signal and the second in-frequency out-of-phase clock signal includes: at least partially based on the One of the output latches of the first processing unit is disabled and the second clock signal represents a specific logic value to enable the second processing unit to receive the data. The method of claim 26, wherein the first in-frequency out-of-phase clock signal includes a first differential signal pair of a first differential signal pair, and wherein the second in-frequency out-of-phase clock signal includes a One of the second differential signal pair is the second differential clock signal. The method of claim 29, wherein generating the second differential clock signal includes: generating the second differential signal pair of the second differential clock signal, which includes responding to one of the first differential signal pair A transition of the first signal and a complementary transition of a second signal of the first differential signal pair set a logical value of the second differential signal pair to match a logical value of the first differential signal pair. A communication method for a co-frequency out-of-phase time control system includes: synchronizing the processing of the first processing unit and the second processing unit to the first co-frequency out-of-phase clock signal and the second co-frequency out-of-phase clock signal, The first in-frequency out-of-phase clock signal and the second in-frequency out-of-phase clock signal have the same frequency and different phases; send data from the first processing unit to the second processing unit; based at least in part on the first in-phase The state of the frequency out-of-phase clock signal and the second in-frequency out-of-phase clock signal is enabled or disabled by the second processing unit to receive the data, wherein the first in-frequency out-of-phase clock signal includes a first differential signal A pair of first differential clock signals, and wherein the second in-frequency out-of-phase clock signal includes a second differential signal pair of a second differential clock signal; and generating the second differential clock The second differential signal pair of the signal includes setting the first in response to a transition of a first signal of the first differential signal pair and a complementary transition of a second signal of the first differential signal pair The logical value of one of the two differential signal pairs matches the logical value of the first differential signal pair. A computer-implemented electronic design automation method includes: a computer synthesizing a schematic diagram of a part of a co-frequency out-of-phase system. The co-frequency out-of-phase system includes operations operable to synchronize respective processing with a plurality of respective co-frequency out-of-phase clock signals A plurality of processing units, the equivalent frequency out-of-phase clock signal includes a first clock signal and a second clock signal, the first clock signal and the second clock signal have a same frequency and different phases respectively, the The processing unit includes a first processing unit operable to synchronize processing with the first clock signal and a second processing unit operable to synchronize processing with the second clock signal. Coupled to receive data from the first processing unit, wherein synthesizing the circuit schematic includes generating a schematic of a latch circuit of the second processing unit, the latch circuit A schematic diagram of a clock buffer coupled to receive data from the first processing unit and configured to operate based on the state of the first clock signal and the second clock signal, and to generate a clock buffer of the second processing unit , The clock buffer is operable to receive the first clock signal from the first processing unit and by shifting a phase of the first clock signal less than one clock period of the first clock signal An amount to generate the second clock signal. The method of claim 32, further comprising: simulating the operation of the circuit diagram by a computer, which includes simulating the operation of the latch circuit. The method of claim 32, further comprising: generating a physical layout of the circuit diagram by a computer. The method of claim 34, further comprising: generating, by a computer, a plurality of mask patterns for manufacturing an integrated circuit including the latch circuit.

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