TWI686901B - Semiconductor device, layout system, and standard cell library - Google Patents

Abstract

A semiconductor device includes a substrate, a first transistor gated by an inverted voltage level of a first input signal to pull up a first node, a second transistor gated by a voltage level of a second input signal to pull down the first node, a third transistor gated by an inverted voltage level of the second input signal to pull up the first node, a fourth transistor gated by a voltage level of the first input signal to pull down the first node, a fifth transistor gated by the voltage level of the second input signal to pull down a second node, a sixth transistor gated by the inverted voltage level of the first input signal to pull up the second node, a seventh transistor gated by the voltage level of the first input signal to pull down the second node, and an eighth transistor gated by the inverted voltage level of the second input signal to pull up the second node.

Description

Semiconductor device, layout system and standard cell library

This application claims Korean Patent Application No. 10-2015-0034357 filed with the Korean Intellectual Property Office on March 12, 2015, and Korean Patent Application filed with the Korean Intellectual Property Office on April 24, 2015 The priority of the case No. 10-2015-0057968, the disclosure content of the Korean patent application is incorporated into this case for reference.

The concept of the present invention relates to a semiconductor device, a layout system for laying out components of a semiconductor device, and a standard cell library for designing a semiconductor device, and a method of manufacturing a semiconductor device using the standard cell library .

It is necessary to minimize the area of the unit of the integrated circuit of the semiconductor device to increase the integrated density of the device. In order to scale down the area of the cell, it is necessary to optimize the position of the transistor, the signal routing path, and the shape and position of the interconnect (ie, the layout of the elements that make up the cell).

According to an aspect of the inventive concept, there is provided a semiconductor device The conductor device includes: a substrate; a first transistor, which is gated by a reverse voltage level of the first input signal to pull up the first node; a second transistor, which is gated by a voltage level of the second input signal to pull down The first node; the third transistor, which is gate-controlled by the inverse voltage of the second input signal to pull up the first node; the fourth transistor, which is gate-controlled by the voltage of the first input signal The first node is pulled down; the fifth transistor is controlled by the voltage level of the second input signal to pull down the second node; the sixth transistor is controlled by the inverse of the first input signal Phase voltage gate control pulls up the second node; a seventh transistor, which pulls down the second node from the voltage input of the first input signal; and an eighth transistor, which is controlled by the The inverted voltage of the second input signal is gated to pull up the second node; and the first metal layer and the second metal layer are disposed on the substrate at different levels. The first metal layer and the second metal layer each include multiple conductive connections. The input terminal of the first transistor and the input terminal of the fourth transistor are electrically connected by the connection of the first metal layer, and the input terminal of the second transistor and the third The input terminal of the transistor is electrically connected by the connection of the second metal layer. In addition, the second transistor and the fifth transistor share a first gate electrode disposed on the substrate, and the fourth transistor and the seventh transistor share a first gate electrode disposed on the substrate The second gate.

According to another aspect of the inventive concept, there is provided a semiconductor device including: a substrate having a first region and a second region of the substrate, the first region being disposed across a first On one side of the axis extending in one direction, and the second region is disposed on the other side of the axis; the first gate, Extending across the first region and the second region in a second direction perpendicular to the first direction, and disposed in a first horizontal plane relative to the substrate in the semiconductor device; a second gate, Spaced apart from the first gate in the first direction, extending across the first region and the second region in the second direction, and disposed in the semiconductor device at the first A horizontal plane; a first connection electrically connecting the input terminal of the first transistor composed of the first gate and the input terminal of the fourth transistor composed of the second gate in the first region , And is disposed at a second horizontal plane higher than the first horizontal plane relative to the substrate; a second connection, electrically connecting the input of the second transistor composed of the first gate electrode in the first region A terminal and an input terminal of a third transistor composed of the second gate, and is disposed at a third level higher than the first level but lower than the second level relative to the substrate; third A connection is placed at the second level in the semiconductor device; and a fourth connection is placed at the third level in the semiconductor device. In addition, the input terminal of the second transistor and the input terminal of the fifth transistor are each constituted by a part of the first gate, and the input terminal of the fourth transistor and the seventh transistor The input terminals are composed of a part of the second gate.

According to yet another aspect of the inventive concept, there is provided a semiconductor device including: a substrate; a power supply rail extending longitudinally on the substrate in a first direction so that the substrate has a location on the power supply A first region on one side of the rail and a second region disposed on the other side of the power rail; a first gate extending across the first in a second direction perpendicular to the first direction Region and Office The second region, and has a first overlapping portion that overlaps the power rail; and a second gate electrode, which is spaced apart from the first gate electrode in the first direction at the second It extends across the first region and the second region in the direction, and has a second overlapping portion that overlaps with the power rail. The first transistor of the semiconductor device is disposed at a position where the first gate electrode extends in the first region, and the fourth transistor of the semiconductor device is disposed at the second gate electrode at the first At a position extending in the region, the seventh transistor of the semiconductor device is disposed at a position where the second gate electrode extends at the second region, and a sixth transistor of the semiconductor device is disposed at the first The position where the gate extends in the second region. The first transistor, the fourth transistor, the seventh transistor and the sixth transistor are gated by the same first input signal. In addition, the second transistor of the semiconductor device is disposed at a position where the first gate electrode extends in the first region, and the third transistor of the semiconductor device is disposed at the second gate electrode at the At a position extending in the first region, a fifth transistor of the semiconductor device is disposed at a position where the first gate electrode extends at the second region, and an eighth transistor of the semiconductor device is disposed at the The position where the second gate extends in the second area. The second transistor, the third transistor, the fifth transistor and the eighth transistor are gated by the same second input signal. The semiconductor device also includes a first metal layer including a connection between the input terminal of the first transistor and the input terminal of the fourth transistor in the first region And a connection between the input terminal of the fifth transistor and the input terminal of the eighth transistor in the second region; and a second metal layer, the second metal layer included in the The first area is electrically connected to the Connection between the input terminal of the second transistor and the input terminal of the third transistor, and electrically connecting the input terminal of the sixth transistor and the input terminal of the seventh transistor in the second region Connection. The first metal layer and the second metal layer are arranged at different levels in the semiconductor device, and the input terminal of the second transistor and the input terminal of the fifth transistor are Are electrically connected by the first overlapping portion, and the input terminal of the fourth transistor and the input terminal of the seventh transistor are electrically connected by the second overlapping portion .

According to yet another aspect of the inventive concept, a semiconductor device is provided, the semiconductor device including: a substrate; a power rail extending longitudinally on the substrate in a first direction; a first input terminal, a second input terminal, The third input terminal and the fourth input terminal are sequentially arranged along the first row extending in the second direction perpendicular to the first direction; the fifth input terminal, the sixth input terminal, the seventh input terminal, and the first Eight input terminals, spaced apart from the first row in the first direction and sequentially arranged along a second row extending in the second direction; a first connection electrically connecting the first input terminal Connected to the sixth input terminal; the second connection crosses the first connection when viewed in a plan view, and is electrically connected to the second input terminal and the fifth input terminal; the third connection is electrically Connect the third input terminal and the eighth input terminal; the fourth connection crosses the third connection when viewed in a plan view, and electrically connects the fourth input terminal and the seventh input terminal ; The first interconnection, when viewed in plan view, crosses the power rail and electrically connects the second input terminal and the third input terminal; and the second interconnection, when viewed in plan view Crossing the power rail and electrically connecting the sixth input terminal with The seventh input terminal. The first interconnection is a part of the first gate constituting the second input terminal and the third input terminal, and the second interconnection is the sixth input terminal and the seventh input Part of the second gate of the terminal.

According to yet another aspect of the inventive concept, there is provided a semiconductor device including: a substrate; a plurality of gate lines, spaced apart from each other in a first direction and each in a second perpendicular to the first direction Extending longitudinally above the substrate in a direction; a first metal layer disposed on the substrate and including a first discrete conductive connection; and a second metal layer disposed on the substrate different from the first A metal layer is at the horizontal level and includes a second discrete conductive connection. The semiconductor device has a plurality of cells arranged side by side in the second direction. Each of the cells is composed of: an active area of the substrate spaced apart from each other in the second direction; a first gate line of the gate lines extending longitudinally above the active area and A second gate line; a first pair of transistors located at corresponding positions of the first gate line extending above the active area, wherein the first gate line is the first pair in the cell Transistors provide input terminals; a second pair of transistors located at corresponding positions of the second gate line extending above the active area, wherein the second gate line is the second pair in the cell The transistor provides an input terminal; one of the connections of the first metal layer; and one of the connections of the second metal layer. In each of the cells, the connection of the first metal layer overlaps the first gate line and the second gate line, and the one of the first pair of transistors The input terminal is electrically connected to the input terminal of one of the second pair of transistors. In addition, in each of the cells, the connection of the second metal layer Stack the first gate line and the second gate line, and electrically connect the input terminal of the other of the first pair of transistors to the other of the second pair of transistors One of the input terminals.

According to yet another aspect of the inventive concept, a layout system for a semiconductor device is provided. The layout system for a semiconductor device includes: a processor; a memory that stores components that can be laid out in one or more standard cell designs; and a layout module Group, using the processor based on one or more of the standard cell designs and laying out semiconductor devices according to defined requirements, wherein the laying out module aligns the first power rail along the first direction on the substrate Layout the layout of the second power rails along the first direction and separated from the first power rails by a first gap in a second direction perpendicular to the first direction. A third power rail that extends in the first direction and is separated from the second power rail by a second gap in the second direction is laid out, where the first power rail and the second power rail Defining a first active region and a second active region between the bars so that the first active region is adjacent to the first power rail and the second active region is adjacent to the second power rail, A third active area and a fourth active area are defined between the second power rail and the third power rail so that the third active area is adjacent to the second power rail and the fourth The active area is adjacent to the third power rail, and the first gate and the first gate that cross the first active area to the fourth active area and extend along the second direction A second gate that is spaced apart and extends in the second direction is laid out, and a first transistor and a second transistor that share the first gate are defined on the first active region to the fourth active region Transistor, fifth transistor, and sixth transistor to make the first transistor and the second transistor A transistor is arranged between the first power rail and the second power rail and the fifth transistor and the sixth transistor are disposed on the second power rail and the third Between the power rails, a third transistor, a fourth transistor, a seventh transistor, and an eighth transistor sharing the second gate are defined on the first active area to the fourth active area So that the third transistor and the fourth transistor are disposed between the first power rail and the second power rail and the seventh transistor and the eighth transistor are disposed Between the second power rail and the third power rail, an input composed of a first metal layer disposed at a first height relative to the substrate for connecting the first transistor The connection of the terminal to the input terminal of the fourth transistor and the connection for connecting the input terminal of the fifth transistor and the input terminal of the eighth transistor are laid out, and are arranged relative to the substrate A second metal layer at a second height smaller than the first height for connecting the input terminal of the second transistor and the input terminal of the third transistor and for connecting the The connection between the input terminal of the sixth transistor and the input terminal of the seventh transistor is laid out.

According to yet another aspect of the inventive concept, a non-transitory computer readable medium (non-transitory computer readable medium) is provided, where at least one standard unit in the layout of the non-transitory computer readable medium storage element is formed Standard cell library, wherein: the power rail extends in the first direction on the substrate; the first area of the substrate is disposed on one side of the power rail, and the second area of the substrate is disposed on the power supply The other side of the rail; the first gate extends across the first region and the second region in a second direction perpendicular to the first direction, and A third vertical direction in which each of the first direction and the second direction is perpendicular is disposed at a first horizontal plane relative to the substrate; a second gate is spaced from the first gate along the second The direction extends across the first area and the second area, and is disposed on the first horizontal plane relative to the substrate; the first connection is connected to the first gate disposed on the first gate in the first area An input terminal of a transistor and an input terminal of a fourth transistor arranged on the second gate, and arranged at a second level higher than the first level relative to the substrate; the second connection is at the The input terminal of the second transistor arranged on the first gate and the input terminal of the third transistor arranged on the second gate are connected in the first region, and are arranged on the substrate A third level which is higher than the first level but lower than the second level; a third connection connects the input terminal of the fifth transistor arranged on the first gate in the second region and the An input terminal of an eighth transistor on the second gate, and disposed at the second horizontal plane; and a fourth connection is connected to an input terminal of a sixth transistor disposed on the first gate in the second region And an input terminal of a seventh transistor arranged on the second gate, and arranged on the third horizontal plane; and wherein the input terminal of the second transistor and the fifth transistor The input terminal is connected by a part of the first gate, and the input terminal of the fourth transistor and the input terminal of the seventh transistor are part of the second gate connection.

1: Layout system

10: processor

20: Memory

30: memory

40: Layout module

50: input device

60: output device

70: bus

102: the first power rail

104: second power rail

106: third power rail

108: Fourth power rail

112: The first active zone

114: Second active zone

116: Third Active Zone

118: Fourth Active Zone

122: first gate

123, 123a, 123b: the first overlap

124: second gate

125, 125a, 125b: second overlap

127: The first overlap

129: Second Overlap

132: First connection

134: Second connection

136: Third connection

138: Fourth connection

1200: Tablet PC

1300: laptop

1400: smart phone

A: The first input signal

B: Second input signal

C1, C2: input signal

D1, D2: input signal

I: first area

II: Second area

III: third area

L-L, M-M: line

L1: the first level

L2: second level

L3: third level

MN1: Transistor

MN2: second transistor

MN3: Transistor

MN4: fourth transistor

MN5: Transistor

MN6: Fifth transistor

MN7: Transistor

MN8: seventh transistor

MN10: Tenth transistor

MN12: The twelfth transistor

MP1: Transistor

MP2: the first transistor

MP3: Transistor

MP4: third transistor

MP5: Transistor

MP6: sixth transistor

MP7: Transistor

MP8: Eighth transistor

MP10: ninth transistor

MP12: Eleventh transistor

VDD: power supply voltage

VSS: ground voltage

Y: the first node

Y’: Second node

The above and other aspects and features of the inventive concept will become more apparent by reading the following detailed description of examples of the inventive concept with reference to the drawings, in In the drawings: FIG. 1 is a block diagram of a layout system according to the inventive concept.

2 is a circuit diagram of an example of a semiconductor device according to the inventive concept.

3A is a layout diagram of an example of a semiconductor device according to the inventive concept.

3B and 3C illustrate other types of semiconductor devices having similar layouts as those shown in FIG. 3A.

4A and 4B are cross-sectional views of the type of semiconductor device having the layout shown in FIG. 3A taken along line L-L shown in FIG. 3A, respectively.

5 is a layout diagram of another example of a semiconductor device according to the inventive concept.

6 is a layout diagram of another example of a semiconductor device according to the inventive concept.

7A and 7B are cross-sectional views of the type of semiconductor device having the layout shown in FIG. 6 taken along the line M-M shown in FIG. 6, respectively.

8 is a layout diagram of another example of a semiconductor device according to the inventive concept.

9 is a layout diagram of another example of a semiconductor device according to the inventive concept.

10 is a layout diagram of another example of a semiconductor device according to the inventive concept.

11, 12, and 13 are respectively front views of examples of electronic devices to which semiconductor devices can be applied according to the inventive concept.

Examples will be explained in detail with reference to the drawings. However, the inventive concept can be exemplified in various different forms and should not be considered limited to the examples shown. To be precise, these examples are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the present invention to those skilled in the art. Therefore, for some of the examples of the inventive concept In these examples, the known processes, components, and technologies will not be described again. Unless otherwise specified, the same reference numbers indicate the same elements throughout the drawings and written descriptions, and therefore will not be described again. In the drawings, the size and relative size of layers and regions can be exaggerated for clarity.

It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and/or sections, these elements, components, regions, The layer and/or section should not be limited by these terms. These terms are only used to distinguish individual elements, components, regions, layers or sections. Therefore, without departing from the teachings of the inventive concept, the first element, component, region, layer, or section discussed below may be referred to as the second element, component, region, layer, or section.

In this article, for ease of explanation, the terms of spatial relativity can be used, such as "beneath", "below", "lower", "in. ..Under (under), (above), (upper), etc. to illustrate the relationship between one element or feature shown in the figure and another (other) element or feature . It should be understood that these spatially relative terms are intended to cover different orientations of the device in use or operation in addition to the orientations shown in the figures. For example, if the device described in the figures is turned over, elements described as "below" or "beneath" or "below" other elements or features would then be oriented as on". Therefore, the exemplary terms "below" and "below" can cover both the orientations above and below. The device may also have other orientations (eg, rotated 90 degrees or other orientations), and the spatially relative descriptors used herein are interpreted accordingly. In addition, it should also be understood that when a layer is referred to as being "between" two layers, the The layer may be the only layer between the two layers, or one or more intermediate layers may also be present.

The terminology used herein is only for illustrating specific examples, and is not intended to limit the inventive concept. Unless the context clearly dictates otherwise, the singular forms "a" and "the" as used herein are intended to include the plural forms as well. It should be further understood that when the terms "comprises" and/or "comprising" are used in this specification, they are used to indicate the existence of the described features, integers, steps, operations, elements and/or components, However, the existence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof is not excluded. The term "and/or" as used herein includes any and all combinations of one or more of the listed items. In addition, the term "exemplary" is intended to refer to an example or description.

It should be understood that when an element or layer is referred to as being “on”, “connected to”, “coupled to” or “adjacent” to another element or layer, the element or layer can be directly located on the The other element or layer may be directly connected to, coupled to, or adjacent to the other element or layer, or an intermediate element or layer may be present. In contrast, when an element is referred to as being “directly on”, “directly connected to”, “directly coupled to” or “immediately” to another element or layer, there are no intervening elements or layers present.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those with ordinary knowledge in the technology to which the inventive concept belongs. It should be further understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and/or this specification, and unless expressly so defined in this text, should not Interpret it as having an idealized or overly formal meaning.

Figure 1 illustrates a layout system 1 according to the inventive concept.

Referring to FIG. 1, the layout system 1 is configured to perform a layout method according to the inventive concept. To this end, the layout system 1 may include one or more instructions (eg, software programs) that enable the layout system 1 to execute the layout method, an example of which is described later. In an example of the inventive concept, the layout system 1 can operate as a stand-alone device or with another device electrically connected to the layout system 1. When connected to another device via, for example, a network, the layout system 1 can operate as a server or client in a server-client environment, and is on a peer-to-peer network network) or distributed network (distributed network) environment as a peer operation.

The layout system 1 may include a processor 10 (for example, a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), and an application-specific integrated circuit (application specific integrated circuit, ASIC, etc.), memory 20, memory 30, layout module 40, input device 50, and output device 60. The processor 10, the memory 20, the storage 30, the layout module 40, the input device 50, and the output device 60 can be electrically connected via the bus bar 70 to exchange data with each other.

The storage 30 may include a computer-readable medium containing instructions for performing a layout method and information about the layout of the semiconductor device. While the layout system 1 executes the method, the instructions may reside in the memory 20 (eg, main memory) or the processor 10 (eg, the cache memory of the processor 10). The information about the layout may include restrictions such as design rules, etc. about the layout of the semiconductor device. Data of various components used, standard unit data, etc. The layout system 1 can use the input device 50 to receive layout data from the user or another device or system connected to the layout system 1, and use the output device 60 to send stored data, result data, etc. related to the layout of the semiconductor device To the user or another device or system connected to the layout system 1.

The layout module 40 may use the processor 10 and lay out one or more standard cells of the semiconductor device according to defined requirements such as design rules. The design of the standard unit can be stored in the storage 30. A specific method by which the layout module 40 according to the concept of the present invention lays out standard cells (ie, designing semiconductor devices) will be explained later with reference to FIG. 3A.

2 illustrates a circuit system of a semiconductor device according to the concept of the present invention.

Referring to FIG. 2, the circuit system includes: a first transistor MP2, which is gate-controlled by the reverse voltage of the first input signal A to pull up the first node Y; a second transistor MN2, which is controlled by the second input signal B The voltage gate is controlled to pull down the first node Y; the third transistor MP4 is controlled to pull up the first node Y by the inverted voltage of the second input signal B; the fourth transistor MN4 is controlled by the first input signal The voltage level of A is gated to pull down the first node Y; the fifth transistor MN6 is driven by the voltage level of the second input signal B to pull down the second node Y'; the sixth transistor MP6 is driven by the first input The inverted voltage level of signal A is gated to pull up the second node Y'; the seventh transistor MN8 is gated down by the voltage level of the first input signal A to pull down the second node Y'; and the eighth transistor MP8 , The second node Y′ is pulled up by the inverted voltage of the second input signal B.

In this example, the first input signal A is transmitted to the first transistor MP2, the fourth transistor MN4, the sixth transistor MP6, and the seventh transistor MN8 of the semiconductor device, and the second input signal B is It is transmitted to the second transistor MN2, the third transistor MP4, the fifth transistor MN6, and the eighth transistor MP8. Therefore, the first transistor MP2, the fourth transistor MN4, the sixth transistor MP6, and the seventh transistor MN8 may have corresponding input terminals electrically connected to each other, and the second transistor MN2, the third transistor MP4, The fifth transistor MN6 and the eighth transistor MP8 may have corresponding input terminals electrically connected to each other.

As will be explained in more detail later with reference to FIG. 3A, in the semiconductor device, the input terminal of the first transistor MP2 and the input terminal of the fourth transistor MN4 can pass through the first metal layer (eg, the "metal 1" layer of the device ), and the input terminal of the second transistor MN2 and the input terminal of the third transistor MP4 can be connected by a second metal layer (for example, the "metal 0" layer of the device). In addition, the input terminal of the fifth transistor MN6 and the input terminal of the eighth transistor MP8 may be connected by a first metal layer (for example, a "metal 1" layer), and the input terminal of the sixth transistor MP6 and the seventh The input terminal of the transistor MN8 can be connected by a second metal layer (for example, a "metal 0" layer).

The second transistor MN2 and the fifth transistor MN6 may share the first gate (ie, constituted by the first gate), and the fourth transistor MN4 and the seventh transistor MN8 may share the second gate. For this, the gate of the second transistor MN2 and the gate of the fifth transistor MN6 may be formed by adjacent gate lines (ie, the first gate). Similarly, the gate of the fourth transistor MN4 and the gate of the seventh transistor MN8 can be The pole line (ie, the second gate) constitutes. In this example, the input terminal of the second transistor MN2 and the input terminal of the fifth transistor MN6 may be connected by a portion (or first interconnection) of the first gate electrode disposed on the substrate, and the fourth electrode The input terminal of the crystal MN4 and the input terminal of the seventh transistor MN8 may be connected by a part (or second interconnection) of the second gate electrode disposed on the substrate.

The first gate and the second gate can be arranged at a first level in the device, the first metal layer can be arranged at a second level higher than the first level, and the second metal layer can be arranged higher than the first level, But the third level is lower than the second level.

In the current example, the first transistor MP2, the third transistor MP4, the sixth transistor MP6, and the eighth transistor MP8 are P-type transistors, while the second transistor MN2, the fourth transistor MN4, the fifth Transistor MN6 and seventh transistor MN8 are N-type transistors. However, the inventive concept is not limited to this. That is, in another example according to the inventive concept, the first transistor MP2, the third transistor MP4, the sixth transistor MP6, and the eighth transistor MP8 are N-type transistors, and the second transistor MN2, The fourth transistor MN4, the fifth transistor MN6, and the seventh transistor MN8 are P-type transistors.

In other examples of the inventive concept, the circuit system further includes: a transistor MP1 connected in series to the first transistor MP2 and gated by the inverse voltage of the input signal C1 to provide the power supply voltage VDD; The crystal MN1 is connected in series to the second transistor MN2 and gated by the voltage level of the input signal C1 to provide the ground voltage VSS; the transistor MP3 is connected in series to the third transistor MP4 and is inverted by the input signal D1 Bit gate control to provide power supply voltage VDD; The transistor MN3 is connected in series to the fourth transistor MN4 and is gated by the voltage level of the input signal D1 to provide the ground voltage VSS.

In some examples according to the concept of the present invention, the circuit system further includes: a transistor MP5 connected in series to the sixth transistor MP6 and gated by the inverted voltage of the input signal C2 to provide the power supply voltage VDD ; Transistor MN5, connected in series to the fifth transistor MN6 and gated by the voltage level of the input signal C2 to provide the ground voltage VSS; Transistor MP7, connected in series to the eighth transistor MP8 and by the reverse of the input signal D2 The phase voltage is gated to provide the power supply voltage VDD; and the transistor MN7 is connected in series to the seventh transistor MN8 and gated by the voltage of the input signal D2 to provide the ground voltage VSS.

FIG. 3A illustrates an example of the layout of a semiconductor device according to the inventive concept. 4A and 4B are cross-sectional views of the semiconductor device having the layout shown in FIG. 3A taken along line L-L shown in FIG. 3A according to the concept of the present invention.

Referring to FIGS. 3A and 4A, the semiconductor device may include a first power rail 102, a second power rail 104, a third power rail 106, a first gate 122 and a second gate 124.

The first power rail 102, the second power rail 104, and the third power rail 106 extend longitudinally on the substrate in the first direction. A first region I is defined on one side of the second power rail 104, and a second region II is defined on the other side of the second power rail 104. Each of the first power rail 102, the second power rail 104, and the third power rail 106 may be a power supply voltage (VDD) rail that provides power or a grounded voltage (VSS) rail that is grounded. In the current example, the first power rail 102 and the third The power rail 106 is a power supply voltage rail, and the second power rail 104 is a ground voltage rail.

The first gate 122 extends across the first region I and the second region II in a second direction perpendicular to the first direction, and the second gate 124 is spaced apart from the first gate 122 in the first direction The two directions extend across the first area I and the second area II. In this example, the first gate 122 and the second gate 124 are arranged in the first horizontal plane in the third direction perpendicular to each of the first direction and the second direction in the device, that is, relative to the substrate At the same distance. Furthermore, in the illustrated example, the first gate 122 and the second gate 124 extend perpendicular to and across the second power rail 104. Therefore, the first gate 122 may include a first overlap portion 123 overlapping the second power rail 104 and the second gate 124 may include a second overlap portion 125 overlapping the second power rail 104. The first gate 122 and the second gate 124 may be polysilicon gates or metal gates.

In the illustrated example, the first transistor MP2, the second transistor MN2, the fifth transistor MN6, and the sixth transistor MP6 may include the first gate 122, and the third transistor MP4, the fourth transistor MN4, The seventh transistor MN8 and the eighth transistor MP8 may include a second gate 124. However, the inventive concept is not limited to this deployment of transistors. Furthermore, in the illustrated example, the second transistor MN2, the fourth transistor MN4, the fifth transistor MN6, and the seventh transistor MN8 are disposed adjacent to the second power rail 104 which is a ground voltage rail. However, the inventive concept is not limited to this deployment of transistors.

In the example shown, the first transistor MP2, the third transistor MP4, the first The six transistors MP6 and the eighth transistor MP8 are P-type transistors, and the second transistor MN2, the fourth transistor MN4, the fifth transistor MN6, and the seventh transistor MN8 are N-type transistors. However, the inventive concept is not limited to this. That is, in another example of the inventive concept, the first transistor MP2, the third transistor MP4, the sixth transistor MP6, and the eighth transistor MP8 are N-type transistors, and the second transistor MN2, the first transistor The quad transistor MN4, the fifth transistor MN6, and the seventh transistor MN8 are P-type transistors.

The semiconductor device according to the illustrated example of the inventive concept may include the first connection 132 and the second connection 134 in the first region I, and the third connection 136 and the fourth connection 138 in the second region II. In the first region I, the first connection 132 connects the input terminal of the first transistor MP2 and the input terminal of the fourth transistor MN4, and the second connection 134 connects the second transistor MN2 disposed on the first gate 122 And the input terminal of the third transistor MP4 disposed on the second gate 124. In the second region II, the third connection 136 connects the input terminal of the fifth transistor MN6 and the input terminal of the eighth transistor MP8, and the fourth connection 138 connects the input terminal of the sixth transistor MP6 and the seventh transistor MN8 Input terminal.

In addition, in this example, the first connection 132 and the third connection 136 are disposed in the device at a second level higher than the first level in the device, and the second connection 134 and the fourth connection 138 are disposed at a lower level relative to the substrate A third level that is higher than the first level but lower than the second level. That is, the first connection 132 and the third connection 136 are disposed at a different height (distance from the substrate) than the second connection 134 and the fourth connection 138. In some versions of this example, the first connection 132 and the second connection 134 crosses, and the third connection 136 crosses the fourth connection 138.

When viewed in a plan view, both the first connection 132 and the third connection 136 may be L-shaped. In the example shown, the first connection 132 and the third connection 136 are oriented the same. However, the orientation of the first connection 132 and the orientation of the third connection 136 may be different. When viewed in a plan view, both the second connection 134 and the fourth connection 138 may be in the shape of a bar, and thus are oriented the same.

In one version of this example of the inventive concept, the first connection 132 and the third connection 136 are portions of the first metal layer disposed on the second horizontal plane, and the second connection 134 and the fourth connection 138 are the second metal layer Of the third level. Referring to FIG. 4A, the first gate 122 and the second gate 124 are disposed at the first horizontal plane L1, the second connection 134 is disposed at the third horizontal plane L3, and the first connection 132 is disposed at the second horizontal plane L2. For example, the first connection 132 may be a "metal 1" layer, and the second connection 134 may be a "metal 0" layer. As another option, the first connection 132 may be a "metal 2" layer, and the second connection 134 may be a "metal 1" layer or a "metal 0" layer.

In addition, in this example of the inventive concept, the first gate 122 or the second gate 124 may be electrically connected to the second connection 134. For example, the upper surface of the first gate 122 or the second gate 124 and the lower surface of the second connection 134 may contact each other to form an electrical connection. As another option, the conductive material used to form the electrical connection may be sandwiched between the upper surface of the first gate 122 or the second gate 124 and the lower surface of the second connection 134.

The first horizontal plane L1, the second horizontal plane L2 and the third horizontal plane described herein L3 represents the relative distance from the substrate to the layout elements (eg, the first gate 122, the second gate 124, the second connection 134, the first connection 132, etc.). Here, the reference point for defining the distance from the layout element to the substrate may be the center point of the layout element in the direction of its thickness (ie, in the vertical direction). That is, the center point of a specific layout element can coincide with its "horizontal level". For example, referring back to FIG. 4A, the distance from the center point of the first gate 122 or the second gate 124 disposed on the first horizontal plane L1 to the substrate may be smaller than the second connection 134 disposed on the third horizontal plane L3 The distance from the center point of the first connection to the substrate, and the distance from the center point of the second connection 134 disposed on the third horizontal plane L3 to the substrate may be less than the distance from the center point of the first connection 132 disposed on the second horizontal plane L2 to the substrate.

In the example of the inventive concept shown in FIG. 4B, the lower surface of the second connection 134 disposed on the third horizontal plane L3 contacts the upper surface of the first gate 122 or the second gate 124 disposed on the first horizontal plane L1 . That is, the distance from the substrate to the lower surface of the second connection 134 disposed at the third horizontal plane L3 may be equal to the distance from the substrate to the upper surface of the first gate 122 or the second gate 124 disposed at the first horizontal plane L1 distance. This relationship (ie, contact) between the first gate 122 or the second gate 124 disposed on the first horizontal plane L1 and the second connection 134 disposed on the third horizontal plane L3 may be the same as that disposed on the third horizontal plane L3 The relationship between the second connection 134 and the first connection 132 disposed on the second horizontal plane L2.

The input terminal of the second transistor MN2 and the input terminal of the fifth transistor MN6 may be connected by a part of the first gate 122 (for example, the first overlapping portion 123 of the first gate 122), and the fourth The input terminal of the crystal MN4 and the seventh transistor The input terminal of the body MN8 may be connected by a part of the second gate 124 (for example, the second overlapping portion 125 of the second gate 124).

The layout module 40 of the layout system 1 described above with reference to FIG. 1 can design the layout of the semiconductor device as follows.

For example, the layout module 40 may lay out the first power rail 102 on the substrate to extend in the first direction, and lay out the second power rail 104 in the second direction perpendicular to the first direction and the first The power rails 102 extend in the first direction at intervals, and the third power rail 106 is laid out to extend in the first direction at a distance from the second power rail 104 in the second direction.

Next, the layout module 40 may define the first active region 112 and the second active region 114 between the first power rail 102 and the second power rail 104. The first active region 112 may be adjacent to the first power rail 102 and the second active region 114 may be adjacent to the second power rail 104. In addition, the layout module 40 may define a third active region 116 and a fourth active region 118 between the second power rail 104 and the third power rail 106. The third active area 116 may be adjacent to the second power rail 104 and the fourth active area 118 may be adjacent to the third power rail 106.

Next, the layout module 40 can lay out the first gate 122 to cross the first active region 112, the second active region 114, the third active region 116, and the fourth active region 118 in the second direction The two gates 124 are arranged along the second direction and spaced apart from the first gate 122.

The layout module 40 may use the first gate 122 and the first active region 112, the second active region 114, the third active region 116, and the fourth active region 118 to the first transistor The positioning of the body MP2, the positioning of the second transistor MN2, the positioning of the fifth transistor MN6, and the positioning of the sixth transistor MP6 are performed. The first transistor MP2 and the second transistor MN2 may be disposed between the first power rail 102 and the second power rail 104, and the fifth transistor MN6 and the sixth transistor MP6 may be disposed on the second power rail 104 and the third power rail 106. The layout module 40 may use the second gate 124 and the first active region 112, the second active region 114, the third active region 116, and the fourth active region 118 to the third transistor MP4, the fourth transistor MN4, the first Seven transistors MN8 and eighth transistor MP8 are laid out. The third transistor MP4 and the fourth transistor MN4 may be disposed between the first power rail 102 and the second power rail 104, and the seventh transistor MN8 and the eighth transistor MP8 may be disposed on the second power rail 104 and the third power rail 106.

Next, the layout module 40 pairs the connection between the input terminal of the first transistor MP2 and the input terminal of the fourth transistor MN4 and between the input terminal of the fifth transistor MN6 and the input terminal of the eighth transistor MP8 The connection is designed, that is, the trajectory composed of the first metal layer disposed at the first height relative to the substrate is designed. In addition, the layout module 40 connects the input terminal of the second transistor MN2 and the input terminal of the third transistor MP4 and the connection between the input terminal of the sixth transistor MP6 and the input terminal of the seventh transistor MN8 Designing, that is, designing a track composed of a second metal layer disposed at a second height lower than the first height relative to the substrate.

3B and 3C illustrate other examples of semiconductor devices that are laid out and manufactured according to the inventive concept.

Referring to FIG. 3B, the example shown is different from the example shown in FIG. 3A in the shape of the third connection 136 disposed in the second region II. Specifically, although a part of the third connection 136 in the example shown in FIG. 3A is vertically juxtaposed to the second gate 124 (ie, along the second gate 124), in the example shown in FIG. 3B, the third A portion of the connection 136 extends longitudinally perpendicular to the first gate 122 (ie, along the first gate 122).

Referring to FIG. 3C, the example shown is different from the example shown in FIG. 3A in that the third connection 136 connects the input terminal of the seventh transistor MN8 disposed on the second gate 124 in the second region II with the The input terminal of the sixth transistor MP6 on a gate 122, and the fourth connection 138 connects the input terminal of the fifth transistor MN6 disposed on the first gate 122 and the second gate in the second region II The input terminal of the eighth transistor MP8 on the pole 124.

5 is a layout diagram of another example of a semiconductor device according to the inventive concept.

5, the example shown is different from the example shown in FIG. 3A in that the first power rail 102 and the third power rail 106 correspond to the ground voltage rail, and the second power rail 104 corresponds to the power supply voltage Rails. In other words, although in the previous example shown in FIG. 3A, the first region I and the second region II share the ground voltage rail, in the example shown in FIG. 5, the first region I and the second region II share the power supply voltage Rails.

Therefore, the fifth transistor MN6 and the seventh transistor MN8 are arranged adjacent to the first power rail 102, the first transistor MP2, the third transistor MP4, and the sixth transistor The crystal MP6 and the eighth transistor MP8 are arranged adjacent to the second power rail 104, and the second transistor MN2 and the fourth transistor MN4 are arranged adjacent to the third power rail 106.

Furthermore, in this example, the input terminal of the sixth transistor MP6 and the input terminal of the first transistor MP2 are connected by a part of the first gate 122 (for example, the overlapping portion 123 of the first gate 122), And the input terminal of the eighth transistor MP8 and the input terminal of the third transistor MP4 are connected by a part of the second gate 124 (for example, the second overlapping portion 125 of the second gate 124).

6 illustrates a layout of other examples of semiconductor devices according to the inventive concept. 7A and 7B are cross-sectional views of different types of examples among the multiple examples taken along line M-M shown in FIG. 6, respectively.

The example shown in FIGS. 6 and 7A differs from the example shown in FIG. 3A in that the first connection 132 connects the input terminal of the second transistor MN2 arranged on the first gate 122 in the first region I and is arranged at The input terminal of the third transistor MP4 on the second gate 124, and the second connection 134 connects the input terminal of the first transistor MP2 and the fourth transistor disposed on the second gate 124 in the first region I Input terminal of MN4. Similarly, the third connection 136 connects the input terminal of the sixth transistor MP6 disposed on the first gate 122 and the input terminal of the seventh transistor MN8 disposed on the second gate 124 in the second region II, And the fourth connection 138 connects the input terminal of the fifth transistor MN6 disposed on the first gate 122 and the input terminal of the eighth transistor MP8 disposed on the second gate 124 in the second region II.

In addition, in this example, the first connection 132 and the third connection 136 are disposed at a second level higher than the first level with respect to the substrate of the device, and the second connection The 134 and the fourth connection 138 are disposed at a third level higher than the first level but lower than the second level relative to the substrate.

The first connection 132 and the third connection 136 may constitute a first metal layer disposed at the second level, and the second connection 134 and the fourth connection 138 may constitute a second metal layer disposed at the third level. Referring to FIG. 7A, the first gate 122 and the second gate 124 are disposed at the first horizontal plane L1, the second connection 134 is disposed at the third horizontal plane L3, and the first connection 132 is disposed at the second horizontal plane L2. For example, the first connection 132 may be a "metal 1" layer, and the second connection 134 may be a "metal 0" layer. As another option, the first connection 132 may be a "metal 2" layer, and the second connection 134 may be a "metal 1" layer or a "metal 0" layer.

In addition, the first gate 122 or the second gate 124 may be electrically connected to the second connection 134. For example, the upper surface of the first gate 122 or the second gate 124 and the lower surface of the second connection 134 may contact each other to form an electrical connection. Alternatively, the conductive material used to form the electrical connection may be sandwiched between the upper surface of the first gate 122 or the second gate 124 and the lower surface of the second connection 134.

Still referring to FIG. 7A, the distance from the center point of the first gate 122 or the second gate 124 disposed on the first horizontal plane L1 to the substrate may be less than the center point of the second connection 134 disposed on the third horizontal plane L3 to The distance of the substrate, and the distance from the center point of the second connection 134 disposed on the third horizontal plane L3 to the substrate may be less than the distance from the center point of the first connection 132 disposed on the second horizontal plane L2 to the substrate.

In the type of semiconductor device shown in FIG. 7B, the lower surface of the second connection 134 disposed on the third horizontal plane L3 contacts the first gate disposed on the first horizontal plane L1 The upper surface of the electrode 122 or the second gate electrode 124. That is, the distance from the substrate to the lower surface of the second connection 134 disposed at the third horizontal plane L3 may be equal to the distance from the substrate to the upper surface of the first gate 122 or the second gate 124 disposed at the first horizontal plane L1 distance. The relationship (ie, contact) between the first gate 122 or the second gate 124 disposed at the first horizontal plane L1 and the second connection 134 disposed at the third horizontal plane L3 may be the same as the first gate disposed at the third horizontal plane L3 The relationship between the second connection 134 and the first connection 132 disposed on the second horizontal plane L2.

8 illustrates the layout of another example of a semiconductor device according to the inventive concept.

Referring to FIG. 8, the example shown is different from the example shown in FIG. 6 in that the first power rail 102 and the third power rail 106 correspond to the ground voltage rail, and the second power rail 104 corresponds to the power supply voltage Rails. In other words, although in the previous example shown in FIG. 6, the first region I and the second region II share the ground voltage rail, in the example shown in FIG. 8, the first region I and the second region II share the power supply voltage Rails.

Therefore, the fifth transistor MN6 and the seventh transistor MN8 are arranged adjacent to the first power rail 102, and the first transistor MP2, the third transistor MP4, the sixth transistor MP6, and the eighth transistor MP8 are adjacent to The second power rail 104 is disposed, and the second transistor MN2 and the fourth transistor MN4 are disposed adjacent to the third power rail 106.

Furthermore, in this example, the input terminal of the sixth transistor MP6 and the input terminal of the first transistor MP2 pass through a part of the first gate 122 (for example, through the overlapping portion 123 of the first gate 122) Connected, and the input of the eighth transistor MP8 The terminal and the input terminal of the third transistor MP4 are connected by a part of the second gate 124 (for example, by the second overlapping portion 125 of the second gate 124).

9 illustrates the layout of yet another example of a semiconductor device according to the inventive concept.

9, the example shown is different from the example shown in FIG. 3A in that the semiconductor device according to the example shown further includes a fourth power rail 108 to define a third region III with the third power rail 106. Therefore, the first gate 122 includes two first overlapping portions 123a and 123b, and the second gate 124 includes two second overlapping portions 125a and 125b. In the third region III, the ninth transistor MP10 and the tenth transistor MN10 are composed of the first gate 122, and the eleventh transistor MP12 and the twelfth transistor MN12 are composed of the second gate 124.

In addition, in the illustrated example, the first transistor MP2, the fourth transistor MN4, the sixth transistor MP6, the seventh transistor MN8, the ninth transistor MP10, and the twelfth transistor MN12 of the semiconductor device share The first input signal A, and the second transistor MN2, the third transistor MP4, the fifth transistor MN6, the eighth transistor MP8, the tenth transistor MN10 and the eleventh transistor MP12 share the second input signal B.

Therefore, the input terminal of the first transistor MP2 and the input terminal of the fourth transistor MN4, the input terminal of the fifth transistor MN6 and the input terminal of the eighth transistor MP8, and the input terminal of the ninth transistor MP10 and the tenth The input terminals of the two transistors MN12 can be connected by a first metal layer (for example, "Metal 1"). In addition, the input terminal of the second transistor MN2 and the input terminal of the third transistor MP4, the first The input terminal of the six transistor MP6 and the input terminal of the seventh transistor MN8, and the input terminal of the tenth transistor MN10 and the input terminal of the eleventh transistor MP12 can be passed through a second metal layer (for example, "Metal 0" ) While connected.

As in the previous example, each of the first power rail 102, the second power rail 104, the third power rail 106, and the fourth power rail 108 may be a power supply voltage rail or a ground voltage rail Article. Therefore, whether the transistor is N-type or P-type may depend on whether the rails (first power rail 102, second power rail 104, third power rail 106, and fourth power rail 108) are power supply voltage rails Or the ground voltage rail.

In addition, the illustrated example of the semiconductor device according to the inventive concept includes the first region I to the third region III, but the inventive concept is not limited to the semiconductor device having only three such regions, but is included in four or more Devices with similar components laid out above each area.

FIG. 10 illustrates yet another example of the layout of a semiconductor device according to the inventive concept.

Referring to FIG. 10, the example shown is different from the example shown in FIG. 3A in that the first overlap portion 127 of the first gate 122 includes a material different from that of other parts of the first gate 122, and the second gate The second overlapping portion 129 of the pole 124 contains a material different from that of the other parts of the second gate 124. For example, the first gate 122 may be a polysilicon gate. In this case, the first overlap 127 may be formed of metal, and the rest of the first gate 122 may be formed of polysilicon. Conversely, the first gate 122 may be a metal gate. In this case, the first overlap 127 is made of polycrystalline Silicon is formed, and the rest of the first gate 122 may be formed of metal.

According to the example of the inventive concept explained above with reference to FIGS. 3A to 10, the area of each of the semiconductor circuits sharing the same input signal can be minimized. In addition, power consumption is minimized due to the reduction in parasitic capacitance and parasitic resistance caused by the reduction in the area of each of the semiconductor circuits sharing the same input signal. That is, according to aspects of the inventive concept, a semiconductor device having a relatively small area and consuming a relatively small amount of power can be provided.

The above examples of the inventive concept can be stored in a computer-readable recording medium (for example, the storage 30) as a standard cell library, and used in the design of semiconductor circuits. That is, the standard cell library may include layouts within the scope of the present invention as illustrated by FIGS. 3A to 10. Examples of computer-readable recording media include: magnetic media such as hard disks, floppy disks, and magnetic tape; optical media such as compact disc read-only memory (CD-ROM) and digital video discs (Digital Video Disk, DVD); magneto-optical media (magneto-optical media), such as floppy disks; and hardware, such as read-only memory (Read-Only Memory, ROM), random access memory (random access memory, RAM) And flash memory.

11 to 13 illustrate examples of electronic devices that may have semiconductor devices according to the concepts of the present invention.

11 illustrates a tablet personal computer (PC) 1200, FIG. 12 illustrates a notebook computer 1300, and FIG. 13 illustrates a smart phone 1400. Each of the tablet personal computer 1200, the notebook computer 1300, and the smartphone 1400 There may be at least one semiconductor device laid out and manufactured according to the inventive concept.

However, as described herein, the semiconductor device according to the concept of the present invention can be applied to various integrated circuit devices in addition to the integrated circuit (IC) devices of the electronic products shown in FIGS. 11 to 13. For example, the concept of the present invention can be applied to desktop computers, Ultra Mobile PCs (UMPCs), workbenches, net-book computers, personal digital assistants , PDA), wireless phones, mobile phones, e-books, portable multimedia players (PMP), portable game consoles, navigation devices, black boxes, digital cameras, 3D TVs, digital Audio recorder, digital audio player, digital picture recorder, digital picture player, digital video recorder, digital video player, etc.

Finally, the examples of the inventive concept have been explained in detail above. However, the inventive concept can be implemented in many different ways and should not be considered limited to the above examples. To be precise, these examples are described in order to make the disclosure content thorough and complete, and fully convey the concept of the present invention to those skilled in the art. Therefore, the true spirit and scope of the inventive concept are not limited by the above examples, but by the following patent applications.

102‧‧‧The first power rail

104‧‧‧The second power rail

106‧‧‧The third power rail

112‧‧‧First active area

114‧‧‧Second Active Area

116‧‧‧The third active area

118‧‧‧The fourth active area

122‧‧‧The first gate

123‧‧‧First Overlap

124‧‧‧Second Gate

125‧‧‧The second overlap

132‧‧‧ First connection

134‧‧‧ Second connection

136‧‧‧ Third connection

138‧‧‧ Fourth connection

A‧‧‧First input signal

B‧‧‧Second input signal

C1, C2‧‧‧Input signal

D1, D2‧‧‧Input signal

I‧‧‧The first area

II‧‧‧Second area

L-L‧‧‧line

MN1‧‧‧Transistor

MN2‧‧‧Second transistor

MN3‧‧‧Transistor

MN4‧‧‧The fourth transistor

MN5‧‧‧transistor

MN6 fifth transistor

MN7‧‧‧Transistor

MN8 ‧‧‧ seventh transistor

MP1‧‧‧Transistor

MP2‧‧‧First transistor

MP3‧‧‧Transistor

MP4‧‧‧third transistor

MP5‧‧‧Transistor

MP6‧‧‧The sixth transistor

MP7‧‧‧Transistor

MP8‧‧‧Eighth transistor

VDD‧‧‧Power supply voltage

VSS‧‧‧Ground voltage

Claims (20)

A semiconductor device includes: a substrate having a first region and a second region of the substrate, the first region is disposed on one side of an axis extending in a first direction across the substrate, and the first Two regions are arranged on the other side of the axis; a first gate electrode extends across the first region and the second region in a second direction perpendicular to the first direction, and in the semiconductor The device is disposed at a first horizontal plane relative to the substrate; a second gate electrode extends across the first region in the second direction and spaced apart from the first gate electrode in the first direction and The second region, and the semiconductor device is disposed on the first horizontal plane; the first connection is electrically connected to the input of the first transistor composed of the first gate electrode in the first region A terminal and an input terminal of a fourth transistor constituted by the second gate electrode, and disposed at a second horizontal plane higher than the first horizontal plane relative to the substrate; a second connection in the first region The input terminal of the second transistor constituted by the first gate is electrically connected to the input terminal of the third transistor constituted by the second gate, and is arranged closer to the first than the substrate A third level that is higher than the second level but lower than the second level; a third connection is placed at the second level in the semiconductor device; and a fourth connection is placed at the first level in the semiconductor device Three levels, and Wherein the input terminal of the second transistor and the input terminal of the fifth transistor are respectively composed of the part of the first gate, and the input terminal of the fourth transistor and the seventh transistor The input terminals are each constituted by a part of the second gate. The semiconductor device according to item 1 of the patent application range, wherein the first connection and the third connection are a first pattern of conductive material, and the first pattern is perpendicular to the upper surface of the substrate The center in the direction is located at the second horizontal plane, and the second connection and the fourth connection are second patterns of conductive material, and the center of the second pattern in the vertical direction is located at the third level. The semiconductor device according to item 1 of the patent application scope, wherein the first connection crosses the second connection and the third connection crosses the fourth connection when viewed in a plan view. The semiconductor device according to item 1 of the patent application scope further includes a power rail extending longitudinally in the first direction, wherein the first gate electrode and the second gate electrode when viewed in a plan view Cross the power rail at a right angle. The semiconductor device according to item 4 of the patent application range, wherein the first gate electrode includes a first overlapped portion overlapping the power rail, and the input terminal of the second transistor and all The input terminal of the fifth transistor is composed of the first overlapping portion. The semiconductor device according to item 4 of the patent application range, wherein the second gate includes a second overlapping portion overlapping the power rail, and the fourth transistor The input terminal of the body and the input terminal of the seventh transistor are constituted by the second overlapping portion. The semiconductor device according to item 4 of the patent application scope, wherein the second transistor, the fourth transistor, the fifth transistor, and the seventh transistor are arranged adjacent to the power rail . The semiconductor device according to item 4 of the patent application scope, wherein the power rail is a ground voltage (VSS) rail, the first transistor, the third transistor, the sixth transistor, and the eighth transistor The crystal is a P-type transistor, and the second transistor, the fourth transistor, the fifth transistor, and the seventh transistor are N-type transistors. The semiconductor device according to item 4 of the patent application scope, wherein the power rail is a power supply voltage (VDD) rail, the first transistor, the third transistor, the sixth transistor, and the eighth The transistor is an N-type transistor, and the second transistor, the fourth transistor, the fifth transistor, and the seventh transistor are P-type transistors. The semiconductor device according to item 1 of the patent application range, wherein the third connection is electrically connected to the input terminal of the fifth transistor and the input terminal of the eighth transistor, and the fourth connection is electrically Connecting the input terminal of the sixth transistor with the input terminal of the seventh transistor, or the third connection electrically connects the input terminal of the sixth transistor with the position of the seventh transistor The input terminal, and the fourth connection electrically connects the input terminal of the fifth transistor and the input terminal of the eighth transistor. A semiconductor device, comprising: a substrate; a power rail, extending longitudinally on the substrate in a first direction, such that the substrate has a first region disposed on one side of the power rail and the power supply A second area on the other side of the rail; a first gate extending across the first area and the second area in a second direction perpendicular to the first direction and having a power rail A first overlapping portion where the strips overlap; a second gate extending across the first region and the first in the second direction at a distance from the first gate in the first direction Two regions, and having a second overlapping portion that overlaps with the power rail, wherein the first transistor of the semiconductor device is disposed at a position where the first gate electrode extends in the first region, so The fourth transistor of the semiconductor device is disposed at a position where the second gate electrode extends in the first region, and the seventh transistor of the semiconductor device is disposed at the second gate electrode in the second region And the sixth transistor of the semiconductor device is disposed at a position where the first gate electrode extends in the second region, the first transistor, the fourth transistor, the The seventh transistor and the sixth transistor are gated by the same first input signal, and the second transistor of the semiconductor device is arranged at a position where the first gate electrode extends in the first region, the The third transistor of the semiconductor device is disposed at a position where the second gate extends in the first region, and the fifth of the semiconductor device The transistor is arranged at a position where the first gate electrode extends in the second region, and the eighth transistor of the semiconductor device is arranged at a position where the second gate electrode extends in the second region, The second transistor, the third transistor, the fifth transistor and the eighth transistor are gated by the same second input signal; a first metal layer, the first metal layer is included in the Connection between the input terminal of the first transistor and the input terminal of the fourth transistor in the first region, and input terminal of the fifth transistor in the second region Connection with the input terminal of the eighth transistor; and a second metal layer including the input terminal and the third of the second transistor electrically connected in the first region The connection of the input terminal of the transistor and the connection between the input terminal of the sixth transistor and the input terminal of the seventh transistor in the second region, wherein the first metal layer and the The second metal layer is disposed at different horizontal planes in the semiconductor device, and the input terminal of the second transistor and the input terminal of the fifth transistor pass the first overlapping portion It is electrically connected, and the input terminal of the fourth transistor and the input terminal of the seventh transistor are electrically connected by the second overlapping portion. The semiconductor device according to item 11 of the patent application range, wherein the second metal layer is disposed in the semiconductor device with respect to the substrate at a lower level than that where the first metal layer is disposed. The semiconductor device according to item 12 of the patent application range, wherein the first overlapping portion and the second overlapping portion are disposed in the semiconductor device in a position lower than the second metal layer with respect to the substrate Low water level. The semiconductor device according to item 11 of the patent application scope, wherein the connection of the first metal layer disposed in the first region and the one disposed in the first region when viewed in a plan view The connections of the second metal layer cross each other. The semiconductor device according to item 11 of the patent application scope, wherein the connection of the first metal layer disposed in the second region and the one disposed in the second region when viewed in a plan view The connections of the second metal layer cross each other. The semiconductor device according to item 11 of the patent application range, wherein the second transistor, the fourth transistor, the fifth transistor, and the seventh transistor are arranged adjacent to the power rail . A semiconductor device, comprising: a substrate; a plurality of gate lines spaced apart from each other in a first direction and each extending longitudinally above the substrate in a second direction perpendicular to the first direction; a first metal layer, Disposed on the substrate and including a first discrete conductive connection; a second metal layer disposed on the substrate at a level different from the first metal layer and including a second discrete conductive connection , And Wherein the semiconductor device has a plurality of cells arranged side by side in the second direction, and each of the cells is composed of: active regions of the substrate spaced apart from each other in the second direction; A first gate line and a second gate line of the gate lines extending longitudinally above the active area; a first pair of transistors are located at corresponding positions of the first gate line extending above the active area , Wherein the first gate line provides input terminals for the first pair of transistors in the unit; the second pair of transistors is located at a corresponding position where the second gate line extends above the active area , Wherein the second gate line provides an input terminal for the second pair of transistors in the cell; one of the first discrete conductive connections of the first metal layer; and One of the second discrete conductive connections of the second metal layer, the one of the first discrete conductive connections of the first metal layer overlaps the first A gate line and a second gate line, and electrically connect the input terminal of one of the first pair of transistors to one of the second pair of transistors in the unit The input terminal, and the one of the second discrete conductive connections of the second metal layer overlaps the first gate line and the second gate line, and The unit electrically connects the input terminal of the other one of the first pair of transistors to the input terminal of the other one of the second pair of transistors. The semiconductor device according to item 17 of the patent application range, wherein the conductive connections of the first metal layer are each L-shaped when viewed in a plan view, And when viewed in a plan view, the conductive connections of the second metal layer each have a bar shape. The semiconductor device according to item 17 of the patent application scope further includes a plurality of rails each extending longitudinally in the first direction above the substrate and spaced in the second direction And each of the units is sandwiched between adjacent rails in the rail in the second direction, all of the rails located on opposite sides of each of the units The adjacent rails respectively include a ground voltage (VSS) rail and a power supply voltage (VDD) rail. When viewed in a plan view, each of the first gate and the second gate A right angle crosses the adjacent rail in the rail, and the conductive connection of one of the first metal layer and the second metal layer is electrically connected to the ground voltage (VSS) One of the rail and the power supply voltage rail, and the conductive connection of the other of the first metal layer and the second metal layer is electrically connected to the ground voltage (VSS ) The rail and the other of the power supply voltage rail. The semiconductor device according to item 17 of the patent application range, wherein the first pair of transistors of each of the cells is one of a P-type transistor and an N-type transistor, and each of the cells The second pair of transistors are the other of P-type transistors and N-type transistors.

Images