TWI683203B - Method for performing signal adjustment and associated timing controller - Google Patents

Abstract

The present invention provides a method for performing signal adjustment and associated timing controller, which is applicable to a controller of a display apparatus. The display apparatus comprises the timing controller, a plurality of data lines, a plurality of scan lines, and a plurality of display units, wherein the timing controller generates multiple control signals according to a clock signal to control the display apparatus, and the method may include performing associated adjustment, to control the charging time of a data line during different horizontal periods tend to be consistent. For example, the aforementioned associated adjustment may include adjust a predetermined configuration or a modulation rate of the clock signal.

Description

Method for adjusting signal and related timing controller

The invention relates to signal control, in particular to a method for signal adjustment and related timing controller, wherein the method is applicable to a timing controller of a display device.

At a signal output, a fixed-frequency clock signal is the main source of electromagnetic interference (Electromagnetic Interference may be referred to as EMI). Among them, the Spread Spectrum Clock technology can effectively reduce EMI through the modulation of the clock. Peak. However, the control signals of the display panel may also be spread, which causes the frequency of the control signals to change with time, so that the signal lines on the display panel have different charging times under different frame cycles, causing the display screen to scroll The water ripples thus give users a poor user experience. Therefore, there is a need for a novel method and related architecture to solve the problems of related technologies without side effects or with less likely side effects.

An object of the present invention is to provide a method for signal adjustment and related timing controller to solve the above problems.

Another object of the present invention is to provide a method for signal adjustment and related timing controller to control the charging time trend of a data line at different levels in a cycle without side effects or less likely to cause side effects Be consistent.

At least one embodiment of the present invention provides a method for signal adjustment, wherein the The method can be applied to a timing controller of a display device including the timing controller, a plurality of data lines, a plurality of scan lines, and a plurality of display units, and the method can include: detection An overall average period of a clock signal, wherein the timing controller generates a plurality of control signals according to the clock signal to control the display device; separately detects the period of the clock signal in each of the plurality of scan lines Average period; compare the average periods with the overall average period to produce a comparison result; according to the comparison results, adjust the predetermined settings of the plurality of scan lines to determine the gates of the plurality of scan lines respectively The pulse width of the polar control signal, wherein the pulse widths respectively correspond to the predetermined settings of the plurality of scan lines; and dynamically adjust the predetermined settings to control a data line at different horizontal periods The charging time tends to be consistent.

At least one embodiment of the present invention provides a timing controller of a display device, wherein the display device may include the timing controller, a plurality of data lines, a plurality of scan lines, and a plurality of display units. The timing controller may include at least one detection circuit, at least one comparison circuit, and at least one adjustment circuit, wherein the at least one detection circuit may be used to detect an overall average period of the clock signal and the plurality of The average period of the period of each of the scan lines, the at least one comparison circuit can be used to compare the average periods with the overall average period respectively to generate comparison results, and the at least one adjustment circuit can be used to The comparison results respectively adjust the predetermined settings of the plurality of scan lines to determine the pulse width of the gate control signal on the plurality of scan lines, wherein the pulse widths respectively correspond to the plurality of scan lines The predetermined settings, for example, the at least one adjustment circuit can dynamically adjust the predetermined settings to control the charging time of a data line to be consistent at different horizontal periods.

At least one embodiment of the present invention provides a method for signal adjustment, wherein the method can be applied to a timing controller of a display device, the display device includes the timing controller, a plurality of data lines, A plurality of scanning lines and a plurality of display units, and the method may include: detecting a horizontal-line frequency (H-line) of the display device frequency), wherein the horizontal line frequency is determined by the frame rate of the display device and the row count of the plurality of display units; the clock signal is adjusted according to the horizontal line frequency, wherein the timing The controller generates a plurality of control signals according to the clock signal to control the display device; dynamically adjusts the clock signal to control the charging time of a data line at different horizontal periods to be consistent.

At least one embodiment of the present invention provides a timing controller of a display device, wherein the display device may include the timing controller, a plurality of data lines, a plurality of scan lines, and a plurality of display units. The timing controller may include a Spread Spectrum Clock (SSC) generator, at least one detection circuit and at least one adjustment circuit, wherein the spread spectrum clock generator may be used to generate the clock signal, the At least one detection circuit can be used to detect a horizontal-line frequency (H-line frequency) of the display device, wherein the horizontal-line frequency is determined by the frame rate of the display device and the plurality of displays The row count of the unit is determined, and the at least one adjustment circuit can be used to adjust the clock signal according to the horizontal line frequency, wherein the timing controller generates a plurality of control signals according to the clock signal to control the display device, For example, the at least one adjustment circuit can dynamically adjust the clock signal to control the charging time of a data line to be consistent at different horizontal periods.

One of the advantages of the present invention is that the present invention can perform related adjustments to control the charging time of a data line at different levels of the cycle to be consistent. The above-mentioned related adjustments may include adjusting a predetermined setting or the modulation frequency of the clock signal. In addition, implementation according to the related embodiments of the present invention does not add much extra cost, therefore, the problems of the related art can be solved, and the overall cost does not increase too much. Compared with the related art, the present invention can control the charging time of a data line at different levels in a period without side effects or less likely to cause side effects.

310,320,330,340,610,620‧‧‧ steps

100‧‧‧Display device

120, 200, 500 ‧‧‧ timing controller

140‧‧‧ source driver

160‧‧‧Gate driver

220‧‧‧ Spread Spectrum Clock Generator

240,540‧‧‧ detection circuit

260‧‧‧Comparison circuit

280,580‧‧‧Adjustment circuit

DU _1,1 ,DU _1,2 ,...,DU _1,M ,DU _2,1 ,DU _2,2 ,...,DU _2,M ,...,DU _N,1 ,DU _{N, 2} ,...DU _N,M ‧‧‧Display unit

DL ₁ ,DL ₂ ,...,DL _M ‧‧‧Data cable

SL ₁ ,SL ₂ ,...,SL _N ‧‧‧scan line

G _EN, G _EN '‧‧‧ gate enable signal

_{G 1, G 2, ...,} G N, G 1 ', G 2', ..., G N '‧‧‧ gate control signal

L ₁ ,L ₂ ,...,L _N ‧‧‧

TP, MR_1, MR_2, MR_3 ‧‧‧ signal

FIG. 1 is a schematic diagram of a display device according to an embodiment of the invention.

FIG. 2 is a schematic diagram of a timing controller according to an embodiment of the invention.

FIG. 3 is a working flow of the timing controller shown in FIG. 2 according to an embodiment of the present invention.

FIG. 4 is an example of a signal adjustment result according to an embodiment of the invention.

FIG. 5 is a schematic diagram of a timing controller according to another embodiment of the invention.

FIG. 6 is a workflow of the timing controller shown in FIG. 5 according to another embodiment of the present invention.

FIG. 7 is an example of the modulation frequency adjustment result according to another embodiment of the present invention.

Embodiments of the present invention provide a method for signal adjustment and a related timing controller. In particular, the method can be applied to a timing controller of a display device. For ease of understanding, the method can pass the operation example of the timing controller To illustrate, the present invention is not limited to this. FIG. 1 is a schematic diagram of a display device 100 according to an embodiment of the present invention, wherein the display device 100 may include a timing controller 120, a source driver 140, a gate driver 160, and a plurality of data lines {DL ₁ , DL ₂ , ...,DL _M }, plural scanning lines {SL ₁ ,SL ₂ ,...,SL _N }, and plural display units {DU _1,1 ,DU _1,2 ,...,DU _{1, M} ,DU _2,1 ,DU _2,2 ,...,DU _2,M ,...,DU _N,1 ,DU _N,2 ,...DU _N,M }, symbols M and N are both A positive integer, where the timing controller can generate multiple control signals (such as multiple gate control signals and gate enable signals (such as GE _N )) for display control and individually control the plurality of display units {DU _1,1 ,DU _1,2 ,...,DU _1,M ,DU _2,1 ,DU _2,2 ,...,DU _2,M ,...,DU _N,1 ,DU _N,2 ,.. .DU _N,M } Charging time, please note that this architecture is for illustrative purposes only, and is not a limitation of the present invention.

FIG. 2 is a schematic diagram of a timing controller 200 according to an embodiment of the present invention. The timing controller 200 can be used as an example of the timing controller 120 shown in FIG. 1, but the present invention is not limited thereto. The timing controller 200 may include a Spread Spectrum Clock generator 220, a detection circuit 240, a comparison circuit 260, and an adjustment circuit 280. In order to suppress the influence of electromagnetic interference (Electromagnetic Interference, EMI), the spread spectrum clock generator 220 can adjust the frequency of the generated clock signal CK to effectively reduce the peak value of electromagnetic interference. However, according to the clock signal CK The generated gate control signals are therefore applied with corresponding spread-spectrum effects. Assuming that the corresponding spread-spectrum effect is not further processed, the corresponding spread-spectrum effect may cause the frequency of each of the plurality of gate control signals to change with time, thereby affecting the plurality of display units {DU _1,1 ,DU _1,2 ,...,DU _1,M ,DU _2,1 ,DU _2,2 ,...,DU _2,M ,...,DU _N,1 ,DU _N,2 ,...DU _N,M } charging time. The architecture of the present invention may include an adjustment mechanism reverse to the frequency change to eliminate the above corresponding spread-spectrum effect, so the plurality of display units {DU _1,1 ,DU _1,2 ,...,DU _{1, M} ,DU _2,1 ,DU _2,2 ,...,DU _2,M ,...,DU _N,1 ,DU _N,2 ,...DU _N,M } The charging time can be maintained normally, There is no adverse effect due to the above-mentioned corresponding spread-spectrum effect.

FIG. 3 is a workflow 300 of the timing controller 200 operating according to an embodiment of the invention.

Step 310: Detect the overall average period of a clock signal. In this embodiment, although the period (or frequency) of the clock signal CK changes with time, from a slightly longer period of time (for example, corresponding to the time period for switching the screen), the period of the clock signal CK has a period The average value, the detection circuit 240 can detect the overall average period T_AVG of the clock signal CK as a reference.

Step 320: Detect the average period of the clock signal in each of the plurality of scan lines separately. In this embodiment, the detection circuit 240 can respectively detect the clock signal CK during the period when the signals of the scanning lines {SL ₁ , SL ₂ ,..., SL _N } are enabled, and the corresponding average The periods are {T_AVG ₁ , T_AVG ₂ ,..., T_AVG _N }.

Step 330: Compare the average periods with the overall average period to generate comparison results. In this embodiment, the comparison circuit 260 can compare the average period {T_AVG ₁ , T_AVG ₂ ,..., T_AVG _N } detected by the detection circuit 240 in step 320 with the detection circuit 240 in step 310 The detected overall average periods T_AVG are compared to produce comparison results {CR ₁ , CR ₂ ,..., CR _N }, respectively.

Step 340: Adjust the predetermined settings of the plurality of scan lines respectively according to the comparison results. In this embodiment, the adjustment circuit 280 may adjust the predetermined corresponding to the scan lines {SL ₁ , SL ₂ ,..., SL _N } according to the comparison results {CR ₁ , CR ₂ ,..., CR _N } Settings, wherein the predetermined settings can respectively determine the pulse width of the gate control signal on the scanning lines {SL ₁ , SL ₂ ,..., SL _N }, and the pulse widths respectively correspond to The predetermined settings of the plurality of scan lines. For example, the predetermined settings respectively indicate the number of cycles corresponding to the pulse widths of the gate control signals {CYCLE ₁ ,CYCLE ₂ ,...,CYCLE _N }, where the number of cycles {CYCLE ₁ ,CYCLE ₂ ,...,CYCLE _N }represents the number of multiple cycles of the clock signal respectively.

For example, when the comparison result CR ₁ indicates that the clock signal CK is in the enabled state during the period of the signal of the scanning line SL ₁ , the corresponding average period T_AVG _{1 is} smaller than the overall average period T_AVG, and the adjustment circuit 280 may increase the corresponding The number of cycles is CYCLE ₁ ; for another example, when the comparison result CR ₂ indicates that the clock signal CK is in the period when the signal of the scanning line SL ₂ is in the activated state, the corresponding average period T_AVG _{2 is} larger than the overall average period T_AVG, and the adjustment circuit 280 may Reduce the corresponding cycle number CYCLE ₂ .

In this embodiment, the timing controller 200 can control a data by repeatedly executing the workflow 300 and dynamically adjusting the predetermined settings (such as the number of cycles {CYCLE ₁ ,CYCLE ₂ ,...,CYCLE _N }) The charging time of the line (such as any of the data lines {DL ₁ , DL ₂ ,..., DL _M }) tends to be consistent at different horizontal periods (or different frame periods), especially, The timing controller 200 can control the coupling to the data line {DL _{1 by} repeatedly executing the work flow 300 and dynamically adjusting the predetermined settings (such as the number of cycles {CYCLE ₁ ,CYCLE ₂ ,...,CYCLE _N }) , DL ₂ ,..., DL _M } any of the multiple display units (such as the data line DL ₁ ) of multiple display units (such as display units {DU _1,1 ,DU _2,1 ,...,DU _{N, 1} }) The charging time in different horizontal periods (or different frame periods) tends to be the same, but the invention is not limited to this.

FIG. 4 is an example of a signal adjustment result according to an embodiment of the invention. The upper part of Figure 4 is the control signal before signal adjustment, in order for the gate enable signal G _EN , the gate control signal G ₁ on the scan line SL ₁ , and the gate on the scan line SL ₂ pole control signals G _2, ... on the scanning line and the gate electrode control signal SL _N G _N, while the lower half of FIG. 4 is a control signal after the signal is adjusted, in order, is to enable the gate signal G _EN ' , the gate electrode of the _scanning line SL control signal G ₁ ', the scan line SL on the gate electrode _2, the control signal G _2', ... and the scan line SL on the gate electrode control signal _N G _N ', wherein the gate The pole control signals {G ₁ ,G ₂ ,...,G _N } (or the gate control signals {G ₁ ',G ₂ ',...,G _N '}) can represent the scanning lines {SL ₁ , SL ₂ ,...,SL _N } During the activation period, the numbers marked on the gate enable signals G _EN and G _EN 'represent the number of cycles of the clock signal CK (such as {CYCLE ₁ ,CYCLE ₂ ,...,CYCLE _N }). As shown in Figure 4, before the signal adjustment, the number of cycles {CYCLE ₁ ,CYCLE ₂ ,...,CYCLE _N } is set to 2000 cycles, however, due to the average of the clock signal CK in each activation period The cycles are inconsistent, so that the pulse widths of the gate control signals {G ₁ , G ₂ ,..., G _N } are inconsistent and the charging time is inconsistent. According to this embodiment, for example, the comparison circuit 260 may indicate that the average period T_AVG _{1 of the} clock signal CK during L _{1 is} smaller than the overall average period T_AVG, and the adjustment circuit 280 adjusts the cycle number CYCLE ₁ from 2000 to 2003; for example, The comparison circuit 260 can indicate that the average period T_AVG _{2 of the} clock signal CK during L _{2 is} larger than the overall average period T_AVG, and the adjustment circuit 280 adjusts the cycle number CYCLE ₂ from 2000 to 1997; and so on. Therefore, the timing controller 200 can control the gate control signal {G ₁ ',G ₂ ',...,G _N '} by dynamically adjusting the number of cycles {CYCLE ₁ ,CYCLE ₂ ,...,CYCLE _N } The pulse width tends to be consistent, so that the charging time tends to be consistent, but the invention is not limited to this.

FIG. 5 is a schematic diagram of a timing controller 500 according to another embodiment of the present invention. The timing controller 500 can be used as an example of the timing controller 120 shown in FIG. 1, but the present invention is not limited thereto. The timing controller 500 may include a spread-spectrum clock generator 220, a detection circuit 540, and an adjustment circuit 580. Related operations can be illustrated by examples in subsequent embodiments.

FIG. 6 is a workflow 600 of the timing controller 500 operating according to another embodiment of the present invention.

Step 610: Detect the horizontal line frequency of the display device 100. The detection circuit 540 can detect a horizontal-line frequency (H-line frequency) of the display device 100, wherein the horizontal-line frequency is determined by the frame rate of the display device 100 and the display unit {DU _{1, 1} ,DU _1,2 ,...,DU _1,M ,DU _2,1 ,DU _2,2 ,...,DU _2,M ,...,DU _N,1 ,DU _N,2 ,. .. DU _N,M } to determine the row count (row count), for example, when the display device 100 operates, the frame frequency is 60 Hz and the display unit row count is 2000 (ie, N is 2000) The frequency of the horizontal line is 60×2000=120kHz.

Step 620: Adjust the clock signal according to the detected horizontal line frequency. For example, when the detection circuit 540 detects that the horizontal line frequency is 120 kHz, the adjustment circuit 580 can control the spread spectrum clock generator 220 to adjust the modulation rate of the clock signal CK to 120 Hz (or 120 kHz) Integer multiple), so that the frequency of the horizontal line and the modulation frequency of the clock signal CK are consistent (or synchronized). In addition, the timing controller 500 can dynamically adjust the modulation frequency of the clock signal CK by repeatedly performing the workflow 600 to control a data line (such as data lines {DL ₁ , DL ₂ ,...,DL _M } Any one of them) the charging time at different horizontal periods (or different frame periods) tends to be consistent, in particular, the timing controller 500 can dynamically adjust the frequency modulation of the clock signal CK by repeatedly executing the workflow 600 To control multiple display units (eg, display units {DU _1,1 , which are coupled to any of the data lines {DL ₁ ,DL ₂ ,...,DL _M } (eg, data lines DL ₁ ) DU _2,1 ,...,DU _N,1 }) charging times at different horizontal periods (or different frame periods) tend to be consistent, but the invention is not limited to this.

According to some embodiments, the timing controller 500 can dynamically adjust the modulation frequency of the clock signal CK by repeatedly executing the workflow 600 to control a data line (such as data lines {DL ₁ , DL ₂ ,... , Any of DL _M }) charging time at different horizontal periods (or different frame periods) tends to be consistent, in particular, the timing controller 500 can dynamically adjust the clock signal by repeatedly performing the workflow 600 CK modulation frequency to control multiple display units (eg display unit {DU) coupled to any one of the data lines {DL ₁ , DL ₂ ,..., DL _M } (eg data line DL ₁ ) _1,1 ,DU _2,1 ,...,DU _N,1 }) The charging time or jitter amount at different horizontal periods (or different frame periods) tends to be the same, but the invention is not limited thereto.

FIG. 7 is an example of the modulation frequency adjustment result according to another embodiment of the present invention. It is assumed that the timing controller 500 generates a pulse wave on the signal TP every time a row of display units is charged. Therefore, the frequency of the signal TP can represent the horizontal line frequency of the display device 100, but the invention is not limited thereto. The frequency change curves MR_1, MR_2, and MR_3 of the clock signal CK can represent the frequency change of the clock signal CK at different modulation frequencies, please note that the signal TP shown in FIG. 7 is the signal size (for example: voltage value ) A schematic diagram of the change with time. The frequency change curves MR_1, MR_2 and MR_3 are schematic diagrams of the frequency of the clock signal CK changing with time. At that time, the modulation frequency of the pulse signal CK is smaller than the frequency of the signal TP (or the horizontal line frequency of the display device 100), as shown by the frequency change curve MR_2, or, when the modulation frequency of the pulse signal CK is lower than the frequency of the signal TP (or display The frequency of the horizontal line of the device 100 is large. As shown in the frequency change curve MR_3, the charging interval of the clock signal CK in the display unit of each column has a different average frequency, so that the charging time of the display unit in each column is inconsistent; The modulation frequency is equal to (or approaches) the frequency of the signal TP (or the horizontal line frequency of the display device 100). As shown in the frequency change curve MR_1, the charging interval of the clock signal CK in each row of display units can have the same ( (Or approximate) the average frequency, so that the display unit charging time of each column tends to be consistent; or, the modulation frequency of the pulse signal CK at that time is equal to (or approaches) the frequency of the signal TP (or the horizontal line frequency of the display device 100) Integer multiple (not shown separately in Figure 7 for simplicity), similarly, the charging interval of the clock signal CK in the display unit of each column may have the same (or approximate) average frequency, so that the The display unit charging time tends to be consistent, but the invention is not limited to this.

In summary, the present invention can selectively adjust the predetermined setting to control the number of cycles of the clock signal CK corresponding to the gate control signal on each scan line or the modulation frequency of the clock signal CK to control a data line at The charging time of different levels of cycles tends to be the same. In addition, implementation according to the related embodiments of the present invention does not add much extra cost, therefore, the problems of the related art can be solved, and the overall cost does not increase too much. Compared with the related art, the present invention can control the charging time of a data line at different levels in a period without side effects or less likely to cause side effects.

The above are only the preferred embodiments of the present invention, and all changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

200‧‧‧sequence controller

220‧‧‧ Spread Spectrum Clock Generator

240‧‧‧ detection circuit

260‧‧‧Comparison circuit

280‧‧‧Adjustment circuit

Claims (8)

A method for signal adjustment can be applied to a timing controller of a display device, the display device includes the timing controller, a plurality of data lines, a plurality of scan lines, and a plurality of display units, The method includes: detecting an overall average period of a clock signal, wherein the timing controller generates a plurality of control signals according to the clock signal to control the display device; and separately detecting the clock signal at the complex number The average period of the period in which the signal of each of the scan lines is in the activated state; comparing the average periods with the overall average period to generate the comparison results respectively; and adjusting the plural ones respectively according to the comparison results The predetermined setting of the scanning lines determines the pulse width of the gate control signals on the plurality of scanning lines, respectively, to control the charging time of a data line in different horizontal periods to be consistent, among which the pulse widths The predetermined settings corresponding to the plurality of scan lines respectively. The method as described in item 1 of the patent application scope, wherein the clock signal is a spread spectrum clock (SSC) signal, wherein the spread spectrum clock signal is obtained by modulating a fixed frequency clock signal It is the signal obtained when the frequency changes with time. The method as described in item 1 of the patent application scope, wherein the predetermined settings respectively indicate the number of cycles corresponding to the pulse widths of the gate control signals, wherein the number of cycles represents the number of the clock signal Number of cycles. The method as described in item 3 of the patent application scope, in which adjustments are made based on the comparison results The predetermined setting of the plurality of scan lines to respectively determine the pulse width of the gate control signal on the plurality of scan lines further includes: when a comparison result indicates that the average period of the period of the clock signal in one scan line is less than that If the overall average period is small, increase the period corresponding to the corresponding gate control signal; and when the comparison result indicates that the average period of the clock signal during the scan line period is greater than the overall average period, reduce the corresponding gate The number of cycles corresponding to the polar control signal. A timing controller of a display device, the display device includes the timing controller, a plurality of data lines, a plurality of scanning lines, and a plurality of display units, the timing controller includes: at least one detection circuit for detecting respectively An overall average period of the clock signal and an average period during a period when the signal of each of the plurality of scan lines is in an activated state; at least one comparison circuit is used to separately perform the average periods and the overall average period Comparison to generate comparison results respectively; and at least one adjustment circuit for adjusting the predetermined settings of the plurality of scan lines according to the comparison results to determine the pulse width of the gate control signal on the plurality of scan lines ( pulse width) to control the charging time of a data line in different horizontal periods to be consistent, wherein the pulse widths respectively correspond to the predetermined settings of the plurality of scan lines. The timing controller as described in item 5 of the patent application scope also includes a Spread Spectrum Clock (SSC) generator, which is used to generate a fixed frequency clock signal by changing the frequency with time. The clock signal obtained. The timing controller as described in item 5 of the patent application, wherein the predetermined settings indicate the number of cycles corresponding to the pulse widths of the gate control signals, wherein the number of cycles is divided Do not represent the number of multiple cycles of the clock signal. The timing controller as described in item 5 of the patent application scope, wherein: when a comparison result indicates that the average period of the clock signal during a scan line period is smaller than the overall average period, the at least one adjustment circuit increases a corresponding The number of cycles corresponding to the gate control signal; and when the comparison result indicates that the average period of the period of the clock signal in the scan line is greater than the overall average period, the at least one adjustment circuit reduces the corresponding gate control signal The corresponding number of cycles.

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