TWI683299B - Timing controller - Google Patents

Abstract

A timing controller is provided. The timing controller includes a bit capture circuit and a gear position signal generation circuit. The bit capture circuit is configured to capture a first part bits from each of a plurality of original sub-pixel data of a video stream. The gear position signal generation circuit determines a gear position signal related to a current frame according to the first part bits. The gear position signal is provided to a gamma voltage generating circuit of a source driver such that the gamma voltage generating circuit changes a plurality of gamma voltages according to the gear position signal.

Description

Timing controller

The present invention relates to a display device, and particularly to a timing controller.

With the advancement of electronic technology, consumer electronic products have become an essential tool in people's lives. In order to provide a good human-machine interface, it has also become a trend to configure high-quality display devices on consumer electronic products. Therefore, how to effectively reduce the number of bits of sub-pixel data received by the digital-to-analog converter (DAC) of the source driver will be a problem for those skilled in the art.

The invention provides a timing controller, which can effectively reduce the number of bits of sub-pixel data received by the digital-to-analog converter of the source driver.

The timing controller of the present invention includes a bit acquisition circuit and a gear signal generation circuit. The bit extraction circuit is used to extract the first part of bits from any one of the plurality of original sub-pixel data of the video stream. The gear signal generating circuit is coupled to the bit extraction circuit to receive the first part of the bit, and determines the gear signal related to the current frame according to the first part of the bit, wherein the gear signal is provided to the source The gamma voltage generating circuit of the driver enables the gamma voltage generating circuit to change a plurality of gamma voltages according to the gear signal.

Based on the above, the timing controllers described in the embodiments of the present invention can use the bit extraction circuit to extract the first part of the original sub-pixel data, and the gear signal generation circuit to use the first part The number of bits determines the gear signal sent to the gamma voltage generating circuit. The gamma voltage generating circuit can adjust the gamma voltage according to the gear signal. Based on the adjusted gamma voltage, the digital-to-analog converter transmits the source driving signal to the display panel.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below in conjunction with the accompanying drawings for detailed description as follows.

The term "coupling (or connection)" used in the entire specification of this case (including the scope of patent application) may refer to any direct or indirect connection means. For example, if it is described that the first device is coupled (or connected) to the second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be connected to another device or a certain device. Connection means indirectly connected to the second device. In addition, wherever possible, elements/components/steps using the same reference numbers in the drawings and embodiments represent the same or similar parts. Elements/components/steps that use the same reference numbers or use the same terminology in different embodiments may refer to related descriptions with each other.

FIG. 1 is a block diagram of a timing controller 100_1 according to an embodiment of the invention. Please refer to FIG. 1. In this embodiment, the timing controller 100_1 includes a bit extraction circuit 110 and a gear signal generation circuit 120. The bit extraction circuit 110 can extract the corresponding first partial bits PB1_1-PB1_N and the processed sub-pixel data SPD1~SPDN from the plurality of original sub-pixel data OSPD1~OSPDN of the video stream. In this embodiment, the processed sub-pixel data SPD1 to SPDN may be the second part of the original sub-pixel data OSPD1 to OSPDN. The number of bits of the first partial bits PB1_1~PB1_N and the number of bits of the processed sub-pixel data SPD1~SPDN can be determined according to design requirements. For example, taking the original sub-pixel data OSPD1 as an example, the first bit PB1_1 may be the two least significant bits (LSB) in the original sub-pixel data OSPD1, and the processed sub-pixel data SPD1 It can be the eight most significant bits (MSB) in the original subpixel data OSPD1. The rest of the original sub-pixel data can be deduced by analogy.

The gear signal generating circuit 120 is coupled to the bit extraction circuit 110 to receive the first part of the bits PB1_1-PB1_N. The gear signal generating circuit 120 determines the gear signal GS related to the current frame according to these first partial bits PB1_1-PB1_N. The gear signal generating circuit 120 may provide the gear signal GS to the gamma voltage generating circuit 210 of the source driver 200.

On the other hand, the source driver 200 includes a gamma voltage generation circuit 210, a latch circuit 220, a digital-to-analog converter (DAC) 230_1~230_N, and output buffers 240_1~240_N. Here, the aforementioned N is a positive integer. The gamma voltage generating circuit 210 is coupled to the gear signal generating circuit 120 to receive the gear signal GS. The gamma voltage generating circuit 210 can provide and change a plurality of gamma voltages VG1-VGn according to the gear signal GS. The latch circuit 220 is coupled to the bit extraction circuit 110 to receive the processed sub-pixel data SPD1-SPDN. The latch circuit 220 can latch the processed sub-pixel data SPD1 to SPDN and provide the processed sub-pixel data SPD1 to SPDN to the digital analog converters 230_1 to 230_N, respectively.

The digital-to-analog converters 230_1-230_N are coupled between the latch circuit 220 and the output buffers 240_1-240_N. The digital-to-analog converters 230_1 ˜ 230_N are coupled to the gamma voltage generating circuit 210 to receive the gamma voltages VG1 ˜VGn. The digital-to-analog converters 230_1 ˜ 230_N respectively receive the processed sub-pixel data SPD1 ˜SPDN from the latch circuit 220. According to the gamma voltages VG1 ˜VGn, the digital analog converters 230_1 ˜ 230_N can respectively convert the corresponding processed sub-pixel data SPD1 ˜SPDN into source drive signals S1 SN. In addition, the digital-to-analog converters 230_1-230_N can transmit the source driving signals S1-SN to the corresponding data lines (or source lines) in the display panel 300 through the output buffers 240_1-240_N.

FIG. 2 is a circuit block diagram illustrating the gear signal generating circuit 120 shown in FIG. 1 according to an embodiment of the invention. Please refer to FIG. 1 and FIG. 2 at the same time. In this embodiment, the gear signal generating circuit 120 includes a plurality of counting circuits C1 ˜Cm and a gear determining circuit 121. The number m of the counting circuits C1 to Cm can be determined according to design requirements. The counting circuits C1 ˜Cm are coupled to the bit extraction circuit 110 to receive the first part of the bits PB1_1 PB1_N. It is worth mentioning that these counting circuits C1 to Cm can have different counting conditions, and each counting circuit C1 to Cm can be used to count the objects that meet the counting conditions in the first part of the bits PB1_1 to PB1_N To obtain the count value V1～Vm. The counting condition can be determined according to design requirements.

For example, in this embodiment, the counting condition of the counting circuit C1 may be "the content of the first bit is 00". That is, the counting circuit C1 is configured to count/count all the first part bits (including the first part bits PB1_1~PB1_N) in the same frame (frame), with the bit value "00" The first part of the number of bits, and provides the count result (count value V1) to the gear determination circuit 121. The counting condition of the counting circuit C2 may be "the content of the first bit is 01". That is, the counting circuit C2 is configured to count/count all the first part bits (including the first part bits PB1_1~PB1_N) of the same frame, with a bit value of "01" A part of the number of bits, and provides the count result (count value V2) to the gear determining circuit 121. The counting condition of the counting circuit C3 may be "the content of the first bit is 10". That is, the counting circuit C3 is configured to count/count all the first part bits (including the first part bits PB1_1~PB1_N) of the same frame, with a bit value of "10" A part of the number of bits, and provides the count result (count value V3) to the gear determining circuit 121. The counting condition of the counting circuit C4 may be "the content of the first part of the bit is 11". That is, the counting circuit C4 is configured to count/count all the first part bits (including the first part bits PB1_1~PB1_N) of the same frame, with the bit value of "11" A part of the number of bits, and provides the count result (count value V4) to the gear determination circuit 121.

According to design requirements, in some embodiments, the counting circuits C1 ˜Cm may include a plurality of group counting circuits (eg, group counting circuit C5 and group counting circuit C6 ). In such an embodiment, all the first partial bits (including the first partial bits PB1_1~PB1_N) in the same frame can be divided into multiple groups (eg, the first group GA and the second Group GB), and the count values V1 ˜Vm may include a plurality of group count values (eg, the first group count value V5 and the second group count value V6). The first group count value V5 can be expressed as the number of the first part of the first group GA, and the second group count value V6 can be expressed as the first part of the second group GB The number of copies.

For example, in this embodiment, the first bit data (for example, the bit value "00") is included in all the first bit bits (including the first bit bits PB1_1~PB1_N) of the same frame ) Or the second bit data (for example, the bit value "01") is classified as the first group GA. In addition, all the first bits (including the first bits PB1_1~PB1_N) of the same frame have the third bit data (for example, the bit value "10") or the fourth bit data (For example, the bit value "11") is classified as the second group GB. In any case, other embodiments of the present invention are not limited to this. The counting condition of the group counting circuit C5 may be "the content of the first part of the bit is 00 or 01". That is, the group counting circuit C5 is configured to count/count all the first bits (including the first bits PB1_1~PB1_N) in the same frame, with a bit value of "00" Or the number of the first part of "01", and provide the count result (the first group count value V5) to the gear determination circuit 121. The counting condition of the group counting circuit C6 may be "the content of the first bit is 10 or 11". That is, the group counting circuit C6 is configured to count/count all the first part bits (including the first part bits PB1_1~PB1_N) in the same frame, with a bit value of "10" Or the number of the first part of "11", and provide the count result (the second group count value V6) to the gear determination circuit 121.

On the other hand, the gear determining circuit 121 is coupled to the counting circuits C1 ˜Cm to receive these counting values V1 ˜Vm. The gear determining circuit 121 can determine the gear signal GS according to the count values V1 ˜Vm. In this embodiment, the gear determination circuit 121 may include a group selection unit 121a and a gear determination unit 121b. In any case, other embodiments of the present invention are not limited to this. The group selection unit 121a is coupled to the counting circuits C1 to Cm to receive the first group count value V5 and the second group count value V6. The group selection unit 121a may determine a selected group according to the first group count value V5 and the second group count value V6, and provide a selection result SG to indicate the selected group. In addition, the gear determination unit 121b is coupled to the group selection unit 121a to receive the selection result SG. The gear determining unit 121b may generate and determine the gear signal GS according to the selected group (selection result SG) and the count values V1˜Vm.

For example, when the group selection unit 121a determines that the difference between the first group count value V5 and the second group count value V6 is greater than the first threshold value VTH1, the group selection unit 121a may select the first group The group GA serves as the selected group, and provides the selection result SG related to the selected group to the gear determination unit 121b. In contrast, when the group selection unit 121a determines that the difference between the first group count value V5 and the second group count value V6 is less than the second threshold VTH2, the group selection unit 121a may select the second group GB serves as the selected group, and provides the selection result SG related to the selected group to the gear determination unit 121b. The first threshold VTH1 and the second threshold VTH2 can be determined according to design requirements. In some embodiments, the first threshold VTH1 is different from the second threshold VTH2, for example, the first threshold VTH1 is greater than the second threshold VTH2. In other embodiments, the first threshold VTH1 may be the same as the second threshold VTH2. It should be noted that when the difference between the first group count value V5 and the second group count value V6 of a current frame is neither greater than the first threshold value VTH1 nor less than the second threshold value VTH2, the group The group selection unit 121a may inherit the group selection result of the previous frame as the selected group of the current frame.

The gear determining unit 121b determines the gear signal GS according to the selected group indicated by the selection result SG and the count values V1 to Vm. For example, when the selection result SG indicates that the selected group is the first group GA, and the count value V1 related to the first bit data (eg, bit value "00") of the count values V1 to Vm and the counter When the difference between the count values V2 of the values V1 to Vm related to the second bit data (for example, the bit value "01") is greater than the third threshold VTH3, the gear determining unit 121b may select the first bit The candidate gear signal (for example, the bit value "00") corresponding to the metadata (for example, the bit value "00") is used as the gear signal GS. In contrast, when the selection result SG indicates that the selected group is the first group GA, and the count value V1 and the count value related to the first bit data (for example, the bit value "00") in the count values V1 to Vm When the difference between the count value V2 of the second bit data (for example, the bit value "01") in V1 to Vm is less than the fourth threshold VTH4, the gear determining unit 121b may select the second bit The candidate gear signal (eg, bit value "01") corresponding to the data (eg, bit value "01") is used as the gear signal GS. The third threshold VTH3 and the fourth threshold VTH4 can be determined according to design requirements.

On the other hand, when the selection result SG indicates that the selected group is the second group GB, and the count value V3 related to the third bit data (for example, the bit value "10") of the count values V1 to Vm and the counter When the difference between the count value V4 of the values V1 to Vm related to the fourth bit data (for example, the bit value "11") is greater than the fifth threshold VTH5, the gear determining unit 121b may select the third bit The candidate gear signal (eg, bit value “10”) corresponding to the metadata (eg, bit value “10”) is used as the gear signal GS. In contrast, when the selection result SG indicates that the selected group is the second group GB, and the count value V3 and the count value related to the third bit data (for example, the bit value "10") in the count values V1 to Vm When the difference between the count value V4 of the fourth bit data (for example, the bit value "11") in V1 to Vm is less than the sixth threshold value VTH6, the gear determining unit 121b may select the fourth bit The candidate gear signal (for example, bit value "11") corresponding to the data (for example, bit value "11") is used as the gear signal GS. The fifth threshold VTH5 and the sixth threshold VTH6 can be determined according to design requirements. In some embodiments, the third to sixth thresholds VTH3 to VTH6 are different from each other. In other embodiments, some (or all) of the threshold values VTH3 to VTH6 may be the same as each other. It should be noted that, when the result determined by the gear determining unit 121b is not the above four cases, the gear determining unit 121b may use the gear signal GS of the previous frame as the gear signal GS of the current frame.

The gamma voltage generating circuit 210 of the source driver 200 can correspondingly change the gamma voltages VG1 ˜VGn according to the gear signal GS provided by the gear signal generating circuit 120. The digital-to-analog converters 230_1~230_N can provide the source driving signals S1~SN according to the gamma voltages VG1~VGn and the processed sub-pixel data SPD1~SPDN. The source driving signals S1 to SN are transmitted to the data lines (or source lines) in the display panel 300 through the output buffers 240_1 to 240_N.

FIG. 3 is a schematic circuit block diagram of a timing controller 100_2 according to another embodiment of the invention. The timing controller 100_2 shown in FIG. 3 can supply the gear signal GS and the processed sub-pixel data SPD1 ˜SPDN to the source driver (for example, the source driver 200 shown in FIG. 1, which will not be repeated here). In the embodiment shown in FIG. 3, the timing controller 100_2 includes a bit extraction circuit 110, a gear signal generation circuit 120, and a bit adjustment circuit 130. The bit extraction circuit 110 and the gear signal generation circuit 120 shown in FIG. 3 can be analogized with reference to the related descriptions of FIG. 1 and FIG. 2, so they will not be repeated here. In the embodiment shown in FIG. 3, the bit adjustment circuit 130 is coupled to the gear signal generating circuit 120 to receive the gear signal GS. The bit adjustment circuit 130 can receive the second partial bits PB2_1~PB2_N in the original sub-pixel data OSPD1~OSPDN. The number of bits of the second partial bits PB2_1 ~ PB2_N can be determined according to design requirements. Taking the original sub-pixel data OSPD1 as an example, for example, the second partial bit PB2_1 may be the eight most significant bits (MSB) of the original sub-pixel data OSPD1. The rest of the original sub-pixel data can be deduced by analogy.

In this embodiment, the bit adjustment circuit 130 may determine whether to adjust the second part of any of the original sub-pixel data OSPD1 to OSPDN according to the gear signal GS, thereby obtaining a plurality of processed sub-pixel data SPD1 ~SPDN. In addition, the bit adjustment circuit 130 may provide the processed sub-pixel data SPD1 ˜SPDN to the latch circuit 220 of the source driver 200.

An example of the operation details of the bit adjustment circuit 130 is described below. When the bit value of the gear signal GS selected by the gear signal generating circuit 120 is the same as the first part of the current sub-pixel data in the original sub-pixel data OSBD1 to OSBDN (for example, two of the current sub-pixel data LSB), the bit adjustment circuit 130 may not adjust the second part of the current sub-pixel data (for example, the eight MSBs of the current sub-pixel data). In contrast, when the bit value of the gear signal GS selected by the gear signal generating circuit 120 is different from the bit value of the first part of the current sub-pixel data in the original sub-pixel data OSBD1 to OSBDN At this time, the bit adjustment circuit 130 may adjust (adjust up or down) or not adjust the second part of the current sub-pixel data.

For example, it is assumed here that the gear signal generation circuit 120 selects the first candidate gear signal corresponding to the first bit data (for example, the bit value “00”) or the second candidate corresponding to the second bit data The gear signal (for example, the bit value "01") is used as the gear signal GS. When the assumption is met, and when the first part of the current sub-pixel data in the original sub-pixel data OSBD1 to OSBDN is the first bit data (for example, the bit value "00 "), the second bit data (for example, bit value "01"), the third bit data (for example, bit value "10"), or the fourth bit data (for example, bit Bit value "11"), the bit adjustment circuit 130 may not adjust the second partial bit of the current sub-pixel data, that is, the second partial bit of the current sub-pixel data As the processed sub-pixel data corresponding to the current sub-pixel data (for example, one of the processed sub-pixel data SPD1 to SPDN).

In contrast, it is assumed here that the gear signal generation circuit 120 selects the third candidate gear signal corresponding to the third bit data (for example, the bit value “10”) or the fourth candidate file corresponding to the fourth bit data The bit signal (for example, the bit value "11") is used as the gear signal GS. When the assumption is met, and when the first part of the current sub-pixel data in the original sub-pixel data OSBD1 to OSBDN is the first bit data (for example, the bit value is "00" ) Or the second bit data (for example, the bit value "01"), then the bit adjustment circuit 130 can reduce the second part of the current sub-pixel data (for example, the The bit value of the two partial bits minus 1) to obtain the processed sub-pixel data corresponding to the current sub-pixel data. When the assumption is met, and when the first part of the current sub-pixel data in the original sub-pixel data OSBD1 to OSBDN is the third bit data (for example, the bit value " 10”) or the fourth bit data (for example, bit value “11”), the bit adjustment circuit 130 may not adjust the second part of the current sub-pixel data, which is The second partial bit of the current sub-pixel data is used as the processed sub-pixel data corresponding to the current sub-pixel data.

The operation details of the bit adjustment circuit 130 may not be limited to the above. In another embodiment, when the gear signal GS is "00" or "01", and when the first part of the current sub-pixel data in the original sub-pixel data OSBD1 to OSBDN is the first bit When describing the third bit data (for example, the bit value "10") or the fourth bit data (for example, the bit value "11"), the bit adjustment circuit 130 may increase the current sub-pixel The second partial bit of the data (for example, the bit value of the second partial bit of the current sub-pixel data is increased by 1) is used as the processed sub-pixel data corresponding to the current sub-pixel data. In other cases, the bit adjustment circuit 130 may not adjust the second partial bit of the current sub-pixel data, that is, use the second partial bit of the current sub-pixel data as the current The processed sub-pixel data corresponding to the sub-pixel data.

In yet another embodiment, when the gear signal GS is "00" or "01", and when the first part of the current sub-pixel data is the third bit data (for example, the bit value " 10”) or the fourth bit data (for example, the bit value “11”), the bit adjustment circuit 130 can increase the second part of the current sub-pixel data (for example, the The bit value of the second partial bit is increased by 1) as the processed sub-pixel data corresponding to the current sub-pixel data. When the gear signal GS is "10" or "11", and when the first part of the current sub-pixel data is the first bit data (for example, the bit value "00") or the first When the two-bit data (for example, the bit value is "01"), the bit adjustment circuit 130 can reduce the second part of the current sub-pixel data (for example, the second part The bit value of the bit minus 1) to obtain the processed sub-pixel data corresponding to the current sub-pixel data. In other cases, the bit adjustment circuit 130 may not adjust the second partial bit of the current sub-pixel data, that is, use the second partial bit of the current sub-pixel data as the current The processed sub-pixel data corresponding to the sub-pixel data.

FIG. 4 is a schematic block diagram of a timing controller 100_3 according to yet another embodiment of the present invention. The timing controller 100_3 shown in FIG. 4 can supply the gear signal GS and the processed sub-pixel data SPD1 to SPDN to the source driver (for example, the source driver 200 shown in FIG. 1, which will not be repeated here). In the embodiment shown in FIG. 4, the timing controller 100_3 includes a bit extraction circuit 110, a gear signal generation circuit 120 and an error diffusion circuit 140. The bit extraction circuit 110 and the gear signal generation circuit 120 shown in FIG. 4 can be analogized with reference to the related descriptions in FIG. 1 and FIG. 2, so they will not be repeated here. In the embodiment shown in FIG. 4, the error diffusion circuit 140 is coupled to the gear signal generating circuit 120 to receive the gear signal GS. The error diffusion circuit 140 further receives the original sub-pixel data OSPD1 to OSPDN. The error diffusion circuit 140 may adjust the original sub-pixel data of the current sub-pixel according to the error value related to at least one adjacent sub-pixel to obtain the processed sub-pixel data of the current sub-pixel.

Specifically, FIG. 5 is a schematic diagram illustrating a current sub-pixel and neighboring sub-pixels according to an embodiment of the invention. The embodiment shown in FIG. 5 illustrates the current sub-pixel Cur, adjacent sub-pixel Cur1, adjacent sub-pixel Cur2, adjacent sub-pixel Cur3 and adjacent sub-pixel Cur4. At present, the sub-pixel Cur and the adjacent sub-pixels Cur1 to Cur4 may have the same color (for example, red, green, or blue).

4 and 5, the error diffusion circuit 140 can calculate the gray scale error of each of the adjacent sub-pixels Cur1 ˜ Cur4. The grayscale error may be the difference between the original subpixel data of the neighboring subpixel and the new subpixel data of the neighboring subpixel. Wherein, the new sub-pixel data may be composed of the second part of the original sub-pixel data of the neighboring sub-pixel (for example, the eight MSBs of the original sub-pixel data) and the gear signal GS. For example, assuming that the gear signal GS of the current frame is "00" and the original subpixel data of the adjacent subpixel Cur4 is "1111 0101 11", the new subpixel data of the adjacent subpixel Cur4 is "1111 0101 00" ( That is, the composition of "1111 0101" and "00"), and the grayscale error of the adjacent sub-pixel Cur4 is the difference of "1111 0101 11" minus "1111 0101 00". The calculation of the grayscale errors of the remaining adjacent sub-pixels Cur1 to Cur3 can be inferred by referring to the description of the adjacent sub-pixel Cur4.

In the embodiment shown in FIG. 4, the error diffusion circuit 140 can adjust the current sub-pixel Cur according to an error value related to the adjacent sub-pixel of the current sub-pixel Cur, so as to obtain the processed sub-pixel data of the current sub-pixel Cur . Then, the error diffusion circuit 140 can transmit the processed sub-pixel data SPD1 ˜SPDN to the source driver 200. In some embodiments, the above-mentioned error value may be a weighted sum of gray-scale errors of these neighboring sub-pixels Cur1˜Cur4. It is worth mentioning that in these neighboring sub-pixels Cur1 to Cur4, the weight of the neighboring sub-pixel closer to the current sub-pixel Cur is larger, and the weight of the neighboring sub-pixels farther away from the current sub-pixel Cur is smaller, but the present invention The other embodiments are not limited to this.

For example, assume that the second part of the original sub-pixel data of the current sub-pixel Cur (such as the eight MSBs of the original sub-pixel data) is D0, and the grayscale errors and weights of the adjacent sub-pixel Cur1 are D1 and W1; The grayscale error and weight of the adjacent sub-pixel Cur2 are D2 and W2; the grayscale error and weight of the adjacent sub-pixel Cur3 are D3 and W3; and the grayscale error and weight of the adjacent sub-pixel Cur4 are D4 and W4, then the current subpixel Cur's processed sub-pixel data SPD = D0 + D1*W1 + D2*W2 + D3*W3 + D4*W4. Wherein, "D1*W1 + D2*W2 + D3*W3 + D4*W4" can be regarded as the error value related to the at least one adjacent sub-pixel. The weights W1 to W4 can be determined according to design requirements. For example (but not limited to), the weight W1 may be 7/16, the weight W2 may be 5/16, the weight W3 may be 3/16, and the weight W4 may be 1/16.

FIG. 6 is a schematic circuit block diagram of a timing controller 100_4 according to another embodiment of the invention. The timing controller 100_4 shown in FIG. 6 can supply the gear signal GS and the processed sub-pixel data SPD1 ˜SPDN to the source driver (for example, the source driver 200 shown in FIG. 1, which will not be repeated here). In the embodiment shown in FIG. 6, the timing controller 100_4 includes a bit extraction circuit 110, a gear signal generation circuit 120, a bit adjustment circuit 130, and an error diffusion circuit 140. The bit extraction circuit 110 and the gear signal generation circuit 120 shown in FIG. 6 can be analogized by referring to the related descriptions of FIG. 1 and FIG. 2, so they will not be repeated here.

The bit adjustment circuit 130 shown in FIG. 6 can be deduced by analogy with reference to the related description of FIG. In the embodiment shown in FIG. 6, the "processed sub-pixel data SPD1~SPDN" originally output from the bit adjustment circuit 130 shown in FIG. 3 is used as the "temporary data TA1~TAN" shown in FIG. The bit adjustment circuit 130 shown in FIG. 6 can determine whether to adjust the second partial bits PB2_1~PB2_N in each of the original sub-pixel data OSPD1~OSPDN according to the gear signal GS to obtain a plurality of temporary data TA1~TAN.

The error diffusion circuit 140 shown in FIG. 6 can be inferred by referring to the related descriptions of FIG. 4 and FIG. 5. The error diffusion circuit 140 shown in FIG. 6 is coupled to the bit adjustment circuit 130 to receive the temporary data TA1 TAN. In addition, the error diffusion circuit 140 shown in FIG. 6 further receives the original sub-pixel data OSPD1 to OSPDN.

The error diffusion circuit 140 shown in FIG. 6 can adjust the current sub-pixel according to the error values related to the multiple adjacent sub-pixels of the current sub-pixel (such as the adjacent sub-pixels Cur1 to Cur4 shown in FIG. 5) 5 present temporary data of the current sub-pixel Cur) to obtain the processed sub-pixel data. For example, assume that the temporary data of the current sub-pixel Cur is TA; the gray-scale error and weight of the neighboring sub-pixel Cur1 are D1 and W1; the gray-scale error and weight of the neighboring sub-pixel Cur2 are D2 and W2; the neighboring sub-pixel The grayscale errors and weights of Cur3 are D3 and W3; and the grayscale errors and weights of adjacent subpixels Cur4 are D4 and W4, then the processed subpixel data SPD of the current subpixel Cur = TA + D1*W1 + D2*W2 + D3*W3 + D4*W4. The error diffusion circuit 140 shown in FIG. 6 can be analogized with reference to the relevant descriptions in FIG. 4 and FIG.

FIG. 7 is a schematic block diagram of the gamma voltage generating circuit 210 shown in FIG. 1 according to an embodiment of the invention. 1 and 7, the gamma voltage generating circuit 210 includes resistor strings RS1 ˜RSn, multiplexers MUX1 ˜MUXn, and buffers BUF1 ˜BUFn. Wherein, each of the resistor strings RS1 to RSn may be composed of a plurality of resistors connected in series with each other. The resistor strings RS1 to RSn are connected in series to provide a divided voltage. In this embodiment, the multiplexers MUX1 to MUXn are coupled to the gear signal generating circuit 120 to receive the gear signal GS. The multiple input terminals of each of the multiplexers MUX1 to MUXn are respectively coupled to different voltage dividing nodes of a corresponding electric string in the electric strings RS1 to RSn, as shown in FIG. 7. Each of the multiplexers MUX1 to MUXn can select a corresponding divided voltage from the plurality of divided voltages of the corresponding electrical string according to the gear signal GS as one of the gamma voltages VG1 to VGn Voltage. The output terminals of these multiplexers MUX1 to MUXn can provide gamma voltages VG1 to VGn to the input terminals of the buffers BUF1 to BUFn.

On the other hand, the buffers BUF1 to BUFn are respectively coupled to the output terminals of the multiplexers MUX1 to MUXn to receive the corresponding gamma voltages VG1 to VGn. The output terminals of the buffers BUF1˜BUFn are coupled to the reference voltage input terminals of the digital analog converters 230_1˜230_N, so as to provide the gamma voltages VG1˜VGn. In addition, each of the digital-to-analog converters 230_1-230_N can generate the source driving signals S1-SN according to the processed sub-pixel data SPD1-SPDN and the gamma voltages VG1-VGn provided by the latch circuit 220, respectively.

8 is a flowchart of an operation method of a timing controller according to an embodiment of the invention. Please refer to FIG. 1 and FIG. 8 at the same time. In step S810, the timing controller 100_1 can extract the first part from any one of the plurality of original sub-pixel data OSPD1 to OSPDN of a video stream by the bit extraction circuit 110. Copy bits PB1_1～PB1_N. In step S820, the timing controller 100_1 can determine the gear signal GS related to a current frame by the gear signal generating circuit 120 according to these first partial bits PB1_1-PB1_N. In step S830, the timing controller 100_1 can provide the gear signal GS to the gamma voltage generating circuit 210 of the source driver 200 through the gear signal generating circuit 120, so that the gamma voltage generating circuit 210 is based on the gear signal GS Multiple gamma voltages VG1 to VGn are changed. The implementation details of each step are described in detail in the foregoing embodiments and implementations, and will not be repeated here.

In summary, the timing controllers described in the embodiments of the present invention can use the bit extraction circuit 110 to capture the first part of the original sub-pixel data, and the gear signal generation circuit 120 to The first part of the bits is used to determine the gear signal GS transmitted to the gamma voltage generating circuit 210. The gamma voltage generating circuit can adjust the gamma voltages VG1 to VGn according to the gear signal GS. The digital-to-analog converter can convert the processed sub-pixel data into source driving signals according to the adjusted gamma voltages VG1˜VGn, and transmit the source driving signals to the display panel. In this way, the number of bits of the sub-pixel data received by the digital-to-analog converter can be effectively reduced, thereby improving the quality of the display image.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

100_1～100_4‧‧‧sequence controller 110‧‧‧bit extraction circuit 120‧‧‧ gear signal generation circuit 130‧‧‧bit adjustment circuit 140‧‧‧ error diffusion circuit 200‧‧‧ source driver 210‧‧‧Gamma voltage generating circuit 220‧‧‧ latch circuit 230_1～230_N‧‧‧Digital analog converter 240_1～240_N‧‧‧Output buffer BUF1～BUFn‧‧‧Buffer 121‧‧‧Gear determination circuit 121a‧‧‧Group selection unit 121b‧‧‧ gear determination unit 300‧‧‧Display panel C1～Cm‧‧‧Counter circuit CSP‧‧‧Current sub-pixel GS‧‧‧ gear signal MUX1～MUXn‧‧‧multiplexer OSPD1～OSPDN‧‧‧ Raw sub-pixel data PB1_1～PB1_N, PB2_1～PB2_N SPD1～SPDN‧‧‧ processed sub-pixel data S1～SN‧‧‧Source drive signal SG‧‧‧Select result TA1～TAN‧‧‧Temporary information RS1～RSn‧‧‧resistor string V1～Vm‧‧‧Counting value VG1～VGn‧‧‧Gamma voltage S810～S830‧‧‧Step

FIG. 1 is a schematic diagram of a circuit block of a timing controller according to an embodiment of the invention. FIG. 2 is a circuit block diagram illustrating the gear signal generating circuit shown in FIG. 1 according to an embodiment of the invention. FIG. 3 is a circuit block diagram of a timing controller according to another embodiment of the invention. 4 is a schematic circuit block diagram of a timing controller according to yet another embodiment of the invention. FIG. 5 is a schematic diagram illustrating a current sub-pixel and neighboring sub-pixels according to an embodiment of the invention. 6 is a schematic circuit block diagram of a timing controller according to another embodiment of the invention. 7 is a schematic block diagram of a gamma voltage generating circuit shown in FIG. 1 according to an embodiment of the invention. 8 is a flowchart of an operation method of a timing controller according to an embodiment of the invention.

100_1‧‧‧sequence controller

110‧‧‧bit extraction circuit

120‧‧‧ gear signal generation circuit

200‧‧‧ source driver

210‧‧‧Gamma voltage generating circuit

220‧‧‧ latch circuit

230_1~230_N‧‧‧Digital analog converter

240_1~240_N‧‧‧Output buffer

300‧‧‧Display panel

GS‧‧‧ gear signal

OSPD1~OSPDN‧‧‧ Raw sub-pixel data

PB1_1~PB1_N‧‧‧Partial bits

SPD1~SPDN‧‧‧ processed sub-pixel data

S1~SN‧‧‧Source drive signal

VG1~VGn‧‧‧Gamma voltage

Claims (10)

A timing controller, including: a bit extraction circuit for extracting a first part of bits from any one of a plurality of original sub-pixel data of a video stream; and a gear signal generation circuit, coupled Connected to the bit extraction circuit to receive the first partial bits and determine a gear signal related to a current frame according to the first partial bits, wherein the gear signal is provided to A gamma voltage generating circuit of a source driver, so that the gamma voltage generating circuit changes a plurality of gamma voltages according to the gear signal. The timing controller as described in item 1 of the patent application scope, wherein the gear signal generating circuit includes: a plurality of counting circuits coupled to the bit extraction circuit, wherein the counting circuits each have different counting conditions, Any one of the counting circuits is used to count the number of the first partial bits that meet the counting condition to obtain a count value; and a gear determining circuit, coupled to the counting circuits to receive the counting circuits The count value is used to determine the gear signal according to the count values. The timing controller according to item 2 of the patent application scope, wherein the first partial bits are divided into a plurality of groups, the count values include a plurality of group count values, and the group count values Any one is the number of the first partial bits in a corresponding group of the groups, and the gear determination circuit includes: a group selection unit coupled to the counting circuits to receive the The group count values are used to determine a selected group based on the group count values; and a gear determination unit is coupled to the group selection unit to determine the selected group and the counts The value determines the gear signal. The timing controller of claim 3, wherein the groups include a first group and a second group, and the group count values include a first group count value and a second group Group count value, wherein, when the difference between the first group count value and the second group count value is greater than a first threshold value, the group selection unit selects the first group as the economy Select a group, wherein, when the difference between the first group count value and the second group count value is less than a second threshold, the group selection unit selects the second group as the selected Group. The timing controller according to item 4 of the patent application scope, wherein the first partial bits belonging to the first group include a first bit data and a second bit data, belonging to the second group The first partial bits of the group include a third bit data and a fourth bit data, wherein, when the selected group is the first group, and the count values are related to the first When the difference between a count value of one bit data and a count value related to the second bit data among the count values is greater than a third critical value, the gear determining unit selects the first bit A candidate gear signal corresponding to the data is used as the gear signal, wherein, when the selected group is the first group, and the count values related to the first bit data among the count values and the When the difference between the count values related to the second bit data among the count values is less than a fourth threshold, the gear determining unit selects a candidate gear corresponding to the second bit data The signal is used as the gear signal, wherein, when the selected group is the second group, and a count value related to the third bit data among the count values and a count value related to the When the difference between a count value of the four-bit data is greater than a fifth critical value, the gear determining unit selects a candidate gear signal corresponding to the third-bit data as the gear signal, and When the selected group is the second group, and the count value related to the third bit data among the count values and the count value related to the fourth bit data among the count values When the difference between them is less than a sixth critical value, the gear determining unit selects a candidate gear signal corresponding to the fourth bit data as the gear signal. The timing controller as described in item 1 of the patent application scope further includes: a bit adjustment circuit, coupled to the gear signal generating circuit to receive the gear signal, and used to determine whether to adjust according to the gear signal A second partial bit of any one of the original sub-pixel data obtains a plurality of processed sub-pixel data, wherein the processed sub-pixel data is provided to the source driver. The timing controller as described in item 6 of the patent application scope, wherein the first partial bits include a first bit data, a second bit data, a third bit data and a fourth bit Data, wherein, when the gear signal generation circuit selects a first candidate gear signal corresponding to the first bit data as the gear signal, and when a current sub-pixel data in the original sub-pixel data When the first partial bit is the first bit data, the bit adjustment circuit uses a second partial bit of the current sub-pixel data as the processed sub-pixel data corresponding to the current sub-pixel data ; And when the gear signal generation circuit selects the first candidate gear signal corresponding to the first bit data as the gear signal, and when the current sub-pixel data in the original sub-pixel data is the When the first part of the bit is the third bit of data, the bit adjustment circuit increases or decreases the second part of the current sub-pixel data to obtain the current corresponding to the current sub-pixel data Processing sub-pixel data. The timing controller as described in item 1 of the patent application scope further includes: an error diffusion circuit, coupled to the gear signal generating circuit to receive the gear signal, to be based on at least one neighboring sub-pixel of a current sub-pixel An error value associated with the pixel adjusts the original sub-pixel data of the current sub-pixel to obtain a processed sub-pixel data of the current sub-pixel, where the processed sub-pixel data is provided to the source driver. The timing controller according to item 8 of the patent application range, wherein the at least one adjacent sub-pixel includes a plurality of adjacent sub-pixels, each of the adjacent sub-pixels has a gray-scale error, and the gray-scale error is the The difference between the original sub-pixel data of the adjacent sub-pixel and a new sub-pixel data of the adjacent sub-pixel, the new sub-pixel data consists of a second part of the original sub-pixel data of the adjacent sub-pixel Element and the gear signal, and the error value is a weighted sum of the gray-scale errors. The timing controller as described in item 1 of the patent application scope further includes: a bit adjustment circuit, coupled to the gear signal generating circuit to receive the gear signal, and used to determine whether to adjust according to the gear signal A second partial bit of any of the original sub-pixel data to obtain a plurality of temporary data; and an error diffusion circuit coupled to the gear signal generating circuit to receive the gear signal and coupled to The bit adjustment circuit receives the temporary data, wherein the error diffusion circuit is used to adjust the temporary data of the current sub-pixel according to an error value associated with at least one adjacent sub-pixel of a current sub-pixel to obtain the current A processed sub-pixel data of the sub-pixel, wherein the processed sub-pixel data is provided to the source driver.

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