TWI683254B - Server power saving system and power saving method thereof - Google Patents

Abstract

This invention provides a server power saving system, the server power saving system comprises a main board and a backplane, and the main board is electrically connected with the back board. The main board includes a complex programmable logic device, a basic input/output control chip, and a clock chip. The basic input/output control chip stores a basic input/output control program. The clock chip is electrically connected to the complex programmable logic device. The backplane includes a hard disk microcontroller and a hard disk port. When a hard disk is electrically connected with the hard disk port, the hard disk microcontroller sends a clock enable signal to the complex programmable logic device, and the complex programmable logic device transmits the clock enable signal to the basic input/output control chip. The basic input/output control chip determines the clock enable signal to respond a confirmation signal to the complex programmable logic device, and the complex programmable logic device determines whether to drive the clock chip to send a clock signal to the hard disk port according to the content of the confirmation signal.

Description

Server power saving system and power saving method

The invention relates to a power-saving system and a method thereof, in particular to a server power-saving system and a power-saving method thereof.

Solid state disks (Solid State Disk) are emerging electronic products in the industry. Solid state disks mainly operate through FLASH chip particles, of which the cost of FLASH chip particles accounts for about 80% of SSDs. The biggest difference between a solid state drive and a traditional mechanical hard drive is that the solid state drive has no mechanical parts such as motors, heads, and discs, so that the read and write speed and response time of the solid state drive far exceed that of traditional mechanical hard drives. It has the advantages of fast speed, low noise, low power consumption, anti-collision, low weight and small size. At present, the capacity of mainstream solid state drives is 128G, and the price is about one thousand yuan. Therefore, the disadvantage of solid state drives is the higher price. However, with the continuous improvement of the FLASH process, the manufacturing cost of solid state drives will be relatively reduced Therefore, the demand for the application of solid state drives (SSD) is becoming more and more extensive,

At the same time, the interface types of solid-state drives are constantly evolving. At present, the most used interface for solid state drives is the PCIE bus interface with a speed of 8Gb/s. Therefore, non-volatile memory solid state drives (NVME SSDs) based on the PCIE bus routing have become the hard disk industry. Mainstream development trends. Generally speaking, each NVME SDD needs four lanes (lane) PCIE signal and 100M clock signal at the same time, making each NVME SDD power consumption up to 25W, but for some users, when there is no need to connect or When not using NVME SDD, how to save power consumption of the server becomes an important goal.

In view of this, there is currently a need for a power saving system that can reduce the overall power consumption of the server and a power saving method that can at least improve the above disadvantages.

According to an embodiment of the present invention, a server power saving system and a power saving method can determine whether to send a clock signal to the hard disk of the server backplane according to user needs, thereby reducing the overall power consumption of the server, To achieve the purpose of saving electricity.

The server power saving system provided by an embodiment of the present invention includes a motherboard and a backplane, wherein the motherboard includes a complex programmable logic device, a clock chip, and a basic input/output control chip. The complex programmable logic devices are respectively The clock chip is electrically connected to the basic input-output control chip, the clock chip is electrically connected to the backplane, and the basic input-output control chip stores the basic input-output control program. The backplane includes a hard disk microcontroller and a hard disk port. The hard disk microcontroller is electrically connected to a complex programmable logic device, and the hard disk port is electrically connected to the hard disk microcontroller. When the hard disk and the hard disk port are electrically connected, the hard disk microcontroller sends a clock enable signal to the complex programmable logic device, and the complex programmable logic device transmits the clock enable signal to the basic input and output control chip. The basic input and output control chip determines the clock enable signal in response to the confirmation signal to the complex programmable logic device. The complex programmable logic device determines whether to drive the clock chip to send the clock signal to the hard disk port based on the content of the confirmation signal.

The main board includes a main board bus, and the back board includes a back board bus. The main board bus is electrically connected to the back board bus and the complex programmable logic device. The back board bus is electrically connected to the hard disk drive. Controller and hard disk port. The hard disk microcontroller transmits the clock enable signal to the complex programmable logic device via the backplane bus and the motherboard bus.

A server power saving system provided by an embodiment of the present invention includes: when a hard disk is electrically connected to a hard disk port, a hard disk microcontroller sends a clock enable signal to a complex programmable logic device; The program logic device transmits the clock enable signal to the basic input and output control chip; the basic input input control chip determines the clock enable signal in response to the confirmation signal to the complex programmable logic device; and the complex programmable logic device is based on the confirmation signal The content determines whether to drive the clock chip to send the clock signal to the hard disk port.

In the past, the CLK enable signal was directly sent to the enable pin of the CLK buffer. Therefore, whether the CLK output is completely determined by the input CLK buffer The clock enable signal has nothing to do with the BIOS of the motherboard, which means that the user cannot control whether the CLK is turned off or not through the BIOS. According to the server power saving system and the power saving method provided by an embodiment of the present invention, with a small change in the hardware structure of the server, the user can control whether the clock chip is controlled by the basic input output control program (BIOS) Send the clock signal to the hard disk port on the back panel, thereby reducing the power consumption caused by the hard disk to the entire server. It is also very easy for users to manage, so it can meet the diverse needs of users.

The above description of the disclosure and the following description of the embodiments are used to demonstrate and explain the spirit and principle of the present invention, and provide a further explanation of the scope of the patent application of the present invention.

The following describes in detail the detailed features and advantages of the present invention in the embodiments. The content is sufficient for any person skilled in the relevant art to understand and implement the technical content of the present invention, and according to the contents disclosed in this specification, the scope of patent application and the drawings Anyone skilled in the relevant art can easily understand the purpose and advantages of the present invention. The following examples further illustrate the views of the present invention in detail, but do not limit the scope of the present invention in any way.

信號、第二

信號以及時脈訊號CLK。於本實施例中，所述PCIE匯流排為八通道規格的匯流排(PCIE-X8)。 FIG. 1 is a schematic diagram illustrating a hardware device of a server power saving system according to a first embodiment of the present invention. As shown in FIG. 1, the server power saving system 100 includes a backplane 10 and a motherboard 20. The backplane 10 may include a set or a plurality of PCIE (PCI Express) backplane bus bars. In the embodiment of FIG. 1, the backplane 10 includes a set of backplane bus bars 11, and the backplane bus bar 11 includes There is a first PCIE bus 111 and a second PCIE bus 112. The first PCIE bus 111 and the second PCIE bus 112 of the backplane 10 are used to receive the first PCIE bus from the motherboard 20

Signal, second

Signal and clock signal CLK. In this embodiment, the PCIE bus is an eight-channel bus (PCIE-X8).

信號與第二

信號，其中第一

信號用於控制PIC控制器的RST指令，而第二

信號來進行點燈(lighting instruction)與

信號解碼。在本實施例中，第一記憶元件14為非揮發性記憶體(NVRAM) 且用於對來自主機板20的第一

信號與第二

信號內所包含的資料作暫存的管理，第一記憶元件14除了電性連接第一硬碟微控制器12及第一信號處理器13，更電性連接於第一PCIE匯流排111。在本實施例中，第二硬碟微控制器15為PIC控制器，第二硬碟微控制器15電性連接於第二PCIE匯流排112、第二信號處理器16與第二記憶元件17，且第二硬碟微控制器15用以產生時脈致能訊號。第二信號處理器16除了電性連接第二硬碟微控制器15，更電性連接於第二PCIE匯流排112、第二記憶元件17及背板硬碟連接埠18，且第二信號處理器16用以處理第一

信號與第二

信號。在本實施例中，第二記憶元件17為非揮發性記憶體(NVRAM) 且用於對來自主機板20的第一

信號與第二

信號內所包含的資料作暫存的管理，第二記憶元件17除了電性連接第二硬碟微控制器15及第二信號處理器16，更電性連接於第二PCIE匯流排112。背板硬碟連接埠18包含有第一硬碟連接埠181、第二硬碟連接埠182、第三硬碟連接埠183以及第四硬碟連接埠184，第一硬碟連接埠181與第二硬碟連接埠182電性連接於第一信號處理器13，而第三硬碟連接埠183與第四硬碟連接埠184電性連接於第二信號處理器16。 As shown in FIG. 1, the backplane 10 further includes a first hard disk microcontroller 12, a first signal processor 13, a first memory element 14, a second hard disk microcontroller 15, and a second signal A processor 16, a second memory element 17, and a set of backplane hard disk ports 18 are provided. In this embodiment, the first hard disk microcontroller 12 is a PIC controller. The first hard disk microcontroller 12 is electrically connected to the first PCIE bus 111, the first signal processor 13 and the first memory element 14 , And the first hard disk microcontroller 12 is used to generate a clock enable signal. The first signal processor 13 is not only electrically connected to the first hard disk microcontroller 12, but also electrically connected to the first PCIE bus 111, the first memory element 14 and the backplane hard disk port 18, and the first signal processing 13 is used to process the first

Signal and second

Signal, where the first

The signal is used to control the RST command of the PIC controller, while the second

Signal for lighting instruction and

Signal decoding. In this embodiment, the first memory element 14 is non-volatile memory (NVRAM) and is used to

Signal and second

The data contained in the signal is used for temporary storage management. The first memory element 14 is electrically connected to the first PCIE bus 111 in addition to the first hard disk microcontroller 12 and the first signal processor 13. In this embodiment, the second hard disk microcontroller 15 is a PIC controller, and the second hard disk microcontroller 15 is electrically connected to the second PCIE bus 112, the second signal processor 16, and the second memory element 17 And the second hard disk microcontroller 15 is used to generate the clock enable signal. The second signal processor 16 is not only electrically connected to the second hard disk microcontroller 15 but also electrically connected to the second PCIE bus 112, the second memory element 17 and the backplane hard disk port 18, and the second signal processing 16 is used to process the first

Signal and second

signal. In this embodiment, the second memory element 17 is a non-volatile memory (NVRAM) and is used for the first memory from the motherboard 20

Signal and second

The data contained in the signal is temporarily stored. The second memory element 17 is electrically connected to the second PCIE bus 112 in addition to the second hard disk microcontroller 15 and the second signal processor 16. The backplane hard disk port 18 includes a first hard disk port 181, a second hard disk port 182, a third hard disk port 183, and a fourth hard disk port 184. The first hard disk port 181 and the first The second hard disk port 182 is electrically connected to the first signal processor 13, and the third hard disk port 183 and the fourth hard disk port 184 are electrically connected to the second signal processor 16.

FIG. 2 is a hardware architecture diagram of a motherboard of the server power saving system of FIG. 1. Referring to FIG. 1 and FIG. 2 together, the motherboard 20 may include a set or multiple arrays of PCIE-specific motherboard bus. In the embodiment of FIGS. 1 and 2, the motherboard 20 includes a set of motherboard bus 21, A baseboard management controller 22, a complex programmable logic device 23, a clock chip 24, a basic input output system chip 25, and a central processing unit (CPU). The motherboard bus 21 includes a third PCIE bus 211 and a fourth PCIE bus 212, the third PCIE bus 211 of the motherboard 20 is electrically connected to the first PCIE bus 111 of the backplane 10, and the motherboard 20 The fourth PCIE bus 212 is electrically connected to the second PCIE bus 112 of the backplane 10. The complex programmable logic device 23 is electrically connected to the third PCIE bus 211 and the fourth PCIE bus 212. The complex programmable logic device 23 has a first general-purpose input-output pin 231 (GPIO), the board management controller 22 has a second general-purpose input-output pin 221, the first general-purpose input-output pin 231 and the second The universal input/output pin 221 is electrically connected. The clock chip 24 is electrically connected to the complex programmable logic device 23, the third PCIE bus 211, and the fourth PCIE bus 212. The basic input/output system chip 25 is electrically connected to the substrate management controller 22, and the substrate input/output system chip 25 stores a basic input/output control program (BIOS).

信號可經由複雜可程式邏輯裝置23傳送至第三PCIE匯流排211與第四PCIE匯流排212，接著第三PCIE匯流排211與第四PCIE匯流排212可將第一

信號分別傳送至第一PCIE匯流排111與第二PCIE匯流排112。最後，背板10的第一PCIE匯流排111與第二PCIE匯流排112可將第一

信號分別傳送至第一信號處理器13與第二信號處理器16以進行處理。 The first from the CPU of the motherboard 20

The signal can be transmitted to the third PCIE bus 211 and the fourth PCIE bus 212 via the complex programmable logic device 23, and then the third PCIE bus 211 and the fourth PCIE bus 212 can transfer the first

The signals are transmitted to the first PCIE bus 111 and the second PCIE bus 112, respectively. Finally, the first PCIE bus 111 and the second PCIE bus 112 of the backplane 10 can

The signals are respectively transmitted to the first signal processor 13 and the second signal processor 16 for processing.

信號亦可經由複雜可程式邏輯裝置23傳送至第三PCIE匯流排211與第四PCIE匯流排212，接著第三PCIE匯流排211與第四PCIE匯流排212可將第二

信號分別傳送至第一PCIE匯流排111與第二PCIE匯流排112。最後，背板10的第一PCIE匯流排111與第二PCIE匯流排112可將第二

信號分別傳送至第一信號處理器13與第二信號處理器16以進行處理。 As for the second from the baseboard management controller 22 of the motherboard 20

The signal can also be transmitted to the third PCIE bus 211 and the fourth PCIE bus 212 via the complex programmable logic device 23, and then the third PCIE bus 211 and the fourth PCIE bus 212 can transfer the second

The signals are transmitted to the first PCIE bus 111 and the second PCIE bus 112, respectively. Finally, the first PCIE bus 111 and the second PCIE bus 112 of the backplane 10 can connect the second

The signals are respectively transmitted to the first signal processor 13 and the second signal processor 16 for processing.

The clock signal (CLK) from the clock chip 24 can be transmitted to the first PCIE bus 111 and the second PCIE bus 112 via the third PCIE bus 211 and the fourth PCIE bus 212, respectively. Finally, the backplane 10 The first PCIE bus 111 and the second PCIE bus 112 can transmit the clock signal (CLK) to the first hard disk port 181, the second hard disk port 182, the third hard disk port 183, and the fourth Hard disk port 184.

FIG. 3 is a flowchart illustrating a power saving method of the server power saving system of FIG. 1. Referring to FIGS. 1 to 3 together, in step S301, when a solid state drive is electrically connected to the first hard disk port 181 of the backplane 10, the solid state drive sends a hard drive confirmation signal to the backplane 10 In the first hard disk microcontroller 12, the hard disk confirmation signal indicates that the first hard disk port 181 of the backplane 10 is electrically connected to a solid-state hard disk. In step S302, the first hard disk microcontroller 12 reads the hard disk confirmation signal to send the clock enable signal to the complex programmable logic device 23 on the motherboard 20, wherein the clock enable signals are electrically connected to each other The backplane bus 11 and the host bus 21 are transferred from the backplane 10 to the complex programmable logic device 23 on the mainboard 20. In step S303, the first universal input-output pin 231 of the complex programmable logic device 23 transmits the clock enable signal to the second universal input-output pin 221 of the substrate management controller 22. In step S304, the substrate management controller 22 transmits the clock enable signal to the basic input-output control chip 25. In step S305, the basic input/output control chip 25 determines the clock enable signal to execute the basic input/output control program (BIOS). In step S306, an operation interface (RBSU) of the basic input output control program (BIOS) is used to display an option for turning on the clock signal and turning off the clock signal. If the user chooses to turn on the clock signal from the operation interface (RBSU) When the option is selected, step S308 is executed; if the user selects the option to turn off the clock signal from the operation interface (RBSU), step S309 is executed.

In step S308, the basic input/output control chip 25 responds to the first confirmation signal to the complex programmable logic device 23, and then proceeds to step S310. In step S310, the complex programmable logic device 23 drives the clock chip 24 to send a clock signal to the first hard disk port 181 according to the first confirmation signal.

In step S309, the basic input/output control chip 25 responds to the second confirmation signal to the complex programmable logic device 23, and then proceeds to step S311. In step S311, the complex programmable logic device 23 does not drive the clock chip 24 to send the clock signal to the first hard disk port 181 according to the second confirmation signal.

In addition, in another embodiment of the present invention, when a solid state drive is electrically connected to the second hard drive port 182 of the backplane 10, the solid state drive sends a hard drive confirmation signal to the first A hard disk microcontroller 12, the hard disk confirmation signal indicates that the second hard disk port 182 of the backplane 10 is electrically connected to a solid state hard disk, and then the first hard disk microcontroller 12 reads the hard disk confirmation signal to send The pulse enable signal is sent to the complex programmable logic device 23 on the motherboard 20. In another embodiment of the present invention, when a solid state drive is electrically connected to the third hard drive port 183 or the fourth hard drive port 184 on the backplane 10, the solid state drive sends a hard drive confirmation signal to The second hard disk microcontroller 15, and after reading the hard disk confirmation signal, the second hard disk microcontroller 15 sends a clock enable signal (CLK En) to the second PCIE bus 112 on the backplane 10. Taking the solid state drive electrically connected to the third hard disk port 183 of the backplane 10 as an example, the second PCIE bus 112 of the backplane 10 and the fourth PCIE bus 212 of the motherboard 20 are electrically connected to each other , The second hard disk microcontroller 15 can send the clock enable signal to the complex programmable logic device 23 on the motherboard 20. The complex programmable logic device 23 transmits the clock enable signal to the second universal input-output pin 221 of the baseboard management controller 22 through the first universal input-output pin 231. The baseboard management controller 22 is used to transmit the clock enable signal to the basic input and output control chip 25. When the basic input and output control chip 25 judges the clock enable signal, the basic input and output control program (BIOS) is executed, and the basic input The operation interface (RBSU) of the output control program (BIOS) will have the option to turn on the clock signal and turn off the clock signal. When the user selects the open clock signal in the operation interface (RBSU), the basic input/output control chip 25 will respond to the first confirmation signal to the complex programmable logic device 23, and the complex programmable logic device 23 is driven according to the first confirmation signal The clock chip 24 sends a clock signal (CLK) to the third hard disk port 183. Conversely, when the user chooses to turn off the clock signal in the operation interface (RBSU), the basic input/output control chip 25 will respond to the second confirmation signal to the complex programmable logic device 23, which is based on the second confirmation signal The clock chip 24 will not be driven to send a clock signal (CLK) to the third hard disk port 183.

FIG. 4 is a schematic diagram illustrating a hardware device of a server power saving system according to a second embodiment of the present invention, and FIG. 5 is a hardware architecture diagram of a motherboard of the server power saving system of FIG. 4. The difference in hardware architecture between the server power saving system of the second embodiment of FIG. 4 and the server power saving system of the first embodiment of FIG. 1 is that the substrate management controller 22 on the motherboard 20 is replaced with a south bridge chipset 26. The Southbridge chipset 26 has a second general-purpose input-output pin 261. The complex programmable logic device 23 transmits the clock enable signal to the second general-purpose chip of the Southbridge chipset 26 through the first general-purpose input-output pin 231. Type I/O pin 261, Southbridge chipset 26 is used to transmit the clock enable signal to the basic input/output control chip 25.

6 is a flowchart illustrating a power saving method of the server power saving system of FIG. 4. The difference between the server power saving method of FIG. 6 and the server power saving method of FIG. 3 is that in step S603, the clock enable signal is sent to the south bridge by the first universal input/output pin 231 of the complex programmable logic device 23 The second universal input-output pin 261 of the chip set 26; and in step S604, the south bridge chip set 26 transmits the clock enable signal to the basic input-output control chip 25.

In the past, the CLK enable signal was directly sent to the enable pin of the CLK buffer. Therefore, whether the CLK output is completely determined by the input CLK buffer The clock enable signal has nothing to do with the BIOS of the motherboard, which means that the user cannot control whether the CLK is turned off or not through the BIOS. According to the server power saving system and the power saving method provided by an embodiment of the present invention, with a small change in the hardware structure of the server, the user can control whether the clock chip is controlled by the basic input output control program (BIOS) Send the clock signal to the hard disk port on the back panel, thereby reducing the power consumption caused by the hard disk to the entire server. It is also very easy for users to manage, so it can meet the diverse needs of users.

Although the present invention is disclosed as the foregoing embodiments, it is not intended to limit the present invention. Without departing from the spirit and scope of the present invention, all modifications and retouching are within the scope of patent protection of the present invention. For the protection scope defined by the present invention, please refer to the attached patent application scope.

100‧‧‧Server power saving system

10‧‧‧Backboard

11‧‧‧Backboard bus

111‧‧‧First PCIE bus

112‧‧‧Second PCIE bus

12‧‧‧ First Hard Disk Microcontroller

13‧‧‧ First signal processor

14‧‧‧ First memory element

15‧‧‧ Second Hard Disk Microcontroller

16‧‧‧Second signal processor

17‧‧‧Second memory element

181‧‧‧ First hard disk port

182‧‧‧ Second hard disk port

183‧‧‧ Third hard disk port

184‧‧‧ Fourth hard disk port

20‧‧‧Motherboard

21‧‧‧Motherboard bus

211‧‧‧The third PCIE bus

212‧‧‧ PCIE bus

22‧‧‧Baseboard management controller

221‧‧‧The second universal input and output pin

23‧‧‧ Complex programmable logic device

231‧‧‧The first universal input and output pin

24‧‧‧clock chip

25‧‧‧Basic input and output system chip

26‧‧‧Southbridge Chipset

261‧‧‧The second universal input and output pin

FIG. 1 is a hardware architecture diagram of a server power saving system according to a first embodiment of the invention. FIG. 2 is a hardware architecture diagram of a motherboard of the server power saving system of FIG. 1. FIG. 3 is a flowchart illustrating a power saving method of the server power saving system of FIG. 1. FIG. 4 is a schematic diagram illustrating a hardware device of a server power saving system according to a second embodiment of the invention. FIG. 5 is a hardware architecture diagram of a motherboard of the server power saving system of FIG. 4. 6 is a flowchart illustrating a power saving method of the server power saving system of FIG. 4.

100‧‧‧Server power saving system

10‧‧‧Backboard

11‧‧‧Backboard bus

111‧‧‧First PCIE bus

112‧‧‧Second PCIE bus

12‧‧‧ First Hard Disk Microcontroller

13‧‧‧ First signal processor

14‧‧‧ First memory element

15‧‧‧ Second Hard Disk Microcontroller

16‧‧‧Second signal processor

17‧‧‧Second memory element

181‧‧‧ First hard disk port

182‧‧‧ Second hard disk port

183‧‧‧ Third hard disk port

184‧‧‧ Fourth hard disk port

20‧‧‧Motherboard

21‧‧‧Motherboard bus

211‧‧‧The third PCIE bus

212‧‧‧ PCIE bus

22‧‧‧Baseboard management controller

221‧‧‧The second universal input and output pin

23‧‧‧ Complex programmable logic device

24‧‧‧clock chip

25‧‧‧Basic input and output system chip

CLK‧‧‧clock signal

Claims (10)

A server power-saving system includes: a motherboard including: a complex programmable logic device; a basic input and output control chip, electrically connected to the complex programmable logic device and storing a basic input and output control program; and a clock Chip, electrically connected to the complex programmable logic device; and a backplane, including: a hard disk microcontroller, electrically connected to the complex programmable logic device; and a hard disk connection port, electrically connected to the Hard disk microcontroller and the clock chip; when a hard disk is electrically connected to the hard disk port, the microcontroller sends a clock enable signal to the complex programmable logic device, the complex programmable logic device Transmitting the clock enable signal to the basic input-output control chip, the basic input-output control chip judges the clock enable signal to execute the basic input-output control program, and the basic input-output control program displays an open clock signal And the option to turn off the clock signal; when the option to turn on the clock signal is selected, the basic input and output control chip responds to a first confirmation signal to the complex programmable logic device, the complex programmable logic device is based on The first confirmation signal determines to drive the clock chip to send a clock signal to the hard disk port; when the option to turn off the clock signal is selected, the basic input output control chip responds to a second confirmation signal to the complex Program logic device, the complex programmable logic device decides not to drive the clock chip to send the clock signal to the hard disk port according to the second confirmation signal. The server power saving system according to claim 1, wherein the motherboard includes a motherboard bus, the backplane includes a backplane bus, the motherboard bus and the backplane bus, respectively, and the complex programmable The logic device is electrically connected, and the backplane bus is electrically connected to the hard disk microcontroller and the hard disk port, respectively, and the hard disk microcontroller communicates with the motherboard bus via the backplane bus The pulse enable signal is sent to the complex programmable logic device. The server power saving system according to claim 1, wherein the backplane further includes a signal processing circuit, the signal processing circuit is electrically connected to the backplane bus, the hard disk microcontroller and the hard disk port respectively . The server power saving system according to claim 1, wherein the motherboard further includes a chipset, and the chipset is electrically connected to the complex programmable logic device and the basic input/output control chip, respectively, the complex programmable logic device The clock enable signal is transmitted to the basic input and output control chip through the chip set. The server power saving system according to claim 4, wherein the complex programmable logic device has a first general-purpose input-output pin, and the chip set has a second general-purpose input-output pin, and the first general-purpose input The output pin is electrically connected to the second general-purpose input-output pin, and the complex programmable logic device transmits the clock enable signal to the second general-purpose type of the chipset through the first general-purpose input-output pin Input and output pins. The server power saving system according to claim 1, wherein the motherboard further includes a baseboard management controller, the baseboard management controller is electrically connected to the complex programmable logic device and the basic input output control chip, respectively, the complex The programmable logic device transmits the clock enable signal to the basic input and output control chip through the baseboard management controller. The server power saving system according to claim 6, wherein the complex programmable logic device has a first general-purpose input and output pin, and the baseboard management controller has a second general-purpose input and output pin, the first general-purpose type The input-output pin is electrically connected to the second general-purpose input-output pin, and the complex programmable logic device transmits the clock-enable signal to the first board-based management controller through the first general-purpose input-output pin. Two general-purpose input and output pins. A server power saving method includes: when a hard disk is electrically connected to a hard disk port, a hard disk microcontroller sends a clock enable signal to a complex programmable logic device; the complex programmable logic The device transmits the clock enable signal to a basic input and output control chip; the basic input and output control chip determines the clock enable signal to execute a basic input and output control program; the basic input and output control program displays an open time The option of the pulse signal and the option of a closed clock signal; when the option of the open clock signal is selected, the basic input and output control chip responds a first confirmation signal to the complex programmable logic device. The program logic device determines to drive the clock chip to send a clock signal to the hard disk port according to the first confirmation signal; and when the option of the off clock signal is selected, the basic input and output control chip responds to a second Confirm the signal to the complex programmable logic device, with the complex programmable logic device According to the second confirmation signal, it is decided not to drive the clock chip to send the clock signal to the hard disk port. The server power saving method as described in claim 8, wherein the complex programmable logic device transmits the clock enable signal to the basic input/output control chip further includes the complex programmable logic device transmitting the clock through a chipset Enable the signal to the basic input and output control chip. The server power saving method according to claim 8, wherein the complex programmable logic device transmits the clock enable signal to the basic input/output control chip and further includes the complex programmable logic device transmitting the Clock enable signal to the basic input and output control chip.

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