TWI680583B - Apparatus and methods of forming fin structures with asymmetric profile - Google Patents

Abstract

The embodiment includes a microelectronic device including a substrate including a protruding portion and a non-protruding portion, wherein a dielectric material is disposed adjacent to the protruding portion; an epitaxial sub-fin structure is disposed on the protruding portion. The bottom part of the epitaxial sub-fin structure includes an asymmetrical shape; and the epitaxial fin device structure is disposed on the sub-fin structure. Other embodiments are described herein.

Description

Device and forming method of fin structure with asymmetrical shape

The invention relates to a device and a method for forming a fin structure having an asymmetrical shape.

In microelectronic device applications, for example, it is highly desirable to integrate epitaxial materials such as indium aluminum phosphide on a substrate such as a silicon substrate. High-quality epitaxial materials enhance the performance of applications such as system-on-chip (SoC), high-voltage and RF devices, and complementary metal-oxide-silicon (CMOS) applications. This integration involves manufacturing challenges due to lattice property mismatches between the two materials.

100‧‧‧Microelectronic device

102‧‧‧ substrate

104‧‧‧fin

105‧‧‧ sidewall

105’‧‧‧second side wall

106‧‧‧ Dielectric Materials

106’‧‧‧ Dielectric material

107‧‧‧ top surface

108‧‧‧ removal

109‧‧‧ height

109’‧‧‧ height

110‧‧‧ isotropic etching

111‧‧‧fin part

112‧‧‧Asymmetric removal processing

113‧‧‧Epicrystalline Materials

114‧‧‧Epicrystalline Process

115‧‧‧Trench

116‧‧‧ height

117‧‧‧first side

117’‧‧‧ the second side

118‧‧‧ Top surface

119‧‧‧first height

119’‧‧‧ second height

121‧‧‧ first angle

122‧‧‧ second angle

126‧‧‧ surface

127‧‧‧Width

130‧‧‧ Sub-fin

131‧‧‧ side wall

131’‧‧‧ sidewall

132‧‧‧ fin device structure

133‧‧‧ height

200‧‧‧ multi-gate device

202‧‧‧ substrate

203‧‧‧ protrusion

206‧‧‧Isolation material

213‧‧‧Epicrystalline Materials

230‧‧‧ Sub-fin

231‧‧‧fin surface

232‧‧‧fin device structure

236‧‧‧Gate oxide

238‧‧‧Gate material

239‧‧‧Channel area

240‧‧‧Source / Drain Region

241‧‧‧wrapped gate structure

400‧‧‧ Mediator

402‧‧‧first substrate

404‧‧‧Second substrate

406‧‧‧ Ball grid array

408‧‧‧metal interconnect

410‧‧‧through hole

412‧‧‧Silicon Perforation

414‧‧‧ Embedded device

500‧‧‧ Computing Device

Although the specification summarizes the patent application scope of certain embodiments that are specifically pointed out and clearly claimed, it will be easier to confirm the advantages of these embodiments by reading the description of the following embodiments in conjunction with the drawings, of which: Figure 1a- 1i represents a cross-sectional view of a structure according to various embodiments.

2a-2c represent cross-sectional views of a structure according to an embodiment.

Figure 3 represents a flowchart of a method according to an embodiment.

FIG. 4 is a mediator implementing one or more embodiments.

FIG. 5 is a computing device built according to an embodiment.

[Summary and Implementation]

In the following detailed description, reference is made to the accompanying drawings that illustrate specific embodiments of implementation methods and structures by way of illustration. These embodiments are explained in sufficient detail to enable those skilled in the art to implement the embodiments. It should be understood that various embodiments, although different, are not necessarily mutually exclusive. For example, a specific feature, structure, or characteristic described in a document related to one embodiment may be implemented in other embodiments without departing from the spirit and scope of the embodiment. In addition, it should be understood that the position or configuration of each element in each disclosed embodiment can be modified without departing from the spirit and scope of the subject matter of the embodiments. In the drawings, like numbers refer to the same or similar functions throughout the several views.

Successively, the various operations are described as a plurality of separate operations in a manner that is most helpful in understanding the embodiments herein, but the order of description should not be interpreted to mean that the operations must be sequence dependent. In particular, these operations need not be performed in the order presented.

Implementation of the embodiments can be formed or performed on a substrate such as a semiconductor substrate. In one embodiment, the semiconductor substrate may be a crystalline substrate formed using bulk silicon or a silicon sub-structure on an insulator. In other implementations, alternative materials may be used to form the semiconductor substrate, and the alternative materials may be in contact with silicon. With or without bonding, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or Group III-V or Group IV Other combinations. Although some examples of materials that can form the substrate are described herein, any material that can be used as a basis for building a semiconductor device falls within the spirit and scope of the embodiments described herein.

A method for forming and utilizing a microelectronic structure and related structures, such as an epitaxial fin structure formed on a substrate, will be described. These methods / structures include forming an epitaxial fin structure provided on a protrusion of a substrate, wherein the protrusion includes a single-sided (111) facet of the protrusion of the substrate. (111) Facets are arranged along the length of the subfins. The asymmetry of the bottom portion of the sub-fin limits the epitaxial fin growth to a single growth leading edge, thus reducing defects.

1a-1i are cross-sectional views of an embodiment of forming a microelectronic structure. For example, the microelectronic structure may be an epitaxial fin structure disposed on a substrate, for example. In an embodiment, the microelectronic device 100 may include a substrate 102 (FIG. 1a). For example, in an embodiment, the substrate 102 may include a silicon substrate, and may be p-type doped with a p-type material / element such as boron. For example, in another embodiment, the substrate 102 may include circuit elements such as transistors and passive elements. In an embodiment, the substrate 102 may include a part of the CMOS substrate 102 and may include a p-type metal oxide semiconductor (PMOS) and an n-type metal oxide semiconductor (NMOS) transistor. In an embodiment, the microelectronic device 100 may include a tri-gate transistor, a surround-gate (GAA) transistor, or any other type of multi-gate transistor. In an embodiment, the microelectronic device 100 may include a portion of a compound (including a III-V material) transistor.

The fin 104, which may include silicon in one embodiment, may be disposed on the substrate 102. In other embodiments, the fins may include any other type of suitable material depending on the particular application. In an embodiment, the fins 104 may be oriented such that they are disposed orthogonally on the substrate 102. In an embodiment, the fin 104 may include the same material as the substrate 102, and in other embodiments, the fin 104 may include a different material from the substrate 102. In an embodiment, at least one fin 104 may be formed on the substrate 102, wherein the fin 104 may include opposite side walls 105 extending from the first surface 104 of the substrate 102 and terminating at the upper surface 107. In some embodiments, the upper surface 107 may include a curved profile, and, in other embodiments, it may include other shapes, such as a more rectangular profile. For the sake of brevity, only two fins 104 are shown in FIG. 1a; however, it should be understood that any suitable number of fins 104 can be made.

In an embodiment, an isolation material such as a dielectric material 106 may be formed on the fin 104 (FIG. 1b). The dielectric material 106 may include a material such as silicon dioxide, and, in some cases, a shallow trench isolation (STI) material, where the dielectric material 106 abuts the opposite fin sidewall 105. In an embodiment, the dielectric material 106 may include, for example, carbon-doped oxide (CDO), silicon nitride, silicon oxynitride, silicon carbide, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene. , Fluorosilicate glass (FSG), and / or materials such as silsesquioxane, siloxane, or organic silicate glass. In an embodiment, the dielectric material 106 may include multiple layers of different materials. In an embodiment, the dielectric material 106 may include a chemical vapor deposition (CVD) deposition material.

In an embodiment, a portion of the isolation material 106 may be removed by using a removal process 108 (FIG. 1 c) such as a chemical mechanical polishing (CMP) process. In an embodiment, a portion of the dielectric material 106 may be removed by using an oxide polishing removal process. For example, in other embodiments, other removal processes may be used, such as various wet and / or dry etch processes. In an embodiment, the top 107 of the fin 104 may be exposed after the removal process 108. Due to the fin profile 107, after the oxide removal process 108, an asymmetric oxide morphology will be created. The height 109 of the dielectric material 106 adjacent to the first sidewall 105 of the fin 104 is higher than that of the fin 104. The height 109 'of the second side wall 105' of the portion 104 is shorter.

In an embodiment, an isotropic etching process 110 may be performed, in which a part of the fin 104 may be removed (FIG. 1d). Since the etching process 110 is isotropic, in the embodiment, the crystal plane (facet) of the material without the specific fin 104 during the isotropic process 110 is better / exposed, and After the isotropic etching process 110 is performed, the shape of the fin portion 111 remaining isotropic includes a curved shape. In an embodiment, the isotropic etching process includes silicon etching, and may include such processes as plasma dry etching process using chlorine or SF6 plasma chemistry, or wet etching such as nitric acid / HF solution may be used Agent. In an embodiment, the adjacent dielectric material regions 106, 106 'that are in contact with the isotropically remaining fin portion 111 remain morphologically asymmetric, that is, the height of the first dielectric material 106 109 is shorter than the height 109 'of the adjacent dielectric material region 106'.

In an embodiment, an asymmetric removal process 112 may be performed, where The (111) facet of the remaining fin portion 103 is exposed (Fig. 1e). In an embodiment, for example, a wet etch such as a tetrapotassium hydroxide (TMAH) etchant and / or an etchant including ammonium hydroxide may be used to remove a portion of the fin structure 104, but Other dry and / or wet etch can also be used depending on the specific application. The asymmetrical remaining fin portion 103 may include a slanted, asymmetrical profile, and include an exposed single-sided main (111) facet. In an embodiment, the asymmetrical remaining fin portion 103 includes a protruding portion of the substrate 102, wherein the upper surface 118 of the protruding portion may include a single-sided (111) facet of the material of the fin 104. In an embodiment, the single-sided (111) facet of the upper surface 118 may include a single-sided silicon (111) facet. In the embodiment, the one-sided (111) facet of the upper surface 118 is arranged along the length of the fin device structure in the channel current direction, which will be described in more detail below. In an embodiment, the protrusion is a portion adjacent to the dielectric material 106.

In an embodiment, the opening 115 may be formed by removing a portion of the fin 104 structure. In an embodiment, the dielectric 106, 106 'sidewalls of the opening 115 may include unequal heights 116, 116'. In an embodiment, the bottom of the opening / groove 115 includes the upper surface 118 of the protruding portion 103 of the substrate 102, and includes a single-sided (111) facet. In an embodiment, the trench opening 115 may include an aspect ratio capture (ART) trench 115, wherein the ratio of the depth of the trench opening to the width of the trench 115 opening may include at least about 2: 1. In other embodiments, for example, the ratio may include 1.5, 1.7, 1.9, 2.1, 2.3, 2.5, 2.7.

In an embodiment, the protruding portion 103 of the substrate 102 may include a first side 117 and the second side 117 '. (See FIG. 1f. For simplicity, only the protruding portion 103 of the substrate 102 is shown). In an embodiment, the first and second sides 117, 117 'may include different heights 119, 119', wherein the first height 119 is shorter than the second height 119 '. In other embodiments, the first and second heights 119, 119 'may include substantially similar heights. In an embodiment, the protruding substrate 103 may include a first angle 121 relative to the substrate 102 and a second angle 123 relative to the substrate 102, wherein, in some embodiments, the first angle 121 may include about 120 degrees to About 130 degrees, and the second angle 123 may include about 85 degrees to about 95 degrees.

In an embodiment, the dielectric material 106 may be planarized (not shown), and an epitaxial material 113 may be formed in the opening 115 (FIG. 1g). In an embodiment, the epitaxial material 113 may include a III-V group epitaxial material 113, and the epitaxial material 113 may be formed in the trench opening 115 using any suitable epitaxial process 114. In an embodiment, the epitaxial material 113 may include any material including elements from Groups III, IV, and / or V of the periodic table, and combinations thereof. In an embodiment, the epitaxial material 113 may be grown using any suitable epitaxial process, and, in some embodiments, the epitaxial material 113 may include a width 127 between about 4 nm and about 80 nm.

In an embodiment, the epitaxial material 113 may include a group III-V material, such as gallium nitride, indium gallium nitride, indium phosphide, gallium arsenide, indium aluminum phosphide, indium gallium arsenide, gallium arsenide, arsenic At least one of indium and indium gallium nitride, germanium, and silicon germanium, and combinations thereof. In an embodiment, the epitaxial material 113 may include a plurality of epitaxial materials formed on each other, which may include multiple Heteroepitaxial layers, wherein the lattice constants of the different layers may be different from each other. In an embodiment, the epitaxial material 113 may include a multi-layer lattice mismatched epitaxial material. In an embodiment, the epitaxial material 113 may begin to grow on the (111) surface of the asymmetric protruding portion 103 of the substrate 102. In the embodiment, since the protruding portion 103 includes a single-sided (111) facet of the fin material, the epitaxial material 113 can grow from a single growth leading edge. Growth from a single growth leading edge is advantageous by avoiding multiple growth leading edges (e.g., when a V-shape is used at the bottom of a trench opening as in some conventional structures), which significantly reduces defects Formation.

In some embodiments, for example, a removal process 125 such as a CMP process may be used to remove an additional portion of the epitaxial material 113 disposed above the surface 126 of the isolation material 106 to become an isolation / intermediate The surface 126 of the electrical material 106 is also flat (FIG. 1h).

In an embodiment, a removal process 128 such as a CMP process may be used to recess a portion of the dielectric material 106, wherein the exposed portion of the epitaxial material 113 forms / includes at least one fin device structure 132 (FIG. 1i). In an embodiment, the fin device structure 132 may extend above the surface 126 of the dielectric material 106 and may include a height 133. In an embodiment, the height 125 of the fin device structure 132 is comprised between about 4 nm and about 80 nm. For example, in the embodiment, a portion of the fin device structure 132 includes a portion of a multi-gate device such as a channel region of the multi-gate device, and a source / drain region during subsequent processing Phase coupling.

In an embodiment, the epitaxial material 113 includes a first portion 130 disposed within a portion of the dielectric material 106, wherein the first portion 130 is It is placed on the protruding portion 103 of the substrate 102. The first portion 130 may include a sub-fin portion 130. In an embodiment, the sub-fin 130 may include side walls 131, 131 'of unequal heights. In an embodiment, the sub-fin 131 may be longer than the sub-fin 131 '. In an embodiment, the bottom portion of the sub-fin structure 130 may include an asymmetrical shape, wherein the bottom portion of the sub-fin structure 130 (directly disposed on the protruding portion 103 of the substrate 102) is because the sub-fin portion 130 The sidewalls 131, 131 'are inclined at unequal heights. In an embodiment, the ratio of the length of the sub-fin 130 to the width of the sub-fin 130 includes at least about 2: 1. The fin device structure 132 may include a second portion 132 of the epitaxial material 113. In an embodiment, the fin device structure 132 is directly disposed on the sub-fin structure 130, wherein the sub-fin structure is disposed under the surface 126 of the isolation material 106.

In an embodiment, a plurality of transistors such as a metal oxide semiconductor field effect transistor (MOSFET or MOS transistor for short) may be manufactured on the substrate 102, and generally may include an epitaxial material 113, and may include a fin装置 结构 132。 Device structure 132. In various implementations of the embodiment, the MOS transistor is a planar transistor, a non-planar transistor, or a combination of the two. Non-planar transistors include FinFET transistors such as double-gate transistors and triple-gate transistors, and wound or wrap-around gate (GAA) transistors such as nano-band and nano-wire transistors. Non-planar and / or planar transistors can be used to implement the embodiments herein.

Each MOS transistor including an epitaxial material / fin device structure may include a gate stack formed by at least two layers, such as a gate dielectric layer and a gate electrode layer. The gate dielectric layer may include a stack of one or more layers. The one or more layers may include silicon oxide, silicon dioxide (SiO ₂ ), and / or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, hafnium, niobium, and zinc. Examples of high-k materials that can be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, Titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead hafnium tantalum oxide, and lead zinc niobium oxide. In some embodiments, when a high-k material is used, an annealing process is performed on the gate dielectric layer to improve its quality.

The gate electrode layer is formed on the gate dielectric layer and is composed of at least one P-type work function metal or N-type work function metal depending on whether the transistor is to be a PMOS or NMOS transistor. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, wherein one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer.

For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides such as ruthenium oxide. The P-type metal layer will be able to form a PMOS gate electrode with a success function between about 4.9 eV and about 5.2 eV. For NMOS transistors, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and, for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide And aluminum carbides. The N-type metal layer will be able to form an NMOS gate electrode with a success function between about 3.9 eV and about 4.2 eV.

In some implementations, the gate electrode may consist of a "U" structure, and The "U" structure includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the upper surface of the substrate. In another implementation, the at least one metal layer forming the gate electrode may simply be a flat layer that is substantially parallel to the upper surface of the substrate and does not include a side wall portion substantially perpendicular to the upper surface of the substrate. In another implementation of the embodiment, the gate electrode may be composed of a combination of a U-shaped structure and a flat non-U-shaped structure. For example, the gate electrode may be composed of one or more U-shaped metal layers formed under one or more flat, non-U-shaped layers.

In some implementations of the embodiment, a pair of sidewall spacers may be formed on opposite sides surrounding the gate stack. The sidewall spacers may be formed of, for example, silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. The process used to form the sidewall spacer is a well-known technique and generally includes deposition and etching process steps. In alternative implementations, multiple spacer pairs may be used, for example, two or four pairs of sidewall spacers may be formed on opposite sides of the gate stack.

As is well known in the art, the source and drain regions are formed in the substrate, adjacent to the gate stack of each MOS transistor. Generally, a source / drain region is formed using a seeding / diffusion process or an etching / deposition process. In the foregoing process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be implanted into the substrate to form source and drain regions. The annealing process that activates the dopants and further diffuses them into the substrate typically follows an ion implantation process. In a later process, the substrate may be etched first to form a recess at the location of the source and drain regions.

An epitaxial deposition process can then be performed to make the source and drain regions Material to fill the recess. In some implementations, silicon alloys such as silicon germanium or silicon carbide can be used to make the source and drain regions. In some implementations, epitaxially deposited silicon alloys can be doped in-situ with dopants such as boron, arsenic, or phosphorus. In other embodiments, the source and drain regions may be formed using one or more alternative semiconductor materials such as germanium or a III-V material or alloy. And in other embodiments, one or more layers of metal and / or metal alloy may be used to form the source and drain regions.

One or more interlayer dielectrics (ILD) are deposited on the MOS transistor. The ILD layer may be formed using a known dielectric material, such as a low-k dielectric material, which has applicability in integrated circuit structures. Examples of usable dielectric materials include, but are not limited to, silicon dioxide (SiO ₂ ), carbon-doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, Fluorosilicate glass (FSG), and materials such as silsesquioxane, siloxane, or organic silicate glass. The ILD layer may contain pores or air gaps to further reduce their dielectric constant.

FIG. 2 a illustrates a cross-sectional view of a microelectronic device 200 including the device structure of the embodiment, such as a three-gate or other type of multi-gate device 200. In an embodiment, the epitaxial material 213 includes a first portion 230, and the first portion 230 may include a sub-fin disposed on a protruding portion 203 of the substrate 202 (for example, similar to the protruding portion of FIG. 1f).部 230。 230. In an embodiment, the first portion 230 includes sidewalls 231, 231 'of different heights. The protruding portion 230 includes a single-sided (111) facet extending along the length of the second portion 232 of the epitaxial material 213, wherein the second The portion 232 may include a fin device structure 232. In an embodiment, a part of the fin device structure 232 may include a part of the channel region of the multi-gate device, wherein the single-sided (111) facet may be configured along the direction of the channel current.

The gate oxide 236 may be disposed on the fin device structure 232 and on the surface 226 of the isolation material 206. The gate oxide 236 may include an oxide material such as a silicon dioxide material. In an embodiment, the gate oxide material includes a high-k dielectric material, wherein the dielectric material includes a dielectric constant greater than a dielectric constant of silicon dioxide.

For example, high-k dielectric materials may include hafnium oxide (HfO ₂ ), hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium dioxide (ZrO ₂ ), zirconium silicon oxide, titanium dioxide (TiO ₂ ), Tantalum pentoxide (Ta ₂ O ₅ ), barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead hafnium tantalum oxide, and lead zinc niobium oxide .

In an embodiment, the gate material 238 may be disposed on the gate oxide 236. In the embodiment, for example, the gate material includes, for example, titanium, tungsten, tantalum, aluminum, and alloys thereof, and alloys having rare earth elements such as ytterbium, rhenium, or noble metals such as platinum, and tantalum nitride, for example. And titanium nitride and other materials. In an embodiment, the fin device structure 232 may include a portion of a channel region having a gate oxide 236 and a gate material 238 disposed thereon.

FIG. 2b depicts a portion of a multi-gate transistor 200, in which a source / drain region 240 is coupled to a channel region 239 of a fin device structure 232. In an embodiment, the material for the source and / or drain may include, for example, silicon, carbon-doped silicon, and silicon-doped silicon for NMOS, boron-doped silicon germanium, Si _X Ge _{1- X} , boron-doped germanium, boron-doped germanium tin, Ge _X Sn _1-X , and p-doped III-V compounds for PMOS applications. In an embodiment, the gate oxide 236 is disposed on the channel region 239 of the fin device structure 232, and the gate material 238 is disposed on the gate oxide 236. The one-sided (111) facet (not shown) of the protruding portion of the substrate 203 is arranged along the direction of the channel 239.

Figure 2c depicts a wrap-around gate structure 241, which may include, for example, a nano-band and / or nano-wire structure. The gate oxide 236 may be disposed to surround (on all sides) the fin device structure 232 and to be disposed on the isolation material 206. The first portion of the epitaxial material 213 may be disposed below the fin device structure 232 and disposed on the substrate 202 and adjacent to the isolation material 206. In an embodiment, the first portion 230, which may include the sub-fin portion 230, includes sidewalls 231, 231 'having unequal heights. The protruding portion 203 of the substrate 202 includes a single-sided (111) facet extending along the length of the fin device structure 232. In an embodiment, a portion of the fin device structure 232 may include a portion of a channel region of a multi-gate device.

3 is a flowchart illustrating a method of forming an epitaxial fin structure on a substrate according to an embodiment. Block 302 includes a substrate. The substrate includes a protruding portion and a non-protruding portion. The dielectric material is disposed adjacent to the protruding portion. Block 304 includes an epitaxial fin structure provided on the protruding portion, wherein the bottom portion of the epitaxial fin structure includes an asymmetrical shape. Block 306 includes providing an epitaxial fin device junction disposed on the sub-fin structure. 结构。 Structure. Block 308 includes forming a gate oxide on the fin device structure. Block 310 includes forming a gate material disposed on a gate oxide.

In an embodiment, the fin device structure of the embodiments described herein may be coupled with any suitable type of package structure, which can be used in the next layer of components (e.g., circuits) that are coupled to a microelectronic device such as a die and the package structure. Board) to provide electrical communication. In another embodiment, the device described herein may be coupled to a package assembly structure, which may include any type of package assembly capable of providing electrical communication between a die and an upper integrated circuit (IC) package assembly Structure, the upper integrated circuit (IC) package assembly is coupled to the device therein.

For example, the devices of the embodiments herein may include circuit elements such as logic elements used in a processor die. The device herein may include a metallization layer and an insulating material, and a conductive contact / bump coupled to the metal layer / interconnect to an external device / layer. For example, the devices shown in the different figures in the text may include portions of silicon logic die or memory die, or any type of suitable microelectronic device / die. In some embodiments, the device may in turn include multiple dies stacked on top of each other, depending on the particular application. In some cases, the dies of the device herein may be provided / attached / embedded on or in the front side, back side, or some combination of front and back sides of the packaging structure. In an embodiment, the die is partially or fully embedded in the package component structure.

Various embodiments of the device structure contained herein can be used in SOC products that require integrated transistors, such as smart phones, notebook computers, tablet computers, and other electronic mobile devices. Description of devices such as multi-gate transistor devices including fin structures with asymmetric bottom profiles Manufacturing. By reducing the number of defects originating from the sidewalls of the isolation material during epitaxial growth, the epitaxial quality of the III-V material is improved. Achieve the ability to manufacture non-silicon CMOS on silicon wafers.

FIG. 4 illustrates an interposer 400 including one or more embodiments included in the text. The interposer 400 is an interposer substrate and is used to bridge the first substrate 402 to the second substrate 404. For example, the first substrate 402 may be an integrated circuit die, where the die may include a device structure such as a fin device structure of the embodiment described herein. For example, the second substrate 404 may be a memory module, a computer motherboard, or another integrated circuit die. The second substrate 404 may be combined with a device structure such as the fin device structure of the embodiment described herein. . In general, the purpose of the mediator 400 is to spread the connections to a wider pitch and / or rearrange the paths of the connections to different connections. For example, the interposer 400 may couple the integrated circuit die to a ball grid array (BGA) 406, which may then be coupled to the second substrate 404. In some embodiments, the first and second substrates 402/404 are attached to opposite sides of the interposer 400. In other embodiments, the first and second substrates 402/404 are attached to the same side of the interposer 400. And in another embodiment, three or more substrates are interconnected by an interposer 400.

The interposer 400 may be formed of an epoxy resin, a glass fiber reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In other implementations, the interposer may be formed from alternative rigid or flexible materials, which may include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other III-V and IV materials.

The mediator may include a metal interconnect 408 and a via 410, and the via 410 includes, but is not limited to, TSV 412. The mediator 400 may further include an embedded device 414, which includes both passive and active devices. These devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices can also be formed on the mediator 400.

FIG. 5 illustrates a computing device 500 including an embodiment of the device structure described herein. The computing device 500 may include multiple components. In an embodiment, these components are attached to one or more motherboards. In alternative embodiments, these components are fabricated on a system-on-chip (SOC) die instead of a motherboard. The components in the computing device 500 include, but are not limited to, an integrated circuit die 502 and at least one communication chip 508. In some implementations, the communication chip 508 is fabricated as part of the integrated circuit die 502. The integrated circuit die 502 may include a CPU 504 and an on-die memory 506. The on-die memory 506 is often used as a cache memory, which may be stored by, for example, embedded DRAM (eDRAM) or spin-transfer torque memory. Technology (STTM or STTM-RAM).

The computing device 500 may include other components that may or may not be physically and electrically coupled to a motherboard or fabricated within a SoC die. These other components include, but are not limited to, electrically dependent memory 510 (e.g., DRAM), non-dependent memory 512 (e.g., ROM or flash memory), graphics processing unit 514 (GPU), digital signal processor 516 Cryptographic processor 542 (special implementation of cryptographic deduction in hardware Processor), chipset 520, antenna 522, display or touch screen display 524, touch screen display controller 526, battery 528 or other power source, power amplifier (not shown), global positioning system (GPS) device 529, Compass 530, motion sub-processor or sensor 532 (including accelerometer, gyroscope, and compass), speaker 534, camera 536, user input device 538 (e.g. keyboard, mouse, stylus, and touch Pads) and mass storage devices 540 (eg, hard drives, compact discs (CDs), digital video discs (DVDs, etc.).

The communication chip 508 can perform wireless communication for data transmission to the computing device 500. The word "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, technologies, communication channels, etc. that use modulated electromagnetic radiation that passes through non-solid media. This term does not mean that the related devices do not contain any wires, however, in some embodiments they do not contain any wires. The communication chip 508 can implement a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, long-range evolution (LTE), Ev-DO, HSPA +, HSDPA +, HSUPA +, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols designated as 3G, 4G, 5G, and beyond. The computing device 500 may include a plurality of communication chips 508. For example, the first communication chip 508 may be dedicated to short-range wireless communications such as Wi-Fi and Bluetooth, and the second communication chip 508 may be dedicated to, for example, GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO , And so on longer range wireless communication.

According to the embodiments herein, the processor 504 of the computing device 500 includes one or more devices, such as transistors or metal interconnects, formed according to the embodiments herein. The term "processor" means any device or device that processes electronic data from a register and / or memory to convert that electronic data into other electronic data that can be stored in the register and / or memory a part.

The communication chip 508 may also include one or more devices, such as a transistor device structure and a package assembly structure, formed according to the embodiments herein. In another embodiment, another component housed in the computing device 500 may include, for example, a transistor device structure and a related package component structure formed according to the embodiments herein.

In various embodiments, the computing device 500 may be a laptop computer, a notebook network computer, a notebook computer, an ultra-thin notebook computer, a smart phone, a tablet computer, a personal digital assistant (PDA), Thin mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder. In other implementations, the computing device 500 may be any other electronic device that processes data.

The above description of the illustrated embodiment, including that described in the Summary of the Invention, is not intended to be all-inclusive or to limit the embodiment to the precise form disclosed. Although specific implementations of the embodiments are exemplified here for the purpose of illustration, as will be understood by those skilled in the art, various equivalent modifications are possible within the scope of the present invention.

In view of the above detailed description, these modifications can be made to the embodiments. in The proper nouns used in the following patent application scope should not be construed to limit the embodiments to the specific implementations disclosed in the specification and the appended patent application scope. On the contrary, the scope of the embodiment is entirely determined by the scope of the patent application attached after being constructed according to the established theory of interpretation of the scope of patent application.

Although the above description indicates certain steps and materials that can be used in the method of the embodiment, those skilled in the art will understand that many modifications and alternatives can be made. Therefore, all such modifications, substitutions, substitutions and additions should be considered to fall within the spirit and scope of the embodiments defined by the scope of the attached patent application. In addition, the drawings provided herein only show some parts of the microelectronic device and related packaging structures exemplified in connection with the implementation of the embodiments. Therefore, the embodiment is not limited to the structure described in the text.

Claims (20)

A microelectronic device structure includes a substrate including a protruding portion and a non-protruding portion, wherein a dielectric material is disposed adjacent to the protruding portion, and wherein an upper surface of the protruding portion includes the protrusion. The single-sided (111) facet of some materials; the sub-fin structure is arranged on the upper surface of the protruding portion, wherein the bottom portion of the sub-fin structure includes an asymmetrical shape; the fin device The structure is provided on the sub-fin structure; the gate oxide is provided on a part of the fin device structure; and the gate material is provided on the gate oxide. For example, the structure of the first scope of the patent application, wherein the sub-fin structure includes a first side and a second side, wherein the first and second sides have unequal lengths. For example, the structure of claim 1 in the patent scope, wherein the fin device structure and the sub-fin structure include an epitaxial material selected from the group consisting of a group III element, a group IV element, and a group V element. For example, the structure of claim 1 in the patent scope, wherein the microelectronic device structure includes a device selected from the group consisting of a multi-gate transistor and a surrounding gate transistor. For example, the structure of the first scope of the patent application, wherein the bottom portion of the sub-fin structure includes the (111) silicon plane of the protruding portion of the substrate. For example, the structure of claim 1 in the patent scope, wherein the one-sided (111) facet is arranged along the length of the fin device structure. For example, the structure of claim 1 in the patent scope, wherein the protruding portion of the substrate includes an asymmetric shape. For example, the structure of claim 1, wherein the fin device structure extends above the surface of the dielectric material. An electronic system includes: a board; and a microelectronic device attached to the board, wherein the microelectronic device includes at least one transistor, and the at least one transistor includes: a substrate including a protruding portion and a non-protruding portion The dielectric material is disposed adjacent to the protruding portion; the epitaxial sub-fin structure is disposed on the protruding portion, wherein the bottom portion of the epitaxial sub-fin structure includes An asymmetric shape; and an epitaxial fin device structure, which is arranged on the sub-fin structure. For example, the system of claim 9, wherein the sub-fin structure and the fin device structure include a material selected from the group consisting of gallium nitride, gallium arsenide, indium phosphide, indium aluminum phosphide, indium gallium arsenide, and arsenide. Epitaxial materials in a group of gallium, indium arsenide, and indium gallium nitride. For example, the system of claim 9 of the patent application scope, wherein the protruding portion of the substrate includes a first angle and a second angle. For example, the system of claim 9 in which a part of the fin device structure includes a channel region of a transistor structure, and a source / drain region is coupled to the channel region. For example, the system of claim 9 in which the upper surface of the protruding portion includes a one-sided (111) facet of the material of the protruding portion. For example, the system of claim 9 in which the ratio of the length of the sub-fin structure to the width of the sub-fin structure is greater than about 2: 1. For example, the system of claim 9 in which the sub-fin structure includes a first side wall, the first side wall includes a first height, and the second side wall includes a second height, wherein the first height is greater than the first height. Two heights are longer. A method for forming a microelectronic device includes: providing a substrate including a protruding portion and a non-protruding portion, wherein a dielectric material is disposed adjacent to the protruding portion; and providing an epitaxial sub-fin structure, The epitaxial sub-fin structure is disposed on the protruding portion, wherein the bottom portion of the epitaxial sub-fin structure includes an asymmetrical shape; the epitaxial fin device structure is provided on the A sub-fin structure; forming a gate oxide on the fin device structure; and forming a gate material disposed on the gate oxide. For example, the method of claim 16 in which the sub-fin structure includes a first side and a second side, wherein the first and second sides have unequal lengths. For example, the method of claim 16 in which the ratio of the length of the sub-fin structure to the width of the sub-fin structure is greater than about 2: 1. For example, the method of claim 16 in which the sub-fin structure and the fin device structure include a member selected from the group consisting of gallium nitride, indium phosphide, indium aluminum phosphide, and indium gallium nitride. Epitaxy material. For example, the method of claim 16 in which the bottom of the sub-fin structure is asymmetric and is disposed on the (111) facet of the protruding portion of the substrate.