TWI680560B - System in package structure and electrostatic discharge protection structure thereof - Google Patents

Abstract

System in package (SiP) structure and its electrostatic discharge protection structure. The ESD protection structure includes a redistribution layer and a first transistor array. The redistribution layer includes a first electrode and a second electrode. The first transistor array is coupled to a pin terminal of the integrated circuit, the first electrode, and the second electrode. The first transistor array has a plurality of transistors, a plurality of first transistors in the transistors are coupled in parallel with each other, and a plurality of second transistors in the transistors are coupled in parallel with each other. The first transistor and the second transistor are used to be turned on to discharge an electrostatic discharge current.

Description

System packaging structure and electrostatic discharge protection structure

This disclosure relates to a system packaging structure and its electrostatic discharge protection structure.

With the advancement of electronic technology, today's electronic devices often perform multiple different functions by configuring multiple integrated circuits. In order to reduce the area required for integrated circuit layout and simplify the wiring complexity between integrated circuits, system packaging has become a popular choice.

In the system package of the conventional technology, a plurality of integrated circuits included in the system package may store a certain degree of electrostatic charge during processing and manufacturing. These electrostatic charges are discharged to the Redistribution Layer (RDL) when the integrated circuit is packaged into the system package, and may cause damage to the integrated circuit or the circuit in the redistribution layer.

The embodiment of the disclosure provides a system package structure and an electrostatic discharge protection structure thereof, which can effectively improve the electrostatic discharge protection capability.

The disclosed ESD protection structure includes a redistribution layer and a first transistor array. The redistribution layer is coupled to at least one integrated circuit. The redistribution layer has a first electrode and a second electrode. The first transistor array is coupled to a pin terminal of the integrated circuit, the first electrode, and the second electrode. The first transistor array has a plurality of transistors, a plurality of first transistors in the transistors are coupled in parallel with each other, and a plurality of second transistors in the transistors are coupled in parallel with each other. The first transistor and the second transistors are used to be turned on to discharge an electrostatic discharge current.

The system package structure of an embodiment of the disclosure includes at least one integrated circuit and the electrostatic discharge protection structure as described above. The electrostatic discharge protection structure is coupled to the pin terminals of at least one integrated circuit, and is used to release the electrostatic discharge current generated on the pin terminals.

Based on the above, the embodiments of the present disclosure provide a transistor array in which a plurality of transistors are coupled in parallel. The transistor array is coupled to the pin terminal of the integrated circuit, and is coupled to the first electrode and the second electrode provided by the redistribution layer. When the electrostatic discharge phenomenon occurs, multiple transistors in the transistor array can be quickly turned on, and the electrostatic discharge current can be quickly discharged to the first electrode or the second electrode, which can effectively perform electrostatic discharge protection and protect the product. The circuit will not be damaged.

In order to make this disclosure more comprehensible, embodiments are exemplified below and described in detail with the accompanying drawings.

Please refer to FIG. 1, which is a schematic cross-sectional structure diagram of a system package structure according to an embodiment of the present disclosure. The system package structure 100 includes an integrated circuit 110 and an ESD protection structure coupled to the integrated circuit 110. The ESD protection structure includes a redistribution layer 130 and a transistor array 120. The redistribution circuit layer 130 includes, for example, a plurality of dielectric layers and a plurality of conductive layers which are alternately stacked. The redistribution layer 130 is coupled to the integrated circuit 110 and performs a rewiring operation on the integrated circuit 110. In this embodiment, the redistribution layer 130 has a first electrode PD1 and a second electrode PD2, wherein the first electrode PD1 and the second electrode PD2 are coupled to the transistor array 120.

Furthermore, in this embodiment, the integrated circuit 110 is provided in the packaging material 101, and the redistribution layer 130 is disposed between the packaging material 101 and the substrate 140.

The substrate 140 in this embodiment may include an organic polymer material, an inorganic polymer material, or an organic-inorganic hybrid material. The organic polymer material may be polyimide (PI), polybenzoxazole (PBO), benzocyclobutene polymer (BCB), or other suitable materials. The inorganic polymer material may be silicon oxide. ), Silicon nitride, silicon oxynitride, polysiloxane, polysilazane, polysiloxazane, polycarbosilane Or other suitable materials, in other application examples, it may be a glass substrate, a printed circuit board, a semiconductor integrated circuit carrier board, or a substrate for a semiconductor process wafer.

The transistor array 120 is further coupled to the pin terminal PIN of the integrated circuit 110. In this embodiment, the transistor array 120 can be coupled to the pin terminal of the integrated circuit 110 through a wire in the redistribution layer 130. PIN. The transistor array 120 includes a plurality of first transistors and a plurality of second transistors. Among them, the plurality of first transistors are connected in parallel to each other between the pin PIN and the first electrode PD1, and the plurality of second transistors are connected in parallel to each other. Between the pin terminal PIN and the second electrode PD2. When an electrostatic discharge phenomenon occurs at the pin PIN of the integrated circuit 110, the first transistor or the second transistor may be correspondingly turned on and used to release the electrostatic discharge current.

In an embodiment of the present disclosure, the transistor array 120 may be disposed in the redistribution layer 130, and the vertical projection plane of the redistribution layer 130 and the vertical projection plane of the redistribution layer 130 of the integrated circuit 120 may completely overlap ( As shown in Figure 1). However, the disclosure is not limited thereto. In other embodiments, the vertical projection plane of the redistribution layer 130 of the transistor array 120 and the vertical projection plane of the redistribution layer 130 of the integrated circuit 120 partially overlap or do not overlap at all.

Please note that the transistor array 120 in this embodiment is formed in the redistribution circuit layer 130 outside the integrated circuit 110 instead of being provided in the integrated circuit 110 or in an interposer of the substrate 140. In this way, the transistor array 120 can perform a high-efficiency electrostatic discharge operation without taking up the layout area of the integrated circuit 110.

Please refer to FIG. 1 and FIG. 2 at the same time. FIG. 2 is a schematic diagram of an equivalent circuit of the transistor array in the embodiment of the present disclosure. In FIG. 2, each of the plurality of first transistors is coupled in a diode configuration (for example, the gate and source of each transistor are coupled together). Parallel to each other, equivalent to diode D1. Each of the plurality of second transistors is coupled in a diode configuration (for example, the gate and source of each transistor are coupled together), and the plurality of second transistors are connected in parallel with each other, which is equivalent It is diode D2. The cathode of the diode D1 is coupled to the first electrode PD1, the anode of the diode D1 is coupled to the pin terminal PIN and coupled to the cathode of the diode D2, and the anode of the diode D2 is coupled Connected to the second electrode PD2.

When a positive voltage electrostatic discharge phenomenon ESD1 occurs on the pin terminal PIN of the integrated circuit 110, the diode D1 can be turned on correspondingly, a current venting path is formed between the pin terminal PIN and the first electrode PD1, and the venting is effective. Electrostatic discharge phenomenon The electrostatic discharge current generated by ESD1. In contrast, when a negative voltage electrostatic discharge phenomenon ESD2 occurs on the pin PIN of the integrated circuit 110, the diode D2 can be turned on correspondingly, and a current leakage path is formed between the pin PIN and the second electrode PD2. , And effectively release the electrostatic discharge current generated by the electrostatic discharge phenomenon ESD2.

In the disclosed embodiment, the diodes D1 and D2 are respectively composed of a plurality of first transistors and a plurality of second transistors. And each transistor (each first transistor or each second transistor) has a relatively small size. For example, the channel length of each transistor can be substantially set between 3 to 10 microns, and the channels of each transistor The width can be set substantially between 3 and 10 microns. The channel length and channel width mentioned above include some errors in the manufacturing process. In addition, the first transistor and the second transistor in this embodiment may be thin film transistors. In this way, when the electrostatic discharge phenomenon ESD1 or ESD2 occurs, each small-sized first transistor or second transistor can be quickly turned on, and a current venting path can be effectively formed to effectively vent the electrostatic discharge current.

In addition, the number of transistors provided in the transistor array 120 may be determined according to the electron mobility of the transistors. Among them, the number of transistors in the transistor array 120 has a negative correlation with its electron mobility. That is, if the electron mobility of the transistor is small, a relatively large number of transistors need to be provided in the transistor array 120. On the other hand, if the electron mobility of the transistor is large, it can be used in the transistor array 120. Set a relatively small number of transistors. Taking into consideration the layout area and the electrostatic discharge capability, in one embodiment, the number of the first transistors in the transistor array 120 may be set between 20 and 1,000. In another embodiment, the first transistors are The number of the first transistor can be set between 20 and 800. In other embodiments, the number of the first transistor can be set between 20 and 300, and the number of the second transistor can be set the same as that of the first transistor. Not limited to this. Alternatively, under the condition that the electrostatic discharge requirements are not strict, the first transistor in the embodiment of the present disclosure may be provided as two.

Please refer to FIG. 3. FIG. 3 is a schematic top view of the ESD protection structure according to the embodiment of the disclosure. The ESD protection structure 300 includes a transistor array 120 and a redistribution layer, wherein the redistribution layer provides a first electrode PD1, a second electrode PD2, and a connection wire PINA connected to a pin end of the integrated circuit. The transistor array 120 is coupled to the connecting wire PINA, and is connected to a pin terminal of the integrated circuit through the connecting wire PINA. The first electrode PD1 and the second electrode PD2 in FIG. 3 are adjacent to the transistor array 120 and are disposed on one side of the transistor array 120. In this embodiment, the distance d1 between the first electrode PD1 and the second electrode PD2 may be greater than or equal to 100 micrometers.

The first electrode PD1 and the second electrode PD2 in FIG. 3 may be connected to the transistor array 120 through connection wires at other positions (or levels) in the redistribution layer.

For details of the implementation of the transistor array according to the present disclosure, please refer to FIGS. 4A to 4D, which are schematic diagrams of different implementations of the transistor array according to the present disclosure. In FIG. 4A, the transistor array 410 includes a plurality of first transistors M11 ~ M1N and a plurality of second transistors M21 ~ M2N. Each first transistor M11 ~ M1N is coupled into a diode configuration, and each first transistor M11 ~ M1N is coupled in parallel with each other and is coupled between the first electrode PD1 and the pin terminal PIN. Each of the second transistors M21 ~ M2N is coupled into a diode configuration, and each of the second transistors M21 ~ M2N is coupled in parallel with each other and is coupled between the pin terminal PIN and the second electrode PD2.

In FIG. 4A, the first transistors M11 to M1N and the second transistors M21 to M2N are P-type transistors, and the gate terminals and the first ends of the first transistors M11 to M1N are commonly coupled to the first transistor. The electrode PD1 and the second ends of the first transistors M11 ~ M1N are commonly coupled to the pin terminal PIN. The gate terminals and the first terminals of the second transistors M21 to M2N are commonly coupled to the pin terminal PIN, and the second terminals of the second transistors M21 to M2N are commonly coupled to the second electrode PD2. The first electrode PD1 may be a power electrode and the second electrode PD         12 can be a ground electrode.       

In FIG. 4B, unlike FIG. 4A, the second transistors M21 to M2N in the transistor array 420 are all N-type transistors, and the first ends of the second transistors M21 to M2N are coupled to the lead. The pin terminal PIN, and the second terminal and the gate terminal of each of the second transistors M21 to M2N are commonly coupled to the second electrode PD2.

In addition, in FIG. 4C, different from FIG. 4B, the first transistors M11 to M1N in the transistor array 430 are also N-type transistors. In addition, a first terminal of each of the first transistors M11 to M1N is coupled to the first electrode PD1, and a second terminal and a gate terminal of each of the first transistors M11 to M1N are commonly coupled to the pin terminal PIN.

In FIG. 4D, the first transistors M11 to M1N in the transistor array 440 include one or more N-type transistors (such as the first transistor M12) and one or more P-type transistors (such as the first transistor). Crystals M11, M1N) and arranged in a staggered arrangement. The second transistors M21 to M2N in the transistor array 440 also include one or more N-type transistors (such as the second transistor M22) and one or more P-type transistors (such as the second transistors M21, M2N). ) And arrange them in a staggered configuration. Each transistor M11 ~ M2N is coupled into a diode configuration. Among them, the anode of the diode formed by the first transistor M11 ~ M1N is coupled to the pin terminal PIN, and the cathode is coupled to the first electrode PD1. . The anode of the diode formed by the second transistors M21 to M2N is coupled to the second electrode PD2, and the cathode is coupled to the pin terminal PIN.

It can be known from the description of FIG. 4D that in the embodiments of FIGS. 4A to 4C, the first transistors M11 ~ M1N or the second transistors M21 ~ M2N can also pass through one or more P-type transistors and one or Multiple N-type transistors are provided, and it is not necessary to select transistors of the same conductivity type.

Please refer to FIG. 5, which illustrates a schematic diagram of another embodiment of the ESD protection structure according to the embodiment of the disclosure. In the ESD protection structure 500, the transistor array 510 may include at least a plurality of transistor strings 511-518, and each of the transistor strings 511-518 may include a plurality of transistors. In addition, each of the transistor strings 511 to 518 is coupled to the pin terminal PIN through a plurality of wires L1 to L8, respectively. In order to improve the consistency of the conduction speed of the transistors in the transistor array 510, the transmission delays provided by the transistor strings 511 to 518 and the wires L1 to L8 between the pin terminals PIN are substantially the same. The transistor strings 511 to 518 are listed above as an example, but the number of transistor strings included in the transistor array 510 is not limited to this. As shown in FIG. 5, the number of transistor strings included in the transistor array 510 is more than eight from 511 to 518, and the transmission delay provided by the wire between each transistor string and the pin at the pin is substantially the same.

Taking the transistor strings 511 and 514 as an example, in order to make the transmission delay between the pin PIN and the transistor strings 511 and 514 substantially the same, it is possible to increase the pin PIN by making more bends in the wire L1. The transmission delay between the transistor string 511 and the wire L4 is laid out with less bending, so as to reduce the transmission delay between the pin PIN and the transistor string 514. In this way, the transmission delay between the pin PIN and the transistor strings 511 and 514 can be substantially the same, and when the electrostatic discharge phenomenon occurs, it can be turned on at the same time as the transistor strings 511 and 514, and Improve the discharge speed of electrostatic discharge current. The wires L1 to L8 may include different line widths and line lengths.

Continuing the above example, the wires L1 and L4 can be designed to have the same width, length, and thickness so that the wires L1 and L4 can have the same transmission delay. Alternatively, the wires L1 and L4 can also be designed through different widths, thicknesses, and / or different lengths, so that they have the same equivalent impedance and generate the same transmission delay. In addition, the layout of the wires L1 to L8 in FIG. 5 is only an illustrative example, and is not intended to limit the scope of implementation of the disclosure. Any layout method known to those having ordinary skill in the art to make the wires have the same transmission delay can be applied to implement the present disclosure without any particular limitation.

Please refer to FIG. 6A and FIG. 6B. FIG. 6A and FIG. 6B are schematic diagrams illustrating another implementation of the transistor array according to the embodiment of the present disclosure. In FIGS. 6A and 6B, a diode corresponding to the transistor may be further disposed in the transistor array. Taking a single transistor in the transistor array as an example, in FIG. 6A, the transistor MA1 and the diode DA1 are coupled in parallel with each other. To further explain, the transistor MA1 is an N-type transistor. The first terminal of transistor MA1 is coupled to the cathode of diode DA1 and forms terminal X, the second terminal of transistor MA1 is coupled to the anode of diode DA1 and forms terminal Y, and the gate of transistor MA1 Is coupled to the terminal S.

In terms of structure, the transistor MA1 and the diode DA1 can be arranged through the integrated structure 610. Please refer to FIG. 6A. FIG. 6A is a top view of the integrated structure 610. The integrated structure 610 includes a gate structure GS1 and doped regions DP1 to DP4. The gate structure GS1 is connected to the terminal S, and is overlapped with the insulating layer (not shown) and the semiconductor material (not shown), and covers the insulating layer and the semiconductor material. The two sides S1 and S2 of the semiconductor material are in contact with the doped regions DP1 and DP2 to DP4, respectively. The first side S1 is opposite to the second side S2. The doped region DP1 is connected to the terminal X, and the doped region DP3 is connected to the terminal Y. In this embodiment, the doped regions DP1, DP2, and DP4 are all N + type, and the doped region DP3 is P + type. . In addition, the semiconductor material may be an N + type, a P + type, or a neutral type (non-doped).

In FIG. 6B, the transistor MA2 and the diode DA2 are coupled in parallel with each other. To further explain, the transistor MA2 is a P-type transistor. The first terminal of transistor MA2 is coupled to the anode of diode DA2 and forms terminal X, the second terminal of transistor MA2 is coupled to the cathode of diode DA2 and forms terminal Y, and the gate of transistor MA2 Is coupled to the terminal S.

In terms of structure, the transistor MA2 and the diode DA2 can be arranged through the integrated structure 620. Please refer to FIG. 6B. FIG. 6B is a top view of the integrated structure 620. The integrated structure 620 includes a gate structure GS2 and doped regions DP5 to DP8. The gate structure GS2 is connected to the terminal S, and is covered with an insulating layer (not shown) and a semiconductor material (not shown). The two sides S1 and S2 of the semiconductor material are in contact with the doped regions DP5 and DP6 to DP8, respectively. The first side S1 and the second side S2 are opposite to each other. The doped region DP5 is connected to the terminal X, and the doped region DP7 is connected to the terminal Y. In this embodiment, the doped regions DP5, DP6, and DP8 are all P + type, and the doped region DP7 is N + type. In addition, the semiconductor material may be an N + type, a P + type, or a neutral type (non-doped).

6C and FIG. 6D, FIG. 6C and FIG. 6D are schematic diagrams of different embodiments of the cross-sectional structure according to the section line A-A 'in the embodiment of FIG. 6A, respectively. In FIG. 6C, the doped regions DP1 and DP3 are respectively disposed on two opposite sides of the semiconductor material SM1. The insulating layer I, the semiconductor material SM1, and the gate structure GS1 are overlapped with each other. The insulating layer I covers the semiconductor material SM1. The insulating layer I can also completely cover, partially cover, or not cover the doped regions DP1 or DP3. The structure GS1 covers the insulating layer I. In addition, the order of arrangement of the semiconductor material SM1, the insulating layer I, and the gate structure GS1 may be different. In FIG. 6D, the insulating layer I, the semiconductor material SM1, and the gate structure GS1 are arranged overlapping each other, and the semiconductor material SM1 covers the insulating layer I. Above, and over the gate structure GS1 over the insulating layer I.

Please refer to FIG. 7, which illustrates a schematic top view of another embodiment of the ESD protection structure disclosed herein. The electrostatic discharge protection structure 700 includes a plurality of transistor arrays 720, 730, 740, and 750, and a redistribution layer, wherein the redistribution layer provides a first electrode PD1, a second electrode PD2, and a connection lead connected to a pin end of the integrated circuit. PINA. The transistor arrays 720, 730, and 740 are coupled to the connecting wire PINA, and are connected to the pin terminals of the integrated circuit through the connecting wire PINA. In this embodiment, when an electrostatic discharge phenomenon occurs on a pin terminal of the integrated circuit, a plurality of transistor arrays 720, 730, 740, and 750 can be used to improve the discharge capability of the electrostatic discharge current.

The number of transistors in the transistor arrays 720, 730, 740, and 750 may be the same or different. In addition, the transistors in the transistor arrays 720, 730, and 740 can be constructed in a manner as shown in FIGS. 4A to 4C or FIGS. 6A and 6B, and are not particularly limited. In addition, the arrangement manners of the transistors in the transistor arrays 720, 730, 740, and 750 may be completely the same, partly the same, or all different, and there is no particular limitation.

Please refer to FIG. 8, which illustrates a schematic diagram of a system package structure according to an embodiment of the present disclosure. The system package structure 800 includes integrated circuits 811 and 812, a redistribution layer 830, and transistor arrays 821 and 822. The redistribution layer 830 and the transistor arrays 821 and 822 are used to construct an electrostatic discharge protection structure. The integrated circuits 811 and 812 are provided in the packaging material 801, and the redistribution layer 830 is disposed between the packaging material 801 and the substrate 840. The transistor arrays 821 and 822 are disposed in the redistribution layer 830, and are coupled to the first electrode PD1 and the second electrode PD2 provided by the redistribution layer 830. In addition, the transistor arrays 821 and 822 are coupled to the pin terminals PIN1 and PIN2 of the integrated circuits 811 and 812, respectively. The transistor arrays 821 and 822 are used to be turned on, and are used to release the electrostatic discharge currents generated at the pin terminals PIN1 and PIN2 of the integrated circuit 811 and 812, respectively.

Please note here that in this disclosure, there is no certain limit on the number of integrated circuits included in the system package structure 800, and there is no corresponding number of transistor arrays corresponding to the number of pin terminals of the integrated circuit. Specific restrictions.

Regarding the implementation details of the electrostatic discharge protection structure of this embodiment, detailed descriptions are given in the foregoing multiple embodiments and implementation manners, and will not be repeated here.

Please refer to FIG. 9 below, which illustrates a schematic top view of a system packaging structure according to an embodiment of the present disclosure. In the system package structure 900, the integrated circuit 920 has a pin terminal PINA, and the pin terminal PINA is connected to the transistor arrays 911 and 912 through the wires L1 and L2 formed by the redistribution layer. The redistribution layer provides wires L3 and L4 to connect the first electrode PD1 and the second electrode PD2 to the transistor arrays 911 and 912.

In the present disclosure, the transistor arrays 911 and 912 are disposed in a portion not covered by the integrated circuit 920 (outside of the edge EDGE of the integrated circuit 920). In other embodiments of the present disclosure, the transistor arrays 911 and 912 may partially overlap the integrated circuit 920, or completely overlap the integrated circuit 920, and there is no specific limitation.

Please refer to FIG. 10A, which is a schematic cross-sectional structure diagram of a system package structure according to an embodiment of the present disclosure. The system package structure 1100 includes an integrated circuit 1010 and an electrostatic discharge protection structure coupled to the integrated circuit 1010. The electrostatic discharge protection structure includes a redistribution layer 1030 and a transistor array 1020. The redistribution circuit layer 1030 includes, for example, a plurality of dielectric layers and a plurality of conductive layers that are alternately stacked, the redistribution layer 1030 is coupled to the integrated circuit 1010, and performs a rewiring operation on the integrated circuit 1010. In this embodiment, the redistribution layer 1030 has a first electrode PD1 and a second electrode PD2, wherein the first electrode PD1 and the second electrode PD2 are coupled to the transistor array 1020. Moreover, in this embodiment, the integrated circuit 1010 is provided in the packaging material 1001, and the redistribution layer 1030 is disposed between the packaging material 1001 and the substrate 1040. It is worth mentioning that the transistor array 1020 in this embodiment is adjacent to the substrate 1040 for configuration. In other embodiments, the transistor array 1020 can be disposed at any position in the redistribution layer 1030 without any specific restrictions.

Please note that the transistor array 1020 in this embodiment is formed in the redistribution circuit layer 1030 outside the integrated circuit 1010, rather than in the integrated circuit 1010 or in the interposer of the substrate 1040. In this way, the transistor array 1020 can perform a high-efficiency electrostatic discharge operation without taking up the layout area of the integrated circuit 1010.

Please refer to FIG. 10B, which is a schematic cross-sectional structure diagram of a system packaging structure according to an embodiment of the present disclosure. The system package structure 1100 includes integrated circuits 1111, 1112, redistribution layers 1130, and transistor arrays 1121 and 1122. The redistribution layer 1130 and the transistor arrays 1121 and 1122 are used to construct an electrostatic discharge protection structure. The integrated circuits 1111 and 1112 are provided in the packaging material 1101, and the redistribution layer 1130 is disposed between the packaging material 1101 and the substrate 1140. The transistor array 1121 is disposed in the redistribution layer 1130 and is coupled to the first electrode PD11 and the second electrode PD21 provided in the redistribution layer 1130. The transistor array 1122 is disposed in the redistribution layer 1130 and is coupled to the first electrode PD12 and the second electrode PD22 provided in the redistribution layer 1130. In addition, the transistor arrays 1121 and 1122 are respectively coupled to the pin terminals PIN1 and PIN2 of the integrated circuit 1111 and 1112. The transistor arrays 1121 and 1122 are used to be turned on, and are used to release the electrostatic discharge currents on the pin terminals PIN1 and PIN2 of the integrated circuit 1111 and 1112, respectively. Unlike the embodiment in FIG. 8, the transistor arrays 1121 and 1122 in the system package structure 1100 are configured adjacent to the substrate 1140. In other embodiments, the transistor arrays 1121 and 1122 can be disposed at any position in the redistribution layer 1030 without any specific restrictions.

In summary, the present disclosure provides a transistor array composed of a plurality of transistors in a redistribution layer. By coupling the transistor array with the pin terminals of the integrated circuit, the electrostatic discharge current of the charged-device model (CDM) generated on the integrated circuit can be transmitted through the transistor array by multiple parallel coupling. The connected transistor is quickly discharged by the current leakage path formed by the conduction, which effectively prevents the rewiring layer or the integrated circuit from being damaged by the electrostatic discharge current.

Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

100, 800, 900, 1000, 1100: system package structure 110, 811, 812, 920, 1010, 1111, 1112: integrated circuit 120, 410, 420, 430, 440, 510, 720, 730, 740, 750, 821, 822, 911, 912, 1020, 1121, 1122: transistor arrays 130, 830, 1030, 1130: redistribution layers 101, 801, 1001, 1101: packaging materials 140, 840, 1040, 1140: substrates 300, 500 , 700: Electrostatic discharge protection structure PIN, PIN1, PIN2, PINA: pin terminals PD1, PD2, PD11, PD12, PD21, PD22: electrodes D1, D2, DA1, DA2: diode ESD1, ESD2: electrostatic discharge phenomenon M11 ~ M1N, M21 ~ M2N, MA1, MA2: Transistor d1: Distance 511 ~ 518: Transistor string L1 ~ L8: Wire PINA: Connecting wire X, Y, S: End point 610, 620: Integrated structure GS1: Gate Pole structure I: insulation layer SM1: semiconductor material DP1 to DP8: doped region S1: first side S2: second side

FIG. 1 is a schematic cross-sectional structure diagram of a system packaging structure according to an embodiment of the disclosure. FIG. 2 is a schematic diagram of an equivalent circuit of a transistor array in the embodiment of the disclosure. FIG. 3 is a schematic top view of the ESD protection structure according to the embodiment of the disclosure. 4A to 4D are schematic diagrams of different implementations of the transistor array according to the embodiment of the disclosure. FIG. 5 is a schematic diagram of another embodiment of the ESD protection structure according to the embodiment of the disclosure. FIG. 6A and FIG. 6B are schematic diagrams illustrating the implementation of the transistor array according to the embodiment of the disclosure. 6C and FIG. 6D are schematic diagrams of different embodiments of the cross-sectional structure shown according to the section line A-A 'in the embodiment of FIG. 6A. FIG. 7 is a schematic top view of another embodiment of the ESD protection structure of the present disclosure. FIG. 8 is a schematic diagram of a system package structure according to an embodiment of the disclosure. FIG. 9 is a schematic top view of a system packaging structure according to an embodiment of the disclosure. FIG. 10A and FIG. 10B are schematic cross-sectional structure diagrams of a system package structure according to different embodiments of the present invention.

Claims (18)

An electrostatic discharge protection structure coupled to at least one integrated circuit includes: a redistribution layer coupled to the at least one integrated circuit, the redistribution layer having a first electrode and a second electrode; and a first electrical circuit A crystal array is disposed in the redistribution layer and is coupled to a pin terminal of the at least one integrated circuit, the first electrode, and the second electrode. The first transistor array has a plurality of transistors. A plurality of first transistors in the transistors are coupled in parallel with each other, a plurality of second transistors in the transistors are coupled in parallel with each other, the first transistors and the second transistors are used to be turned on to Discharge static discharge current. The electrostatic discharge protection structure according to item 1 of the scope of patent application, wherein the first transistors correspond to the second transistors, respectively, and the first ends of the first transistors are coupled to the first electrodes, each The second terminal of the first transistor is coupled to the first terminal of the corresponding second transistor and the pin terminal, and the second terminal of the second transistor corresponding to each of the first transistors is coupled to the second transistor. electrode. According to the electrostatic discharge protection structure described in the first item of the patent application scope, each of the first transistors is a P-type transistor or an N-type transistor, and each of the second transistors is a P-type transistor or an N-type transistor. The electrostatic discharge protection structure according to item 1 of the scope of patent application, wherein the transistors are coupled in a diode configuration. The electrostatic discharge protection structure according to item 1 of the scope of patent application, wherein the number of the transistors is determined according to the electron mobility of the transistors. The electrostatic discharge protection structure according to item 5 of the scope of patent application, wherein the number of the transistors is negatively related to the electron mobility. According to the electrostatic discharge protection structure described in item 5 of the scope of patent application, the number of the first transistors and the second transistors is between 20 and 1000. The electrostatic discharge protection structure according to item 1 of the scope of the patent application, wherein the transistors are arranged into a plurality of transistor strings, and the transistor strings are respectively coupled to the pin terminal through a plurality of wires, and the wires are The transmission delays provided separately are substantially the same. According to the electrostatic discharge protection structure described in item 1 of the scope of the patent application, the channel width of each transistor is substantially between 3 to 10 microns, and the channel length of each transistor is substantially between 3 to 10 microns. The electrostatic discharge protection structure according to item 1 of the scope of patent application, wherein the integrated circuit's vertical projection surface of the redistribution layer completely overlaps with the vertical projection surface of the first transistor array on the redistribution layer, partially Overlapping or non-overlapping. The electrostatic discharge protection structure according to item 1 of the scope of patent application, further includes: a plurality of diodes, and the diodes are respectively coupled in parallel with the transistors. The electrostatic discharge protection structure according to item 11 of the scope of the patent application, wherein each of the diodes and the corresponding transistor includes: a semiconductor material; an insulating layer is arranged overlapping the semiconductor material; a gate structure, It is arranged to overlap with the insulating layer; a first doped region is arranged on a first side of the semiconductor material and is coupled to the first end of each transistor and the first end of each corresponding diode A second doped region, a third doped region, and a fourth doped region, which are disposed on a second side of the semiconductor material, wherein the first side is opposite to the second side, and The third doped region is coupled to the second end of each transistor and the second end of each diode. The first doped region, the second doped region, and the fourth doped region are doped. The types are the same, and the doping types of the first doped region and the third doped region are opposite. The electrostatic discharge protection structure according to item 12 of the scope of patent application, wherein the doping types of the first doped region, the second doped region, and the fourth doped region are N-type, and the corresponding electrical The crystal is an N-type transistor, the first end of each corresponding diode is a cathode, and the first end of each corresponding diode is an anode. The electrostatic discharge protection structure according to item 12 of the scope of the patent application, wherein the doping types of the first doped region, the second doped region, and the fourth doped region are P-type, and the corresponding electrical The crystal is a P-type transistor, the first end of each corresponding diode is an anode, and the first end of each corresponding diode is a cathode. The electrostatic discharge protection structure according to item 1 of the scope of the patent application, wherein the transistors are thin film transistors. The electrostatic discharge protection structure according to item 1 of the scope of patent application, further comprising: at least a second transistor array coupled to the pin terminal, the first electrode, and the second electrode of the at least one integrated circuit. The second transistor array is used to be turned on to release an electrostatic discharge current. The electrostatic discharge protection structure according to item 1 of the patent application scope, wherein the first electrode is a power electrode and the second electrode is a ground electrode. A system packaging structure includes: at least one integrated circuit; and the electrostatic discharge protection structure described in Patent Application Scope 1, which is coupled to the pin terminal of the at least one integrated circuit and is used to vent the pin terminal. Electrostatic discharge current.