TWI670935B - Semiconductor device and electronic device - Google Patents

Abstract

The present invention discloses a semiconductor device including a first buffer circuit, a level transfer circuit, a second buffer circuit, a first wiring, a second wiring, and a third wiring. The level transfer circuit and the second buffer circuit are both electrically connected to the second wiring and the third wiring. A power supply voltage is applied to the first buffer circuit by converting the potential supplied to the first wiring from the third potential to the first potential. A power supply voltage is applied to the level transfer circuit and the second buffer circuit by converting the potential supplied to the second wiring from the third potential to the second potential. When the potential supplied to the first wiring is converted from the third potential to the first potential, the potential supplied to the second wiring is converted from the third potential to the second potential. The second potential is higher than the first potential, and the third potential is lower than the first potential and the second potential.

Description

Semiconductor device and electronic device

One embodiment of the present invention is directed to a semiconductor device and an electronic device.

Further, an embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in the present specification and the like relates to an object, a method or a manufacturing method. Further, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, a semiconductor device, a display device, a light-emitting device, a power storage device, an imaging device, a memory device, and a driving method of these devices are exemplified as examples of the technical field of one embodiment of the present invention disclosed in the present specification. Or the method of manufacturing these devices.

In addition, in the present specification and the like, a semiconductor device refers to an element, a circuit, a device, or the like that can operate by utilizing semiconductor characteristics. As an example, a semiconductor element such as a transistor or a diode is a semiconductor device. Further, as another example, the circuit including the semiconductor element is a semiconductor device. Further, as another example, a device including a circuit including a semiconductor element is a semiconductor device.

A semiconductor device capable of realizing data retention by using an oxide semiconductor (Oxide Semiconductor: OS) for a transistor of a semiconductor layer (hereinafter referred to as an OS transistor) or a combination of germanium (Si) for a semiconductor layer a transistor (hereinafter referred to as a Si transistor) and A semiconductor device capable of realizing data holding by an OS transistor is attracting attention (see Patent Documents 1 and 2).

Conventional technical literature:

[Patent Document 1] Japanese Patent Laid-Open Publication No. 2012-39059

[Patent Document 2] Japanese Patent Laid-Open Publication No. 2012-256820

In order to control the turn-on or turn-off of the OS transistor, a signal with a large amplitude is required. Therefore, the boosted signal is supplied to the gate of the OS transistor. A circuit for boosting requires multiple supply voltages. In the semiconductor device, the data can be held even without the supply of the power source voltage, so that the supply of the plurality of power source voltages can be stopped.

However, when a plurality of power supply voltages are supplied again, if the high level potential is unintentionally applied to the gate of the OS transistor, the held data may disappear.

One of the objects of one embodiment of the present invention is to provide a novel semiconductor device, novel electronic device, and the like.

Further, an object of one embodiment of the present invention is to provide a semiconductor device or the like having a novel structure capable of preventing data loss due to erroneous operation of a semiconductor device. Alternatively, it is an object of one embodiment of the present invention to provide a semiconductor device or the like which can realize a novel structure with low power consumption. Alternatively, it is an object of one embodiment of the present invention to provide a semiconductor device or the like having a novel structure capable of suppressing a high level potential from unintentionally outputting a plurality of power supply voltages and boosting a signal.

Further, the object of one embodiment of the present invention is not limited to the above enumerated objects. The above enumerated purposes do not preclude the existence of other purposes. In addition, other objects are the objects described below which are not described in this section. Those skilled in the art can use instructions or drawings, etc. The description derives and appropriately extracts the purpose not described in this section. Additionally, one embodiment of the present invention achieves at least one of the objects enumerated above and/or other objects.

One embodiment of the present invention is a semiconductor device including: a first buffer circuit; a level transfer circuit; a second buffer circuit; and first to third wirings, wherein the first wiring supplies the first potential, The second wiring supplies a second potential greater than the first potential, the third wiring is supplied with a third potential smaller than the first potential and the second potential, and the first buffer circuit is electrically connected to the first wiring and the third wiring, and the level shifting circuit And each of the second buffer circuits is electrically connected to the second wiring and the third wiring, and the power supply voltage is supplied to the first buffer circuit by converting the potential supplied to the first wiring from the third potential to the first potential. The power supply voltage is supplied to the level transfer circuit and the second buffer circuit by converting the potential supplied to the second wiring from the third potential to the second potential, and the potential supplied to the first wiring is converted from the third potential After the first potential, the potential supplied to the second wiring is converted from the third potential to the second potential.

The semiconductor device of one embodiment of the present invention preferably further includes a memory unit, wherein the memory unit includes a transistor having a function of maintaining a charge corresponding to the material in a node connected to the transistor in a closed state, and The second buffer circuit is electrically connected to the gate of the second transistor.

In the semiconductor device of one embodiment of the present invention, the transistor preferably includes an oxide semiconductor in the channel formation region.

Further, other embodiments of the present invention are described in the following description of the embodiments and the drawings.

One embodiment of the present invention can provide a novel semiconductor device, novel electronic device, and the like.

Further, an embodiment of the present invention can provide a semiconductor device or the like having a novel structure capable of preventing data loss due to erroneous operation of a semiconductor device. Alternatively, an embodiment of the present invention can provide a semiconductor device or the like having a novel structure capable of achieving low power consumption. Alternatively, an embodiment of the present invention can provide a semiconductor device or the like having a novel structure capable of suppressing a high level potential from unintentionally outputting a plurality of power supply voltages and boosting a signal.

Further, the effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not prevent the existence of other effects. In addition, other effects are effects which are described in the following description and which are not described in this section. Those skilled in the art can derive and appropriately extract the effects not described in this section from the descriptions of the specification, the drawings, and the like. Further, one embodiment of the present invention has at least one of the effects listed above and/or other effects. Therefore, one embodiment of the present invention sometimes does not have the effects enumerated above depending on the circumstances.

BUF1‧‧‧ buffer circuit

BUF2‧‧‧ buffer circuit

MC‧‧‧ memory unit

LS‧‧‧bit transfer circuit

IN‧‧‧ terminal

C1‧‧‧Capacitive components

C2‧‧‧Capacitive components

DEMOD_SIG0‧‧‧ signal

FN1‧‧‧ node

FN3‧‧‧ node

INV1‧‧‧Inverter Circuit

INV3‧‧‧Inverter Circuit

M1‧‧‧O crystal

M2‧‧‧O crystal

M3‧‧‧O crystal

M4‧‧‧O crystal

M5‧‧‧O crystal

M6‧‧‧O crystal

OM‧‧•O crystal

OM_B‧‧•O crystal

OM1‧‧‧O crystal

OM2‧‧•O crystal

OM3‧‧‧O crystal

SW1‧‧‧O crystal

SW3‧‧‧Optoelectronics

WL _ret ‧‧‧wiring

BL_A‧‧‧ wiring

BL_B‧‧‧Wiring

MN‧‧‧ node

OUT‧‧‧ node

OUTB‧‧‧ node

FN‧‧‧ node

BL‧‧‧Wiring

SL‧‧‧Wiring

WWL‧‧‧ wiring

T1‧‧‧ moments

T7‧‧‧ moments

T8‧‧‧ moments

T9‧‧‧ moments

T10‧‧‧ moments

VH1‧‧‧ wiring

VH2‧‧‧ wiring

11‧‧‧Inverter circuit

12‧‧‧Inverter circuit

13‧‧‧Inverter circuit

14‧‧‧Inverter circuit

15‧‧‧Optoelectronics

15_A‧‧‧Optocrystal

17‧‧‧Capacitive components

18_A‧‧‧Optoelectronics

18_B‧‧‧Optocrystal

19‧‧‧Capacitive components

19_1‧‧‧Capacitive components

19_2‧‧‧Capacitive components

19_3‧‧‧Capacitive components

21‧‧‧Substrate

23‧‧‧ impurity area

24‧‧‧ impurity area

25‧‧‧Insulation

27‧‧‧Insulation

29‧‧‧ Conductive layer

31‧‧‧Insulation

33‧‧‧Insulation

35‧‧‧Insulation

37‧‧‧Insulation

39‧‧‧ Conductive layer

41‧‧‧ Conductive layer

43‧‧‧ Conductive layer

45‧‧‧Insulation

47‧‧‧ Conductive layer

100‧‧‧Output circuit

200‧‧‧Semiconductor device

201‧‧‧Memory Cell Array

202‧‧‧Select drive

203‧‧‧ column selection drive

301‧‧ layer

302‧‧‧ wiring layer

303‧‧ layer

700‧‧‧Electronic components

701‧‧‧ lead

702‧‧‧Printed circuit board

703‧‧‧Development Department

704‧‧‧Circuit board

801‧‧‧Shell

802‧‧‧ shell

803a‧‧‧Display Department

803b‧‧‧Display Department

804‧‧‧Select button

805‧‧‧ keyboard

810‧‧‧ e-book terminal

811‧‧‧ Shell

812‧‧‧Shell

813‧‧‧Display Department

814‧‧‧Display Department

815‧‧‧Axis

816‧‧‧Power switch

817‧‧‧ operation keys

818‧‧‧Speaker

820‧‧‧TV

821‧‧‧ Shell

822‧‧‧Display Department

823‧‧‧ bracket

824‧‧‧Remote operator

830‧‧‧ Subject

831‧‧‧ Display Department

832‧‧‧Speaker

833‧‧‧ microphone

834‧‧‧ operation button

841‧‧‧ Subject

842‧‧‧Display Department

843‧‧‧Operation switch

900‧‧‧Wireless sensor

901‧‧‧Antenna

902‧‧‧ Circuit Department

903‧‧‧ sensor

910‧‧‧Input/Output Department

911‧‧‧Rectifier circuit

912‧‧‧Limiter circuit

913‧‧‧Demodulation circuit

914‧‧‧Modulation circuit

920‧‧‧ analogy

921‧‧‧Power circuit

922‧‧‧Oscillation circuit

923‧‧‧Voltage detection circuit

924‧‧‧Reset circuit

925‧‧‧ buffer circuit

930‧‧‧ Memory Department

931‧‧‧Charge pump circuit

940‧‧‧Logic Department

950‧‧‧A/D converter

961‧‧‧Voltage generation circuit

962‧‧‧Voltage generation circuit

971‧‧‧Voltage generation circuit

981‧‧‧CRC circuit

982‧‧‧Decoder circuit

983‧‧‧ Controller

984‧‧‧Output signal generation circuit

985‧‧‧Selector Circuit

986‧‧‧CRC register

987‧‧‧ Clock generation circuit

1A and 1B are block diagrams and timing diagrams for explaining one embodiment of the present invention; and FIGS. 2A and 2B are circuit diagrams and timing diagrams for explaining one embodiment of the present invention; 4 is a circuit diagram for explaining one embodiment of the present invention; FIG. 4 is a circuit diagram for explaining one embodiment of the present invention; FIG. 5 is a circuit diagram for explaining one embodiment of the present invention; FIG. 7 is a circuit diagram for explaining one embodiment of the present invention; FIGS. 8A to 8F are circuit diagrams for explaining one embodiment of the present invention; and FIG. 9 is a circuit diagram for explaining the present invention. a block diagram of an embodiment; 10A to 10C are circuit diagrams for explaining one embodiment of the present invention; FIGS. 11A to 11C are diagrams for explaining one embodiment of the present invention; and FIG. 12 is a schematic view for explaining an embodiment of the present invention; 13A to 13D are plan views for explaining one embodiment of the present invention; Fig. 14 is a schematic cross-sectional view for explaining one embodiment of the present invention; and Fig. 15 is a cross section for explaining an embodiment of the present invention; Figure 16 is a block diagram for explaining one embodiment of the present invention; Figures 17A and 17B are circuit diagrams for explaining one embodiment of the present invention; and Figures 18A to 18C are diagrams for explaining an embodiment of the present invention; 19A and 19B are circuit diagrams for explaining one embodiment of the present invention; FIG. 20 is a circuit diagram for explaining one embodiment of the present invention; and FIG. 21 is a view for explaining an embodiment of the present invention. FIG. 22 is a circuit diagram for explaining one embodiment of the present invention; FIG. 23 is a circuit diagram for explaining one embodiment of the present invention; FIG. 25A and FIG. 25B are flowcharts and perspective views for explaining one embodiment of the present invention; FIGS. 26A to 26E are diagrams of an electronic device to which one embodiment of the present invention can be applied; 27A to 27C are circuit diagrams for explaining one embodiment of the present invention; and Fig. 28 is a circuit diagram for explaining one embodiment of the present invention.

Hereinafter, an embodiment will be described with reference to the drawings. However, the embodiments may be implemented in a plurality of different manners, and those skilled in the art can easily understand that the manner and details can be changed to various types without departing from the spirit and scope of the invention. form. Therefore, the present invention should not be construed as being limited to the contents described in the embodiments shown below.

In addition, in the present specification and the like, ordinal numbers such as "first", "second", and "third" are added to avoid confusion of constituent elements. Therefore, this is not attached to limit the number of constituent elements. Further, this is not added to limit the order of the constituent elements. For example, a constituent element having "first" in one of the embodiments of the present specification and the like may have "second" attached to other embodiments or patent applications. Further, for example, constituent elements with "first" attached to one of the embodiments of the present specification and the like may be omitted in other embodiments or patent applications.

In the drawings, the same elements, elements having the same functions, elements of the same material, elements formed at the same time, and the like are denoted by the same reference numerals, and the repeated description may be omitted.

[Embodiment 1] In this embodiment, a semiconductor device according to an embodiment of the disclosed invention will be described. In particular, in the present embodiment, a configuration of a semiconductor device including an output circuit that outputs a signal to a memory cell will be described.

FIG. 1A shows an output circuit 100 and a memory cell MC. The memory unit MC includes a transistor OM. The transistor OM is connected to the wiring BL and the node MN. In the output circuit 100, a signal is input to the terminal 1N and output to the wiring WL _ret connected to the gate of the transistor OM.

In addition, the transistor OM has a function as a switch. The transistor OM is preferably a transistor having a small current (off-state current) flowing between the source and the drain in a closed state. As the transistor having a small off-state current, a transistor (OS transistor) containing an oxide semiconductor in the channel formation region is preferable. The OS transistor has an advantage that the off-state current is small and can be manufactured in such a manner as to overlap with the Si transistor. The OS transistor will be described in detail in the following embodiments.

In the memory cell MC, a voltage (data voltage) corresponding to the material applied to the wiring BL is written to the node MN or held by controlling the turn-on or turn-off of the transistor OM. In the case where the transistor OM is an n-channel transistor, the transistor is turned on by applying a high level potential to the wiring WL _{ret which is} the gate of the transistor OM, thereby writing the data voltage. Further, by continuously applying a low level potential to the wiring WL _ret , the transistor is turned off, whereby the data voltage is held.

The output circuit 100 is a circuit that outputs a signal to the wiring WL _ret . The output circuit 100 can maintain the transistor OM in a closed state by setting the low level potential supplied to the wiring WL _ret to the ground potential even if the operation of the output circuit is intentionally stopped. Alternatively, in the case where the power supply voltage cannot be continuously supplied as in the case of the wireless device, the transistor OM can be continuously kept in the off state even if the operation of the output circuit 100 is intermittently stopped. Therefore, even if the supply of the power supply voltage to the output circuit 100 is stopped, the data voltage stored in the memory cell MC can be held.

Since the output circuit 100 writes the data voltage by turning on the transistor, a signal having a large amplitude is required. In the output circuit 100, different power supply voltages are supplied to a plurality of circuits to obtain a signal having a large amplitude. As an example, the output circuit 100 includes a buffer circuit BUF1, a level shift circuit LS, and a buffer circuit BUF2.

The buffer circuit BUF1 is connected to the wiring VH1, and controls the supply of the power supply voltage to the buffer circuit BUF1. The level transfer circuit LS and the buffer circuit BUF2 are connected to the wiring VH2, and control the supply of the power supply voltage to the level transfer circuit LS and the buffer circuit BUF2. When the power supply voltage is supplied, the voltage VDD1 is supplied to the wiring VH1, and the voltage VDD2 is supplied to the wiring VH2. When the power supply voltage is stopped, the wirings VH1 and VH2 are all set to the ground voltage.

When the supply and stop of the power supply voltage are alternately performed, the potential of each node in the output circuit 100 is unstable. In particular, in the node that is affected by the wiring VH2 that performs the voltage rise and fall, an unintended potential fluctuation occurs instantaneously due to the potential fluctuation, and a high level signal is output to the wiring WL _ret . Therefore, the off state of the transistor OM becomes unstable, and sometimes the data voltage of the memory cell MC disappears.

In one embodiment of the present invention, when the power supply voltage is supplied again, the timing at which the wiring VH1 is set to the voltage VDD1 is made different from the timing at which the wiring VH2 is set to the voltage VDD2. The operation will be described with reference to the timing chart shown in FIG. 1B.

In the timing chart shown in FIG. 1B, a case where the signal of the terminal IN is at a low level will be described. In the initial state before time T7, the voltages of the wirings VH1, VH2 are at a low level.

At time T7, the wiring VH1 is set to the voltage VDD1. The output of the buffer circuit BUF1 is determined by the voltage rise of the wiring VH1.

By determining the output of the buffer circuit BUF1, the operation of the level transfer circuit LS becomes stable. That is, the level shift circuit LS is in a state of stably outputting a voltage of a signal corresponding to the terminal IN. At time T7, the voltage of the wiring VH2 is set to the ground voltage. Therefore, the signal output from the buffer circuit BUF2 to the wiring WL _ret can be kept at a low level.

Next, at time T8, the wiring VH2 is set to the voltage VDD2. At the timing of time T7, the output of the buffer circuit BUF1 is supplied to the level shift circuit LS, and stable operation can be performed. Here, the low level potential is supplied to the terminal IN, and the buffer circuit BUF1 operates in a manner of outputting a low level potential from the level transfer circuit LS. Therefore, the output of the level transfer circuit LS is not affected even when the potential of the wiring VH2 rises. The buffer circuit BUF2 supplied with the low level potential output from the level transfer circuit LS can output the low level potential to the wiring WL _ret .

Therefore, when the supply of the power supply voltage is restarted in order to switch the signal level, the wiring WL _ret can be continuously maintained at a low level. Therefore, it is possible to prevent the disappearance of data due to _{unintentional} output to the wiring WL _ret due to the high level potential.

In addition, FIG. 2A shows an example of a circuit diagram of the output circuit 100 of FIG. 1A. The buffer circuit BUF1 in FIG. 2A includes inverter circuits 11, 12. The level transfer circuit LS in FIG. 2A includes a transistor M1 to a transistor M6. The buffer circuit BUF2 in FIG. 2A includes inverter circuits 13, 14. As shown in FIG. 2A, the power supply voltage is supplied from the wirings VH1, VH2 to the respective circuits.

The output circuit 100 shown in FIG. 2A has a function of outputting a low level signal to the wiring WL _ret by supplying a low level signal to the terminal IN. The level transfer circuit LS includes a node OUT and a node OUTB. In the level shift circuit LS, the potential of the node OUT is made low by the signal output from the buffer circuit BUF1, and then the wiring VH2 is set to the voltage VDD2, whereby a stable low level signal can be output to the wiring WL _ret .

FIG. 2B shows a timing diagram illustrating the operation of the output circuit 100 shown in FIG. 2A.

In the timing chart shown in FIG. 2B, the case where the signal of the terminal IN is a low level will be described. In the initial state before time T9, the voltages of the wirings VH1, VH2 are at a low level. At this time, the nodes OUT and OUTB are in an electrically floating state. In addition, the wiring WL _{ret is} in an electrically floating state. The wiring WL _ret eventually becomes a low level potential due to a leakage current or the like flowing through the buffer circuit BUF2, and becomes a floating state. Therefore, in FIG. 2B, the wiring WL _{ret is} illustrated as a low level potential.

At time T9, the wiring VH1 is set to the voltage VDD1. The output of the inverter circuits 11, 12 is determined by the voltage rise of the wiring VH1. The gates of the transistors M2 and M3 are supplied with a low level potential, and the gates of the transistors M5 and M6 are supplied with a high level potential. Therefore, the transistor M2 M6 is turned on, and transistors M3 and M5 are turned off. Therefore, the potential of the node OUT becomes a low level as the ground voltage.

Next, at time T10, the wiring VH2 is set to the voltage VDD2. At the timing of time T9, the node OUT is at a low level, and the transistor M1 is turned on as the potential of the wiring VH2 rises. Then, the node OUTB becomes a high level. The transistor M4 is turned off.

Before the wiring VH2 is set to the voltage VDD2, the wiring VH1 is set to the voltage VDD1, whereby the state of the voltage of the node OUT can be determined before the wiring VH2 is set to the voltage VDD2. Therefore, the output of the level transfer circuit LS is not affected even when the potential of the wiring VH2 rises. The buffer circuit BUF2 supplied with the low level potential output from the level transfer circuit LS can output the low level potential to the wiring WL _ret .

Therefore, when the supply of the power supply voltage is resumed in order to switch the signal level, the potential of the wiring WL _ret can be continuously maintained at a low level. Therefore, it is possible to prevent the disappearance of data due to _{unintentional} output to the wiring WL _ret due to the high level potential.

Further, although the configuration of the capacitive element having no voltage for holding the nodes OUT, OUTB is explained in the circuit diagram shown in FIG. 2A, it may have a capacitive element. FIG. 3 shows a circuit diagram having capacitive elements C1, C2 in the circuit diagram of FIG. 2A. One electrode of the capacitive element C1 is connected to the node OUTB, and the other electrode is connected to the wiring VH2. One electrode of the capacitive element C2 is connected to the node OUT, and the other electrode is connected to a wiring for supplying a ground voltage.

By adopting the structure of the circuit diagram shown in FIG. 3, immediately after the time T10 of FIG. 2B, the node in the electrically floating state can be raised by the capacitive coupling in the capacitive element C1 as the voltage of the wiring VH2 rises. The voltage of OUTB.

Further, the transistor M1 to the transistor M6 preferably include germanium in the channel formation region. The transistor (Si transistor). By adding impurities or the like, variations in the threshold voltage of the Si transistor at the time of manufacturing in the same process can be reduced. Further, it is preferable that the capacitor elements C1 and C2 are stacked on the transistor M1 to the transistor M6. By adopting such a configuration, it is possible to suppress an increase in the layout area due to the addition of the capacitive elements C1 and C2.

It is preferable that the capacitance elements C1, C2 overlapping the transistor M1 to the transistor M6 are disposed in the same layer as the OS transistor of the memory cell MC. When the structure is employed, it is preferable to dispose one electrode of the capacitor element in the same layer as the gate electrode of the OS transistor, and to set the other electrode of the capacitor element to the source electrode of the OS transistor and the anode. The pole electrodes are in the same layer. By adopting such a structure, the same layer as the gate insulating layer of the OS transistor can be used to form an insulating layer between the electrodes constituting the capacitor element. Since the gate insulating layer is thinner than the interlayer insulating layer, the capacitance value per unit area can be increased.

Further, in the present embodiment, by setting the node OUT to a low level, the wiring WL _ret becomes a low level because the buffer circuit BUF2 includes an inverter circuit of an even-numbered stage (two stages in FIG. 2A). If the buffer circuit BUF2 includes an odd-numbered inverter circuit, the wiring WL _ret becomes a low level when the node OUT is at a high level. Therefore, it suffices to change the arrangement of the capacitance elements C1, C2 in accordance with the number of stages of the inverter circuit of the buffer circuit BUF2.

Further, in order to confirm the effects of the embodiment of the present invention described above, the simulation was performed using a computer. 11A to 11C are diagrams showing changes in voltage of the wiring WL _ret when the timings at which the voltages of the wirings VH1 and VH2 are raised from the ground voltage are different in the circuit diagram shown in FIG. 2A.

FIG. 11A shows a voltage change of the wiring WL _ret (in the drawing, the wiring WWL in the drawing) when the voltages of the wirings VH1 and VH2 are raised from the ground voltage at the same timing. FIG. 11B shows a voltage change of the wiring WL _ret (in the drawing, denoted as the wiring WWL) when the voltage of the wiring VH2 is raised from the ground voltage before the voltage of the wiring VH1 is raised. FIG. 11C shows a voltage change of the wiring WL _ret (in the drawing, denoted as the wiring WWL) when the voltage of the wiring VH1 is raised from the ground voltage before the voltage of the wiring VH2 is raised. In FIGS. 11A to 11C, "V1" represents the voltage of the wiring VH1, and "V2" represents the voltage of the wiring VH2.

As shown in FIGS. 11A to 11C, in the case where the voltages of the wirings VH1, VH2 are raised from the ground voltage at the same timing or the voltage of the wiring VH2 is raised from the ground voltage before the voltage of the wiring VH1 is raised, , confirm the voltage change to WWL. On the other hand, when the voltage of the wiring VH1 is raised from the ground voltage before raising the voltage of the wiring VH2, the voltage of WWL is constant, which is 0 V of the ground voltage. Therefore, when the voltage of the wiring VH1 is raised from the ground voltage before raising the voltage of the wiring VH2, it is confirmed that the potential of the wiring WL _ret can be continuously maintained at a low level.

[Embodiment 2] In this embodiment, a modified example of the output circuit described in the first embodiment, an example of the memory cell MC, an example of a semiconductor device including the memory cell MC, and a modified example of the memory cell MC will be described. .

<Modification Example of Output Circuit> FIGS. 4 to 8F and FIG. 28 show a modified example of the circuit configuration that can be employed in the output circuit explained in FIGS. 1A and 1B.

4 shows the configuration when the positions of the capacitive elements C1, C2 are changed in the configuration of the circuit diagram shown in FIG. 3 and the buffer circuit BUF2 includes a one-stage inverter circuit. In the circuit diagram shown in FIG. 4, the capacitive element C1 is disposed between the wiring VH2 and the node OUT. In the circuit diagram shown in FIG. 4, the capacitive element C2 is disposed between the ground line and the node OUTB.

By adopting the configuration of FIG. 4, the potential of the node OUT can be raised to a high level potential when the wiring VH2 is set to the voltage VDD2. As the potential of the node OUT and the wiring VH2 rises due to the capacitive coupling generated in the capacitive element C1, the transistor M1 can be more reliably turned off. By determining the node OUT as a high level, the signal outputted to the wiring WL _ret by the inverter circuit 13 can be kept at a low level.

Fig. 5 shows the structure in which the transistors M2, M5 are omitted in the circuit diagrams explained in Figs. 2A and 2B. Even if the number of transistors is reduced as shown in FIG. 5, the potential fluctuations of the nodes OUT and OUTB can be suppressed. Therefore, the disappearance of data due to the high-level potential output to the wiring WL _ret can be prevented, and the number of components of the semiconductor device can be reduced.

Further, as shown in FIG. 6, it is also effective to apply the configuration of the omitted transistors M2, M5 shown in FIG. 5 to the configuration of the circuit diagram explained in FIG. That is, even in the configuration in which the positions of the capacitance elements C1, C2 are changed and the buffer circuit BUF2 includes the one-stage inverter circuit, the transistor can be omitted. Therefore, the disappearance of data due to the high-level potential output to the wiring WL _ret can be prevented, and the number of components of the semiconductor device can be reduced.

In the structure shown in FIG. 5, the transistor M4 and the transistor M6 can function as a buffer by making the channel width of the transistors M4, M6 larger than the channel width of the transistors M1, M3. As a result, the buffer circuit BUF2 can be omitted as shown in FIG. FIG. 7 shows a circuit diagram of an output circuit in which the buffer circuit BUF2 is omitted. It is possible to prevent the disappearance of data due to the high level potential output to the wiring WL _ret and to reduce the number of components of the semiconductor device.

Further, as shown in FIG. 28, a transistor M7 may be added. The transistor M7 is controlled to be in an on state when the wiring WL _ret is at a low level by the control signal EN. By adopting this configuration, it is possible to more reliably make the wiring WL _ret a low level.

<An Example of Memory Cell MC> Next, FIGS. 8A to 8F are shown in FIG. 1A and An example of a circuit configuration that can be employed by the memory cell MC illustrated in FIG. 1B. In the circuit diagram of the memory cell shown in FIGS. 8A to 8F, writing or reading of the material voltage can be controlled by writing the material voltage from the wiring SL or the wiring BL and controlling the voltages of the wiring WWL and the wiring RWL.

The memory cell MC_A shown in FIG. 8A includes a transistor 15, a transistor OM, and a capacitor element 17. The transistor 15 is a p-channel transistor. By turning off the transistor OM, the charge corresponding to the data voltage can be held in the node FN. The structure of FIG. 8A can be applied to the memory cell MC of FIGS. 1A and 1B.

The memory cell MC_B shown in FIG. 8B includes a transistor 15_A, a transistor OM, and a capacitor element 17. The transistor 15_A is an n-channel transistor. By turning off the transistor OM, the charge corresponding to the data voltage can be held in the node FN. The structure of FIG. 8B can be applied to the memory cell MC of FIGS. 1A and 1B.

The memory cell MC_C shown in FIG. 8C includes a transistor 15, a transistor OM_B, and a capacitor element 17. The transistor OM_B has a back gate, and the back gate can be controlled by the wiring BGL. By adopting this structure, the threshold voltage of the transistor OM_B can be controlled. By turning off the transistor OM_B, the charge corresponding to the data voltage can be held in the node FN. The structure of FIG. 8C can be applied to the memory cell MC of FIGS. 1A and 1B.

The memory cell MC_D shown in FIG. 8D includes a transistor 15_A, a transistor OM, a capacitor element 17, and a transistor 18_A. The transistor 18_A is the same as the transistor 15_A and is an n-channel transistor. By turning off the transistor OM, the charge corresponding to the data voltage can be held in the node FN. The structure of FIG. 8D can be applied to the memory cell MC of FIGS. 1A and 1B. In addition, as shown in the circuit diagram shown in Fig. 27A, the position of the transistor 18_A can be changed.

The memory cell MC_E shown in FIG. 8E includes a transistor 15, a transistor OM, and a capacitor. Element 17 and transistor 18_B. The transistor 18_B is the same as the transistor 15, and is a p-channel transistor. By turning off the transistor OM, the charge corresponding to the data voltage can be held in the node FN. The structure of FIG. 8E can be applied to the memory cell MC of FIGS. 1A and 1B. Further, as shown in the circuit diagram of the memory cell MC_K shown in Fig. 27B, the position of the transistor 18_B can be changed.

The memory cell MC_F shown in FIG. 8F includes a transistor 15, a transistor OM, and a capacitor element 17. The transistor 15 is connected to the wiring BL_A, and the transistor OM is connected to the wiring BL_B. In the configuration of FIG. 8F, for example, the wiring RBL can be used as a wiring for reading data voltage, and the wiring WBL can be used as a wiring for writing data voltage. By turning off the transistor OM, the charge corresponding to the data voltage can be held in the node FN. The structure of FIG. 8F can be applied to the memory cell MC of FIGS. 1A and 1B. Further, as shown in the circuit diagram of the memory cell MC_L shown in FIG. 27C, the transistor 18_B can be added.

<An example of a block diagram including the memory cell MC> FIG. 9 is a block diagram showing a configuration example of a semiconductor device when the memory cell MC_A of FIG. 8A is applied to the memory cell MC described in FIGS. 1A and 1B.

The semiconductor device 200 shown in FIG. 9 includes a memory cell array 201 provided with a plurality of memory cells MC, an output circuit 100, a row selection driver 202, and a column selection driver 203. The semiconductor device 200 includes memory cells MC arranged in a matrix of m rows×n columns. In addition, in FIG. 9, the wiring WWL, the wiring RWL, the wiring BL, and the wiring SL are shown in the (m-1)th row of the wiring WWL[m-1], the wiring RWL[m-1], and the mth row. Wiring WWL[m], wiring RWL[m], wiring (BL-1) of the (n-1)th column, wiring BL[n] of the nth column, and wiring SL[n of the (n-1)th column -1] and the wiring SL[n] of the nth column.

In the memory cell array 201 shown in FIG. 9, the memory cells MC are set as a matrix shape. The description of each configuration of the memory cell MC is the same as that of FIG. 8A.

Further, in the memory cell array 201 shown in FIG. 9, an output circuit 100 is provided between the row selection driver 202 that outputs a write word signal, and between the wiring WWL[m-1] and the wiring WWL[m]. By adopting this configuration, the signal output from the output circuit 100 can be supplied to the gate of the transistor OM included in the memory cell MC.

The row selection driver 202 is a circuit that outputs a signal for selecting the memory cells MC of the respective rows. The column selection driver 203 is a circuit that outputs a signal for writing a material voltage to the memory cell MC and reading the material voltage from the memory cell MC. The row selection driver 202 and the column selection driver 203 include circuits such as decoders, and can output signals or data voltages to respective rows and columns.

<Other Modification Examples of Memory Cell MC> FIGS. 10A to 10C show examples of circuit configurations different from those of FIGS. 8A to 8F which can be employed by the memory cell MC illustrated in FIGS. 1A and 1B.

The memory cell MC_G shown in FIG. 10A includes a transistor OM and a capacitor element 19. The memory cell MC_G controls the voltage of the wiring WWL to control writing of the material voltage from the wiring BL to the node FN, and reading the material voltage from the node FN to the wiring BL. By turning off the transistor OM, the charge corresponding to the data voltage can be held in the node FN. The structure of FIG. 10A can be applied to the memory cell MC of FIGS. 1A and 1B.

The memory cell MC_H shown in FIG. 10B includes an SRAM, a transistor OM1, a transistor OM2, a capacitance element 19_1, and a capacitance element 19_2. The SRAM includes a transistor SW1, a transistor SW2, an inverter circuit INV1, and an inverter circuit INV2. The memory cell MC_H backs up the data voltages of the nodes Q, QB of the SRAM to the nodes FN1, FN2 by controlling the voltage of the wiring WWL and restores the data voltage from the nodes FN1, FN2 to the nodes Q, QB. By making the transistors OM1, OM2 Turning off, the charge corresponding to the data voltage can be held in the nodes FN1, FN2. The structure of FIG. 10B can be applied to the memory cell MC of FIGS. 1A and 1B.

The memory cell MC_I shown in FIG. 10C includes an SRAM, a transistor OM3, an inverter circuit INV3, a capacitive element 19_3, and a transistor SW3. The memory cell MC_I backs up the data voltage of the node Q or the node QB of the SRAM to the node FN3 and restores the data voltage from the node FN3 to the node Q or the node QB by controlling the voltages of the wiring WWL and the wiring REN. By turning off the transistor OM3, the charge corresponding to the data voltage can be held in the node FN3. The structure of FIG. 10C can be applied to the memory cell MC of FIGS. 1A and 1B.

As described above, one embodiment of the present invention can be operated with various modified examples.

[Embodiment 3] In this embodiment, an OS transistor described in the above embodiment will be described.

<About Off-State Current Characteristics> In the OS transistor, by reducing the impurity concentration in the oxide semiconductor, the oxide semiconductor is made essential or substantially essential, and the off-state current can be reduced. Here, "substantially essential" means that the carrier density in the oxide semiconductor is less than 8 × 10 ¹¹ /cm ³ , preferably less than 1 × 10 ¹¹ /cm ³ , more preferably less than 1 × 10 ¹⁰ /cm ³ is 1 × 10 ^-9 /cm ³ or more. In the oxide semiconductor, hydrogen, nitrogen, carbon, ruthenium, and a metal element other than the main component are impurities. For example, hydrogen and nitrogen cause the formation of a donor energy level and increase the carrier density.

A transistor using an oxide semiconductor having an essential or substantially essential nature has a low carrier density, and thus the transistor rarely has an electrical characteristic of a negative threshold voltage. Further, since the oxide semiconductor of the transistor using the oxide semiconductor has few carrier traps, it is possible to realize a transistor having low variation in electrical characteristics and high reliability. A transistor using the oxide semiconductor can be turned off The state current is very small.

Further, in the OS transistor in which the off-state current is reduced, the normalized off-state current per 1 μm of the channel width can be set to 1 × 10 ^-18 A or less, preferably 1 at room temperature (about 25 ° C). ×10 ^-21 A or less, more preferably 1 × 10 ^-24 A or less, or 1 × 10 ^-15 A or less, preferably 1 × 10 ^-18 A or less, more preferably at a temperature of 85 ° C It is 1 × 10 ^-21 A or less.

<Off-State Current> In the present specification, the off-state current refers to a drain current when the transistor is in a closed state (also referred to as a non-conduction state or an off state) unless otherwise specified. Unless otherwise specified, in the n-channel transistor, the off state refers to a state in which the voltage Vgs between the gate and the source is lower than the threshold voltage Vth. In the p-channel transistor, the off state refers to the gate. A state in which the voltage Vgs between the source and the source is higher than the threshold voltage Vth. For example, the off-state current of the n-channel transistor sometimes refers to the drain current when the voltage Vgs between the gate and the source is lower than the threshold voltage Vth.

The off-state current of the transistor sometimes depends on Vgs. Therefore, when there is a Vgs in which the off-state current of the transistor is 1 or less, the off-state current of the transistor is sometimes referred to as I or less. The off-state current of a transistor sometimes refers to an off-state current when Vgs is a prescribed value; an off-state current when Vgs is a value within a prescribed range; or when Vgs is capable of obtaining a sufficiently reduced off-state current The off-state current when the value is.

As an example, consider an n-channel transistor with a threshold voltage Vth of 0.5V, a drain current of 1×10 ^-9 A at a Vgs of 0.5V, and a drain current of 0.1V at a Vgs of 0.1V. of 1 × 10 ^-13 a, Vgs is the drain current at -0.5V was 1 × 10 ^-19 a, Vgs is the drain current at -0.8V is 1 × 10 ^-22 A. When the Vgs is -0.5 V or the Vgs is -0.5 V to -0.8 V, the transistor has a drain current of 1 × 10 ^-19 A or less, so the off-state current of the transistor is sometimes referred to as 1 × 10 ^-19 A or less. Since the gate current of the transistor is Vgs of 1 × 10 ^-22 A or less, the off-state current of the transistor is sometimes referred to as 1 × 10 ^-22 A or less.

In the present specification, the off-state current of the transistor having the channel width W is sometimes expressed by the value of the width W per channel. Further, the off-state current of the transistor having the predetermined channel width W may be expressed by a current value per predetermined channel width (for example, 1 μm). In the latter case, the unit of the off-state current is sometimes expressed in terms of current/length (for example, A/μm).

The off-state current of a transistor sometimes depends on the temperature. In the present specification, the off-state current sometimes indicates an off-state current at room temperature, 60 ° C, 85 ° C, 95 ° C or 125 ° C unless otherwise specified. Or, it is sometimes indicated that the temperature at which the reliability of the semiconductor device including the transistor or the like is ensured or the temperature of the semiconductor device including the transistor (for example, any one of 5 ° C to 35 ° C) is used. State current. The temperature at which the reliability of the semiconductor device including the transistor or the semiconductor device or the like including the transistor is used at room temperature, 60 ° C, 85 ° C, 95 ° C, and 125 ° C (for example, 5 ° C to 35) When any of the temperatures of °C is present, when the off-state current of the transistor is Vgs of 1 or less, the off-state current of the transistor is sometimes referred to or less.

The off-state current of the transistor sometimes depends on the voltage Vds between the drain and the source. In the present specification, the off-state current sometimes indicates that the absolute value of Vds is 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, unless otherwise specified. Off current at 16V or 20V. Alternatively, it is sometimes indicated that the off-state current when Vds including the reliability of the semiconductor device or the like of the transistor or the Vds used in the semiconductor device including the transistor is secured. When the Vds of the transistor is set to a predetermined value, and the off-state current of the transistor is Vgs of 1 or less, the off-state current of the transistor may be referred to as I or less. Here, for example, the predetermined values are: 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, 20V, warranty package The value of Vds of the reliability of the semiconductor device or the like of the transistor or the value of Vds used in a semiconductor device or the like including the transistor.

In the above description of the off-state current, the drain can be referred to as a source. That is to say, the off-state current sometimes refers to the current flowing through the source when the transistor is in the off state.

In the present specification, the off-state current may be described as a leakage current in the same sense as the off-state current.

In the present specification, an off-state current, for example, sometimes refers to a current flowing between a source and a drain when the transistor is in a closed state.

<Composition of Oxide Semiconductor> Further, the oxide semiconductor used for the semiconductor layer of the OS transistor preferably contains at least indium (In) or zinc (Zn). It is especially preferred to include In and Zn. Further, in addition to the above elements, it is preferred to further contain a stabilizer which strongly binds oxygen. The stabilizer may be at least one of gallium (Ga), tin (Sn), zirconium (Zr), hafnium (Hf), and aluminum (Al).

Further, as other stabilizers, lanthanum (La), cerium (Ce), strontium (Pr), strontium (Nd), strontium (Sm), europium (Eu), strontium (Gd), strontium may be contained. One or more of (Tb), Dy, Ho, Er, Tm, Yb, and Lu.

For example, as the oxide semiconductor used for the semiconductor layer of the transistor, for example, indium oxide, tin oxide, zinc oxide, an In-Zn-based oxide, a Sn-Zn-based oxide, an Al-Zn-based oxide, or Zn- can be used. Mg-based oxide, Sn-Mg-based oxide, In-Mg-based oxide, In-Ga-based oxide, In-Ga-Zn-based oxide (also referred to as IGZO), In-Al-Zn-based oxide, In-Sn-Zn-based oxide, Sn-Ga-Zn-based oxide, Al-Ga-Zn-based oxide, Sn-Al-Zn-based oxide, In-Hf-Zn-based Oxide, In-Zr-Zn-based oxide, In-Ti-Zn-based oxide, In-Sc-Zn-based oxide, In-Y-Zn-based oxide, In-La-Zn-based oxide, In- Ce-Zn-based oxide, In-Pr-Zn-based oxide, In-Nd-Zn-based oxide, In-Sm-Zn-based oxide, In-Eu-Zn-based oxide, In-Gd-Zn-based oxidation , In-Tb-Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Zn-based oxide, In-Tm-Zn-based oxide, In-Yb -Zn-based oxide, In-Lu-Zn-based oxide, In-Sn-Ga-Zn-based oxide, In-Hf-Ga-Zn-based oxide, In-Al-Ga-Zn-based oxide, In- Sn-Al-Zn-based oxide, In-Sn-Hf-Zn-based oxide, In-Hf-Al-Zn-based oxide, or the like.

For example, it is possible to use an atomic ratio of In:Ga:Zn=1:1:1, In:Ga:Zn=3:1:2, In:Ga:Zn=4:2:3 or In:Ga: An In-Ga-Zn-based oxide of Zn=2:1:3 or an oxide having a composition similar thereto.

<Impurity in Oxide Semiconductor> When a large amount of hydrogen is contained in the oxide semiconductor film constituting the semiconductor layer, the hydrogen is bonded to the oxide semiconductor to cause a part of the hydrogen to be a donor, and thus electrons as carriers are generated. As a result, the threshold voltage of the transistor is caused to drift in the negative direction. Therefore, it is preferable to perform high-purification by removing dehydration treatment (dehydrogenation treatment) after forming the oxide semiconductor film, and removing hydrogen or moisture from the oxide semiconductor film so as not to contain impurities as much as possible.

Further, in some cases, the oxide semiconductor film is dehydrated (dehydrogenation treatment), and oxygen is also reduced from the oxide semiconductor film. Therefore, it is preferable to perform a process of adding oxygen to the oxide semiconductor film in order to fill in oxygen defects which are increased by dehydration treatment (dehydrogenation treatment) of the oxide semiconductor film.

As described above, by performing dehydration treatment (dehydrogenation treatment) to remove hydrogen or moisture from the oxide semiconductor film, and performing oxidation treatment to fill oxygen defects, an i-type (essential) oxide semiconductor film or An i-type (essential) oxide semiconductor film that is infinitely close to the i-type. Note that "substantially essential" means that in the oxide semiconductor film, the carrier from the donor is extremely small (near zero), and the carrier density is less than 8 × 10 ¹¹ /cm ³ , preferably less than 1 ×10 ¹¹ /cm ³ , more preferably less than 1 × 10 ¹⁰ /cm ³ , is 1 × 10 ^-9 /cm ³ or more.

<Structure of Oxide Semiconductor> The structure of the oxide semiconductor will be described.

In the present specification, "parallel" means a state in which the angle formed by two straight lines is -10° or more and 10° or less. Therefore, the case where the angle is -5 or more and 5 or less is also included. In addition, “substantially parallel” means a state in which the angle formed by the two straight lines is -30° or more and 30° or less. Further, "vertical" means a state in which the angle of the two straight lines is 80° or more and 100° or less. Therefore, the case where the angle is 85° or more and 95° or less is also included. In addition, "substantially perpendicular" means a state in which the angle formed by the two straight lines is 60° or more and 120° or less.

Further, in the present specification, when the crystal is a trigonal system and a rhombohedral system, it is represented as a hexagonal system.

The oxide semiconductor film can be classified into a non-single-crystal oxide semiconductor film and a single-crystal oxide semiconductor film. Alternatively, the oxide semiconductor can be classified into, for example, a crystalline oxide semiconductor and an amorphous oxide semiconductor.

Examples of the non-single-crystal oxide semiconductor include CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor), polycrystalline oxide semiconductor, microcrystalline oxide semiconductor, and amorphous oxide semiconductor. . Examples of the crystalline oxide semiconductor include a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, and a microcrystalline oxide semiconductor.

First, the CAAC-OS film will be described.

The CAAC-OS film is one of oxide semiconductor films including a plurality of crystal portions of the c-axis alignment.

By observing a composite image of a bright field image of a CAAC-OS film and a diffraction pattern by a transmission electron microscope (TEM: Transmission Electron Microscope) (also referred to as a high-resolution TEM image), a plurality of crystal parts can be observed. . On the other hand, even a high-resolution TEM image does not reveal a clear boundary between the crystal portion and the crystal portion, that is, a grain boundary. Therefore, it can be said that in the CAAC-OS film, the decrease in the electron mobility due to the grain boundary is less likely to occur.

When the high-resolution TEM image of the cross section of the CAAC-OS film was observed from the direction substantially parallel to the sample surface, it was confirmed that the metal atoms were arranged in a layered shape in the crystal portion. Each metal atomic layer has a convex or concave shape reflecting a surface on which a CAAC-OS film is formed (also referred to as a formed surface) or a CAAC-OS film, and is formed in a plane parallel to the CAAC-OS film or CAAC. - The arrangement of the top surface of the OS film.

On the other hand, when the high-resolution TEM image of the plane of the CAAC-OS film was observed from a direction substantially perpendicular to the sample surface, it was confirmed that the metal atoms were arranged in a triangular shape or a hexagonal shape in the crystal portion. However, the arrangement of metal atoms between different crystal parts is not regular.

Structural analysis of the CAAC-OS membrane was performed using an X-ray Diffraction (XRD) apparatus. For example, when the CAAC-OS film including InGaZnO4 crystal is analyzed by the out-of-plane method (out-of-plane method), there is a case where a peak appears at a diffraction angle (2θ) of 31°. Since the peak is derived from the (009) plane of the InGaZnO4 crystal, it is understood that the crystal in the CAAC-OS film has c-axis orientation and the c-axis is oriented substantially perpendicular to the formed or top surface of the CAAC-OS film. The direction.

Further, when the CAAC-OS film including InGaZnO4 crystal was analyzed by the out-of-plane method, in addition to the peak near 2θ of 31°, a peak appeared in the vicinity of 2θ of 36°. A peak in the vicinity of 2θ of 36° indicates that a part of the CAAC-OS film contains crystals having no c-axis alignment property. Preferably, in the CAAC-OS film, a peak appears in the vicinity of 2θ of 31° and a peak does not occur in the vicinity of 2θ of 36°.

The CAAC-OS film is an oxide semiconductor film having a low impurity concentration. The impurity refers to an element other than the main component of the oxide semiconductor film such as hydrogen, carbon, ruthenium or a transition metal element. In particular, an element having a stronger binding force with oxygen than oxygen, which is a combination of a metal element constituting the oxide semiconductor film and oxygen, causes crystallinity to disturb the atomic arrangement of the oxide semiconductor film by abstracting oxygen from the oxide semiconductor film. The main factor of reduction. In addition, heavy metals such as iron or nickel, argon, carbon dioxide, and the like have a large atomic radius (or molecular radius), and when they are contained inside the oxide semiconductor film, they become a main factor that disrupts the atomic arrangement of the oxide semiconductor film and causes a decrease in crystallinity. Further, the impurities contained in the oxide semiconductor film sometimes become a carrier trap or a carrier generation source.

Further, the CAAC-OS film is an oxide semiconductor film having a low defect state density. For example, an oxygen defect in an oxide semiconductor film may become a carrier trap or a carrier generation source by trapping hydrogen.

A state in which the impurity concentration is low and the defect state density is low (the oxygen deficiency is small) is referred to as "high purity essence" or "substantially high purity essence". An oxide semiconductor film having a high-purity essence or a substantially high-purity essence has a small carrier generation source and thus can have a low carrier density. Therefore, the transistor using the oxide semiconductor film rarely has an electrical characteristic of a negative threshold voltage (also referred to as a normally-on characteristic). In addition, an oxide semiconductor having a high purity essence or a substantially high purity essence The membrane has fewer carrier traps. Therefore, the transistor using the oxide semiconductor film is a transistor having a small variation in electrical characteristics and high reliability. Further, it takes a long time for the charge trapped by the carrier trap of the oxide semiconductor film to be released, and it may operate like a fixed charge. Therefore, the electrical characteristics of a transistor using an oxide semiconductor film having a high impurity concentration and a high defect state density may be unstable.

Further, in a transistor using a CAAC-OS film, fluctuations in electrical characteristics due to irradiation with visible light or ultraviolet light are small.

Next, the microcrystalline oxide semiconductor film will be described.

In the high-resolution TEM image of the microcrystalline oxide semiconductor film, a region where the crystal portion can be observed and a region where the crystal portion is not observed are observed. The size of the crystal portion included in the microcrystalline oxide semiconductor film is usually 1 nm or more and 100 nm or less, or 1 nm or more and 10 nm or less. In particular, an oxide semiconductor film having a crystal size of 1 nm or more and 10 nm or less or 1 nm or more and 3 nm or less of microcrystals is referred to as nc-OS (nanocrystalline Oxide Semiconductor). Semiconductor) film. Further, for example, in a high-resolution TEM image of an nc-OS film, a clear grain boundary may not be observed.

The nc-OS film has a periodic arrangement of atoms in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). In addition, the regularity of crystal alignment was not observed between the different crystal portions of the nc-OS film. Therefore, no alignment property was observed on the entire film. Therefore, sometimes the nc-OS film and the amorphous oxide semiconductor film cannot be distinguished due to the analysis method. For example, when the nc-OS film is subjected to structural analysis using an XRD apparatus having a beam diameter larger than that of the crystal portion, when the analysis is performed by the out-of-plane method, the peak indicating the crystal plane is not detected. In addition, if the beam spot diameter is larger than the crystal portion (for example, 50 nm or more) The sub-rays are electronically diffracted to the nc-OS film (also referred to as selected area electron diffraction), and a diffraction pattern such as a halo pattern is observed. On the other hand, if the electron beam of the beam spot diameter close to the crystal portion or smaller than the crystal portion is used to perform nanobeam electron diffraction on the nc-OS film, spots are observed. Further, when the nc-OS film is subjected to nanobeam electron diffraction, a region having a high (bright) brightness such as a circle may be observed. Further, if the nc-OS film is subjected to nanobeam electron diffraction, a plurality of spots are sometimes observed in the annular region.

The nc-OS film is an oxide semiconductor film whose regularity is higher than that of the amorphous oxide semiconductor film. Therefore, the defect state density of the nc-OS film is lower than that of the amorphous oxide semiconductor film. However, the regularity of crystal alignment was not observed between the different crystal portions of the nc-OS film. Therefore, the defect state density of the nc-OS film is higher than that of the CAAC-OS film.

Next, an amorphous oxide semiconductor film will be described.

The amorphous oxide semiconductor film is an oxide semiconductor film in which atoms in the film are disorderly arranged and does not have a crystal portion. An example of this is an oxide semiconductor film having an amorphous state such as quartz.

In the high-resolution TEM image of the amorphous oxide semiconductor film, no crystal portion was observed.

The amorphous oxide semiconductor film was subjected to structural analysis using an XRD device. When the analysis was performed by the out-of-plane method, the peak indicating the crystal plane was not detected. Further, if the amorphous oxide semiconductor film is subjected to electron diffraction, a halo pattern is observed. Further, if the amorphous oxide semiconductor film was subjected to nanobeam electron diffraction, no spots were observed, and a halo pattern was observed.

Further, the oxide semiconductor film sometimes has a structure exhibiting physical properties between the nc-OS film and the amorphous oxide semiconductor film. An oxide semiconductor film having such a structure is particularly referred to as Amorphous-like oxide semiconductor (a-like OS: amorphous-like Oxide Semiconductor) film.

In high-resolution TEM images of a-like OS films, voids (also called voids) are sometimes observed. Further, in the high-resolution TEM image of the a-like OS film, a region in which the crystal portion is clearly confirmed and a region in which the crystal portion is not confirmed are confirmed. The a-like OS film may be crystallized by a small amount of electron irradiation at the TEM observation degree, whereby the growth of the crystal portion is observed. On the other hand, in the case of a good nc-OS film, crystallization due to a small amount of electron irradiation by the TEM observation was hardly observed.

Further, the measurement of the size of the crystal portion of the a-like OS film and the nc-OS film can be performed using a high-resolution TEM image. For example, InGaZnO4 crystal has a layered structure with two Ga-Zn-O layers between the In-O layers. The unit cell of the InGaZnO4 crystal has a structure in which a total of nine layers of three In-O layers and six Ga-Zn-O layers are stacked in a c-axis direction. Therefore, the interval between the layers close to each other is substantially equal to the interplanar spacing (also referred to as the d value) of the (009) plane, and the value is obtained from the crystal structure analysis, that is, 0.29 nm. Therefore, focusing on the lattice fringes of the high-resolution TEM image, each lattice fringe corresponds to the a-b plane of the InGaZnO4 crystal in a region where the lattice fringe interval is 0.28 nm or more and 0.30 nm or less.

Further, the density of the oxide semiconductor film sometimes differs depending on the structure. For example, when the composition of a certain oxide semiconductor film is known, the structure of the oxide semiconductor film can be estimated by comparison with the density of the single crystal oxide semiconductor film having the same composition. For example, the density of the a-like OS film is 78.6% or more and less than 92.3% of the density of the single crystal oxide semiconductor film. Further, for example, the density of the nc-OS film and the density of the CAAC-OS film are 92.3% or more and less than 100% of the density of the single crystal oxide semiconductor film. Further, forming a density lower than that of the single crystal oxide semiconductor film An oxide semiconductor film having a density of 78% is difficult.

The above content will be described using a specific example. For example, in the oxide semiconductor film in which the atomic number ratio satisfies In:Ga:Zn=1:1:1, the density of the single crystal InGaZnO 4 having a rhombohedral structure is 6.357 g/cm 3 . Therefore, for example, in the oxide semiconductor film in which the atomic number ratio satisfies In:Ga:Zn=1:1:1, the density of the a-like OS film is 5.0 g/cm 3 or more and less than 5.9 g/cm 3 . Further, for example, in the oxide semiconductor film in which the atomic number ratio satisfies In:Ga:Zn=1:1:1, the density of the nc-OS film and the density of the CAAC-OS film are 5.9 g/cm3 or more and less than 6.3. g/cm3.

Further, a single crystal oxide semiconductor film of the same composition sometimes does not exist. At this time, by combining the single crystal oxide semiconductor films having different compositions in an arbitrary ratio, the density of the single crystal oxide semiconductor film corresponding to the desired composition can be calculated. For the ratio of the single crystal oxide semiconductor films having different combinations, the density of the single crystal oxide semiconductor film having a desired composition can be calculated using a weighted average. However, it is preferable to calculate the density by combining a small number of single crystal oxide semiconductor films as much as possible.

In addition, the oxide semiconductor film may be, for example, a laminated film of two or more kinds including an amorphous oxide semiconductor film, an a-like OS film, a microcrystalline oxide semiconductor film, and a CAAC-OS film.

As described above, the OS transistor can achieve extremely excellent off-state current characteristics.

[Embodiment 4] In this embodiment, a schematic diagram of an output circuit described in the above embodiment, a schematic diagram showing a layout of each layer, a layout diagram, and a schematic cross-sectional view corresponding to a layout diagram will be described with reference to Figs. 12 to 15 . one example.

Figure 12 is a schematic diagram of the level transfer circuit LS of the output circuit. FIG. 12 shows a layer 301 including a Si transistor, a wiring layer 302, and a layer 303 including a capacitive element. The layer 301 and the layer 303 are connected by a conductive layer and a wiring layer 302 provided in the opening. As shown in Figure 12, layers can be stacked 301, wiring layer 302 and layer 303. Therefore, there is an advantage that even if a capacitor element is added in order to prevent data loss due to erroneous operation of the semiconductor device, the layout area is not increased.

13A through 13D illustrate layers in the layout of Fig. 12. FIG. 13A shows a configuration of a conductive layer and an opening in a layer including the capacitive elements C1, C2. Fig. 13B shows the arrangement of the conductive layer and the opening portion in the wiring layer under the layer shown in Fig. 13A. Fig. 13C shows the arrangement of the conductive layer and the opening portion in the wiring layer under the layer shown in Fig. 13B. Fig. 13D shows the arrangement of the conductive layer and the semiconductor layer constituting the transistor M1 to the transistor M6, the conductive layer corresponding to the wiring VH2 and the ground line, and the opening portion, which are located under the layer shown in Fig. 13C. In addition, FIG. 13D shows terminals IN, INB, nodes OUT, OUTB.

Fig. 14 is a schematic cross-sectional view taken along the one-dot chain line X1-X2 of Figs. 13A to 13D. Fig. 15 is a cross-sectional view showing the alternate long and short dash line Y1-Y2 of Figs. 13A to 13D.

In FIGS. 14 and 15, a substrate 21, an impurity region 23, an impurity region 24, an insulating layer 25, an insulating layer 27, a conductive layer 29, an insulating layer 31, an insulating layer 33, an insulating layer 35, an insulating layer 37, and a conductive layer are illustrated. The layer 39, the conductive layer 41, the conductive layer 43, the insulating layer 45, and the conductive layer 47.

As the substrate 21, for example, a single crystal germanium substrate (including a p-type semiconductor substrate or an n-type semiconductor substrate), a compound semiconductor substrate made of tantalum carbide or gallium nitride, or SOI (Silicon On Insulator) can be used. A substrate or a glass substrate or the like.

The impurity region 23 and the impurity region 24 are formed in the semiconductor layer. As the semiconductor layer, an amorphous semiconductor, a microcrystalline semiconductor, a polycrystalline semiconductor, or the like can be used. For example, amorphous germanium or microcrystalline germanium or the like can be used. Further, a compound semiconductor such as tantalum carbide, gallium arsenide, an oxide semiconductor, or a nitride semiconductor, or an organic semiconductor can also be used. Further, in FIGS. 14 and 15, the transistors M3, M4 are shown, and the polarities of these transistors are different. In this case, by making the impurity region 23 and the impurity region 24 The impurities introduced in the process are different to separate the n-channel transistor and the p-channel transistor.

The conductive layer 29, the conductive layer 39, the conductive layer 41, the conductive layer 43, and the conductive layer 47 are preferably made of a metal material such as aluminum, copper, titanium, tantalum or tungsten. Further, polycrystalline germanium to which an impurity such as phosphorus is added may be used. As the formation method, various film formation methods such as a vapor deposition method, a PE-CVD method, a sputtering method, and a spin coating method can be employed.

The insulating layer 25, the insulating layer 27, the insulating layer 31, the insulating layer 33, the insulating layer 35, the insulating layer 37, and the insulating layer 45 preferably form an inorganic insulating layer or an organic insulating layer in a single layer or a plurality of layers. As the inorganic insulating layer, a tantalum nitride film, a hafnium oxynitride film, a hafnium oxynitride film, or the like is preferably formed in a single layer or a plurality of layers. As the organic insulating layer, it is preferred to form a polyimide or an acrylic resin in a single layer or a plurality of layers. Further, the method for producing each insulating layer is not particularly limited, and for example, a sputtering method, an MBE method, a PE-CVD method, a pulsed laser deposition method, an ALD method, or the like can be suitably used.

Further, when the capacitive elements C1, C2 and the OS transistor are formed in the same layer, the conductive layer 43 and the gate electrode of the OS transistor are preferably disposed in the same layer. Moreover, when the capacitive elements C1, C2 and the OS transistor are disposed in the same layer, the conductive layer 47 and the source electrode or the drain electrode of the OS transistor are preferably disposed in the same layer. By adopting such a structure, the same insulating layer can be used for the insulating layer 45 between the conductive layer 43 and the conductive layer 47 and the gate insulating layer of the OS transistor. Since the gate insulating layer is thinner than the interlayer insulating layer, the capacitive elements C1 and C2 which can obtain a larger capacitance value can be formed.

[Embodiment 5] Fig. 16 is a block diagram of a wireless sensor in which a memory unit is mounted, in which a signal is output from the output circuit described in the above embodiment.

The line sensor 900 includes an antenna 901, a circuit portion 902, and a sensor 903. The circuit unit 902 has a function of processing a signal received by the antenna 901, and generates a signal based on the received signal. The function of responding to the data and the function of transmitting the response data from the antenna 901. The circuit unit 902 includes, for example, an input/output unit (IN/OUT) 910, an analog unit 920, a memory unit 930, a logic unit 940, and an A/D converter 950.

<Input/Output Unit> The input/output unit 910 includes a rectifier circuit 911, a limiter circuit 912, a demodulation converter circuit 913, and a modulation circuit 914. FIG. 17A is a circuit diagram showing a configuration example of the rectifier circuit 911 and the limiter circuit 912. 17B is a circuit diagram showing a configuration example of the demodulation circuit 913 and the modulation circuit 914.

The rectifier circuit 911 is a circuit that rectifies an input signal (carrier ANT) from the antenna 901 to generate a voltage VIN. The voltage VIN is output to each circuit of the analog portion 920.

The limiter circuit 912 is a protection circuit for preventing the voltage VIN from becoming a large voltage.

The demodulation conversion circuit 913 is a circuit for demodulating the carrier ANT received by the antenna 901. The demodulation circuit 913 generates the demodulated signal DEMOD_OUT and outputs it to the analog portion 920.

The modulation circuit 914 is a circuit for modulating the response data (digital signal) MOD_OUT output from the logic unit 940 and transmitting it using the carrier ANT. As the modulation method, for example, an ASK (Amplitude Shift Keying) method can be employed.

The analogy section analogy section 920 includes a power supply circuit 921, an oscillation circuit 922, a voltage detection circuit 923, a reset circuit 924, and a buffer circuit 925.

FIG. 18A is a block diagram showing a structural example of the power supply circuit 921. The power supply circuit 921 is a circuit that generates an operating voltage of the memory unit 930, the logic unit 940, and the A/D converter 950. Here, the power supply circuit 921 generates two operating voltages (VDD, VDD_ADC) from the voltage VIN. The power supply circuit 921 includes: a voltage generating circuit that generates a bias voltage BIAS and a reference voltage REF from the voltage VIN 961; and voltage generating circuits 962, 963 for generating an operating voltage from the bias voltage BIAS, the reference voltage REF, and the voltage VIN.

FIG. 18B is a circuit diagram showing an example of the configuration of the voltage generating circuit 961. 18C is a circuit diagram showing an example of the configuration of the voltage generating circuits 962, 963.

The oscillation circuit 922 is a circuit that generates a reference clock signal (ORIGIN_CLK) from the voltage VDD generated by the power supply circuit 921. FIG. 19A shows an example of the configuration of the oscillation circuit 922, and FIG. 19B shows an example of the configuration of the voltage generation circuit 971 which generates the bias voltage (BIASP, BIASN) of the oscillation circuit 922.

FIG. 20 is a circuit diagram showing an example of the configuration of the voltage detecting circuit 923. The voltage detecting circuit 923 has a function of detecting whether the voltage VIN is larger than a predetermined value or smaller than a predetermined value and generating a digital signal corresponding to the detection result. This digital signal is used as a trigger signal for causing the logic portion 940 to operate. The voltages BIAS and REF are input from the voltage generating circuit 961 of the power supply circuit 921 to the comparator of the voltage detecting circuit 923. In the example of FIG. 20, the voltage detecting circuit 923 includes a comparator. The comparator generates and outputs a signal VIN_SENSE.

The reset circuit 924 has a function of monitoring the voltage generated in the power supply circuit 921 and generating a reset signal for resetting the logic portion 940. FIG. 21 is a circuit diagram showing an example of the configuration of the reset circuit 924. In this example, the reset circuit 924 detects the rise of the voltage VDD and generates a reset signal INI_RESET.

The buffer circuit 925 is a circuit for transmitting the signal DEMOD_OUT demodulated in the demodulation circuit 913 to the logic portion 940. FIG. 22 is a circuit diagram showing an example of the configuration of the buffer circuit 925. In the buffer circuit 925, the signal DEMOD_OUT becomes the signal DEMOD_SIG0 by the second-stage inverter and is input to the logic portion 940.

<Memory Unit> The memory unit 930 includes a charge pump circuit 931 in addition to the memory unit. Regarding the structure of the memory unit, reference can be made to the above-described first embodiment.

The charge pump circuit 931 is a circuit for boosting the operating voltage VDD to generate a voltage required to drive the memory portion 930. FIG. 23 is a circuit diagram showing an example of the configuration of the charge pump circuit 931. In the charge pump circuit 931, the operating voltage VDD is boosted to become the voltage V _MEM and input to the memory circuit.

By generating the voltage supplied to the memory portion 930 by the charge pump circuit 931, the power consumption of the wireless sensor 900 can be reduced. The memory portion 930 operates using a higher voltage (2.5V to 4V) than other circuits. Although it is also possible to adopt a configuration in which a high voltage is generated in the power supply circuit 921 and supplied to the memory portion 930 in advance, the power consumed in the power supply circuit 921, the oscillation circuit 922, or the voltage detection circuit becomes large in this configuration, and thus the efficiency is low. . On the other hand, in the configuration shown in FIG. 16, a low voltage (1.2 V) is generated in the power supply circuit 921 and the voltage is stepped down or boosted in the charge pump circuit 931 located before the memory portion 930. Therefore, the power consumed by the wireless sensor 900 is low, so the efficiency is high.

The output circuit described in the above first embodiment is used in the drive circuit for driving the memory unit. In the output circuit, voltages are supplied from the power supply circuit 921 to the wiring VH1 and supplied from the charge pump circuit 931 to the wiring VH2, respectively. The wireless sensor 900 generates a voltage using a wireless signal. Therefore, if the supply of the wireless signal is interrupted, the voltages supplied to the wirings VH1 and VH2 become the ground voltage. In the wireless sensor, when a wireless signal is supplied again, a voltage is generated. Since the output circuit described above is included, even if a voltage is supplied to the wirings VH1, VH2, it is possible to prevent the potential of the high level from being unintentionally outputted, whereby the data of the memory unit can be prevented from disappearing.

<Logic Unit> FIG. 24 is a block diagram showing an example of the configuration of the logic unit 940. logic The portion 940 includes a CRC circuit 981, a decoder circuit 982, a controller 983, an output signal generating circuit 984, a selector circuit 985, and a CRC register 986 clock generation circuit 987.

The decoder circuit 982 is a circuit that performs decoding of the signal DEMOD_SIG0. The decoded signal is input to the controller 983 and the CRC circuit 981.

The CRC circuit 981 is a circuit that calculates a CRC (Cyclic Redundancy Check) code based on an input signal from the decoder circuit 982. The CRC code calculated by the CRC circuit 981 is output to the controller 983.

The controller 983 is a circuit that controls the entire logic unit 940.

The CRC register 986 is a register that functions as a CRC area in which the CRC code is stored.

The clock generation circuit 987 has a function of generating a clock signal used in the logic unit 940 from the signal ORIGIN_CLK.

Access to the memory portion 930 and the CRC register 986 is performed by the selector circuit 985. The controller 983 and the output signal generating circuit 984 output an access request signal (Acc_Rq) to the selector circuit 985. The selector circuit 985 writes the memory data (Mem_D) to the memory unit 930 or the CRC register 986 or reads the memory data (Mem_D) from the memory unit 930 or the CRC register 986 in accordance with the access request signal.

<A/D Converter> The A/D converter 950 has a function of converting a sensor signal SENSOR of an analog voltage output from the sensor 903 into a digital signal and outputting it.

The A/D converter 950 has a function of converting the potential of the sensor signal SENSOR as an analog value into a digital value and outputting it to the outside. In addition to the flash A/D converter, the A/D converter 950 can also use a successive comparison A/D converter, multi-slope A/D conversion. Converter and Delta-sigma A/D converter.

The wireless sensor described above can perform intermittent operation by receiving a wireless signal without causing the data held in the memory portion 930 to disappear.

[Embodiment 6] Although the conductive layer or the semiconductor layer disclosed in the above embodiment may be formed by a sputtering method, for example, it may be formed by another method such as a thermal CVD method. Examples of the thermal CVD method include a MOCVD (Metal Organic Chemical Vapor Deposition) method or an ALD (Atomic Layer Deposition) method.

Since the thermal CVD method is a film formation method that does not use plasma, it has the advantage that no defects are generated due to plasma damage.

The thermal CVD method can form a film by setting the pressure in the processing chamber to atmospheric pressure or reduced pressure, and simultaneously supplying the material gas and the oxidizing agent into the processing chamber to cause a reaction in the vicinity of the substrate or on the substrate to be deposited. On the substrate.

Further, the ALD method can form a film by setting the pressure in the processing chamber to atmospheric pressure or reduced pressure, sequentially introducing the material gas for the reaction into the processing chamber, and repeating the order of gas introduction. For example, by switching each of the on-off valves (also referred to as a high-speed valve), two or more kinds of material gases are sequentially supplied to the processing chamber, and inertia is introduced at the same time as or after the introduction of the first material gas without mixing the plurality of material gases. A gas (argon gas, nitrogen gas, etc.) or the like is then introduced into the second material gas. Further, when the first source gas and the inert gas are simultaneously introduced, the inert gas becomes a carrier gas, and an inert gas may be introduced while introducing the second source gas. Alternatively, instead of introducing an inert gas, the first material gas may be discharged by vacuum evacuation, and then the second material gas may be introduced. The first material gas is adsorbed to the surface of the substrate to form a first single atom The layer, the second raw material gas introduced thereafter, reacts with the first monoatomic layer, whereby the second monoatomic layer is laminated on the first monoatomic layer to form a thin film. By controlling the order in which the gas is introduced and repeating it a plurality of times until it becomes a desired thickness, a film having a good step coverage can be formed. Since the thickness of the film can be adjusted by repeating the order of the gas introduction order, the ALD method can precisely adjust the film thickness and is suitable for the case of manufacturing a minute FET.

The conductive film or the semiconductor film disclosed in the above-described embodiments can be formed by a thermal CVD method such as MOCVD or ALD. For example, when an InGaZnO _X (X>0) film is formed, trimethylindium and three are used. Methyl gallium and dimethyl zinc. Further, the chemical formula of trimethylindium is In(CH ₃ ) ₃ . In addition, the chemical formula of trimethylgallium is Ga(CH ₃ ) ₃ . Further, the chemical formula of dimethyl zinc is Zn(CH ₃ ) ₂ . Further, it is not limited to the above combination, and triethylgallium (chemical formula Ga(C ₂ H ₅ ) ₃ ) may be used instead of trimethylgallium, and diethylzinc (chemical formula Zn(C ₂ H ₅ ) ₂ ) may be used. ) instead of dimethyl zinc.

For example, when a tungsten film is formed by a deposition apparatus using ALD, an initial tungsten film is sequentially formed by sequentially introducing WF ₆ gas and B ₂ H ₆ gas, and then a WF ₆ gas and a H ₂ gas are repeatedly introduced in order to form a tungsten film. Alternatively, SiH ₄ gas may be used instead of B ₂ H ₆ gas.

For example, when an oxide semiconductor film such as an InGaZnO _X (X>0) film is formed by a deposition apparatus using ALD, In(CH ₃ ) ₃ gas and O ₃ gas are repeatedly introduced in this order to form an InO ₂ layer, and then sequentially introduced again. The Ga(CH ₃ ) ₃ gas and the O ₃ gas form a GaO layer, and then Zn(CH ₃ ) ₂ gas and O ₃ gas are repeatedly introduced in order to form a ZnO layer. In addition, the order of these layers is not limited to the above examples. Further, these gases may be mixed to form a mixed compound layer such as an InGaO ₂ layer, an InZnO ₂ layer, a GaInO layer, a ZnInO layer, or a GaZnO layer. Further, although H ₂ O gas obtained by bubbling with an inert gas such as Ar may be used instead of O ₃ gas, it is preferable to use O ₃ gas not containing H. Alternatively, In(C ₂ H ₅ ) ₃ gas may be used instead of In(CH ₃ ) ₃ gas. Further, a Ga(C ₂ H ₅ ) ₃ gas may be used instead of the Ga(CH ₃ ) ₃ gas. Further, Zn(CH ₃ ) ₂ gas can also be used.

[Embodiment 7] In this embodiment, an example in which the semiconductor device described in the above embodiment is applied to an electronic component and an example of an electronic device including the electronic component will be described with reference to FIGS. 25A to 26E.

In Fig. 25A, an example in which the semiconductor device described in the above embodiment is applied to an electronic component will be described. In addition, electronic components are also referred to as semiconductor packages or IC packages. The electronic component has a plurality of specifications and names depending on the terminal take-out direction or the shape of the terminal. In the present embodiment, an example thereof will be described.

The semiconductor device including the transistor shown in FIGS. 12 to 15 of the above-described fourth embodiment is completed through an assembly process (post process). Further, the electronic component is completed by combining a plurality of components or semiconductor devices detachable with respect to the printed circuit board.

The post process can be completed by performing the various processes shown in Fig. 25A. Specifically, after the element substrate obtained by the pre-process is completed (step S1), the back surface of the substrate is polished (step S2). By thinning the substrate in this step, it is used to reduce the warpage of the substrate or the like which is generated in the previous process, thereby achieving downsizing of the component.

A dicing process of polishing the back surface of the substrate and dividing the substrate into a plurality of wafers is performed. Further, a die bonding process in which each of the cut wafers is picked up and attached to the lead frame is performed (step S3). The bonding of the wafer to the lead frame in the wafer bonding process can be appropriately selected according to the product, such as adhesion using a resin or adhesion using a tape. Further, in the wafer bonding process, each wafer may be mounted on an interposer to achieve bonding.

Next, wire bonding is performed to electrically connect the leads of the lead frame and the electrodes on the wafer by metal wires (step S4). As the metal thin wire, a silver wire or a gold wire can be used. Further, the wire bonding may use ball bonding or wedge bonding.

The wire bonding wafer is subjected to a molding process using an epoxy resin or the like (step S5). By performing the molding process, the inside of the electronic component is filled with the resin, and damage to the built-in circuit portion and the fine metal wires due to mechanical external force can be reduced, and deterioration of characteristics due to moisture or dust can be reduced.

Next, the lead of the lead frame is subjected to a plating treatment. Further, the lead wire is cut and molded (step S6). By this plating treatment, it is possible to prevent the lead from being rusted, so that soldering can be performed more reliably when the lead is mounted on the printed circuit board later.

Next, printing is performed on the package surface (step S7). Further, the electronic component is completed by the final inspection step (step S8) (step S9).

The electronic component described above may include the semiconductor device described in the above embodiment. Therefore, electronic components with less erroneous operation and low power consumption can be realized.

In addition, FIG. 25B shows a perspective view of the completed electronic component. In FIG. 25B, a stereo schematic diagram of a QFP (Quad Flat Package) is shown as an example of an electronic component. The electronic component 700 shown in FIG. 25B includes a lead 701 and a circuit portion 703. The electronic component 700 shown in FIG. 25B is mounted, for example, on a printed circuit board 702. By combining a plurality of such electronic components 700 and electrically connecting them to the printed circuit board 702, they can be mounted in an electronic device. The completed circuit board 704 is disposed inside the electronic device or the like.

Next, the use of the above electronic component for a computer, a portable information terminal (package) In the case of electronic devices such as mobile phones, portable game consoles, and audio reproduction devices, electronic paper, televisions (also known as televisions or television receivers), and digital cameras.

Fig. 26A shows a portable information terminal including a casing 801, a casing 802, a first display portion 803a, a second display portion 803b, and the like. The semiconductor device shown in the previous embodiment is provided in at least a portion of the outer casing 801 and the outer casing 802. Therefore, a portable information terminal with less erroneous work and low power consumption can be realized.

Further, the first display portion 803a is a panel having a touch input function. For example, as shown in the left diagram of FIG. 26A, the selection button 804 displayed by the first display portion 803a can select whether to perform "touch input" or "keyboard input". ". Since the selection buttons can be displayed in various sizes, people of all ages can feel easy to use. Here, for example, when "keyboard input" is selected, as shown in the right diagram of FIG. 26A, the keyboard 805 is displayed on the first display portion 803a. As a result, similarly to the conventional information terminal, text input or the like can be quickly performed by using keyboard input.

Further, as shown in the right diagram of FIG. 26A, the portable information terminal shown in FIG. 26A can be detached from one of the first display portion 803a and the second display portion 803b. By using the panel having the touch input function as the second display portion 803b, it is possible to further reduce the weight at the time of carrying, and it is convenient to hold the outer casing 802 with one hand and operate with the other hand.

The portable information terminal shown in FIG. 26A may have functions of displaying various information (such as still images, motion pictures, text images, etc.); displaying functions of calendar, date, time, etc. on the display unit; operation or editing is displayed in The function of displaying information on the part; the function of controlling the processing using various software (programs); and the like. Further, an external connection terminal (earphone terminal, USB terminal, etc.), a recording medium insertion portion, or the like may be provided on the back surface or the side surface of the casing.

In addition, the portable information terminal shown in FIG. 26A can be sent wirelessly. Or the composition of the received information. It is also possible to adopt a configuration in which a desired book material or the like is purchased and downloaded from an electronic book server by wireless means.

Further, the casing 802 shown in Fig. 26A may be provided with an antenna, a microphone function, and a wireless communication function to be used as a mobile phone.

Fig. 26B shows an electronic book terminal 810 on which electronic paper is mounted, which is composed of two outer casings, that is, a casing 811 and a casing 812. A display portion 813 and a display portion 814 are provided in the outer casing 811 and the outer casing 812, respectively. The outer casing 811 and the outer casing 812 are connected by a shaft portion 815, and can be opened and closed with the shaft portion 815 as an axis. Further, the housing 811 includes a power switch 816, an operation key 817, a speaker 818, and the like. The semiconductor device shown in the previous embodiment is provided in at least one of the outer casing 811 and the outer casing 812. Therefore, an e-book terminal with less erroneous work and low power consumption can be realized.

Fig. 26C shows a television set including a housing 821, a display portion 822, a bracket 823, and the like. The operation of the television set 820 can be performed by a switch or remote control operator 824 that the housing 821 has. The semiconductor device shown in the previous embodiment is provided in the casing 821 and the remote controller 824. Therefore, it is possible to realize a television set with less erroneous work and low power consumption.

Fig. 26D shows a smartphone, and a display portion 831, a speaker 832, a microphone 833, an operation button 834, and the like are provided on the main body 830 thereof. The semiconductor device shown in the previous embodiment is provided in the main body 830. Therefore, it is possible to realize a smart phone with less erroneous work and low power consumption.

FIG. 26E illustrates a digital camera including a main body 841, a display portion 842, an operation switch 843, and the like. The semiconductor device shown in the previous embodiment is provided in the main body 841. Therefore, a digital camera with less erroneous operation and low power consumption can be realized.

As described above, the semiconductor device of the previous embodiment is provided in the electronic device described in the present embodiment. Therefore, an electronic device with less erroneous operation and low power consumption can be realized.

Additional description of the description of the present specification and the like: Hereinafter, the description of each configuration in the above-described embodiments and embodiments will be additionally described.

<Additional Description of One Embodiment of the Present Invention Illustrated in the Embodiments> The configuration shown in each embodiment can be combined with the configuration shown in the other embodiments as appropriate to constitute one embodiment of the present invention. In addition, when a plurality of structural examples are shown in one embodiment, these structural examples may be combined with each other as appropriate.

In addition, the content (or a portion thereof) described in one embodiment may be applied to other content (or a part thereof) described in the embodiment and/or content described in one or more other embodiments (or a part thereof) Combining the content (or a portion thereof) described in one embodiment with the other content (or a portion thereof) described in the embodiment and/or the content (or a portion thereof) described in one or more other embodiments The content (or a portion thereof) described in the embodiment and/or the content (or a portion thereof) described in one or more other embodiments is replaced with the content (or a portion thereof) described in the embodiment.

In addition, the content described in the embodiment refers to the content described in each of the drawings or the contents described in the specification.

In addition, the drawings (or portions thereof) shown in one embodiment may be combined with other portions of the drawings, other drawings (or portions thereof) and/or one or more of the embodiments shown in the embodiments. Combinations of the drawings (or portions thereof) shown in other embodiments may constitute more figures.

Further, in the present embodiment, an embodiment of the present invention has been described. Alternatively, in another embodiment, an embodiment of the present invention will be described. However, one embodiment of the present invention is not limited to these. That is, in the present embodiment and other embodiments, Since various embodiments of the invention are described, an embodiment of the present invention is not limited to a specific embodiment. For example, as an embodiment of the present invention, an example in which an oxide semiconductor is formed in a channel formation region, a source region drain region, or the like of a transistor such as a transistor OM is shown, but an embodiment of the present invention is not limited thereto. Depending on the circumstances or conditions, various transistors of one embodiment of the present invention, a channel formation region of a transistor, or a source region drain region of a transistor or the like may contain various semiconductors. Depending on the circumstances or conditions, the various transistor of the embodiment of the present invention, the channel formation region of the transistor, or the source region of the transistor may also include germanium, antimony, bismuth, antimony carbide, gallium arsenide. At least one of aluminum gallium arsenide, indium phosphide, gallium nitride, and an organic semiconductor. Further, for example, depending on the circumstances or conditions, various transistors of one embodiment of the present invention, a channel formation region of a transistor, or a source region drain region of a transistor may not include an oxide semiconductor. Therefore, depending on the situation or condition, the transistor such as the transistor OM, the channel formation region of the transistor, or the source region drain region of the transistor may not include an oxide semiconductor. For example, although an example in which one embodiment of the present invention is applied to a memory unit is shown, an embodiment of the present invention is not limited thereto. For example, one embodiment of the present invention can also be applied to circuits having other functions depending on the situation or situation. Further, for example, one embodiment of the present invention may not be applied to the memory unit depending on the situation or the situation.

<Additional Description of the Description of the Drawings> In the present specification and the like, the words "upper", "lower", and the like are used to describe the positional relationship of the constituent elements for convenience of reference to the drawings. The positional relationship of the constituent elements is appropriately changed in accordance with the direction in which each constituent element is described. Therefore, the words indicating the arrangement are not limited to the descriptions described in the present specification, and the expressions can be appropriately changed depending on the situation.

In addition, the terms "upper" or "lower" do not limit the positional relationship of the constituent elements to "Up" or "down" and direct contact. For example, when it is described as "electrode B on the insulating layer A", the electrode B does not necessarily have to be formed in direct contact with the insulating layer A, and may include another constituent element between the insulating layer A and the electrode B.

Further, in the present specification and the like, the constituent elements are classified according to functions and are represented by blocks which are independent of each other in the block diagram. However, there are cases where it is difficult to distinguish constituent elements by function in an actual circuit or the like, one circuit involves a plurality of functions, or a plurality of circuits involve one function. Therefore, the blocks in the block diagram are not limited to the constituent elements described in the specification, and may be expressed in a different manner depending on the situation.

Moreover, for ease of explanation, the dimensions, thicknesses or regions of the layers are arbitrarily shown in the drawings. Therefore, the invention is not limited to the dimensions in the drawings. Further, the drawings are schematically shown for the sake of clarity, and are not limited to the shapes, numerical values, and the like shown in the drawings. For example, it may include signal, voltage or current unevenness caused by noise, or signal, voltage or current unevenness caused by time deviation, and the like.

In addition, in the drawings of a plan view (also referred to as a plan view, a floor plan) or a perspective view, some of the components may be omitted for clarity.

<Additional Explanation of Description That Can Be Expressed Another Way> In the present specification and the like, when describing the connection relationship of the transistors, it is described as "one of the source and the drain" (or the first electrode or the first terminal) or "The other of the source and drain" (or the second electrode or the second terminal). This is because the source and the drain of the transistor vary depending on the structure of the transistor, operating conditions, and the like. Further, depending on the case, the source and drain of the transistor may be appropriately referred to as a source (drain) terminal or a source (drain) electrode or the like.

In addition, in this specification and the like, terms such as "electrode" or "wiring" are not used. It is possible to limit its constituent elements. For example, "electrodes" are sometimes used as part of "wiring" and vice versa. Furthermore, the term "electrode" or "wiring" also includes a case where a plurality of "electrodes" or "wirings" are integrally formed.

Further, in the present specification and the like, the voltage and the potential can be appropriately changed. The voltage is a potential difference from the potential that becomes the reference. For example, when the potential to be the reference is the ground potential, the voltage can be referred to as the potential. The ground potential does not necessarily mean 0V. Further, the potentials are opposite, and the potential supplied to the wiring or the like may vary depending on the voltage to be the reference.

Further, in the present specification and the like, words such as "film" and "layer" may be interchanged depending on the situation or situation. For example, the term "conductive layer" may sometimes be changed to the term "conductive film". Further, for example, the term "insulating film" may be changed to the term "insulating layer".

<Additional Explanation of Definition of Words and Expressions> Next, definitions of words and phrases not mentioned in the above embodiment will be described.

<Regarding Switch> In the present specification and the like, the switch refers to an element having a function of controlling whether or not a current flows by changing to an on state (on state) or a non-conduction state (off state). Alternatively, a switch refers to an element having a function of selecting and switching a path through which a current flows.

For example, an electric switch or a mechanical switch or the like can be used. That is, the switch is not limited to a specific component as long as it can control the current.

Examples of electrical switches include transistors (eg, bipolar transistors or MOS transistors, etc.), diodes (eg, PN diodes, PIN diodes, Schottky diodes, metal-insulator-metals (MIM)) A diode, a metal-insulator-semiconductor (MIS) diode or a diode-connected transistor, or the like, or a logic circuit in which these elements are combined.

Further, when a transistor is used as a switch, the "on state" of the transistor means a state in which the source and the drain of the transistor are regarded as being electrically short-circuited. In addition, the "non-conducting state" of the transistor means that the source and the drain of the transistor are regarded as being electrically disconnected. Further, when the transistor is used only as a switch, there is no particular limitation on the polarity (conductivity type) of the transistor.

Examples of mechanical switches include switches that utilize MEMS (Micro Electro Mechanical Systems) technology, such as digital micromirror devices (DMDs). The switch has an electrically movable electrode and operates by controlling the conduction and non-conduction by moving the electrode.

<About channel length> In the present specification and the like, for example, the channel length means a region in which a semiconductor (or a portion where a current flows in a semiconductor when the transistor is in an on state) and a gate overlap in a plan view of the transistor or The distance between the source and the drain in the region where the channel is formed.

In addition, in a transistor, the channel length does not necessarily have the same value in all regions. That is to say, the channel length of one transistor is sometimes not limited to one value. Therefore, in the present specification, the channel length is determined to be any value, maximum value, minimum value, or average value in the region in which the channel is formed.

<About Channel Width> In the present specification and the like, for example, the channel width refers to a semiconductor (or a portion where a current flows in the semiconductor when the transistor is in an on state) and a region where the gate overlaps or a source in a region where the channel is formed. The length of the opposite part of the pole and the bungee.

In addition, in one transistor, the channel width does not necessarily have the same value in all regions. That is to say, the channel width of one transistor is sometimes not limited to one value. Therefore, in the present specification, the channel width is determined to be any value, maximum value, minimum value, or average value in the region in which the channel is formed.

In addition, depending on the structure of the transistor, the channel width in the region where the channel is actually formed (hereinafter referred to as the effective channel width) and the channel width shown in the top view of the transistor (hereinafter referred to as the channel width in appearance) different. For example, in a transistor having a three-dimensional structure, sometimes the effective channel width is larger than the apparent channel width shown in the top view of the transistor, and the influence thereof cannot be ignored. For example, in a transistor having a minute and three-dimensional structure, the proportion of the channel region formed on the side surface of the semiconductor sometimes becomes large. In this case, the effective channel width obtained when actually forming the channel is larger than the apparent channel width shown in the top view.

However, in a transistor having a three-dimensional structure, it is sometimes difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known in advance. Therefore, when the shape of the semiconductor is not clear, it is difficult to accurately measure the effective channel width.

Therefore, in the present specification, the length of the portion of the source opposite to the drain in the region where the semiconductor and the gate electrode overlap in the plan view of the transistor is sometimes referred to as the width of the channel in the appearance. SCW: Surrounded Channel Width)". Further, in the present specification, when only referred to as "channel width", it is sometimes referred to as the width of the channel around the width or appearance of the channel. Alternatively, in the present specification, when it is only described as "channel width", it sometimes means the effective channel width. Further, by taking a cross-sectional TEM image or the like and analyzing it, the channel length, the channel width, the effective channel width, the apparent channel width, the surrounding channel width, and the like can be determined.

In addition, when the field effect mobility of the transistor or the current value of each channel width or the like is obtained by calculation, it is sometimes calculated using the surrounding channel width. In this case, the value is sometimes different from the value calculated using the effective channel width.

<About Connection> In the present specification and the like, "A and B are connected" include a case where A and B are electrically connected in addition to the case where A and B are directly connected. Here, "A and B are electrically connected" means that when an object having a certain electrical action exists between A and B, an electrical signal can be transmitted and received between A and B.

Further, for example, the source (or the first terminal, etc.) of the transistor is electrically connected to X by Z1 (or not by Z1), the drain of the transistor (or the second terminal, etc.) by Z2 (or no When Z2 is electrically connected to Y, the source (or first terminal, etc.) of the transistor is directly connected to a part of Z1, and the other part of Z1 is directly connected to X, and the drain of the transistor (or the second terminal) When it is directly connected to a part of Z2 and another part of Z2 is directly connected to Y, it can be expressed as follows.

For example, it can be expressed as "X, Y, the source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.) are electrically connected to each other, and the source of the X, the transistor (or One terminal, etc.), the drain of the transistor (or the second terminal, etc.), and the order of Y are electrically connected. Alternatively, it can be expressed as "the source of the transistor (or the first terminal, etc.) is electrically connected to X, and the drain of the transistor (or the second terminal, etc.) is electrically connected to Y, with the source of X, the transistor (or The first terminal or the like), the drain of the transistor (or the second terminal, etc.), and the order of Y are electrically connected. Alternatively, it can be expressed as "X is electrically connected to Y by the source (or the first terminal, etc.) of the transistor and the drain (or the second terminal, etc.), according to the source of the X, the transistor (or the first terminal, etc.) ), the gate of the transistor (or the second terminal, etc.), and the connection order of Y are set. By specifying the connection order in the circuit structure using the same expression method as these examples, the source (or the first terminal, etc.) of the transistor and the drain (or the second terminal, etc.) can be distinguished to determine the technical range.

In addition, as another expression method, for example, it can be expressed as "the source of the transistor" (or the first terminal or the like) is electrically connected to X by at least a first connection path, the first connection path does not have a second connection path, and the second connection path is a source of a transistor through a transistor a path between (or a first terminal, etc.) and a drain (or a second terminal, etc.) of the transistor, the first connection path being a path through Z1, a drain of the transistor (or a second terminal, etc.) Connected to Y at least by a third connection path, the third connection path does not have the second connection path, and the third connection path is a path by Z2. Alternatively, it may also be expressed as a "transistor" The source (or the first terminal, etc.) is electrically connected to X by Z1 at least by the first connection path, the first connection path does not have a second connection path, and the second connection path has a transistor a connection path, a drain (or a second terminal, etc.) of the transistor is electrically connected to Y by at least a third connection path, and the third connection path does not have the second connection path". It can also be expressed as "the source of the transistor (or the first terminal, etc.) is at least by the first circuit Electrically coupled to X by Z1, the first circuit does not have a second circuit via, the second circuit is from the source (or first terminal, etc.) of the transistor to the drain of the transistor (or The circuit of the second terminal or the like is electrically connected to the drain (or the second terminal, etc.) of the transistor through at least the third circuit via Z2, and the third circuit does not have the fourth circuit. The fourth circuit is a circuit from a drain (or a second terminal, etc.) of the transistor to a source (or a first terminal, etc.) of the transistor. The circuit is specified by using the same expression method as these examples. The connection path in the structure can distinguish the source (or the first terminal, etc.) of the transistor and the drain (or the second terminal, etc.) to determine the technical range.

Further, these expression methods are merely examples, and are not limited to the above expression methods. Here, X, Y, Z1, and Z2 are objects (for example, devices, components, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

Claims (8)

A semiconductor device comprising: a first buffer circuit; a quasi-transfer circuit; a second buffer circuit; and a first wiring, a second wiring, and a third wiring, wherein the level transfer circuit and the The second buffer circuit is electrically connected to the second wiring and the third wiring, wherein the first buffer circuit is powered by converting a potential supplied to the first wiring from a third potential to a first potential a voltage, wherein a power supply voltage is applied to the level transfer circuit and the second buffer circuit by converting a potential supplied to the second wiring from the third potential to a second potential, wherein when supplied to the first After the potential of a wiring is converted from the third potential to the first potential, the potential supplied to the second wiring is converted from the third potential to the second potential, wherein the second potential is greater than the first potential The potential is high, and the third potential is lower than the first potential and the second potential. The semiconductor device of claim 1, further comprising: a memory unit, wherein the memory unit comprises a first transistor, wherein the memory unit is in a node connected to the first transistor in a closed state A charge corresponding to a data is maintained, wherein the second buffer circuit is electrically coupled to the gate of the first transistor. A semiconductor device comprising: a first buffer circuit; a quasi-transfer circuit; and a first wiring, a second wiring, and a third wiring, wherein the first buffer circuit and the first wiring and the third a wiring electrical connection, wherein the level transfer circuit is electrically connected to the second wiring and the third wiring, Wherein, at a first time, the potential of the first wiring is converted from a third potential to a first potential, wherein at a second time, the potential of the second wiring is converted from the third potential to a first potential a second potential, wherein the second time is after the first time, wherein the second potential is higher than the first potential, and the third potential is lower than the first potential and the second potential. The semiconductor device of claim 3, further comprising: a memory unit, wherein the memory unit comprises a first transistor, wherein the memory unit is held in a node connected to the first transistor in a closed state Corresponding to a charge of a data, wherein the level transfer circuit is electrically connected to the gate of the first transistor. The semiconductor device of claim 2, wherein the first transistor comprises an oxide semiconductor in the channel formation region. The semiconductor device of claim 2, wherein the level transfer circuit comprises a second transistor, and the second transistor comprises germanium. The semiconductor device according to claim 1 or 3, wherein the third potential is a ground potential. An electronic device comprising: the semiconductor device according to claim 1 or 3; and a display portion.