TWI668885B - Nitride semiconductor device and manufacturing method thereof and application package structure - Google Patents
Nitride semiconductor device and manufacturing method thereof and application package structure Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 1071
- 150000004767 nitrides Chemical class 0.000 title claims abstract description 1020
- 238000004519 manufacturing process Methods 0.000 title description 13
- 230000004888 barrier function Effects 0.000 claims abstract description 365
- 239000000463 material Substances 0.000 claims description 230
- 229910052782 aluminium Inorganic materials 0.000 claims description 83
- 229910052738 indium Inorganic materials 0.000 claims description 71
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- 230000000903 blocking effect Effects 0.000 claims description 64
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- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 claims description 40
- 229910052749 magnesium Inorganic materials 0.000 claims description 40
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- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 16
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
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- Led Devices (AREA)
Abstract
一種氮化物半導體元件，其包括P型氮化物半導體、N型氮化物半導體、氮化物半導體量子井發光結構、基板以及緩衝層。氮化物半導體量子井發光結構位於P型氮化物半導體以及N型氮化物半導體之間，且包括多個井層以及多個阻擋層。各個井層以及各個阻擋層彼此交錯配置。多個阻擋層包括配置於最接近P型氮化物半導體位置的第一阻擋層、配置於最接近N型氮化物半導體位置的第二阻擋層以及多個第三阻擋層。第一阻擋層的厚度小於100埃(Å)。各個第三阻擋層位於相鄰的兩個井層之間。緩衝層位於N型氮化物半導體以及基板之間。A nitride semiconductor device comprising a P-type nitride semiconductor, an N-type nitride semiconductor, a nitride semiconductor quantum well light-emitting structure, a substrate, and a buffer layer. The nitride semiconductor quantum well light emitting structure is located between the P-type nitride semiconductor and the N-type nitride semiconductor, and includes a plurality of well layers and a plurality of barrier layers. Each well layer and each barrier layer are staggered with each other. The plurality of barrier layers include a first barrier layer disposed closest to the P-type nitride semiconductor site, a second barrier layer disposed closest to the N-type nitride semiconductor site, and a plurality of third barrier layers. The first barrier layer has a thickness of less than 100 angstroms (Å). Each third barrier layer is located between two adjacent well layers. The buffer layer is between the N-type nitride semiconductor and the substrate.
Description
本發明有關於一種半導體元件及其製造方法，且特別是有關於一種可以提昇發光效率及改善製程良率的氮化物半導體元件及其製造方法。The present invention relates to a semiconductor device and a method of fabricating the same, and, in particular, to a nitride semiconductor device capable of improving luminous efficiency and improving process yield, and a method of fabricating the same.
發光二極體（light emitting diode；LED）具有諸如壽命長、體積小、高抗震性、低熱產生及低功率消耗等優點，因此已被廣泛應用於家用及各種設備中的指示器或光源。近年來，發光二極體已朝多色彩及高亮度發展，因此其應用領域已擴展至大型戶外看板、交通號誌燈及相關領域。在目前，發光二極體已經成為兼具省電及環保功能的主要照明光源。Light emitting diodes (LEDs) have advantages such as long life, small size, high shock resistance, low heat generation, and low power consumption, and thus have been widely used as indicators or light sources in households and various devices. In recent years, light-emitting diodes have developed toward multiple colors and high brightness, so their application fields have expanded to large outdoor billboards, traffic lights and related fields. At present, the light-emitting diode has become a main illumination source that has both power saving and environmental protection functions.
因此，如何進一步提升發光二極體的發光效率，實已成目前亟欲解決的課題。Therefore, how to further improve the luminous efficiency of the light-emitting diode has become a problem that is currently being solved.
本發明提供多種氮化物半導體元件，其可以提昇發光效率及改善製程良率。The present invention provides a plurality of nitride semiconductor elements which can improve luminous efficiency and improve process yield.
本發明還提供多種氮化物半導體元件的製造方法，其用以製作上述的氮化物半導體元件。The present invention also provides a method of fabricating a plurality of nitride semiconductor devices for fabricating the above-described nitride semiconductor device.
本發明還提供多種封裝結構，其應用於上述的氮化物半導體元件。The present invention also provides various package structures for use in the above-described nitride semiconductor device.
本發明提供一種氮化物半導體元件，其包括P型氮化物半導體、N型氮化物半導體、氮化物半導體量子井發光結構、基板以及緩衝層。氮化物半導體量子井發光結構位於P型氮化物半導體以及N型氮化物半導體之間。基板包含相對的第一面以及第二面。緩衝層位於N型氮化物半導體以及基板的第一面之間。氮化物半導體量子井發光結構具有多個井層以及多個阻擋層。多個阻擋層包含配置於最接近P型氮化物半導體的第一阻擋層、配置於最接近N型氮化物半導體位置的第二阻擋層以及多個第三阻擋層。多個第三阻擋層被多個井層夾住。第一阻擋層的厚度小於100埃(angstrom；Å)。The present invention provides a nitride semiconductor device including a P-type nitride semiconductor, an N-type nitride semiconductor, a nitride semiconductor quantum well light-emitting structure, a substrate, and a buffer layer. The nitride semiconductor quantum well light emitting structure is located between the P-type nitride semiconductor and the N-type nitride semiconductor. The substrate includes opposing first and second faces. The buffer layer is between the N-type nitride semiconductor and the first side of the substrate. The nitride semiconductor quantum well light emitting structure has a plurality of well layers and a plurality of barrier layers. The plurality of barrier layers include a first barrier layer disposed closest to the P-type nitride semiconductor, a second barrier layer disposed closest to the N-type nitride semiconductor site, and a plurality of third barrier layers. A plurality of third barrier layers are sandwiched by a plurality of well layers. The first barrier layer has a thickness of less than 100 angstroms (Åstrom).
在本發明的一實施例中，上述的第二阻擋層的厚度大於上述的第一阻擋層的厚度。In an embodiment of the invention, the thickness of the second barrier layer is greater than the thickness of the first barrier layer.
在本發明的一實施例中，上述的第三阻擋層的厚度大於上述的第一阻擋層的厚度。In an embodiment of the invention, the thickness of the third barrier layer is greater than the thickness of the first barrier layer.
在本發明的一實施例中，上述的第二阻擋層的厚度大於或是等於上述的第三阻擋層的厚度。In an embodiment of the invention, the thickness of the second barrier layer is greater than or equal to the thickness of the third barrier layer.
在本發明的一實施例中，上述的第二阻擋層的厚度小於或是等於上述的第三阻擋層的厚度。In an embodiment of the invention, the thickness of the second barrier layer is less than or equal to the thickness of the third barrier layer.
在本發明的一實施例中，上述的第一阻擋層的厚度小於50埃(Å)。In an embodiment of the invention, the first barrier layer has a thickness of less than 50 angstroms (Å).
在本發明的一實施例中，上述的P型氮化物半導體包括P側應力釋放層、高濃度電洞層、電子阻擋層以及P型歐姆接觸層。其中配置於最接近上述的第一阻擋層為上述的P側應力釋放層，配置於最遠離上述的第一阻擋層的為上述的P型歐姆接觸層，上述的高濃度電洞層以及上述的電子阻擋層依序堆疊於上述的P側應力釋放層上方，上述的電子阻擋層被上述的高濃度電洞層以及上述的P型歐姆接觸層所夾住。In an embodiment of the invention, the P-type nitride semiconductor includes a P-side stress releasing layer, a high-concentration hole layer, an electron blocking layer, and a P-type ohmic contact layer. The first barrier layer disposed closest to the first barrier layer is the P-side stress relief layer, and the P-type ohmic contact layer disposed at a distance from the first barrier layer, the high-concentration hole layer and the above-mentioned The electron blocking layer is sequentially stacked above the P-side stress releasing layer, and the electron blocking layer is sandwiched by the high-concentration hole layer and the P-type ohmic contact layer.
在本發明的一實施例中，上述的P側應力釋放層可為超晶格(superlattice)結構，其材料包含氮化鋁鎵(AlGaN)以及氮化鎵(GaN)所構成的超晶格結構，或是由氮化鋁鎵(Alx GaN)以及氮化鋁鎵(Aly GaN)所構成的超晶格結構，或是由氮化鋁鎵(AlGaN)以及氮化鋁銦鎵(InAlGaN)所構成的超晶格結構，上述的超晶格結構小於20對。In an embodiment of the invention, the P-side stress relief layer may be a superlattice structure, the material comprising a superlattice structure composed of aluminum gallium nitride (AlGaN) and gallium nitride (GaN). Or a superlattice structure composed of aluminum gallium nitride (Al x GaN) and aluminum gallium nitride (Al y GaN), or aluminum gallium nitride (AlGaN) and aluminum indium gallium nitride (InAlGaN) The superlattice structure is composed of less than 20 pairs of superlattice structures.
在本發明的一實施例中，上述的高濃度電洞層可由氮化鎵(GaN)或是氮化鋁鎵(AlGaN)所構成，上述的高濃度電洞層的鎂摻雜濃度(concentration)高於上述的P側應力釋放層的鎂摻雜濃度以及上述的電子阻擋層的鎂摻雜濃度。In an embodiment of the invention, the high-concentration hole layer may be composed of gallium nitride (GaN) or aluminum gallium nitride (AlGaN), and the magnesium concentration of the high-concentration hole layer is concentrated. It is higher than the magnesium doping concentration of the P-side stress releasing layer described above and the magnesium doping concentration of the above-described electron blocking layer.
在本發明的一實施例中，上述的高濃度電洞層的鎂(Mg)摻雜濃度高於1x1019 原子數/立方公分(Atoms/cm3 )。In an embodiment of the invention, the high concentration hole layer has a magnesium (Mg) doping concentration higher than 1 x 10 19 atoms/cm 3 (Atoms/cm 3 ).
在本發明的一實施例中，上述的電子阻擋層可由氮化鋁鎵(AlGaN)所構成，上述的電子阻擋層的鋁成份百分比高於上述的P側應力釋放層的鋁成份百分比以及高於上述的高濃度電洞層的鋁成份百分比。In an embodiment of the invention, the electron blocking layer may be composed of aluminum gallium nitride (AlGaN), and the percentage of the aluminum component of the electron blocking layer is higher than the percentage of the aluminum component of the P-side stress releasing layer and higher than The percentage of aluminum component of the high concentration hole layer described above.
在本發明的一實施例中，上述的P型歐姆接觸層可由氮化鎵(GaN)所構成，上述的P型歐姆接觸層的鎂摻雜濃度高於上述的電子阻擋層的鎂摻雜濃度。In an embodiment of the invention, the P-type ohmic contact layer may be composed of gallium nitride (GaN), and the magnesium doping concentration of the P-type ohmic contact layer is higher than the magnesium doping concentration of the electron blocking layer. .
在本發明的一實施例中，上述的高濃度電洞層的鎂(Mg)摻雜濃度高於1x1019 (Atoms/cm3 )，且上述的高濃度電洞層的鋁成份百分比低於上述的電子阻擋層的鋁成份百分比。In an embodiment of the invention, the high concentration hole layer has a magnesium (Mg) doping concentration higher than 1×10 19 (Atoms/cm 3 ), and the high concentration hole layer has a lower aluminum component percentage than the above. The percentage of aluminum component of the electronic barrier layer.
在本發明的一實施例中，上述的N型氮化物半導體包括N側第一應力釋放層、N側第二應力釋放層、低濃度電子層以及N型歐姆接觸層，其中配置於最接近上述的第二阻擋層為上述的N側第一應力釋放層，配置於最遠離上述的第二阻擋層為上述的N型歐姆接觸層，上述的低濃度電子層以及上述的第二應力釋放層依序堆疊於上述的N型歐姆接觸層上方，上述的低濃度電子層被上述的N型歐姆接觸層及上述的第二應力釋放層所夾住。In an embodiment of the invention, the N-type nitride semiconductor includes an N-side first stress relief layer, an N-side second stress relief layer, a low-concentration electron layer, and an N-type ohmic contact layer, wherein the N-type ohmic contact layer is disposed closest to the above The second barrier layer is the N-side first stress relief layer, and the second barrier layer disposed farthest from the above is the N-type ohmic contact layer, and the low-concentration electron layer and the second stress-relieving layer are The stack is stacked above the N-type ohmic contact layer, and the low-concentration electron layer is sandwiched by the N-type ohmic contact layer and the second stress-relieving layer.
在本發明的一實施例中，上述的N側第一應力釋放層可為超晶格結構，其材料包含氮化銦鎵(InGaN)以及氮化鎵(GaN)所構成的超晶格結構，或是由氮化銦鎵(Inx GaN))以及氮化銦鎵(Iny GaN)所構成的超晶格結構，上述的超晶格結構小於20對。In an embodiment of the invention, the N-side first stress relief layer may be a superlattice structure, and the material thereof comprises a superlattice structure composed of indium gallium nitride (InGaN) and gallium nitride (GaN). Or a superlattice structure composed of indium gallium nitride (In x GaN) and indium gallium nitride (In y GaN), the superlattice structure described above is less than 20 pairs.
在本發明的一實施例中，上述的N側第二應力釋放層可為超晶格結構，其材料包含氮化銦鎵(InGaN)以及氮化鎵(GaN)所構成的超晶格結構，或是由氮化銦鎵(Inx GaN))以及氮化銦鎵(Iny GaN)所構成的超晶格結構，上述的超晶格結構小於20對。In an embodiment of the invention, the N-side second stress relief layer may be a superlattice structure, and the material thereof comprises a superlattice structure composed of indium gallium nitride (InGaN) and gallium nitride (GaN). Or a superlattice structure composed of indium gallium nitride (In x GaN) and indium gallium nitride (In y GaN), the superlattice structure described above is less than 20 pairs.
在本發明的一實施例中，上述的N側第一應力釋放層的銦(Indium)成份百分比高於上述的N側第二應力釋放層的銦成份百分比。In an embodiment of the invention, the indium component percentage of the N-side first stress-relieving layer is higher than the percentage of the indium component of the N-side second stress-relieving layer.
在本發明的一實施例中，上述的低濃度電子層可由氮化鎵(GaN)、氮化銦鎵(InGaN)或是氮化鋁鎵(AlGaN)所構成，上述的低濃度電子層的矽摻雜濃度低於上述的N型歐姆接觸層的矽摻雜濃度。In an embodiment of the invention, the low-concentration electron layer may be composed of gallium nitride (GaN), indium gallium nitride (InGaN) or aluminum gallium nitride (AlGaN), and the germanium of the low-concentration electron layer The doping concentration is lower than the erbium doping concentration of the N-type ohmic contact layer described above.
在本發明的一實施例中，上述的低濃度電子層的矽摻雜濃度低於1x1018 (Atoms/cm3 )。In an embodiment of the invention, the low concentration electron layer has a germanium doping concentration of less than 1 x 10 18 (Atoms/cm 3 ).
在本發明的一實施例中，上述的N型歐姆接觸層可由氮化鎵(GaN)、氮化銦鎵(InGaN)或是氮化鋁鎵(AlGaN)所構成，上述的N型歐姆接觸層的矽摻雜濃度高於上述的N側第一應力釋放層、上述的N側第二應力釋放層以及上述的低濃度電子層的矽摻雜濃度。In an embodiment of the invention, the N-type ohmic contact layer may be formed of gallium nitride (GaN), indium gallium nitride (InGaN) or aluminum gallium nitride (AlGaN), and the above-mentioned N-type ohmic contact layer The cerium doping concentration is higher than the cerium doping concentration of the N-side first stress-relieving layer, the N-side second stress-relieving layer, and the low-concentration electron layer described above.
在本發明的一實施例中，上述的P側應力釋放層的上述的超晶格結構小於10對。In an embodiment of the invention, the super-lattice structure of the P-side stress relief layer is less than 10 pairs.
在本發明的一實施例中，上述的N側第一應力釋放層的上述的超晶格結構小於10對。In an embodiment of the invention, the above-described superlattice structure of the N-side first stress relief layer is less than 10 pairs.
在本發明的一實施例中，上述的N側第二應力釋放層的上述的超晶格結構小於10對。In an embodiment of the invention, the above-mentioned N-side second stress relief layer has a super-lattice structure of less than 10 pairs.
在本發明的一實施例中，上述的基板係選自包含III-V族，IV族，II-VI族的元素與合金、氧化鋅(ZnO)、尖晶石(spinel)、氮化鎵(GaN)、藍寶石(sapphire)或矽(Si)。In an embodiment of the invention, the substrate is selected from the group consisting of III-V, Group IV, II-VI elements and alloys, zinc oxide (ZnO), spinel, gallium nitride ( GaN), sapphire or bismuth (Si).
在本發明的一實施例中，上述的緩衝層包括第一緩衝層以及第二緩衝層。其中上述的第一緩衝層被上述的基板的上述的第一面以及上述的第二緩衝層所夾住，上述的第一緩衝層缺陷密度高於上述的第二緩衝層，上述的第二緩衝層上部為一平坦且缺陷密度低於上述的第一緩衝層。In an embodiment of the invention, the buffer layer includes a first buffer layer and a second buffer layer. The first buffer layer is sandwiched by the first surface of the substrate and the second buffer layer, and the first buffer layer has a higher defect density than the second buffer layer, and the second buffer layer The upper portion of the layer is a flat and defect density lower than the first buffer layer described above.
在本發明的一實施例中，上述的第一緩衝層的材料可為單晶氮化鎵(GaN)、單晶氮化鋁(AlN)或是單晶氮化鋁鎵(AlGaN)。In an embodiment of the invention, the material of the first buffer layer may be single crystal gallium nitride (GaN), single crystal aluminum nitride (AlN) or single crystal aluminum gallium nitride (AlGaN).
在本發明的一實施例中，上述的第一緩衝層的材料可為非單晶氮化鎵(GaN)、非單晶氮化鋁(AlN)或是非單晶氮化鋁鎵(AlGaN)。In an embodiment of the invention, the material of the first buffer layer may be non-single-crystal gallium nitride (GaN), non-single-crystal aluminum nitride (AlN) or non-single-crystal aluminum gallium nitride (AlGaN).
在本發明的一實施例中，上述的緩衝層的材料包含氮化鎵(GaN)，氮化鋁(AlN)或氮化鋁鎵(AlGaN)所構成。In an embodiment of the invention, the material of the buffer layer comprises gallium nitride (GaN), aluminum nitride (AlN) or aluminum gallium nitride (AlGaN).
在本發明的一實施例中，上述的基板的上述的第一面包括成長表面以及多個位於上述的成長表面上的微結構，上述的多個微結構具有非圓滑的蝕刻側面。In an embodiment of the invention, the first surface of the substrate includes a growth surface and a plurality of microstructures on the growth surface, and the plurality of microstructures have non-smooth etched sides.
在本發明的一實施例中，上述的成長表面的表面粗糙度低於10埃(Å)。In an embodiment of the invention, the growth surface has a surface roughness of less than 10 Å.
在本發明的一實施例中，上述的微結構的表面粗糙度低於10埃(Å)。In an embodiment of the invention, the microstructure has a surface roughness of less than 10 angstroms (Å).
在本發明的一實施例中，上述的微結構為週期性突出結構，上述的週期性突出結構包括高度、寬度以及底面間距。In an embodiment of the invention, the microstructure is a periodic protruding structure, and the periodic protruding structure includes a height, a width, and a bottom surface spacing.
在本發明的一實施例中，上述的高度介於1微米(micrometer；µm)至3微米之間。In an embodiment of the invention, the height is between 1 micrometer (μm) and 3 micrometers.
在本發明的一實施例中，上述的寬度介於1微米至3微米之間。In an embodiment of the invention, the width is between 1 micrometer and 3 micrometers.
在本發明的一實施例中，上述的底面間距介於0.1微米至3微米之間。In an embodiment of the invention, the bottom surface spacing is between 0.1 microns and 3 microns.
在本發明的一實施例中，上述的基板的第二面粗糙度大於上述的成長表面以及上述的多個微結構的表面。In an embodiment of the invention, the second surface roughness of the substrate is greater than the growth surface and the surface of the plurality of microstructures.
在本發明的一實施例中，上述的微結構的外型為半球體(hemisphere)。In an embodiment of the invention, the microstructure of the microstructure is a hemisphere.
在本發明的一實施例中，上述的微結構的外型為錐體(cone)。In an embodiment of the invention, the microstructure of the microstructure is a cone.
在本發明的一實施例中，上述的微結構的外型為截頭錐體(truncated-cone)。In an embodiment of the invention, the microstructure of the microstructure is a truncated-cone.
在本發明的一實施例中，上述的微結構的外型為金字塔(pyramid)。In an embodiment of the invention, the microstructure of the above microstructure is a pyramid.
在本發明的一實施例中，上述的微結構的外型為截頭金字塔(truncated-pyramid)。In an embodiment of the invention, the microstructure of the above structure is a truncated-pyramid.
在本發明的一實施例中，上述的微結構的外型為方柱(square pillar)。In an embodiment of the invention, the microstructure of the microstructure is a square pillar.
在本發明的一實施例中，上述的微結構的外型為圓桶(cylinder)。In an embodiment of the invention, the microstructure of the above structure is a cylinder.
在本發明的一實施例中，上述的氮化物半導體元件更包括平台結構、N型電極、電流阻擋層、透明導電層、P型電極、絕緣層以及高反射絕緣層。平台結構露出部分上述的N型歐姆接觸層。N型電極與上述的N型歐姆接觸層電性連接。電流阻擋層與上述的P型歐姆接觸層直接接觸。透明導電層覆蓋上述的電流阻擋層以及與上述的P型歐姆接觸層直接接觸。P型電極位於上述的透明導電層的上方，且藉由透明導電層與上述的P型歐姆接觸層電性連接。絕緣層覆蓋上述的N型電極以及上述的P型電極及上述的平台結構的側壁。高反射絕緣層，位於上述的基板的第二面。In an embodiment of the invention, the nitride semiconductor device further includes a terrace structure, an N-type electrode, a current blocking layer, a transparent conductive layer, a P-type electrode, an insulating layer, and a highly reflective insulating layer. The platform structure exposes a portion of the N-type ohmic contact layer described above. The N-type electrode is electrically connected to the N-type ohmic contact layer described above. The current blocking layer is in direct contact with the P-type ohmic contact layer described above. The transparent conductive layer covers the current blocking layer described above and is in direct contact with the P-type ohmic contact layer described above. The P-type electrode is located above the transparent conductive layer, and is electrically connected to the P-type ohmic contact layer described above by a transparent conductive layer. The insulating layer covers the N-type electrode and the P-type electrode described above and the sidewall of the above-described platform structure. A highly reflective insulating layer is located on the second side of the substrate.
在本發明的一實施例中，上述的高反射絕緣層由多個介電材料對(pair)組成。上述的多個介電材料對包括多個第一介電對以及多個第二介電對。In an embodiment of the invention, the high reflective insulating layer is composed of a plurality of pairs of dielectric materials. The plurality of dielectric material pairs described above include a plurality of first dielectric pairs and a plurality of second dielectric pairs.
在本發明的一實施例中，上述的第一介電對包括第一材料層以及第二材料層，其中上述的第一材料層折射系數(refractive index)大於第二材料層。In an embodiment of the invention, the first dielectric pair includes a first material layer and a second material layer, wherein the first material layer has a refractive index greater than the second material layer.
在本發明的一實施例中，上述的第一材料層以及上述的第二材料層的光學厚度小於四分之一的波長(波長/4)，上述的波長為上述的氮化物半導體量子井發光結構所發出的波長。In an embodiment of the invention, the first material layer and the second material layer have an optical thickness less than a quarter wavelength (wavelength / 4), and the wavelength is the above-mentioned nitride semiconductor quantum well illumination The wavelength emitted by the structure.
在本發明的一實施例中，上述的第二介電對包括第一材料層以及第二材料層，其中上述的第一材料層折射系數(refractive index)大於第二材料層。In an embodiment of the invention, the second dielectric pair includes a first material layer and a second material layer, wherein the first material layer has a refractive index greater than the second material layer.
在本發明的一實施例中，上述的第一材料層的光學厚度小於(波長/4)，上述的第二材料層的光學厚度大於(波長/4)，上述的波長為上述的氮化物半導體量子井發光結構所發出的波長。In an embodiment of the invention, the optical thickness of the first material layer is less than (wavelength / 4), the optical thickness of the second material layer is greater than (wavelength / 4), and the wavelength is the nitride semiconductor. The wavelength emitted by the quantum well luminescent structure.
在本發明的一實施例中，上述的高反射絕緣層由多個介電材料對(pair)組成。上述的多個介電材料對包括多個第三介電對以及多個第二介電對。In an embodiment of the invention, the high reflective insulating layer is composed of a plurality of pairs of dielectric materials. The plurality of dielectric material pairs described above includes a plurality of third dielectric pairs and a plurality of second dielectric pairs.
在本發明的一實施例中，上述的第三介電對包括第一材料層以及第二材料層，其中上述的第一材料層折射系數(refractive index)大於第二材料層。In an embodiment of the invention, the third dielectric pair includes a first material layer and a second material layer, wherein the first material layer has a refractive index greater than the second material layer.
在本發明的一實施例中，上述的第一材料層以及上述的第二材料層的光學厚度大於四分之一的波長(波長/4)，上述的波長為上述的氮化物半導體量子井發光結構所發出的波長。In an embodiment of the invention, the first material layer and the second material layer have an optical thickness greater than a quarter wavelength (wavelength / 4), and the wavelength is the above-described nitride semiconductor quantum well illumination The wavelength emitted by the structure.
在本發明的一實施例中，上述的第二介電對包括第一材料層以及第二材料層，其中上述的第一材料層折射系數(refractive index)大於第二材料層。In an embodiment of the invention, the second dielectric pair includes a first material layer and a second material layer, wherein the first material layer has a refractive index greater than the second material layer.
在本發明的一實施例中，上述的第一材料層的光學厚度小於(波長/4)，上述的第二材料層的光學厚度大於(波長/4)，上述的波長為上述的氮化物半導體量子井發光結構所發出的波長。In an embodiment of the invention, the optical thickness of the first material layer is less than (wavelength / 4), the optical thickness of the second material layer is greater than (wavelength / 4), and the wavelength is the nitride semiconductor. The wavelength emitted by the quantum well luminescent structure.
在本發明的一實施例中，上述的高反射絕緣層由多個介電材料對(pair)組成。上述的多個介電材料對包括多個第一介電對以及多個第三介電對。In an embodiment of the invention, the high reflective insulating layer is composed of a plurality of pairs of dielectric materials. The plurality of dielectric material pairs described above includes a plurality of first dielectric pairs and a plurality of third dielectric pairs.
在本發明的一實施例中，上述的第一介電對包括第一材料層以及第二材料層，其中上述的第一材料層折射系數(refractive index)大於第二材料層。In an embodiment of the invention, the first dielectric pair includes a first material layer and a second material layer, wherein the first material layer has a refractive index greater than the second material layer.
在本發明的一實施例中，上述的第一材料層以及上述的第二材料層的光學厚度小於四分之一的波長(波長/4)，上述的波長為上述的氮化物半導體量子井發光結構所發出的波長。In an embodiment of the invention, the first material layer and the second material layer have an optical thickness less than a quarter wavelength (wavelength / 4), and the wavelength is the above-mentioned nitride semiconductor quantum well illumination The wavelength emitted by the structure.
在本發明的一實施例中，上述的第三介電對包括第一材料層以及第二材料層，其中上述的第一材料層折射系數(refractive index)大於第二材料層。In an embodiment of the invention, the third dielectric pair includes a first material layer and a second material layer, wherein the first material layer has a refractive index greater than the second material layer.
在本發明的一實施例中，上述的第一材料層以及上述的第二材料層的光學厚度大於四分之一的波長(波長/4)，上述的波長為上述的氮化物半導體量子井發光結構所發出的波長。In an embodiment of the invention, the first material layer and the second material layer have an optical thickness greater than a quarter wavelength (wavelength / 4), and the wavelength is the above-described nitride semiconductor quantum well illumination The wavelength emitted by the structure.
在本發明的一實施例中，上述的高反射絕緣層由多個介電材料對(pair)組成。上述的多個介電材料對包括至少一個第一介電對以及至少一個第二介電對，以及至少一個第三介電對。In an embodiment of the invention, the high reflective insulating layer is composed of a plurality of pairs of dielectric materials. The plurality of dielectric material pairs described above includes at least one first dielectric pair and at least one second dielectric pair, and at least one third dielectric pair.
在本發明的一實施例中，上述的第一介電對包括第一材料層以及第二材料層，其中上述的第一材料層折射系數(refractive index)大於第二材料層。In an embodiment of the invention, the first dielectric pair includes a first material layer and a second material layer, wherein the first material layer has a refractive index greater than the second material layer.
在本發明的一實施例中，上述的第一材料層以及上述的第二材料層的光學厚度小於四分之一的波長(波長/4)，上述的波長為可見光中心波長550nm。In an embodiment of the invention, the first material layer and the second material layer have an optical thickness of less than a quarter of a wavelength (wavelength / 4), and the wavelength is a visible light center wavelength of 550 nm.
在本發明的一實施例中，上述的第二介電對包括第一材料層以及第二材料層，其中上述的第一材料層折射系數(refractive index)大於第二材料層。In an embodiment of the invention, the second dielectric pair includes a first material layer and a second material layer, wherein the first material layer has a refractive index greater than the second material layer.
在本發明的一實施例中，上述的第一材料層的光學厚度小於(波長/4)，上述的第二材料層的光學厚度大於(波長/4)，上述的波長為可見光中心波長550nm。In an embodiment of the invention, the first material layer has an optical thickness less than (wavelength / 4), the second material layer has an optical thickness greater than (wavelength / 4), and the wavelength is a visible light center wavelength of 550 nm.
在本發明的一實施例中，上述的第三介電對包括第一材料層以及第二材料層，其中上述的第一材料層折射系數(refractive index)大於第二材料層。In an embodiment of the invention, the third dielectric pair includes a first material layer and a second material layer, wherein the first material layer has a refractive index greater than the second material layer.
在本發明的一實施例中，上述的第一材料層以及上述的第二材料層的光學厚度大於四分之一的波長(波長/4)，上述的波長為可見光中心波長550nm。In an embodiment of the invention, the first material layer and the second material layer have an optical thickness greater than a quarter wavelength (wavelength / 4), and the wavelength is a visible light center wavelength of 550 nm.
在本發明的一實施例中，上述的第一介電對可以靠近或遠基板。In an embodiment of the invention, the first dielectric pair may be adjacent to or far from the substrate.
在本發明的一實施例中，上述的第二介電對可以靠近或遠基板。In an embodiment of the invention, the second dielectric pair may be adjacent to or far from the substrate.
在本發明的一實施例中，上述的第三介電對可以靠近或遠基板。In an embodiment of the invention, the third dielectric pair may be adjacent to or far from the substrate.
在本發明的一實施例中，上述的第二介電對可以位於第一介電對及第三介電對之間。In an embodiment of the invention, the second dielectric pair may be located between the first dielectric pair and the third dielectric pair.
在本發明的一實施例中，上述的第一介電對可以位於第二介電對及第三介電對之間。In an embodiment of the invention, the first dielectric pair may be located between the second dielectric pair and the third dielectric pair.
在本發明的一實施例中，上述的第三介電對可以位於第一介電對及第二介電對之間。In an embodiment of the invention, the third dielectric pair may be located between the first dielectric pair and the second dielectric pair.
在本發明的一實施例中，上述的高反射絕緣層下方可以有一金屬反射層，該金屬反射層材料可為鋁或銀或其他高反射率金屬組成。In an embodiment of the invention, the high reflective insulating layer may have a metal reflective layer underneath, and the metal reflective layer material may be aluminum or silver or other high reflectivity metal.
在本發明的一實施例中，上述的高反射絕緣層上方可以有一介面層，該介面層材料可與高反射絕緣層材料相同。In an embodiment of the invention, the upper reflective insulating layer may have an interposer layer thereon, and the interposer layer material may be the same as the high reflective insulating layer material.
在本發明的一實施例中，上述的透明導電層可以是銦錫氧化物(Indium Tin Oxide；ITO)、銦鋅氧化物(indium zinc oxide；IZO)、氧化鋅（Zinc Oxide；ZnO）或氧化鋅鋁(Aluminum Zinc Oxide；AZO)。In an embodiment of the invention, the transparent conductive layer may be Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), Zinc Oxide (ZnO) or Oxidation. Aluminum Zinc Oxide (AZO).
在本發明的一實施例中，上述的絕緣層包括氧化矽(SiOX )、氮化矽(SiNX )、聚醯亞胺(Polyimide)或其他高分子材料。In an embodiment of the present invention, the above-described insulating layer include silicon oxide (SiO X), silicon nitride (SiN X), polyimide (Polyimide) or other polymeric materials.
在本發明的一實施例中，上述的高反射絕緣層的材料包括氧化物，氮化物，以及至少包含矽(Si)、鈦(Ti)、鋯(Zr)、鈮(Nb)、鉭(Ta)或鋁(Al)元素所組成的氧化物或氮化物。In an embodiment of the invention, the material of the high reflective insulating layer comprises an oxide, a nitride, and at least bismuth (Si), titanium (Ti), zirconium (Zr), niobium (Nb), tantalum (Ta). Or an oxide or nitride composed of an aluminum (Al) element.
在本發明的一實施例中，上述的N型電極的材料包括銀(Ag)、鋁(Al)、鎳(Ni)、銠(Rh)、金(Au)、銅(Cu)、鈦(Ti)、鉑(Pt)、鈀(Pd)、鉬(Mo)、鉻(Cr)、鎢(W)或上述金屬的合金。In an embodiment of the invention, the material of the N-type electrode includes silver (Ag), aluminum (Al), nickel (Ni), rhenium (Rh), gold (Au), copper (Cu), and titanium (Ti). ), platinum (Pt), palladium (Pd), molybdenum (Mo), chromium (Cr), tungsten (W) or an alloy of the above metals.
在本發明的一實施例中，上述的P型電極的材料包括Ag、Al、Ni、Rh、Au、Cu、Ti、Pt、Pd、Mo、Cr、W或上述金屬的合金。In an embodiment of the invention, the material of the P-type electrode includes Ag, Al, Ni, Rh, Au, Cu, Ti, Pt, Pd, Mo, Cr, W or an alloy of the above metals.
在本發明的一實施例中，上述的氮化物半導體元件設置於封裝載體以及封裝基板上，其中上述的封裝基板包括電路板以及二個銲墊。上述的二個銲墊設置於上述的電路板上。上述的封裝載體包括支架、二個導電引腳、樹脂、二個導電材料、透明膠以及螢光粉。上述的導電引腳設置於上述的支架上，用以與上述的二個銲墊電性連接，其中上述的氮化物半導體元件設置於上述的二個導電引腳上，並與上述的二個導電引腳電性連接。上述的樹脂設置於上述的支架上，並用以容納上述的氮化物半導體元件及上述的二個導電引腳。上述的二個導電材料用以電性連接上述的上述的氮化物半導體元件及上述的二個導電引腳。上述的透明膠用以包覆上述的氮化物半導體元件及上述的二個導電引腳。上述的螢光粉用以填入於上述的透明膠中。In an embodiment of the invention, the nitride semiconductor device is disposed on a package carrier and a package substrate, wherein the package substrate comprises a circuit board and two pads. The above two pads are disposed on the above circuit board. The package carrier described above comprises a bracket, two conductive pins, a resin, two conductive materials, a transparent glue, and a phosphor powder. The conductive pin is disposed on the bracket for electrically connecting to the two solder pads, wherein the nitride semiconductor component is disposed on the two conductive pins and electrically conductive with the two The pins are electrically connected. The above resin is disposed on the above-mentioned bracket and is used to accommodate the above-described nitride semiconductor device and the above two conductive pins. The two conductive materials are electrically connected to the nitride semiconductor device and the two conductive pins. The transparent adhesive is used to cover the nitride semiconductor device and the two conductive pins described above. The above phosphor powder is used to fill in the above transparent glue.
在本發明的一實施例中，上述的螢光粉其係由具高穩定發光特性的材料所製成，例如石榴石系(Garnet)、硫化物(Sulfate)、氮化物(Nitrate)、矽酸鹽(Silicate)、鋁酸鹽(Aluminate)或上述材料的任意組合，但不以此為限，其發光波長約為300nm至700nm。其中上述的螢光粉的粒徑為1~25μm。In an embodiment of the invention, the phosphor powder is made of a material having high stable luminescent properties, such as Garnet, Sulfate, Nitrate, and Citrate. Silicate, aluminate or any combination of the above materials, but not limited thereto, has an emission wavelength of about 300 nm to 700 nm. The above-mentioned phosphor powder has a particle diameter of 1 to 25 μm.
在本發明的一實施例中，上述的導電材料包含銲線、金、銀、銅、鋁或混合材料。In an embodiment of the invention, the conductive material comprises a bonding wire, gold, silver, copper, aluminum or a mixed material.
在本發明的一實施例中，上述的透明膠材包括環氧樹脂。In an embodiment of the invention, the transparent adhesive material comprises an epoxy resin.
在本發明的一實施例中，上述的導電引腳可為纯金屬材料、金、銀、銅、鋁、低熔點金屬合金、金錫合金、錫、鉍或錫鉍合金。In an embodiment of the invention, the conductive pins may be pure metal materials, gold, silver, copper, aluminum, low melting point metal alloys, gold tin alloys, tin, antimony or tin antimony alloys.
在本發明的一實施例中，上述的氮化物半導體元件更包括平台結構、N型電極、電流阻擋層、透明導電層、P型電極、絕緣層、高反射絕緣層、第一銲墊層、第二銲墊層、第一連接電極以及第二連接電極。上述的平台結構露出部分上述的N型歐姆接觸層。上述的N型電極與上述的N型歐姆接觸層電性連接。上述的電流阻擋層與上述的P型歐姆接觸層直接接觸。上述的透明導電層覆蓋上述的電流阻擋層以及與上述的P型歐姆接觸層直接接觸。上述的P型電極位於上述的透明導電層的上方，藉由透明導電層與上述的P型歐姆接觸層電性連接。上述的絕緣層覆蓋上述的N型電極以及上述的P型電極及上述的平台結構的側壁。上述的高反射絕緣層位於上述的覆蓋部分上述的絕緣層覆。上述的第一銲墊層與上述的N型電極電性連接。上述的第二銲墊層與上述的P型電極電性連接。上述的第一連接電極與上述的第一銲墊層電性連接。上述的第二連接電極與上述的第二銲墊層電性連接。In an embodiment of the invention, the nitride semiconductor device further includes a platform structure, an N-type electrode, a current blocking layer, a transparent conductive layer, a P-type electrode, an insulating layer, a highly reflective insulating layer, a first pad layer, a second pad layer, a first connection electrode, and a second connection electrode. The above-described platform structure exposes some of the above-described N-type ohmic contact layers. The N-type electrode described above is electrically connected to the N-type ohmic contact layer described above. The current blocking layer is in direct contact with the P-type ohmic contact layer described above. The transparent conductive layer covers the current blocking layer and is in direct contact with the P-type ohmic contact layer described above. The P-type electrode is located above the transparent conductive layer, and is electrically connected to the P-type ohmic contact layer by a transparent conductive layer. The insulating layer covers the N-type electrode and the P-type electrode and the sidewall of the above-described terrace structure. The above-mentioned highly reflective insulating layer is located on the above-mentioned insulating portion of the covering portion. The first pad layer is electrically connected to the N-type electrode. The second pad layer is electrically connected to the P-type electrode. The first connection electrode is electrically connected to the first pad layer. The second connection electrode is electrically connected to the second pad layer.
在本發明的一實施例中，上述的高反射絕緣層由多個介電材料對(pair)組成，上述的多個介電材料對包括多個第一介電對以及多個第二介電對。In an embodiment of the invention, the high reflective insulating layer is composed of a plurality of pairs of dielectric materials, and the plurality of dielectric material pairs include a plurality of first dielectric pairs and a plurality of second dielectrics. Correct.
在本發明的一實施例中，上述的第一介電對包括第一材料層以及第二材料層，其中上述的第一材料層折射系數(refractive index)大於上述的第二材料層。In an embodiment of the invention, the first dielectric pair includes a first material layer and a second material layer, wherein the first material layer has a refractive index greater than the second material layer.
在本發明的一實施例中，上述的第一材料層以及上述的第二材料層的光學厚度小於四分之一的波長，上述的波長為上述的氮化物半導體量子井發光結構所發出的波長。In an embodiment of the invention, the first material layer and the second material layer have an optical thickness of less than a quarter of a wavelength, and the wavelength is a wavelength emitted by the nitride semiconductor quantum well emitting structure. .
在本發明的一實施例中，上述的第二介電對包括第一材料層以及第二材料層，其中上述的第一材料層折射系數(refractive index)大於上述的第二材料層。In an embodiment of the invention, the second dielectric pair includes a first material layer and a second material layer, wherein the first material layer has a refractive index greater than the second material layer.
在本發明的一實施例中，上述的第一材料層的光學厚度小於四分之一的波長，上述的第二材料層的光學厚度大於四分之一的波長，上述的波長為上述的氮化物半導體量子井發光結構所發出的波長。In an embodiment of the invention, the first material layer has an optical thickness of less than a quarter of a wavelength, and the second material layer has an optical thickness greater than a quarter of a wavelength, wherein the wavelength is the nitrogen The wavelength emitted by the quantum structure of a quantum well.
在本發明的一實施例中，上述的透明導電層可以是銦錫氧化物(Indium Tin Oxide；ITO)、銦鋅氧化物(indium zinc oxide；IZO)、氧化鋅（Zinc Oxide；ZnO）或氧化鋅鋁(Aluminum Zinc Oxide；AZO)。In an embodiment of the invention, the transparent conductive layer may be Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), Zinc Oxide (ZnO) or Oxidation. Aluminum Zinc Oxide (AZO).
在本發明的一實施例中，上述的絕緣層包括氧化矽(SiOX )、氮化矽(SiNX )、聚醯亞胺(Polyimide)或其他高分子材料。In an embodiment of the present invention, the above-described insulating layer include silicon oxide (SiO X), silicon nitride (SiN X), polyimide (Polyimide) or other polymeric materials.
在本發明的一實施例中，上述的高反射絕緣層的材料包括氧化物、氮化物或至少包含Si、Ti、Zr、Nb、Ta或Al元素所組成的氧化物或氮化物。In an embodiment of the invention, the material of the high-reflection insulating layer comprises an oxide, a nitride or an oxide or nitride composed of at least Si, Ti, Zr, Nb, Ta or Al elements.
在本發明的一實施例中，上述的N型電極的材料包括Ag、Al、Ni、Rh、Au、Cu、Ti、Pt、Pd、Mo、Cr、W或上述金屬的合金。In an embodiment of the invention, the material of the N-type electrode includes Ag, Al, Ni, Rh, Au, Cu, Ti, Pt, Pd, Mo, Cr, W or an alloy of the above metals.
在本發明的一實施例中，上述的P型電極的材料包括Ag、Al、Ni、Rh、Au、Cu、Ti、Pt、Pd、Mo、Cr、W或上述金屬的合金。In an embodiment of the invention, the material of the P-type electrode includes Ag, Al, Ni, Rh, Au, Cu, Ti, Pt, Pd, Mo, Cr, W or an alloy of the above metals.
在本發明的一實施例中，上述的第一導電引腳的材料包括Ag、Al、Ni、Rh、Au、Cu、Ti、Pt、Pd、Mo、Cr、W、錫(Sn)或上述金屬的合金。In an embodiment of the invention, the material of the first conductive pin comprises Ag, Al, Ni, Rh, Au, Cu, Ti, Pt, Pd, Mo, Cr, W, tin (Sn) or the above metal. Alloy.
在本發明的一實施例中，上述的第二導電引腳的材料包括Ag、Al、Ni、Rh、Au、Cu、Ti、Pt、Pd、Mo、Cr、W、Sn或上述金屬的合金。In an embodiment of the invention, the material of the second conductive pin comprises Ag, Al, Ni, Rh, Au, Cu, Ti, Pt, Pd, Mo, Cr, W, Sn or an alloy of the above metals.
在本發明的一實施例中，上述的氮化物半導體元件設置於封裝載體以及封裝基板上，其中上述的封裝基板包括電路板以及二個銲墊。上述的二個銲墊設置於上述的電路板上。其中上述的封裝載體包括支架、二個導電引腳、樹脂、二個導電材料、透明膠以及螢光粉。上述的二個導電引腳設置於上述的支架上，用以與上述的二個銲墊電性連接，其中上述的氮化物半導體元件設置於上述的二個導電引腳上，並與上述的二個導電引腳電性連接。上述的樹脂設置於上述的支架上，並用以容納上述的氮化物半導體元件及上述的二個導電引腳。上述的二個導電材料，用以電性連接上述的上述的氮化物半導體元件及上述的二個導電引腳。上述的透明膠用以包覆上述的上述的氮化物半導體元件及上述的二個導電引腳。上述的螢光粉用以填入於上述的透明膠中。In an embodiment of the invention, the nitride semiconductor device is disposed on a package carrier and a package substrate, wherein the package substrate comprises a circuit board and two pads. The above two pads are disposed on the above circuit board. The package carrier described above comprises a bracket, two conductive pins, a resin, two conductive materials, a transparent glue and a phosphor powder. The two conductive pins are disposed on the bracket for electrically connecting to the two solder pads, wherein the nitride semiconductor component is disposed on the two conductive pins, and the two The conductive pins are electrically connected. The above resin is disposed on the above-mentioned bracket and is used to accommodate the above-described nitride semiconductor device and the above two conductive pins. The two conductive materials are electrically connected to the above-mentioned nitride semiconductor device and the two conductive pins. The above transparent adhesive is used to coat the above-described nitride semiconductor device and the above two conductive pins. The above phosphor powder is used to fill in the above transparent glue.
在本發明的一實施例中，上述的螢光粉其係由具高穩定發光特性的材料所製成，例如石榴石系(Garnet)、硫化物(Sulfate)、氮化物(Nitrate)、矽酸鹽(Silicate)、鋁酸鹽(Aluminate)或上述材料的任意組合，但不以此為限，其發光波長約為300nm至700nm。其中上述的螢光粉的粒徑為1~25μm。In an embodiment of the invention, the phosphor powder is made of a material having high stable luminescent properties, such as Garnet, Sulfate, Nitrate, and Citrate. Silicate, aluminate or any combination of the above materials, but not limited thereto, has an emission wavelength of about 300 nm to 700 nm. The above-mentioned phosphor powder has a particle diameter of 1 to 25 μm.
在本發明的一實施例中，上述的透明膠材包括環氧樹脂。In an embodiment of the invention, the transparent adhesive material comprises an epoxy resin.
在本發明的一實施例中，上述的導電引腳可為纯金屬材料、金、銀、銅、鋁、或低熔點金屬合金、金錫合金、錫、鉍或錫鉍合金。In an embodiment of the invention, the conductive pins may be pure metal materials, gold, silver, copper, aluminum, or low melting point metal alloys, gold tin alloys, tin, antimony or tin antimony alloys.
在本發明的一實施例中，上述的氮化物半導體元件可應用於車用照明領域。In an embodiment of the invention, the nitride semiconductor device described above can be applied to the field of automotive lighting.
在本發明的一實施例中，上述的氮化物半導體元件可應用於一般照明領域。In an embodiment of the invention, the nitride semiconductor device described above can be applied to the field of general illumination.
在本發明的一實施例中，上述的氮化物半導體元件可應用於閃光燈領域。In an embodiment of the invention, the nitride semiconductor device described above can be applied to the field of flash lamps.
在本發明的一實施例中，上述的氮化物半導體元件可應用於背光領域。In an embodiment of the invention, the nitride semiconductor device described above can be applied to the field of backlights.
在本發明的一實施例中，上述的氮化物半導體元件可應用於戶外看板領域。In an embodiment of the invention, the nitride semiconductor device described above can be applied to the field of outdoor signage.
在本發明的一實施例中，上述的氮化物半導體元件的發光效率高於220流明每瓦(lm/W) 。In an embodiment of the invention, the nitride semiconductor device has a luminous efficiency higher than 220 lumens per watt (lm/W).
在本發明的一實施例中，上述的氮化物半導體元件的顯色指數中對紅色的顯示能力(R9)大於90。In an embodiment of the invention, the display index (R9) for red in the color rendering index of the nitride semiconductor device is greater than 90.
在本發明的一實施例中，上述的氮化物半導體元件的演色性指數(Color Rendering Index；CRI)大於90。In an embodiment of the invention, the nitride semiconductor element has a Color Rendering Index (CRI) greater than 90.
在本發明的一實施例中，上述的氮化物半導體元件的平均演色評價指數（Ra）大於90。In an embodiment of the invention, the nitride semiconductor device has an average color rendering index (Ra) of more than 90.
在本發明的一實施例中，上述的氮化物半導體元件可以是水平式發光晶片。In an embodiment of the invention, the nitride semiconductor device may be a horizontal light-emitting wafer.
在本發明的一實施例中，上述的氮化物半導體元件可以是垂直式發光晶片。In an embodiment of the invention, the nitride semiconductor device may be a vertical light-emitting chip.
在本發明的一實施例中，上述的氮化物半導體元件可以是覆晶式發光晶片。In an embodiment of the invention, the nitride semiconductor device may be a flip-chip light-emitting chip.
本發明提供一種氮化物半導體元件，其包括P型氮化物半導體、N型氮化物半導體、緩衝層、氮化物半導體量子井發光結構、高反射絕緣層、P型高反射歐姆電極、N型電極、第一焊接金屬層、第二焊接金屬層、接合基板以及基板電極。上述的氮化物半導體量子井發光結構位於上述的P型氮化物半導體及上述的N型氮化物半導體之間。上述的高反射絕緣層覆蓋於上述的P型氮化物半導體。上述的P型高反射歐姆電極覆蓋於上述的高反射絕緣層以及上述的P型氮化物半導體，並與上述的P型氮化物半導體電性連接。上述的N型電極覆蓋於上述的緩衝層，並與上述的N型氮化物半導體電性連接。上述的第一焊接金屬層覆蓋於上述的P型高反射歐姆電極，並與上述的P型氮化物半導體電性連接。上述的第二焊接金屬層覆蓋於上述的第一焊接金屬層，並與上述的P型氮化物半導體電性連接。上述的接合基板覆蓋於上述的第二焊接金屬層，並與上述的P型氮化物半導體電性連接。上述的基板電極覆蓋於上述的接合基板，並與上述的P型氮化物半導體電性連接。其中上述的氮化物半導體量子井發光結構具有多個井層和多個阻擋層，上述的多個阻擋層包含一配置於最接近前述P型氮化物半導體位置的第一阻擋層、一配置於最接近前述N型氮化物半導體位置的第二阻擋層以及多個第三阻擋層，其中上述的多個第三阻擋層被上述的多個井層夾住，其中上述的第一阻擋層的厚度小於100埃。The present invention provides a nitride semiconductor device including a P-type nitride semiconductor, an N-type nitride semiconductor, a buffer layer, a nitride semiconductor quantum well light-emitting structure, a highly reflective insulating layer, a P-type high-reflection ohmic electrode, an N-type electrode, a first solder metal layer, a second solder metal layer, a bonding substrate, and a substrate electrode. The above-described nitride semiconductor quantum well light-emitting structure is located between the above-described P-type nitride semiconductor and the above-described N-type nitride semiconductor. The above-described highly reflective insulating layer covers the above-described P-type nitride semiconductor. The P-type high-reflection ohmic electrode described above covers the above-described high-reflection insulating layer and the above-described P-type nitride semiconductor, and is electrically connected to the above-described P-type nitride semiconductor. The N-type electrode described above covers the buffer layer and is electrically connected to the N-type nitride semiconductor described above. The first solder metal layer is covered on the P-type high-reflection ohmic electrode and electrically connected to the P-type nitride semiconductor. The second solder metal layer covers the first solder metal layer and is electrically connected to the P-type nitride semiconductor. The bonding substrate described above covers the second solder metal layer and is electrically connected to the P-type nitride semiconductor described above. The substrate electrode described above covers the bonded substrate and is electrically connected to the P-type nitride semiconductor described above. The nitride semiconductor quantum well light-emitting structure has a plurality of well layers and a plurality of barrier layers, and the plurality of barrier layers include a first barrier layer disposed at a position closest to the P-type nitride semiconductor, and a first barrier layer disposed at the most a second barrier layer adjacent to the position of the N-type nitride semiconductor and a plurality of third barrier layers, wherein the plurality of third barrier layers are sandwiched by the plurality of well layers, wherein the thickness of the first barrier layer is less than 100 angstroms.
在本發明的一實施例中，上述的第二阻擋層的厚度大於上述的第一阻擋層的厚度。In an embodiment of the invention, the thickness of the second barrier layer is greater than the thickness of the first barrier layer.
在本發明的一實施例中，上述的第三阻擋層的厚度大於上述的第一阻擋層的厚度。In an embodiment of the invention, the thickness of the third barrier layer is greater than the thickness of the first barrier layer.
在本發明的一實施例中，上述的第二阻擋層的厚度大於或是等於上述的第三阻擋層的厚度。In an embodiment of the invention, the thickness of the second barrier layer is greater than or equal to the thickness of the third barrier layer.
在本發明的一實施例中，上述的第二阻擋層的厚度小於或是等於上述的第三阻擋層的厚度。In an embodiment of the invention, the thickness of the second barrier layer is less than or equal to the thickness of the third barrier layer.
在本發明的一實施例中，上述的第一阻擋層的厚度小於50埃。In an embodiment of the invention, the first barrier layer has a thickness of less than 50 angstroms.
在本發明的一實施例中，上述的P型氮化物半導體包括P側應力釋放層、高濃度電洞層、電子阻擋層以及P型歐姆接觸層。其中配置於最接近前述上述的第一阻擋層為上述的P側應力釋放層，配置於最遠離前述上述的第一阻擋層為上述的P型歐姆接觸層，上述的高濃度電洞層以及電子阻擋層依序堆疊於上述的P側應力釋放層上方，上述的電子阻擋層被上述的高濃度電洞層以及上述的P型歐姆接觸層所夾住。In an embodiment of the invention, the P-type nitride semiconductor includes a P-side stress releasing layer, a high-concentration hole layer, an electron blocking layer, and a P-type ohmic contact layer. The first barrier layer disposed closest to the above is the P-side stress releasing layer, and is disposed at a distance from the first barrier layer as described above to the P-type ohmic contact layer, the high-concentration hole layer and the electrons. The barrier layer is sequentially stacked over the P-side stress relief layer described above, and the electron blocking layer is sandwiched by the high-concentration hole layer and the P-type ohmic contact layer.
在本發明的一實施例中，上述的P側應力釋放層可為超晶格結構，其材料包含氮化鋁鎵(AlGaN)以及氮化鎵(GaN)所構成的超晶格結構，或是由氮化鋁鎵(Alx GaN)以及氮化鋁鎵(Aly GaN)所構成的超晶格結構，或是由氮化鋁鎵(AlGaN)以及氮化鋁銦鎵(InAlGaN)所構成的超晶格結構，上述的超晶格結構小於20對。In an embodiment of the invention, the P-side stress relief layer may be a superlattice structure, the material of which comprises a superlattice structure composed of aluminum gallium nitride (AlGaN) and gallium nitride (GaN), or a superlattice structure composed of aluminum gallium nitride (Al x GaN) and aluminum gallium nitride (Al y GaN), or composed of aluminum gallium nitride (AlGaN) and aluminum indium gallium nitride (InAlGaN) Superlattice structure, the above superlattice structure is less than 20 pairs.
在本發明的一實施例中，上述的高濃度電洞層可由氮化鎵(GaN)或是氮化鋁鎵(AlGaN)所構成，上述的高濃度電洞層的鎂摻雜濃度(concentration)高於上述的P側應力釋放層的鎂摻雜濃度以及上述的電子阻擋層的鎂摻雜濃度。In an embodiment of the invention, the high-concentration hole layer may be composed of gallium nitride (GaN) or aluminum gallium nitride (AlGaN), and the magnesium concentration of the high-concentration hole layer is concentrated. It is higher than the magnesium doping concentration of the P-side stress releasing layer described above and the magnesium doping concentration of the above-described electron blocking layer.
在本發明的一實施例中，上述的高濃度電洞層的鎂(Mg)摻雜濃度高於1x1019 (Atoms/cm3 )。In an embodiment of the invention, the high concentration hole layer has a magnesium (Mg) doping concentration higher than 1 x 10 19 (Atoms/cm 3 ).
在本發明的一實施例中，上述的電子阻擋層可由氮化鋁鎵(AlGaN)所構成，上述的電子阻擋層的鋁成份百分比高於上述的P側應力釋放層的鋁成份百分比以及高於上述的高濃度電洞層的鋁成份百分比。In an embodiment of the invention, the electron blocking layer may be composed of aluminum gallium nitride (AlGaN), and the percentage of the aluminum component of the electron blocking layer is higher than the percentage of the aluminum component of the P-side stress releasing layer and higher than The percentage of aluminum component of the high concentration hole layer described above.
在本發明的一實施例中，上述的P型歐姆接觸層可由氮化鎵(GaN)所構成，上述的P型歐姆接觸層的鎂摻雜濃度高於上述的電子阻擋層的鎂摻雜濃度。In an embodiment of the invention, the P-type ohmic contact layer may be composed of gallium nitride (GaN), and the magnesium doping concentration of the P-type ohmic contact layer is higher than the magnesium doping concentration of the electron blocking layer. .
在本發明的一實施例中，上述的高濃度電洞層的鎂(Mg)摻雜濃度高於1x1019 (Atoms/cm3 )且上述的高濃度電洞層的鋁成份百分比低於上述的電子阻擋層的鋁成份百分比。In an embodiment of the invention, the high concentration hole layer has a magnesium (Mg) doping concentration higher than 1×10 19 (Atoms/cm 3 ) and the high concentration hole layer has a lower aluminum component percentage than the above. The percentage of aluminum component of the electron blocking layer.
在本發明的一實施例中，上述的N型氮化物半導體包括N側第一應力釋放層、N側第二應力釋放層、低濃度電子層以及N型歐姆接觸層。其中配置於最接近前述上述的第二阻擋層為上述的N側第一應力釋放層，配置於最遠離述上述的第二阻擋層為上述的N型歐姆接觸層，上述的低濃度電子層以及上述的第二應力釋放層依序堆疊於上述的N型歐姆接觸層上方，上述的低濃度電子層被N型歐姆接觸層及上述的第二應力釋放層所夾住。In an embodiment of the invention, the N-type nitride semiconductor includes an N-side first stress relief layer, an N-side second stress relief layer, a low concentration electron layer, and an N-type ohmic contact layer. The second barrier layer disposed closest to the above is the N-side first stress relief layer, and the second barrier layer farthest from the above is the N-type ohmic contact layer, the low-concentration electron layer, and The second stress relief layer is sequentially stacked over the N-type ohmic contact layer, and the low-concentration electron layer is sandwiched by the N-type ohmic contact layer and the second stress relief layer.
在本發明的一實施例中，上述的N側第一應力釋放層可為超晶格結構，其材料包含氮化銦鎵(InGaN)以及氮化鎵(GaN)所構成的超晶格結構，或是由氮化銦鎵(Inx GaN))以及氮化銦鎵(Iny GaN)所構成的超晶格結構，或是由，上述的超晶格結構小於20對。In an embodiment of the invention, the N-side first stress relief layer may be a superlattice structure, and the material thereof comprises a superlattice structure composed of indium gallium nitride (InGaN) and gallium nitride (GaN). Or a superlattice structure composed of indium gallium nitride (In x GaN) and indium gallium nitride (In y GaN), or the above superlattice structure is less than 20 pairs.
在本發明的一實施例中，上述的N側第二應力釋放層可為超晶格結構，其材料包含氮化銦鎵(InGaN)以及氮化鎵(GaN)所構成的超晶格結構，或是由氮化銦鎵(Inx GaN))以及氮化銦鎵(Iny GaN)所構成的超晶格結構，或是由，上述的超晶格結構小於20對。In an embodiment of the invention, the N-side second stress relief layer may be a superlattice structure, and the material thereof comprises a superlattice structure composed of indium gallium nitride (InGaN) and gallium nitride (GaN). Or a superlattice structure composed of indium gallium nitride (In x GaN) and indium gallium nitride (In y GaN), or the above superlattice structure is less than 20 pairs.
在本發明的一實施例中，上述的N側第一應力釋放層的銦成份百分比高於上述的N側第二應力釋放層的銦成份百分比。In an embodiment of the invention, the percentage of indium component of the N-side first stress-relieving layer is higher than the percentage of the indium component of the N-side second stress-relieving layer.
在本發明的一實施例中，上述的N型氮化物半導體，上述的低濃度電子層可由氮化鎵(GaN)所構成或是氮化銦鎵(InGaN) 或是氮化鋁鎵(AlGaN)所構成，上述的低濃度電子層的矽摻雜濃度低於上述的N型歐姆接觸層的矽摻雜濃度。In an embodiment of the present invention, the N-type nitride semiconductor, the low-concentration electron layer may be formed of gallium nitride (GaN) or indium gallium nitride (InGaN) or aluminum gallium nitride (AlGaN). The cerium doping concentration of the low-concentration electron layer described above is lower than the cerium doping concentration of the N-type ohmic contact layer described above.
在本發明的一實施例中，上述的低濃度電子層的矽摻雜濃度低於1x1018 (Atoms/cm3 )。In an embodiment of the invention, the low concentration electron layer has a germanium doping concentration of less than 1 x 10 18 (Atoms/cm 3 ).
在本發明的一實施例中，上述的N型歐姆接觸層可由氮化鎵(GaN)所構成或是氮化銦鎵(InGaN) 或是氮化鋁鎵(AlGaN)所構成，上述的N型歐姆接觸層的矽摻雜的濃度高於上述的N側第一應力釋放層及上述的N側第二應力釋放層及上述的低濃度電子層。In an embodiment of the invention, the N-type ohmic contact layer may be formed of gallium nitride (GaN) or indium gallium nitride (InGaN) or aluminum gallium nitride (AlGaN). The concentration of germanium doping of the ohmic contact layer is higher than the above-described N-side first stress-relieving layer and the above-described N-side second stress releasing layer and the above-described low-concentration electron layer.
在本發明的一實施例中，上述的P側應力釋放層的上述的超晶格結構小於10對。In an embodiment of the invention, the super-lattice structure of the P-side stress relief layer is less than 10 pairs.
在本發明的一實施例中，上述的N側第一應力釋放層的上述的超晶格結構小於10對。In an embodiment of the invention, the above-described superlattice structure of the N-side first stress relief layer is less than 10 pairs.
在本發明的一實施例中，上述的N側第二應力釋放層的上述的超晶格結構小於10對。In an embodiment of the invention, the above-mentioned N-side second stress relief layer has a super-lattice structure of less than 10 pairs.
在本發明的一實施例中，上述的N型電極的材料包括Ag、Al、Ni、Rh、Au、Cu、Ti、Pt、Pd、Mo、Cr、W或上述金屬的合金。In an embodiment of the invention, the material of the N-type electrode includes Ag, Al, Ni, Rh, Au, Cu, Ti, Pt, Pd, Mo, Cr, W or an alloy of the above metals.
在本發明的一實施例中，上述的P型高反射歐姆電極包括Ag、Al、Ni、Rh、Au、Cu、Ti、Pt、Pd、Mo、Cr、W或上述金屬的合金。In an embodiment of the invention, the P-type high reflection ohmic electrode includes Ag, Al, Ni, Rh, Au, Cu, Ti, Pt, Pd, Mo, Cr, W or an alloy of the above metals.
在本發明的一實施例中，上述的基板電極包括Ag、Al、Ni、Rh、Au、Cu、Ti、Pt、Pd、Mo、Cr、W或上述金屬的合金。In an embodiment of the invention, the substrate electrode comprises Ag, Al, Ni, Rh, Au, Cu, Ti, Pt, Pd, Mo, Cr, W or an alloy of the above metals.
在本發明的一實施例中，上述的第一焊接金屬層材料包含Ag、Al、Ni、Rh、Au、Cu、Ti、Pt、Pd、Mo、Cr、W、Sn或上述金屬的合金。In an embodiment of the invention, the first solder metal layer material comprises Ag, Al, Ni, Rh, Au, Cu, Ti, Pt, Pd, Mo, Cr, W, Sn or an alloy of the above metals.
在本發明的一實施例中，上述的第二焊接金屬層材料包含Ag、Al、Ni、Rh、Au、Cu、Ti、Pt、Pd、Mo、Cr、W、Sn或上述金屬的合金。In an embodiment of the invention, the second solder metal layer material comprises Ag, Al, Ni, Rh, Au, Cu, Ti, Pt, Pd, Mo, Cr, W, Sn or an alloy of the above metals.
在本發明的一實施例中，上述的接合基板包含純金屬基板、銅基板、鎢基板、鋁基板、合金基板、銅鎢基板、陶瓷基板、氧化鋁基板、矽基板或碳化矽基板。In an embodiment of the invention, the bonding substrate includes a pure metal substrate, a copper substrate, a tungsten substrate, an aluminum substrate, an alloy substrate, a copper tungsten substrate, a ceramic substrate, an alumina substrate, a germanium substrate, or a tantalum carbide substrate.
在本發明的一實施例中，上述的接合基板的熱膨脹係數高於或等於上述的緩衝層的熱膨脹係數。In an embodiment of the invention, the bonded substrate has a thermal expansion coefficient higher than or equal to a thermal expansion coefficient of the buffer layer.
在本發明的一實施例中，上述的接合基板的熱膨脹係數低於或等於上述的緩衝層的熱膨脹係數。In an embodiment of the invention, the bonded substrate has a thermal expansion coefficient lower than or equal to a thermal expansion coefficient of the buffer layer.
在本發明的一實施例中，上述的緩衝層具有表面粗化結構，增加光取出效率。In an embodiment of the invention, the buffer layer has a surface roughening structure to increase light extraction efficiency.
在本發明的一實施例中，上述的高反射絕緣層由多個介電材料對(pair)組成，上述的多個介電材料對包括多個第一介電對以及多個第二介電對。In an embodiment of the invention, the high reflective insulating layer is composed of a plurality of pairs of dielectric materials, and the plurality of dielectric material pairs include a plurality of first dielectric pairs and a plurality of second dielectrics. Correct.
在本發明的一實施例中，上述的第一介電對包括第一材料層以及第二材料層。其中上述的第一材料層折射系數(refractive index)大於第二材料層。In an embodiment of the invention, the first dielectric pair includes a first material layer and a second material layer. Wherein the first material layer has a refractive index greater than the second material layer.
在本發明的一實施例中，上述的第一材料層以及上述的第二材料層的光學厚度小於四分之一的波長，上述的波長為上述的氮化物半導體量子井發光結構所發出的波長。In an embodiment of the invention, the first material layer and the second material layer have an optical thickness of less than a quarter of a wavelength, and the wavelength is a wavelength emitted by the nitride semiconductor quantum well emitting structure. .
在本發明的一實施例中，上述的第二介電對包括第一材料層以及第二材料層。其中上述的第一材料層折射系數(refractive index)大於第二材料層。In an embodiment of the invention, the second dielectric pair includes a first material layer and a second material layer. Wherein the first material layer has a refractive index greater than the second material layer.
在本發明的一實施例中，上述的第一材料層的光學厚度小於四分之一的波長，上述的第二材料層的光學厚度大於四分之一的波長，上述的波長為上述的氮化物半導體量子井發光結構所發出的波長。In an embodiment of the invention, the first material layer has an optical thickness of less than a quarter of a wavelength, and the second material layer has an optical thickness greater than a quarter of a wavelength, wherein the wavelength is the nitrogen The wavelength emitted by the quantum structure of a quantum well.
在本發明的一實施例中，上述的氮化物半導體元件設置於封裝載體以及封裝基板上，其中上述的封裝基板包括電路板以及二個銲墊。上述的二個銲墊設置於上述的電路板上。其中上述的封裝載體包括支架、二個導電引腳、樹脂、二個導電材料、透明膠以及螢光粉。上述的二個導電引腳設置於上述的支架上，用以與上述的二個銲墊電性連接，其中上述的氮化物半導體元件設置於上述的二個導電引腳上，並與上述的二個導電引腳電性連接。上述的樹脂設置於上述的支架上，並用以容納上述的氮化物半導體元件及上述的二個導電引腳。上述的二個導電材料用以電性連接上述的上述的氮化物半導體元件及上述的二個導電引腳。上述的透明膠用以包覆上述的上述的氮化物半導體元件及上述的二個導電引腳。上述的螢光粉用以填入於上述的透明膠中。In an embodiment of the invention, the nitride semiconductor device is disposed on a package carrier and a package substrate, wherein the package substrate comprises a circuit board and two pads. The above two pads are disposed on the above circuit board. The package carrier described above comprises a bracket, two conductive pins, a resin, two conductive materials, a transparent glue and a phosphor powder. The two conductive pins are disposed on the bracket for electrically connecting to the two solder pads, wherein the nitride semiconductor component is disposed on the two conductive pins, and the two The conductive pins are electrically connected. The above resin is disposed on the above-mentioned bracket and is used to accommodate the above-described nitride semiconductor device and the above two conductive pins. The two conductive materials are electrically connected to the nitride semiconductor device and the two conductive pins. The above transparent adhesive is used to coat the above-described nitride semiconductor device and the above two conductive pins. The above phosphor powder is used to fill in the above transparent glue.
在本發明的一實施例中，上述的螢光粉其係由具高穩定發光特性的材料所製成，例如石榴石系(Garnet)、硫化物(Sulfate)、氮化物(Nitrate)、矽酸鹽(Silicate)、鋁酸鹽(Aluminate)或上述材料的任意組合，但不以此為限，其發光波長約為300nm至700nm。其中上述的螢光粉的粒徑為1~25μm。In an embodiment of the invention, the phosphor powder is made of a material having high stable luminescent properties, such as Garnet, Sulfate, Nitrate, and Citrate. Silicate, aluminate or any combination of the above materials, but not limited thereto, has an emission wavelength of about 300 nm to 700 nm. The above-mentioned phosphor powder has a particle diameter of 1 to 25 μm.
在本發明的一實施例中，上述的導電材料包含銲線或金、銀、銅、鋁、或是混合材料。In an embodiment of the invention, the conductive material comprises a bonding wire or gold, silver, copper, aluminum, or a mixed material.
在本發明的一實施例中，上述的透明膠材包括環氧樹脂。In an embodiment of the invention, the transparent adhesive material comprises an epoxy resin.
在本發明的一實施例中，上述的導電引腳可為纯金屬材料、金、銀、銅、鋁、或低熔點金屬合金、金錫合金、錫、鉍或錫鉍合金。In an embodiment of the invention, the conductive pins may be pure metal materials, gold, silver, copper, aluminum, or low melting point metal alloys, gold tin alloys, tin, antimony or tin antimony alloys.
在本發明的一實施例中，上述的氮化物半導體元件可應用於車用照明領域。In an embodiment of the invention, the nitride semiconductor device described above can be applied to the field of automotive lighting.
在本發明的一實施例中，上述的氮化物半導體元件可應用於一般照明領域。In an embodiment of the invention, the nitride semiconductor device described above can be applied to the field of general illumination.
在本發明的一實施例中，上述的氮化物半導體元件可應用於閃光燈領域。In an embodiment of the invention, the nitride semiconductor device described above can be applied to the field of flash lamps.
在本發明的一實施例中，上述的氮化物半導體元件可應用於背光領域。In an embodiment of the invention, the nitride semiconductor device described above can be applied to the field of backlights.
在本發明的一實施例中，上述的氮化物半導體元件可應用於戶外看板領域。In an embodiment of the invention, the nitride semiconductor device described above can be applied to the field of outdoor signage.
在本發明的一實施例中，上述的氮化物半導體元件的發光效率高於220流明每瓦(lm/W)。In an embodiment of the invention, the nitride semiconductor device has a luminous efficiency higher than 220 lumens per watt (lm/W).
在本發明的一實施例中，上述的氮化物半導體元件的顯色指數中對紅色的顯示能力(R9)大於90。In an embodiment of the invention, the display index (R9) for red in the color rendering index of the nitride semiconductor device is greater than 90.
在本發明的一實施例中，上述的氮化物半導體元件的演色性指數(Color Rendering Index；CRI)大於90。In an embodiment of the invention, the nitride semiconductor element has a Color Rendering Index (CRI) greater than 90.
在本發明的一實施例中，上述的氮化物半導體元件的平均演色評價指數（Ra）大於90。In an embodiment of the invention, the nitride semiconductor device has an average color rendering index (Ra) of more than 90.
在本發明的一實施例中，上述的微結構為週期性突出結構，上述的週期性突出結構包括高度、寬度以及底面間距。In an embodiment of the invention, the microstructure is a periodic protruding structure, and the periodic protruding structure includes a height, a width, and a bottom surface spacing.
在本發明的一實施例中，上述的高度介於1微米至3微米之間。In an embodiment of the invention, the height is between 1 micrometer and 3 micrometers.
在本發明的一實施例中，上述的寬度介於1微米至3微米之間。In an embodiment of the invention, the width is between 1 micrometer and 3 micrometers.
在本發明的一實施例中，上述的底面間距介於0.1微米至3微米之間。In an embodiment of the invention, the bottom surface spacing is between 0.1 microns and 3 microns.
在本發明的一實施例中，上述的基板上述的第二面的粗糙度大於上述的成長表面以及上述的多個微結構的表面。In an embodiment of the invention, the roughness of the second surface of the substrate is greater than the growth surface and the surface of the plurality of microstructures.
在本發明的一實施例中，上述的微結構的外型為半球體(hemisphere)。In an embodiment of the invention, the microstructure of the microstructure is a hemisphere.
在本發明的一實施例中，上述的微結構的外型為錐體(cone)。In an embodiment of the invention, the microstructure of the microstructure is a cone.
在本發明的一實施例中，上述的微結構的外型為截頭錐體(truncated-cone)。In an embodiment of the invention, the microstructure of the microstructure is a truncated-cone.
在本發明的一實施例中，上述的微結構的外型為金字塔(pyramid)。In an embodiment of the invention, the microstructure of the above microstructure is a pyramid.
在本發明的一實施例中，上述的微結構的外型為截頭金字塔(truncated-pyramid)。In an embodiment of the invention, the microstructure of the above structure is a truncated-pyramid.
在本發明的一實施例中，上述的微結構的外型為方柱(square pillar)。In an embodiment of the invention, the microstructure of the microstructure is a square pillar.
在本發明的一實施例中，上述的微結構的外型為圓桶(cylinder)。In an embodiment of the invention, the microstructure of the above structure is a cylinder.
本發明提供一種氮化物半導體元件，其包括P型氮化物半導體、N型氮化物半導體、氮化物半導體量子井發光結構、基板以及緩衝層。上述的氮化物半導體量子井發光結構位於上述的P型氮化物半導體及上述的N型氮化物半導體之間。上述的基板包含相對的第一面以及第二面。上述的緩衝層位於上述的N型氮化物半導體以及上述的基板的上述的第一面之間。其中上述的氮化物半導體量子井發光結構具有多個井層和多個阻擋層，上述的多個阻擋層包含配置於最接近上述的P型氮化物半導體位置的第一阻擋層、配置於最接近上述的N型氮化物半導體位置的第二阻擋層以及多個第三阻擋層，其中上述的多個第三阻擋層被上述的多個井層夾住，其中上述的第一阻擋層的厚度小於上述的第二阻擋層的厚度。The present invention provides a nitride semiconductor device including a P-type nitride semiconductor, an N-type nitride semiconductor, a nitride semiconductor quantum well light-emitting structure, a substrate, and a buffer layer. The above-described nitride semiconductor quantum well light-emitting structure is located between the above-described P-type nitride semiconductor and the above-described N-type nitride semiconductor. The substrate described above includes opposing first and second faces. The buffer layer is located between the N-type nitride semiconductor and the first surface of the substrate. Wherein the nitride semiconductor quantum well light-emitting structure has a plurality of well layers and a plurality of barrier layers, and the plurality of barrier layers include a first barrier layer disposed at a position closest to the P-type nitride semiconductor, and disposed closest to a second barrier layer of the N-type nitride semiconductor position and a plurality of third barrier layers, wherein the plurality of third barrier layers are sandwiched by the plurality of well layers, wherein the thickness of the first barrier layer is less than The thickness of the second barrier layer described above.
在本發明的一實施例中，上述的第二阻擋層的厚度與上述的第三阻擋層的厚度相同。In an embodiment of the invention, the thickness of the second barrier layer is the same as the thickness of the third barrier layer.
在本發明的一實施例中，上述的第二阻擋層的厚度與上述的第三阻擋層的厚度不同。In an embodiment of the invention, the thickness of the second barrier layer is different from the thickness of the third barrier layer.
本發明的氮化物半導體元件包括P型氮化物半導體、N型氮化物半導體、氮化物半導體量子井發光結構、基板以及緩衝層。上述的氮化物半導體量子井發光結構位於上述的P型氮化物半導體及上述的N型氮化物半導體之間。上述的基板包含相對的第一面以及第二面。上述的緩衝層位於上述的N型氮化物半導體以及上述的基板的上述的第一面之間。其中上述的氮化物半導體量子井發光結構具有多個井層和多個阻擋層，上述的多個阻擋層包含一配置於最接近前述P型氮化物半導體位置的第一阻擋層、一配置於最接近前述N型氮化物半導體位置的第二阻擋層以及多個第三阻擋層，其中上述的多個第三阻擋層被上述的多個井層夾住，其中上述的第一阻擋層的厚度小於上述的第三阻擋層的厚度。The nitride semiconductor device of the present invention includes a P-type nitride semiconductor, an N-type nitride semiconductor, a nitride semiconductor quantum well light-emitting structure, a substrate, and a buffer layer. The above-described nitride semiconductor quantum well light-emitting structure is located between the above-described P-type nitride semiconductor and the above-described N-type nitride semiconductor. The substrate described above includes opposing first and second faces. The buffer layer is located between the N-type nitride semiconductor and the first surface of the substrate. The nitride semiconductor quantum well light-emitting structure has a plurality of well layers and a plurality of barrier layers, and the plurality of barrier layers include a first barrier layer disposed at a position closest to the P-type nitride semiconductor, and a first barrier layer disposed at the most a second barrier layer adjacent to the position of the N-type nitride semiconductor and a plurality of third barrier layers, wherein the plurality of third barrier layers are sandwiched by the plurality of well layers, wherein the thickness of the first barrier layer is less than The thickness of the third barrier layer described above.
在本發明的一實施例中，上述的第二阻擋層的厚度與上述的第三阻擋層的厚度相同。In an embodiment of the invention, the thickness of the second barrier layer is the same as the thickness of the third barrier layer.
在本發明的一實施例中，上述的第二阻擋層的厚度與上述的第三阻擋層的厚度不同。In an embodiment of the invention, the thickness of the second barrier layer is different from the thickness of the third barrier layer.
本發明提供一種氮化物半導體元件，其包括P型氮化物半導體、N型氮化物半導體、緩衝層、氮化物半導體量子井發光結構、高反射絕緣層、P型高反射歐姆電極、N型電極、第一焊接金屬層、第二焊接金屬層、接合基板以及基板電極。上述的氮化物半導體量子井發光結構位於上述的P型氮化物半導體及上述的N型氮化物半導體之間。上述的高反射絕緣層覆蓋於上述的P型氮化物半導體。上述的P型高反射歐姆電極覆蓋於上述的高反射絕緣層以及上述的P型氮化物半導體，並與上述的P型氮化物半導體電性連接。上述的N型電極覆蓋於上述的緩衝層，並與上述的N型氮化物半導體電性連接。上述的第一焊接金屬層覆蓋於上述的P型高反射歐姆電極，並與上述的P型氮化物半導體電性連接。上述的第二焊接金屬層覆蓋於上述的第一焊接金屬層，並與上述的P型氮化物半導體電性連接。上述的接合基板覆蓋於上述的第二焊接金屬層，並與上述的P型氮化物半導體電性連接。上述的基板電極覆蓋於上述的接合基板，並與上述的P型氮化物半導體電性連接。上述的氮化物半導體量子井發光結構具有多個井層和多個阻擋層，上述的多個阻擋層包含一配置於最接近前述P型氮化物半導體位置的第一阻擋層、一配置於最接近前述N型氮化物半導體位置的第二阻擋層以及多個第三阻擋層，其中上述的多個第三阻擋層被上述的多個井層夾住，其中上述的第一阻擋層的厚度小於上述的第二阻擋層的厚度。The present invention provides a nitride semiconductor device including a P-type nitride semiconductor, an N-type nitride semiconductor, a buffer layer, a nitride semiconductor quantum well light-emitting structure, a highly reflective insulating layer, a P-type high-reflection ohmic electrode, an N-type electrode, a first solder metal layer, a second solder metal layer, a bonding substrate, and a substrate electrode. The above-described nitride semiconductor quantum well light-emitting structure is located between the above-described P-type nitride semiconductor and the above-described N-type nitride semiconductor. The above-described highly reflective insulating layer covers the above-described P-type nitride semiconductor. The P-type high-reflection ohmic electrode described above covers the above-described high-reflection insulating layer and the above-described P-type nitride semiconductor, and is electrically connected to the above-described P-type nitride semiconductor. The N-type electrode described above covers the buffer layer and is electrically connected to the N-type nitride semiconductor described above. The first solder metal layer is covered on the P-type high-reflection ohmic electrode and electrically connected to the P-type nitride semiconductor. The second solder metal layer covers the first solder metal layer and is electrically connected to the P-type nitride semiconductor. The bonding substrate described above covers the second solder metal layer and is electrically connected to the P-type nitride semiconductor described above. The substrate electrode described above covers the bonded substrate and is electrically connected to the P-type nitride semiconductor described above. The nitride semiconductor quantum well light-emitting structure has a plurality of well layers and a plurality of barrier layers, and the plurality of barrier layers include a first barrier layer disposed at a position closest to the P-type nitride semiconductor, and a first barrier layer disposed at a closest position a second barrier layer of the N-type nitride semiconductor position and a plurality of third barrier layers, wherein the plurality of third barrier layers are sandwiched by the plurality of well layers, wherein the thickness of the first barrier layer is less than the above The thickness of the second barrier layer.
在本發明的一實施例中，上述的第二阻擋層的厚度與上述的第三阻擋層的厚度相同。In an embodiment of the invention, the thickness of the second barrier layer is the same as the thickness of the third barrier layer.
在本發明的一實施例中，上述的第二阻擋層的厚度與上述的第三阻擋層的厚度不同。In an embodiment of the invention, the thickness of the second barrier layer is different from the thickness of the third barrier layer.
本發明提供一種氮化物半導體元件，其包括P型氮化物半導體、N型氮化物半導體、緩衝層、氮化物半導體量子井發光結構、高反射絕緣層、P型高反射歐姆電極、N型電極、第一焊接金屬層、第二焊接金屬層、接合基板以及基板電極。上述的氮化物半導體量子井發光結構位於上述的P型氮化物半導體及上述的N型氮化物半導體之間。上述的高反射絕緣層覆蓋於上述的P型氮化物半導體。上述的P型高反射歐姆電極覆蓋於上述的高反射絕緣層以及上述的P型氮化物半導體，並與上述的P型氮化物半導體電性連接。上述的N型電極覆蓋於上述的緩衝層，並與上述的N型氮化物半導體電性連接。上述的第一焊接金屬層覆蓋於上述的P型高反射歐姆電極，並與上述的P型氮化物半導體電性連接。上述的第二焊接金屬層覆蓋於上述的第一焊接金屬層，並與上述的P型氮化物半導體電性連接。上述的接合基板覆蓋於上述的第二焊接金屬層，並與上述的P型氮化物半導體電性連接。上述的基板電極覆蓋於上述的接合基板，並與上述的P型氮化物半導體電性連接。上述的氮化物半導體量子井發光結構具有多個井層和多個阻擋層，上述的多個阻擋層包含一配置於最接近前述P型氮化物半導體位置的第一阻擋層、一配置於最接近前述N型氮化物半導體位置的第二阻擋層以及多個第三阻擋層，其中上述的多個第三阻擋層被上述的多個井層夾住，其中上述的第一阻擋層的厚度小於上述的第三阻擋層的厚度。The present invention provides a nitride semiconductor device including a P-type nitride semiconductor, an N-type nitride semiconductor, a buffer layer, a nitride semiconductor quantum well light-emitting structure, a highly reflective insulating layer, a P-type high-reflection ohmic electrode, an N-type electrode, a first solder metal layer, a second solder metal layer, a bonding substrate, and a substrate electrode. The above-described nitride semiconductor quantum well light-emitting structure is located between the above-described P-type nitride semiconductor and the above-described N-type nitride semiconductor. The above-described highly reflective insulating layer covers the above-described P-type nitride semiconductor. The P-type high-reflection ohmic electrode described above covers the above-described high-reflection insulating layer and the above-described P-type nitride semiconductor, and is electrically connected to the above-described P-type nitride semiconductor. The N-type electrode described above covers the buffer layer and is electrically connected to the N-type nitride semiconductor described above. The first solder metal layer is covered on the P-type high-reflection ohmic electrode and electrically connected to the P-type nitride semiconductor. The second solder metal layer covers the first solder metal layer and is electrically connected to the P-type nitride semiconductor. The bonding substrate described above covers the second solder metal layer and is electrically connected to the P-type nitride semiconductor described above. The substrate electrode described above covers the bonded substrate and is electrically connected to the P-type nitride semiconductor described above. The nitride semiconductor quantum well light-emitting structure has a plurality of well layers and a plurality of barrier layers, and the plurality of barrier layers include a first barrier layer disposed at a position closest to the P-type nitride semiconductor, and a first barrier layer disposed at a closest position a second barrier layer of the N-type nitride semiconductor position and a plurality of third barrier layers, wherein the plurality of third barrier layers are sandwiched by the plurality of well layers, wherein the thickness of the first barrier layer is less than the above The thickness of the third barrier layer.
在本發明的一實施例中，上述的第二阻擋層的厚度與上述的第三阻擋層的厚度相同。In an embodiment of the invention, the thickness of the second barrier layer is the same as the thickness of the third barrier layer.
在本發明的一實施例中，上述的第二阻擋層的厚度與上述的第三阻擋層的厚度不同。In an embodiment of the invention, the thickness of the second barrier layer is different from the thickness of the third barrier layer.
本發明提供一種氮化物半導體元件的製造方法，其包括下列步驟。形成半導體晶圓。以隱形雷射方式切割上述的半導體晶圓，形成如上述任一實施例中的氮化物半導體元件。The present invention provides a method of fabricating a nitride semiconductor device comprising the following steps. Forming a semiconductor wafer. The semiconductor wafer is cut in a stealth laser manner to form a nitride semiconductor device according to any of the above embodiments.
本發明提供一種封裝結構，其包括電路板、支架、以及如上述任一實施例中的氮化物半導體元件。上述的支架設置於上述的電路板上。上述的氮化物半導體元件設置於上述的支架上。The present invention provides a package structure including a circuit board, a holder, and a nitride semiconductor element as in any of the above embodiments. The above bracket is provided on the above circuit board. The nitride semiconductor device described above is provided on the above-described holder.
在本發明的一實施例中，上述的封裝結構更包括透明膠覆蓋上述的氮化物半導體元件。In an embodiment of the invention, the package structure further includes a transparent adhesive covering the nitride semiconductor device.
在本發明的一實施例中，上述的封裝結構更包括螢光粉，填入於上述的透明膠內。In an embodiment of the invention, the package structure further comprises a phosphor powder filled in the transparent glue.
在本發明的一實施例中，上述的螢光粉的濃度係均勻分佈於上述的透明膠內。In an embodiment of the invention, the concentration of the phosphor powder is uniformly distributed in the transparent paste.
在本發明的一實施例中，上述的螢光粉的濃度係不均勻分佈於上述的透明膠內。In an embodiment of the invention, the concentration of the phosphor powder is unevenly distributed in the transparent paste.
在本發明的一實施例中，上述的螢光粉的濃度係由上述的氮化物半導體元件的表面往上述的透明膠的表面逐漸增加。In an embodiment of the invention, the concentration of the phosphor powder is gradually increased from the surface of the nitride semiconductor element to the surface of the transparent paste.
在本發明的一實施例中，上述的螢光粉的濃度係由上述的氮化物半導體元件的表面往上述的透明膠的表面逐漸減少。In an embodiment of the invention, the concentration of the phosphor powder is gradually reduced from the surface of the nitride semiconductor element to the surface of the transparent paste.
在本發明的一實施例中，上述的螢光粉其係由具高穩定發光特性的材料所製成，例如石榴石系(Garnet)、硫化物(Sulfate)、氮化物(Nitrate)、矽酸鹽(Silicate)、鋁酸鹽(Aluminate)或上述材料的任意組合，但不以此為限，其發光波長約為300nm至700nm。其中上述的螢光粉的粒徑為1~25μm。In an embodiment of the invention, the phosphor powder is made of a material having high stable luminescent properties, such as Garnet, Sulfate, Nitrate, and Citrate. Silicate, aluminate or any combination of the above materials, but not limited thereto, has an emission wavelength of about 300 nm to 700 nm. The above-mentioned phosphor powder has a particle diameter of 1 to 25 μm.
本發明提供一種氮化物半導體元件，其包括基板、緩衝層、第一N型氮化物半導體、氮化物半導體量子井發光結構、P型氮化物半導體、穿隧接面(Tunnel Junction)以及第二N型氮化物半導體。上述的基板具有相對的第一面及第二面。上述的緩衝層設置於上述的基板的上述的第一面上。上述的第一N型氮化物半導體設置於上述的緩衝層上。上述的氮化物半導體量子井發光結構設置於上述的第一N型氮化物半導體上。上述的P型氮化物半導體設置於上述的氮化物半導體量子井發光結構上。上述的穿隧接面設置於上述的氮化物半導體量子井發光結構上。上述的穿隧接面包括重摻雜P型(P+)氮化物半導體以及重摻雜N型(N+)氮化物半導體。上述的重摻雜P型(P+)氮化物半導體設置於上述的氮化物半導體量子井發光結構上。上述的重摻雜N型(N+)氮化物半導體設置於上述的重摻雜P型氮化物半導體上。上述的第二N型氮化物半導體設置於上述的穿隧接面的上述的重摻雜N型氮化物半導體上。其中上述的氮化物半導體量子井發光結構具有多個井層和多個阻擋層，上述的多個阻擋層包含配置於最接近上述的P型氮化物半導體位置的第一阻擋層、配置於最接近上述的第一N型氮化物半導體位置的第二阻擋層以及多個第三阻擋層，其中上述的多個第三阻擋層被上述的多個井層夾住，其中上述的第一阻擋層的厚度小於100埃(Å)。The present invention provides a nitride semiconductor device including a substrate, a buffer layer, a first N-type nitride semiconductor, a nitride semiconductor quantum well light emitting structure, a P-type nitride semiconductor, a tunnel junction, and a second N Type nitride semiconductor. The substrate has opposite first and second faces. The buffer layer is provided on the first surface of the substrate described above. The first N-type nitride semiconductor described above is provided on the buffer layer described above. The nitride semiconductor quantum well light-emitting structure described above is provided on the first N-type nitride semiconductor described above. The above-described P-type nitride semiconductor is provided on the above-described nitride semiconductor quantum well light-emitting structure. The tunneling junction surface described above is disposed on the nitride semiconductor quantum well light emitting structure. The tunneling junction described above includes a heavily doped P-type (P+) nitride semiconductor and a heavily doped N-type (N+) nitride semiconductor. The above heavily doped P-type (P+) nitride semiconductor is provided on the above-described nitride semiconductor quantum well light-emitting structure. The above heavily doped N-type (N+) nitride semiconductor is provided on the above-described heavily doped P-type nitride semiconductor. The second N-type nitride semiconductor is provided on the above-described heavily doped N-type nitride semiconductor on the tunnel junction surface. Wherein the nitride semiconductor quantum well light-emitting structure has a plurality of well layers and a plurality of barrier layers, and the plurality of barrier layers include a first barrier layer disposed at a position closest to the P-type nitride semiconductor, and disposed closest to a second barrier layer of the first N-type nitride semiconductor position and a plurality of third barrier layers, wherein the plurality of third barrier layers are sandwiched by the plurality of well layers, wherein the first barrier layer The thickness is less than 100 angstroms (Å).
在本發明的一實施例中，上述的重摻雜P型半導體層的能隙(Energy Bandgap)越靠近上述的P型氮化物半導體越高，上述的重摻雜N型氮化物半導體層的能隙越靠近上述的第二N型氮化物半導體越高。In an embodiment of the invention, the energy bandgap of the heavily doped P-type semiconductor layer is higher as the P-type nitride semiconductor is higher, and the energy of the heavily doped N-type nitride semiconductor layer is higher. The closer the gap is to the second N-type nitride semiconductor described above.
在本發明的一實施例中，上述的重摻雜P型半導體層的厚度約為1nm～100nm，上述的重摻雜N型氮化物半導體層的厚度約為1奈米(nanometer；nm)～100nm。In an embodiment of the invention, the heavily doped P-type semiconductor layer has a thickness of about 1 nm to 100 nm, and the heavily doped N-type nitride semiconductor layer has a thickness of about 1 nm (nanometer; nm). 100nm.
在本發明的一實施例中，上述的第二阻擋層的厚度大於上述的第一阻擋層的厚度，第三阻擋層的厚度大於上述的第一阻擋層的厚度，第二阻擋層的厚度大於或是等於上述的第三阻擋層的厚度。In an embodiment of the invention, the thickness of the second barrier layer is greater than the thickness of the first barrier layer, the thickness of the third barrier layer is greater than the thickness of the first barrier layer, and the thickness of the second barrier layer is greater than Or equal to the thickness of the third barrier layer described above.
在本發明的一實施例中，上述的第二阻擋層的厚度大於上述的第一阻擋層的厚度，第三阻擋層的厚度大於上述的第一阻擋層的厚度，上述的第二阻擋層的厚度小於或是等於上述的第三阻擋層的厚度。In an embodiment of the invention, the thickness of the second barrier layer is greater than the thickness of the first barrier layer, the thickness of the third barrier layer is greater than the thickness of the first barrier layer, and the second barrier layer is The thickness is less than or equal to the thickness of the third barrier layer described above.
在本發明的一實施例中，上述的第一N型氮化物半導體及上述的第二N型氮化物半導體的至少一者具有粗糙表面，用以增加上述的氮化物半導體元件的出光效果。In an embodiment of the invention, at least one of the first N-type nitride semiconductor and the second N-type nitride semiconductor has a rough surface for increasing the light-emitting effect of the nitride semiconductor device.
在本發明的一實施例中，上述的P型氮化物半導體包括P側應力釋放層、高濃度電洞層以及電子阻擋層。其中配置於最接近上述的第一阻擋層為上述的P側應力釋放層，配置於最遠離上述的第一阻擋層為上述的電子阻擋層，上述的高濃度電洞層被上述的P側應力釋放層以及上述的電子阻擋層所夾住。In an embodiment of the invention, the P-type nitride semiconductor includes a P-side stress releasing layer, a high-concentration hole layer, and an electron blocking layer. The first barrier layer disposed closest to the first barrier layer is the P-side stress relief layer described above, and the first barrier layer disposed farthest from the above is the above-described electron blocking layer, and the high-concentration hole layer is subjected to the P-side stress described above. The release layer and the above-described electron blocking layer are sandwiched.
在本發明的一實施例中，上述的P側應力釋放層可為超晶格結構，其材料包含氮化鋁鎵(AlGaN)以及氮化鎵(GaN)所構成的超晶格結構，或是由氮化鋁鎵(Alx GaN)以及氮化鋁鎵(Aly GaN)所構成的超晶格結構，或是由氮化鋁鎵(AlGaN)以及氮化鋁銦鎵(InAlGaN)所構成的超晶格結構，其中，x不等於y，上述的超晶格結構小於20對。In an embodiment of the invention, the P-side stress relief layer may be a superlattice structure, the material of which comprises a superlattice structure composed of aluminum gallium nitride (AlGaN) and gallium nitride (GaN), or a superlattice structure composed of aluminum gallium nitride (Al x GaN) and aluminum gallium nitride (Al y GaN), or composed of aluminum gallium nitride (AlGaN) and aluminum indium gallium nitride (InAlGaN) A superlattice structure in which x is not equal to y and the superlattice structure described above is less than 20 pairs.
在本發明的一實施例中，上述的高濃度電洞層可由氮化鎵(GaN)或是氮化鋁鎵(AlGaN)所構成，上述的高濃度電洞層的鎂摻雜濃度(concentration)高於上述的P側應力釋放層的鎂摻雜濃度以及上述的電子阻擋層的鎂摻雜濃度。In an embodiment of the invention, the high-concentration hole layer may be composed of gallium nitride (GaN) or aluminum gallium nitride (AlGaN), and the magnesium concentration of the high-concentration hole layer is concentrated. It is higher than the magnesium doping concentration of the P-side stress releasing layer described above and the magnesium doping concentration of the above-described electron blocking layer.
在本發明的一實施例中，上述的高濃度電洞層的鎂(Mg)摻雜濃度高於1x1019 (Atoms/cm3 )。In an embodiment of the invention, the high concentration hole layer has a magnesium (Mg) doping concentration higher than 1 x 10 19 (Atoms/cm 3 ).
在本發明的一實施例中，上述的電子阻擋層可由氮化鋁鎵(AlGaN)所構成，上述的電子阻擋層的鋁成份百分比高於上述的P側應力釋放層的鋁成份百分比以及高於上述的高濃度電洞層的鋁成份百分比。In an embodiment of the invention, the electron blocking layer may be composed of aluminum gallium nitride (AlGaN), and the percentage of the aluminum component of the electron blocking layer is higher than the percentage of the aluminum component of the P-side stress releasing layer and higher than The percentage of aluminum component of the high concentration hole layer described above.
在本發明的一實施例中，上述的穿隧接面更包括中間半導體，設置於上述的重摻雜P型(P+)氮化物半導體及上述的重摻雜N型(N+)氮化物半導體之間。In an embodiment of the invention, the tunneling junction further includes an intermediate semiconductor disposed on the heavily doped P-type (P+) nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor. between.
在本發明的一實施例中，上述的高濃度電洞層的鎂(Mg)摻雜濃度高於1x1019 (Atoms/cm3 )，且上述的高濃度電洞層的鋁成份百分比低於上述的電子阻擋層的鋁成份百分比。In an embodiment of the invention, the high concentration hole layer has a magnesium (Mg) doping concentration higher than 1×10 19 (Atoms/cm 3 ), and the high concentration hole layer has a lower aluminum component percentage than the above. The percentage of aluminum component of the electronic barrier layer.
在本發明的一實施例中，上述的第一N型氮化物半導體包括N側第一應力釋放層、N側第二應力釋放層、低濃度電子層以及N型歐姆接觸層。其中配置於最接近上述的第二阻擋層為上述的N側第一應力釋放層，配置於最遠離述上述的第二阻擋層為上述的N型歐姆接觸層，上述的低濃度電子層以及上述的第二應力釋放層依序堆疊於上述的N型歐姆接觸層上方，上述的低濃度電子層被上述的N型歐姆接觸層及上述的N側第二應力釋放層所夾住。In an embodiment of the invention, the first N-type nitride semiconductor includes an N-side first stress relief layer, an N-side second stress relief layer, a low concentration electron layer, and an N-type ohmic contact layer. The second barrier layer disposed closest to the above is the N-side first stress relief layer, and the second barrier layer farthest from the above is the N-type ohmic contact layer, the low-concentration electron layer and the above The second stress relief layer is sequentially stacked over the N-type ohmic contact layer, and the low-concentration electron layer is sandwiched by the N-type ohmic contact layer and the N-side second stress-relieving layer.
在本發明的一實施例中，上述的N側第一應力釋放層可為超晶格結構，其材料包含氮化銦鎵(InGaN)以及氮化鎵(GaN)所構成的超晶格結構，或是由氮化銦鎵(Inx GaN)以及氮化銦鎵(Iny GaN)所構成的超晶格結構，其中x不等於y，上述的超晶格結構小於20對。In an embodiment of the invention, the N-side first stress relief layer may be a superlattice structure, and the material thereof comprises a superlattice structure composed of indium gallium nitride (InGaN) and gallium nitride (GaN). Or a superlattice structure composed of indium gallium nitride (In x GaN) and indium gallium nitride (In y GaN), wherein x is not equal to y, and the superlattice structure described above is less than 20 pairs.
在本發明的一實施例中，上述的N側第二應力釋放層可為超晶格結構，其材料包含氮化銦鎵(InGaN)以及氮化鎵(GaN)所構成的超晶格結構，或是由氮化銦鎵(Inx GaN))以及氮化銦鎵(Iny GaN)所構成的超晶格結構，其中x不等於y，上述的超晶格結構小於20對。In an embodiment of the invention, the N-side second stress relief layer may be a superlattice structure, and the material thereof comprises a superlattice structure composed of indium gallium nitride (InGaN) and gallium nitride (GaN). Or a superlattice structure composed of indium gallium nitride (In x GaN) and indium gallium nitride (In y GaN), wherein x is not equal to y, and the superlattice structure described above is less than 20 pairs.
在本發明的一實施例中，上述的N側第一應力釋放層的銦成份百分比高於上述的N側第二應力釋放層的銦成份百分比。In an embodiment of the invention, the percentage of indium component of the N-side first stress-relieving layer is higher than the percentage of the indium component of the N-side second stress-relieving layer.
在本發明的一實施例中，上述的低濃度電子層可由氮化鎵(GaN)、氮化銦鎵(InGaN)、氮化鋁鎵(AlGaN)或氮化銦鋁鎵(InAlGaN)所構成，上述的低濃度電子層的矽摻雜濃度低於上述的N型歐姆接觸層的矽摻雜濃度。In an embodiment of the invention, the low-concentration electron layer may be formed of gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), or indium aluminum gallium nitride (InAlGaN). The above-mentioned low-concentration electron layer has a germanium doping concentration lower than that of the above-described N-type ohmic contact layer.
在本發明的一實施例中，上述的低濃度電子層的矽摻雜濃度低於1x1018 (Atoms/cm3 )。In an embodiment of the invention, the low concentration electron layer has a germanium doping concentration of less than 1 x 10 18 (Atoms/cm 3 ).
在本發明的一實施例中，上述的N型歐姆接觸層可由氮化鎵(GaN)、氮化銦鎵(InGaN)、氮化鋁鎵(AlGaN)或氮化銦鋁鎵(InAlGaN)所構成，上述的N型歐姆接觸層的矽摻雜濃度高於上述的N側第一應力釋放層的矽摻雜濃度、上述的N側第二應力釋放層的矽摻雜濃度及上述的低濃度電子層的矽摻雜濃度。In an embodiment of the invention, the N-type ohmic contact layer may be formed of gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN) or indium aluminum gallium nitride (InAlGaN). The cerium doping concentration of the N-type ohmic contact layer is higher than the cerium doping concentration of the N-side first stress-relieving layer, the cerium doping concentration of the N-side second stress-relieving layer, and the low-concentration electrons described above. The erbium doping concentration of the layer.
在本發明的一實施例中，上述的P側應力釋放層的上述的超晶格結構小於10對。In an embodiment of the invention, the super-lattice structure of the P-side stress relief layer is less than 10 pairs.
在本發明的一實施例中，上述的N側第一應力釋放層的上述的超晶格結構小於10對。In an embodiment of the invention, the above-described superlattice structure of the N-side first stress relief layer is less than 10 pairs.
在本發明的一實施例中，上述的N側第二應力釋放層的上述的超晶格結構小於10對。In an embodiment of the invention, the above-mentioned N-side second stress relief layer has a super-lattice structure of less than 10 pairs.
在本發明的一實施例中，上述的基板係選自包含III-V族、IV族、II-VI族的元素與合金、氧化鋅(ZnO)、尖晶石(spinel)、氮化鎵(GaN)、藍寶石(sapphire)、矽(Si)所組成的群組中的至少一者。In an embodiment of the invention, the substrate is selected from the group consisting of elements and alloys including Group III-V, Group IV, Group II-VI, zinc oxide (ZnO), spinel, and gallium nitride ( At least one of a group consisting of GaN), sapphire, and bismuth (Si).
在本發明的一實施例中，上述的緩衝層包括第一緩衝層以及第二緩衝層。其中上述的第一緩衝層被上述的基板的上述的第一面及上述的第二緩衝層所夾住，上述的第一緩衝層的缺陷密度高於上述的第二緩衝層的缺陷密度，上述的第二緩衝層上部為一平坦，且上述的第二緩衝層的缺陷密度低於上述的第一緩衝層的缺陷密度。In an embodiment of the invention, the buffer layer includes a first buffer layer and a second buffer layer. The first buffer layer is sandwiched by the first surface of the substrate and the second buffer layer, and the defect density of the first buffer layer is higher than the defect density of the second buffer layer. The upper portion of the second buffer layer is flat, and the defect density of the second buffer layer is lower than the defect density of the first buffer layer.
在本發明的一實施例中，上述的第一緩衝層的材料可為單晶氮化鎵(GaN)、單晶氮化鋁(AlN)、單晶氮化鋁鎵(AlGaN)或單晶氮化銦鋁鎵(InAlGaN)。In an embodiment of the invention, the material of the first buffer layer may be single crystal gallium nitride (GaN), single crystal aluminum nitride (AlN), single crystal aluminum gallium nitride (AlGaN) or single crystal nitrogen. Indium aluminum gallium (InAlGaN).
在本發明的一實施例中，上述的第一緩衝層的材料可為非單晶氮化鎵(GaN)、非單晶氮化鋁(AlN)、非單晶氮化鋁鎵(AlGaN)或非單晶氮化銦鋁鎵(InAlGaN)。In an embodiment of the invention, the material of the first buffer layer may be non-single crystal gallium nitride (GaN), non-single-crystal aluminum nitride (AlN), non-single-crystal aluminum gallium nitride (AlGaN) or Non-single crystal indium aluminum gallium nitride (InAlGaN).
在本發明的一實施例中，上述的緩衝層的材料包含氮化鎵(GaN)、氮化鋁(AlN)、氮化鋁鎵(AlGaN)或氮化銦鋁鎵(InAlGaN)。In an embodiment of the invention, the material of the buffer layer comprises gallium nitride (GaN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN) or indium aluminum gallium nitride (InAlGaN).
在本發明的一實施例中，上述的基板的上述的第一面包括成長表面以及多個位於上述的成長表面上的微結構，上述的多個微結構具有非圓滑的蝕刻側面。In an embodiment of the invention, the first surface of the substrate includes a growth surface and a plurality of microstructures on the growth surface, and the plurality of microstructures have non-smooth etched sides.
在本發明的一實施例中，上述的成長表面的表面粗糙度低於10埃(Å)。In an embodiment of the invention, the growth surface has a surface roughness of less than 10 Å.
在本發明的一實施例中，上述的微結構的表面粗糙度低於10埃(Å)。In an embodiment of the invention, the microstructure has a surface roughness of less than 10 angstroms (Å).
在本發明的一實施例中，上述的微結構為週期性突出結構，上述的週期性突出結構包括高度、寬度以及底面間距。In an embodiment of the invention, the microstructure is a periodic protruding structure, and the periodic protruding structure includes a height, a width, and a bottom surface spacing.
在本發明的一實施例中，上述的高度介於1微米至3微米之間。In an embodiment of the invention, the height is between 1 micrometer and 3 micrometers.
在本發明的一實施例中，上述的寬度介於1微米至3微米之間。In an embodiment of the invention, the width is between 1 micrometer and 3 micrometers.
在本發明的一實施例中，上述的底面間距介於0.1微米至3微米之間。In an embodiment of the invention, the bottom surface spacing is between 0.1 microns and 3 microns.
在本發明的一實施例中，上述的基板的上述的第二面的粗糙度大於上述的成長表面的粗糙度以及上述的多個微結構的表面的粗糙度。In an embodiment of the invention, the roughness of the second surface of the substrate is greater than the roughness of the growth surface and the roughness of the surface of the plurality of microstructures.
在本發明的一實施例中，上述的微結構的外型為半球體(hemisphere)、錐體(cone)、截頭錐體(truncated-cone)、金字塔(pyramid)、截頭金字塔(truncated-pyramid)、方柱(square pillar)或圓桶(cylinder)。In an embodiment of the invention, the microstructure of the above microstructure is a hemisphere, a cone, a truncated-cone, a pyramid, and a truncated pyramid. Pyramid), square pillar or cylinder.
在本發明的一實施例中，上述的穿隧接面更包括中間半導體，設置於上述的重摻雜P型(P+)氮化物半導體及上述的重摻雜N型(N+)氮化物半導體之間，上述的中間半導體相對於上述的重摻雜P型(P+)氮化物半導體及上述的重摻雜N型(N+)氮化物半導體形成異質接面，以建立極化場，使得上述的重摻雜P型(P+)氮化物半導體的價帶及上述的重摻雜N型(N+)氮化物半導體的導帶相互對應。In an embodiment of the invention, the tunneling junction further includes an intermediate semiconductor disposed on the heavily doped P-type (P+) nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor. The intermediate semiconductor is formed into a heterojunction with respect to the above-mentioned heavily doped P-type (P+) nitride semiconductor and the above-mentioned heavily doped N-type (N+) nitride semiconductor to establish a polarization field, so that the above-mentioned weight The valence band of the doped P-type (P+) nitride semiconductor and the conduction band of the above-described heavily doped N-type (N+) nitride semiconductor correspond to each other.
在本發明的一實施例中，上述的重摻雜P型(P+)氮化物半導體及上述的重摻雜N型(N+)氮化物半導體的至少一者的能隙大於上述的氮化物半導體量子井發光結構的能隙。In an embodiment of the invention, at least one of the heavily doped P-type (P+) nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor has a larger energy gap than the nitride semiconductor quantum The energy gap of the well-emitting structure.
在本發明的一實施例中，上述的中間半導體包含氮化鋁鎵(AlGaN)、氮化鎵(GaN)、氮化銦鎵(InGaN)或氮化銦鋁鎵(InAlGaN)。In an embodiment of the invention, the intermediate semiconductor comprises aluminum gallium nitride (AlGaN), gallium nitride (GaN), indium gallium nitride (InGaN) or indium aluminum gallium nitride (InAlGaN).
在本發明的一實施例中，上述的中間半導體具有內部帶穿隧阻擋層(inter band tunnel barrier)，上述的重摻雜P型(P+)氮化物半導體具有P型空乏阻擋層(P-depletion barrier)，上述的重摻雜N型(N+)氮化物半導體具有N型空乏阻擋層(N-depletion barrier)。In an embodiment of the invention, the intermediate semiconductor has an internal band gap barrier, and the heavily doped P-type (P+) nitride semiconductor has a P-type depletion barrier (P-depletion). Barrier), the above heavily doped N-type (N+) nitride semiconductor has an N-depletion barrier.
在本發明的一實施例中，上述的中間半導體的厚度約為0.5nm～10nm。In an embodiment of the invention, the intermediate semiconductor has a thickness of about 0.5 nm to 10 nm.
在本發明的一實施例中，上述的中間半導體具有側面材料能隙波動(lateral material energy bandgap fluctuations)，其包含多個低及高能隙區域(low and high bandgap regions)。In an embodiment of the invention, the intermediate semiconductor has lateral material energy bandgaps, which includes a plurality of low and high band gap regions.
在本發明的一實施例中，上述的氮化物半導體元件更包括平台結構、第一N型電極、電流阻擋層、透明導電層、第二N型電極、絕緣層以及高反射絕緣層。上述的平台結構露出部分上述的N型歐姆接觸層。上述的第一N型電極與上述的N型歐姆接觸層電性連接。上述的電流阻擋層與上述的第二N型氮化物半導體直接接觸。上述的透明導電層覆蓋上述的電流阻擋層以及與上述的第二N型氮化物半導體直接接觸。上述的第二N型電極位於上述的透明導電層的上方，藉由透明導電層與上述的第二N型氮化物半導體電性連接。上述的絕緣層覆蓋上述的第一N型電極以及上述的第二N型電極及上述的平台結構的側壁。上述的高反射絕緣層位於上述的基板的上述的第二面。In an embodiment of the invention, the nitride semiconductor device further includes a platform structure, a first N-type electrode, a current blocking layer, a transparent conductive layer, a second N-type electrode, an insulating layer, and a highly reflective insulating layer. The above-described platform structure exposes some of the above-described N-type ohmic contact layers. The first N-type electrode is electrically connected to the N-type ohmic contact layer described above. The current blocking layer is in direct contact with the second N-type nitride semiconductor described above. The transparent conductive layer covers the current blocking layer and is in direct contact with the second N-type nitride semiconductor. The second N-type electrode is located above the transparent conductive layer, and is electrically connected to the second N-type nitride semiconductor by a transparent conductive layer. The insulating layer covers the first N-type electrode and the second N-type electrode and the sidewall of the above-mentioned platform structure. The high-reflection insulating layer described above is located on the second surface of the substrate described above.
在本發明的一實施例中，上述的高反射絕緣層由多個介電材料對(pair)所組成，上述的多個介電材料對包括多個第一介電對以及多個第二介電對。In an embodiment of the invention, the high reflective insulating layer is composed of a plurality of pairs of dielectric materials, and the plurality of dielectric material pairs include a plurality of first dielectric pairs and a plurality of second dielectric layers. Electric pair.
在本發明的一實施例中，上述的第一介電對包括第一材料層以及第二材料層，其中上述的第一材料層的介電係數大於上述的第二材料層的介電係數。In an embodiment of the invention, the first dielectric pair includes a first material layer and a second material layer, wherein the first material layer has a dielectric constant greater than a dielectric constant of the second material layer.
在本發明的一實施例中，上述的第一材料層以及上述的第二材料層的光學厚度小於四分之一的波長，上述的波長為上述的氮化物半導體量子井發光結構所發出的波長。In an embodiment of the invention, the first material layer and the second material layer have an optical thickness of less than a quarter of a wavelength, and the wavelength is a wavelength emitted by the nitride semiconductor quantum well emitting structure. .
在本發明的一實施例中，上述的第二介電對包括第一材料層以及第二材料層，其中上述的第一材料層的介電係數大於上述的第二材料層的介電係數。In an embodiment of the invention, the second dielectric pair includes a first material layer and a second material layer, wherein the first material layer has a dielectric constant greater than a dielectric constant of the second material layer.
在本發明的一實施例中，上述的第一材料層的光學厚度小於四分之一的波長，上述的第二材料層的光學厚度大於四分之一的波長，上述的波長為上述的氮化物半導體量子井發光結構所發出的波長。In an embodiment of the invention, the first material layer has an optical thickness of less than a quarter of a wavelength, and the second material layer has an optical thickness greater than a quarter of a wavelength, wherein the wavelength is the nitrogen The wavelength emitted by the quantum structure of a quantum well.
在本發明的一實施例中，上述的透明導電層可以是銦錫氧化物(Indium Tin Oxide；ITO)、銦鋅氧化物(indium zinc oxide；IZO)、氧化鋅（Zinc Oxide；ZnO）或氧化鋅鋁(Aluminum Zinc Oxide；AZO)。In an embodiment of the invention, the transparent conductive layer may be Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), Zinc Oxide (ZnO) or Oxidation. Aluminum Zinc Oxide (AZO).
在本發明的一實施例中，上述的絕緣層包括氧化矽(SiOX )、氮化矽(SiNX )、聚醯亞胺(Polyimide)或其他高分子材料。In an embodiment of the present invention, the above-described insulating layer include silicon oxide (SiO X), silicon nitride (SiN X), polyimide (Polyimide) or other polymeric materials.
在本發明的一實施例中，上述的高反射絕緣層的材料包括氧化物、氮化物、或至少包含Si、Ti、Zr、Nb、Ta、Al元素所組成的氧化物或氮化物。In an embodiment of the invention, the material of the high-reflection insulating layer includes an oxide, a nitride, or an oxide or a nitride composed of at least Si, Ti, Zr, Nb, Ta, and Al elements.
在本發明的一實施例中，上述的第一N型電極的材料包括Ag、Al、Ni、Rh、Au、Cu、Ti、Pt、Pd、Mo、Cr、W或上述金屬的合金。In an embodiment of the invention, the material of the first N-type electrode includes Ag, Al, Ni, Rh, Au, Cu, Ti, Pt, Pd, Mo, Cr, W or an alloy of the above metals.
在本發明的一實施例中，上述的第二N型電極的材料包括Ag、Al、Ni、Rh、Au、Cu、Ti、Pt、Pd、Mo、Cr、W或上述金屬的合金。In an embodiment of the invention, the material of the second N-type electrode includes Ag, Al, Ni, Rh, Au, Cu, Ti, Pt, Pd, Mo, Cr, W or an alloy of the above metals.
在本發明的一實施例中，上述的氮化物半導體元件設置於封裝載體以及封裝基板上。其中上述的封裝基板包括電路板以及二個銲墊。上述的二個銲墊設置於上述的電路板上。其中上述的封裝載體包括支架或載板、二個導電引腳、樹脂、二個導電材料、透明膠以及螢光粉。上述的支架或上述的載板設置於上述的電路板上。上述的二個導電引腳設置於上述的支架或上述的載板上，用以與上述的二個銲墊電性連接，其中上述的氮化物半導體元件設置於上述的二個導電引腳上，其中上述的第一N型電極及上述的第二N型電極並與上述的二個導電引腳對應地電性連接。上述的樹脂設置於上述的支架或上述的載板上，並用以容納上述的氮化物半導體元件及上述的二個導電引腳。上述的二個導電材料用以電性連接上述的上述的氮化物半導體元件的上述的第一N型電極及上述的第二N型電極以及上述的二個導電引腳。上述的透明膠用以包覆上述的上述的氮化物半導體元件及上述的二個導電引腳。上述的螢光粉用以填入於上述的透明膠中。In an embodiment of the invention, the nitride semiconductor device is disposed on the package carrier and the package substrate. The above package substrate comprises a circuit board and two solder pads. The above two pads are disposed on the above circuit board. The package carrier described above comprises a bracket or a carrier, two conductive pins, a resin, two conductive materials, a transparent glue and a phosphor powder. The above bracket or the above carrier is provided on the above circuit board. The two conductive pins are disposed on the bracket or the carrier board for electrically connecting to the two solder pads, wherein the nitride semiconductor component is disposed on the two conductive pins. The first N-type electrode and the second N-type electrode are electrically connected to the two conductive pins. The above resin is disposed on the above-mentioned bracket or the above-mentioned carrier, and is for accommodating the above-described nitride semiconductor device and the above two conductive pins. The two conductive materials are used to electrically connect the first N-type electrode and the second N-type electrode of the nitride semiconductor device described above and the two conductive leads. The above transparent adhesive is used to coat the above-described nitride semiconductor device and the above two conductive pins. The above phosphor powder is used to fill in the above transparent glue.
在本發明的一實施例中，上述的螢光粉係由具高穩定發光特性的材料所製成，包含石榴石系(Garnet)、硫化物(Sulfate)、氮化物(Nitrate)、矽酸鹽(Silicate)、鋁酸鹽(Aluminate)或上述材料的任意組合，但不以此為限，其發光波長約為300nm至700nm，其中上述的螢光粉的粒徑為1~25μm，其中上述的氮化物半導體元件所產生的一部份的光線可以激發上述的螢光粉，使得上述的螢光粉產生較長波長的光線，上述的氮化物半導體元件的剩餘一部份未被上述的螢光粉轉換的光線與上述的螢光粉產生的光線可以混合成白光。In an embodiment of the invention, the phosphor powder is made of a material having high stable luminescent properties, and includes Garnet, Sulfate, Nitrate, and Citrate. (Silicate), aluminate (Aluminate) or any combination of the above materials, but not limited thereto, the emission wavelength is about 300 nm to 700 nm, wherein the above-mentioned phosphor powder has a particle diameter of 1 to 25 μm, wherein the above A portion of the light generated by the nitride semiconductor device can excite the phosphor powder to cause the phosphor powder to generate light of a longer wavelength, and the remaining portion of the nitride semiconductor device is not subjected to the above-described phosphor The light converted by the powder and the light produced by the above-mentioned phosphor powder can be mixed into white light.
在本發明的一實施例中，上述的導電材料包含銲線、金、銀、銅、鋁或是混合材料。In an embodiment of the invention, the conductive material comprises a bonding wire, gold, silver, copper, aluminum or a mixed material.
在本發明的一實施例中，上述的透明膠材包括環氧樹脂。In an embodiment of the invention, the transparent adhesive material comprises an epoxy resin.
在本發明的一實施例中，上述的導電引腳可為纯金屬材料、金、銀、銅、鋁、低熔點金屬合金、金錫合金、錫、鉍或錫鉍合金。In an embodiment of the invention, the conductive pins may be pure metal materials, gold, silver, copper, aluminum, low melting point metal alloys, gold tin alloys, tin, antimony or tin antimony alloys.
在本發明的一實施例中，上述的氮化物半導體元件更包括平台結構、第一N型電極、電流阻擋層、透明導電層、第二N型電極、絕緣層、高反射絕緣層、第一銲墊層、第二銲墊層、第一連接電極以及第二連接電極。上述的平台結構，露出部分上述的N型歐姆接觸層。上述的第一N型電極，與上述的N型歐姆接觸層電性連接。上述的電流阻擋層，與上述的第二N型氮化物半導體直接接觸。上述的透明導電層，覆蓋上述的電流阻擋層以及與上述的第二N型氮化物半導體直接接觸。上述的第二N型電極，位於上述的透明導電層的上方，藉由透明導電層與上述的第二N型氮化物半導體電性連接。上述的絕緣層，覆蓋上述的第一N型電極以及上述的第二N型電極及上述的平台結構的側壁。上述的高反射絕緣層位於上述的覆蓋部分上述的絕緣層。上述的第一銲墊層與上述的第一N型電極電性連接。上述的第二銲墊層與上述的第二N型電極電性連接。上述的第一連接電極與上述的第一銲墊層電性連接。上述的第二連接電極與上述的第二銲墊層電性連接。In an embodiment of the invention, the nitride semiconductor device further includes a platform structure, a first N-type electrode, a current blocking layer, a transparent conductive layer, a second N-type electrode, an insulating layer, a highly reflective insulating layer, and the first a pad layer, a second pad layer, a first connection electrode, and a second connection electrode. The above-described platform structure exposes some of the N-type ohmic contact layers described above. The first N-type electrode described above is electrically connected to the N-type ohmic contact layer described above. The current blocking layer is in direct contact with the second N-type nitride semiconductor described above. The transparent conductive layer covers the current blocking layer and is in direct contact with the second N-type nitride semiconductor. The second N-type electrode is located above the transparent conductive layer, and is electrically connected to the second N-type nitride semiconductor by a transparent conductive layer. The insulating layer covers the first N-type electrode and the second N-type electrode and the sidewall of the platform structure. The above-mentioned highly reflective insulating layer is located on the above-mentioned insulating layer of the covering portion. The first pad layer is electrically connected to the first N-type electrode. The second pad layer is electrically connected to the second N-type electrode. The first connection electrode is electrically connected to the first pad layer. The second connection electrode is electrically connected to the second pad layer.
在本發明的一實施例中，上述的高反射絕緣層由多個介電材料對(pair)組成，上述的多個介電材料對包括多個第一介電對以及多個第二介電對。In an embodiment of the invention, the high reflective insulating layer is composed of a plurality of pairs of dielectric materials, and the plurality of dielectric material pairs include a plurality of first dielectric pairs and a plurality of second dielectrics. Correct.
在本發明的一實施例中，上述的第一介電對包括第一材料層以及第二材料層，其中上述的第一材料層的介電係數大於上述的第二材料層的介電係數。In an embodiment of the invention, the first dielectric pair includes a first material layer and a second material layer, wherein the first material layer has a dielectric constant greater than a dielectric constant of the second material layer.
在本發明的一實施例中，上述的第一材料層以及上述的第二材料層的光學厚度小於四分之一的波長，上述的波長為上述的氮化物半導體量子井發光結構所發出的波長。In an embodiment of the invention, the first material layer and the second material layer have an optical thickness of less than a quarter of a wavelength, and the wavelength is a wavelength emitted by the nitride semiconductor quantum well emitting structure. .
在本發明的一實施例中，上述的第二介電對包括第一材料層以及第二材料層，其中上述的第一材料層的介電係數大於上述的第二材料層的介電係數。In an embodiment of the invention, the second dielectric pair includes a first material layer and a second material layer, wherein the first material layer has a dielectric constant greater than a dielectric constant of the second material layer.
在本發明的一實施例中，上述的第一材料層的光學厚度小於四分之一的波長，上述的第二材料層的光學厚度大於四分之一的波長，上述的波長為上述的氮化物半導體量子井發光結構所發出的波長。In an embodiment of the invention, the first material layer has an optical thickness of less than a quarter of a wavelength, and the second material layer has an optical thickness greater than a quarter of a wavelength, wherein the wavelength is the nitrogen The wavelength emitted by the quantum structure of a quantum well.
在本發明的一實施例中，上述的透明導電層可以是銦錫氧化物(Indium Tin Oxide；ITO)、銦鋅氧化物(indium zinc oxide；IZO)、氧化鋅（Zinc Oxide；ZnO）或氧化鋅鋁(Aluminum Zinc Oxide；AZO)。In an embodiment of the invention, the transparent conductive layer may be Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), Zinc Oxide (ZnO) or Oxidation. Aluminum Zinc Oxide (AZO).
在本發明的一實施例中，上述的絕緣層包括氧化矽(SiOX )、氮化矽(SiNX )、聚醯亞胺(Polyimide)或其他高分子材料。In an embodiment of the present invention, the above-described insulating layer include silicon oxide (SiO X), silicon nitride (SiN X), polyimide (Polyimide) or other polymeric materials.
在本發明的一實施例中，上述的高反射絕緣層的材料包括氧化物、氮化物、以及至少包含Si、Ti、Zr、Nb、Ta、Al元素所組成的氧化物或氮化物。In an embodiment of the invention, the material of the high-reflection insulating layer includes an oxide, a nitride, and an oxide or nitride composed of at least Si, Ti, Zr, Nb, Ta, and Al elements.
在本發明的一實施例中，上述的第一N型電極的材料包括Ag、Al、Ni、Rh、Au、Cu、Ti、Pt、Pd、Mo、Cr、W或上述金屬的合金。In an embodiment of the invention, the material of the first N-type electrode includes Ag, Al, Ni, Rh, Au, Cu, Ti, Pt, Pd, Mo, Cr, W or an alloy of the above metals.
在本發明的一實施例中，上述的第二N型電極的材料包括Ag、Al、Ni、Rh、Au、Cu、Ti、Pt、Pd、Mo、Cr、W或上述金屬的合金。In an embodiment of the invention, the material of the second N-type electrode includes Ag, Al, Ni, Rh, Au, Cu, Ti, Pt, Pd, Mo, Cr, W or an alloy of the above metals.
在本發明的一實施例中，上述的第一導電引腳的材料包括Ag、Al、Ni、Rh、Au、Cu、Ti、Pt、Pd、Mo、Cr、W、Sn、In或上述金屬的合金。In an embodiment of the invention, the material of the first conductive pin comprises Ag, Al, Ni, Rh, Au, Cu, Ti, Pt, Pd, Mo, Cr, W, Sn, In or the above metal. alloy.
在本發明的一實施例中，上述的第二導電引腳的材料包括Ag、Al、Ni、Rh、Au、Cu、Ti、Pt、Pd、Mo、Cr、W、Sn、In或上述金屬的合金。In an embodiment of the invention, the material of the second conductive pin comprises Ag, Al, Ni, Rh, Au, Cu, Ti, Pt, Pd, Mo, Cr, W, Sn, In or the above metal. alloy.
在本發明的一實施例中，上述的氮化物半導體元件設置於封裝載體以及封裝基板上，其中上述的封裝基板包括電路板以及二個銲墊。上述的二個銲墊設置於上述的電路板上。其中上述的封裝載體包括支架或載板、二個導電引腳、樹脂、二個導電材料、透明膠以及螢光粉。上述的支架或上述的載板設置於上述的電路板上。上述的二個導電引腳設置於上述的支架或上述的載板上，用以與上述的二個銲墊電性連接，其中上述的氮化物半導體元件設置於上述的二個導電引腳上，其中上述的第一N型電極及上述的第二N型電極並與上述的二個導電引腳對應地電性連接。上述的樹脂設置於上述的支架或上述的載板上，並用以容納上述的氮化物半導體元件及上述的二個導電引腳。上述的二個導電材料用以電性連接上述的上述的氮化物半導體元件的上述的第一N型電極及上述的第二N型電極以及上述的二個導電引腳。上述的透明膠用以包覆上述的上述的氮化物半導體元件及上述的二個導電引腳。上述的螢光粉用以填入於上述的透明膠中。In an embodiment of the invention, the nitride semiconductor device is disposed on a package carrier and a package substrate, wherein the package substrate comprises a circuit board and two pads. The above two pads are disposed on the above circuit board. The package carrier described above comprises a bracket or a carrier, two conductive pins, a resin, two conductive materials, a transparent glue and a phosphor powder. The above bracket or the above carrier is provided on the above circuit board. The two conductive pins are disposed on the bracket or the carrier board for electrically connecting to the two solder pads, wherein the nitride semiconductor component is disposed on the two conductive pins. The first N-type electrode and the second N-type electrode are electrically connected to the two conductive pins. The above resin is disposed on the above-mentioned bracket or the above-mentioned carrier, and is for accommodating the above-described nitride semiconductor device and the above two conductive pins. The two conductive materials are used to electrically connect the first N-type electrode and the second N-type electrode of the nitride semiconductor device described above and the two conductive leads. The above transparent adhesive is used to coat the above-described nitride semiconductor device and the above two conductive pins. The above phosphor powder is used to fill in the above transparent glue.
在本發明的一實施例中，上述的螢光粉係由具高穩定發光特性的材料所製成，包含石榴石系(Garnet)、硫化物(Sulfate)、氮化物(Nitrate)、矽酸鹽(Silicate)、鋁酸鹽(Aluminate)或上述材料的任意組合，其發光波長約為300nm至700nm，其中上述的螢光粉的粒徑為1~25μm，其中上述的氮化物半導體元件所產生的一部份的光線可以激發上述的螢光粉，使得上述的螢光粉產生較長波長的光線，上述的氮化物半導體元件的剩餘一部份未被上述的螢光粉轉換的光線與上述的螢光粉產生的光線可以混合成白光。In an embodiment of the invention, the phosphor powder is made of a material having high stable luminescent properties, and includes Garnet, Sulfate, Nitrate, and Citrate. (Silicate), aluminate (Aluminate) or any combination of the above materials, having an emission wavelength of about 300 nm to 700 nm, wherein the above-mentioned phosphor powder has a particle diameter of 1 to 25 μm, wherein the above-described nitride semiconductor device is produced. A portion of the light illuminates the phosphor powder to cause the phosphor powder to generate a longer wavelength of light, and the remaining portion of the nitride semiconductor device is not converted by the phosphor powder and the above The light produced by the phosphor can be mixed into white light.
在本發明的一實施例中，上述的透明膠材包括環氧樹脂。In an embodiment of the invention, the transparent adhesive material comprises an epoxy resin.
在本發明的一實施例中，上述的導電引腳可為纯金屬材料、金、銀、銅、鋁、低熔點金屬合金、金錫合金、錫、鉍或錫鉍合金。In an embodiment of the invention, the conductive pins may be pure metal materials, gold, silver, copper, aluminum, low melting point metal alloys, gold tin alloys, tin, antimony or tin antimony alloys.
在本發明的一實施例中，上述的氮化物半導體元件可應用於車用照明領域。In an embodiment of the invention, the nitride semiconductor device described above can be applied to the field of automotive lighting.
在本發明的一實施例中，上述的氮化物半導體元件可應用於一般照明領域。In an embodiment of the invention, the nitride semiconductor device described above can be applied to the field of general illumination.
在本發明的一實施例中，上述的氮化物半導體元件可應用於閃光燈領域。In an embodiment of the invention, the nitride semiconductor device described above can be applied to the field of flash lamps.
在本發明的一實施例中，上述的氮化物半導體元件可應用於背光領域。In an embodiment of the invention, the nitride semiconductor device described above can be applied to the field of backlights.
在本發明的一實施例中，上述的氮化物半導體元件可應用於戶外看板領域。In an embodiment of the invention, the nitride semiconductor device described above can be applied to the field of outdoor signage.
在本發明的一實施例中，上述的氮化物半導體元件的發光效率高於220流明每瓦(lm/W)。In an embodiment of the invention, the nitride semiconductor device has a luminous efficiency higher than 220 lumens per watt (lm/W).
在本發明的一實施例中，上述的氮化物半導體元件的顯色指數中對紅色的顯示能力(R9)大於90。In an embodiment of the invention, the display index (R9) for red in the color rendering index of the nitride semiconductor device is greater than 90.
在本發明的一實施例中，上述的氮化物半導體元件的演色性指數(Color Rendering Index；CRI)大於90。In an embodiment of the invention, the nitride semiconductor element has a Color Rendering Index (CRI) greater than 90.
在本發明的一實施例中，上述的氮化物半導體元件的平均演色評價指數（Ra）大於90。In an embodiment of the invention, the nitride semiconductor device has an average color rendering index (Ra) of more than 90.
在本發明的一實施例中，上述的氮化物半導體元件可以是水平式發光晶片。In an embodiment of the invention, the nitride semiconductor device may be a horizontal light-emitting wafer.
在本發明的一實施例中，上述的氮化物半導體元件可以是垂直式發光晶片。In an embodiment of the invention, the nitride semiconductor device may be a vertical light-emitting chip.
在本發明的一實施例中，上述的氮化物半導體元件可以是覆晶式發光晶片。In an embodiment of the invention, the nitride semiconductor device may be a flip-chip light-emitting chip.
在本發明的一實施例中，上述的微結構為週期性突出結構，上述的週期性突出結構包括高度、寬度以及底面間距。In an embodiment of the invention, the microstructure is a periodic protruding structure, and the periodic protruding structure includes a height, a width, and a bottom surface spacing.
在本發明的一實施例中，上述的高度介於1微米至3微米之間。In an embodiment of the invention, the height is between 1 micrometer and 3 micrometers.
在本發明的一實施例中，上述的寬度介於1微米至3微米之間。In an embodiment of the invention, the width is between 1 micrometer and 3 micrometers.
在本發明的一實施例中，上述的底面間距介於0.1微米至3微米之間。In an embodiment of the invention, the bottom surface spacing is between 0.1 microns and 3 microns.
在本發明的一實施例中，上述的基板的上述的第二面的粗糙度大於上述的成長表面的粗糙度以及上述的多個微結構的表面的粗糙度。In an embodiment of the invention, the roughness of the second surface of the substrate is greater than the roughness of the growth surface and the roughness of the surface of the plurality of microstructures.
在本發明的一實施例中，上述的微結構的外型為半球體(hemisphere) 、錐體(cone)、截頭錐體(truncated-cone)、金字塔(pyramid)、截頭金字塔(truncated-pyramid)、方柱(square pillar)或圓桶(cylinder)。In an embodiment of the invention, the microstructure of the above-mentioned microstructure is a hemisphere, a cone, a truncated-cone, a pyramid, and a truncated pyramid. Pyramid), square pillar or cylinder.
在本發明的一實施例中，上述的穿隧接面更包括中間半導體，設置於上述的重摻雜P型(P+)氮化物半導體及上述的重摻雜N型(N+)氮化物半導體之間，上述的中間半導體相對於上述的重摻雜P型(P+)氮化物半導體及上述的重摻雜N型(N+)氮化物半導體形成異質接面，以建立極化場，使得上述的重摻雜P型(P+)氮化物半導體的價帶及上述的重摻雜N型(N+)氮化物半導體的導帶相互對應。In an embodiment of the invention, the tunneling junction further includes an intermediate semiconductor disposed on the heavily doped P-type (P+) nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor. The intermediate semiconductor is formed into a heterojunction with respect to the above-mentioned heavily doped P-type (P+) nitride semiconductor and the above-mentioned heavily doped N-type (N+) nitride semiconductor to establish a polarization field, so that the above-mentioned weight The valence band of the doped P-type (P+) nitride semiconductor and the conduction band of the above-described heavily doped N-type (N+) nitride semiconductor correspond to each other.
在本發明的一實施例中，上述的重摻雜P型(P+)氮化物半導體及上述的重摻雜N型(N+)氮化物半導體的至少一者的能隙大於上述的氮化物半導體量子井發光結構的能隙。In an embodiment of the invention, at least one of the heavily doped P-type (P+) nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor has a larger energy gap than the nitride semiconductor quantum The energy gap of the well-emitting structure.
在本發明的一實施例中，上述的中間半導體包含氮化鋁鎵(AlGaN)、氮化鎵(GaN)、氮化銦鎵(InGaN)或氮化銦鋁鎵(InAlGaN)。In an embodiment of the invention, the intermediate semiconductor comprises aluminum gallium nitride (AlGaN), gallium nitride (GaN), indium gallium nitride (InGaN) or indium aluminum gallium nitride (InAlGaN).
在本發明的一實施例中，上述的中間半導體具有內部帶穿隧阻擋層(inter band tunnel barrier)，上述的重摻雜P型(P+)氮化物半導體具有P型空乏阻擋層(P-depletion barrier)，上述的重摻雜N型(N+)氮化物半導體具有N型空乏阻擋層(N-depletion barrier)。In an embodiment of the invention, the intermediate semiconductor has an internal band gap barrier, and the heavily doped P-type (P+) nitride semiconductor has a P-type depletion barrier (P-depletion). Barrier), the above heavily doped N-type (N+) nitride semiconductor has an N-depletion barrier.
在本發明的一實施例中，上述的中間半導體的厚度約為0.5nm～10nm。In an embodiment of the invention, the intermediate semiconductor has a thickness of about 0.5 nm to 10 nm.
在本發明的一實施例中，上述的中間半導體具有側面材料能隙波動(lateral material energy bandgap fluctuations)，其包含多個低及高能隙區域(low and high bandgap regions)。In an embodiment of the invention, the intermediate semiconductor has lateral material energy bandgaps, which includes a plurality of low and high band gap regions.
在本發明的一實施例中，上述的第二N型氮化物半導體及上述的重摻雜N型(N+)氮化物半導體不會吸收上述的氮化物半導體量子井發光結構所發出光線。In an embodiment of the invention, the second N-type nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor do not absorb light emitted by the nitride semiconductor quantum well light-emitting structure.
在本發明的一實施例中，上述的第二N型氮化物半導體及上述的重摻雜N型(N+)氮化物半導體的能隙大於上述的氮化物半導體量子井發光結構的能隙。In an embodiment of the invention, the energy gap of the second N-type nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor is larger than the energy gap of the nitride semiconductor quantum well light-emitting structure.
在本發明的一實施例中，上述的多個氮化物半導體元件係可電性串聯而形成氮化物半導體高壓元件。In an embodiment of the invention, the plurality of nitride semiconductor elements are electrically connected in series to form a nitride semiconductor high voltage element.
在本發明的一實施例中，上述的氮化物半導體元件可以發出UV光線、藍色光線或綠色光線。In an embodiment of the invention, the nitride semiconductor device may emit UV light, blue light or green light.
在本發明的一實施例中，上述的氮化物半導體元件可以應用於燈絲(Filament)產品。In an embodiment of the invention, the nitride semiconductor device described above can be applied to a filament product.
在本發明的一實施例中，上述的氮化物半導體元件可以應用於COB(Chip on Board)產品。In an embodiment of the invention, the nitride semiconductor device described above can be applied to a COB (Chip on Board) product.
在本發明的一實施例中，上述的氮化物半導體元件可以應用於雷射二極體(Laser Diode)產品。In an embodiment of the invention, the nitride semiconductor device described above can be applied to a laser diode product.
在本發明的一實施例中，上述的氮化物半導體元件可以應用於發光二極體(Light Emitting Diode)產品。In an embodiment of the invention, the nitride semiconductor device described above can be applied to a Light Emitting Diode product.
本發明提供一種氮化物半導體元件，其包括第一N型電極、第一N型氮化物半導體、氮化物半導體量子井發光結構、P型氮化物半導體、穿隧接面(Tunnel Junction)、第二N型氮化物半導體、高反射絕緣層、N型高反射歐姆電極、第一焊接金屬層、第二焊接金屬層、接合基板以及第二N型電極。上述的第一N型氮化物半導體設置於上述的第一N型電極上。上述的氮化物半導體量子井發光結構設置於上述的第一N型氮化物半導體上。上述的P型氮化物半導體設置於上述的氮化物半導體量子井發光結構上。上述的穿隧接面(Tunnel Junction)設置於上述的氮化物半導體量子井發光結構上。上述的穿隧接面包括重摻雜P型(P+)氮化物半導體以及重摻雜N型(N+)氮化物半導體。上述的重摻雜P型(P+)氮化物半導體設置於上述的氮化物半導體量子井發光結構上。上述的重摻雜N型(N+)氮化物半導體設置於上述的重摻雜P型氮化物半導體上。上述的第二N型氮化物半導體設置於上述的穿隧接面的上述的重摻雜N型氮化物半導體上。上述的高反射絕緣層設置於上述的第二N型氮化物半導體上，並暴露出部份的上述的第二N型氮化物半導體。上述的N型高反射歐姆電極設置於上述的第二N型氮化物半導體上，並覆蓋上述的高反射絕緣層及上述的第二N型氮化物半導體。上述的第一焊接金屬層設置於上述的N型高反射歐姆電極上。上述的第二焊接金屬層設置於上述的第一焊接金屬層上。上述的接合基板設置於上述的第二焊接金屬層上，並與上述的第一焊接金屬層電性連接。上述的第二N型電極設置上述的接合基板上，並與上述的接合基板電性連接。其中上述的氮化物半導體量子井發光結構具有多個井層和多個阻擋層，上述的多個阻擋層包含配置於最接近上述的P型氮化物半導體位置的第一阻擋層、配置於最接近上述的第一N型氮化物半導體位置的第二阻擋層以及多個第三阻擋層，其中上述的多個第三阻擋層被上述的多個井層夾住，其中上述的第一阻擋層的厚度小於100埃。The present invention provides a nitride semiconductor device including a first N-type electrode, a first N-type nitride semiconductor, a nitride semiconductor quantum well light-emitting structure, a P-type nitride semiconductor, a tunnel junction, and a second An N-type nitride semiconductor, a highly reflective insulating layer, an N-type highly reflective ohmic electrode, a first solder metal layer, a second solder metal layer, a bonding substrate, and a second N-type electrode. The first N-type nitride semiconductor described above is provided on the first N-type electrode described above. The nitride semiconductor quantum well light-emitting structure described above is provided on the first N-type nitride semiconductor described above. The above-described P-type nitride semiconductor is provided on the above-described nitride semiconductor quantum well light-emitting structure. The above tunnel junction is disposed on the nitride semiconductor quantum well light-emitting structure described above. The tunneling junction described above includes a heavily doped P-type (P+) nitride semiconductor and a heavily doped N-type (N+) nitride semiconductor. The above heavily doped P-type (P+) nitride semiconductor is provided on the above-described nitride semiconductor quantum well light-emitting structure. The above heavily doped N-type (N+) nitride semiconductor is provided on the above-described heavily doped P-type nitride semiconductor. The second N-type nitride semiconductor is provided on the above-described heavily doped N-type nitride semiconductor on the tunnel junction surface. The high-reflection insulating layer is disposed on the second N-type nitride semiconductor and exposes a portion of the second N-type nitride semiconductor. The N-type high-reflection ohmic electrode is provided on the second N-type nitride semiconductor and covers the high-reflection insulating layer and the second N-type nitride semiconductor. The first solder metal layer described above is disposed on the N-type high reflection ohmic electrode described above. The second solder metal layer is disposed on the first solder metal layer. The bonding substrate is provided on the second solder metal layer and electrically connected to the first solder metal layer. The second N-type electrode is provided on the above-described bonding substrate, and is electrically connected to the bonding substrate described above. Wherein the nitride semiconductor quantum well light-emitting structure has a plurality of well layers and a plurality of barrier layers, and the plurality of barrier layers include a first barrier layer disposed at a position closest to the P-type nitride semiconductor, and disposed closest to a second barrier layer of the first N-type nitride semiconductor position and a plurality of third barrier layers, wherein the plurality of third barrier layers are sandwiched by the plurality of well layers, wherein the first barrier layer The thickness is less than 100 angstroms.
在本發明的一實施例中，上述的重摻雜P型半導體層的能隙越靠近上述的P型氮化物半導體越高，上述的重摻雜N型氮化物半導體層的能隙越靠近上述的第二N型氮化物半導體越高。In an embodiment of the present invention, the closer the energy gap of the heavily doped P-type semiconductor layer is to the P-type nitride semiconductor, the closer the energy gap of the heavily doped N-type nitride semiconductor layer is to the above. The higher the second N-type nitride semiconductor.
在本發明的一實施例中，上述的重摻雜P型半導體層的厚度約為1nm～100nm，上述的重摻雜N型氮化物半導體層的厚度約為1nm～100nm。In an embodiment of the invention, the heavily doped P-type semiconductor layer has a thickness of about 1 nm to 100 nm, and the heavily doped N-type nitride semiconductor layer has a thickness of about 1 nm to 100 nm.
在本發明的一實施例中，上述的第二阻擋層的厚度大於上述的第一阻擋層的厚度，第三阻擋層的厚度大於上述的第一阻擋層的厚度，第二阻擋層的厚度大於或是等於上述的第三阻擋層的厚度。In an embodiment of the invention, the thickness of the second barrier layer is greater than the thickness of the first barrier layer, the thickness of the third barrier layer is greater than the thickness of the first barrier layer, and the thickness of the second barrier layer is greater than Or equal to the thickness of the third barrier layer described above.
在本發明的一實施例中，上述的第二阻擋層的厚度大於上述的第一阻擋層的厚度，第三阻擋層的厚度大於上述的第一阻擋層的厚度，上述的第二阻擋層的厚度小於或是等於上述的第三阻擋層的厚度。In an embodiment of the invention, the thickness of the second barrier layer is greater than the thickness of the first barrier layer, the thickness of the third barrier layer is greater than the thickness of the first barrier layer, and the second barrier layer is The thickness is less than or equal to the thickness of the third barrier layer described above.
在本發明的一實施例中，上述的第一N型氮化物半導體及上述的第二N型氮化物半導體的至少一者具有粗糙表面，用以增加上述的氮化物半導體元件的出光效果。In an embodiment of the invention, at least one of the first N-type nitride semiconductor and the second N-type nitride semiconductor has a rough surface for increasing the light-emitting effect of the nitride semiconductor device.
在本發明的一實施例中，上述的P型氮化物半導體包括P側應力釋放層、高濃度電洞層以及電子阻擋層。其中配置於最接近上述的第一阻擋層為上述的P側應力釋放層，配置於最遠離上述的第一阻擋層為上述的電子阻擋層，上述的高濃度電洞層被上述的高濃度電洞層以及上述的電子阻擋層所夾住。In an embodiment of the invention, the P-type nitride semiconductor includes a P-side stress releasing layer, a high-concentration hole layer, and an electron blocking layer. The first barrier layer disposed closest to the first barrier layer is the P-side stress relief layer, and the first barrier layer disposed farthest from the above is the above-described electron blocking layer, and the high-concentration hole layer is electrically concentrated as described above. The hole layer and the above-mentioned electron blocking layer are sandwiched.
在本發明的一實施例中，上述的P側應力釋放層可為超晶格結構，其材料包含氮化鋁鎵(AlGaN)以及氮化鎵(GaN)所構成的超晶格結構，或是由氮化鋁鎵(AlxGaN)以及氮化鋁鎵(AlyGaN)所構成的超晶格結構，或是由氮化鋁鎵(AlGaN)以及氮化鋁銦鎵(InAlGaN)所構成的超晶格結構，其中，x不等於y，上述的超晶格結構小於20對。In an embodiment of the invention, the P-side stress relief layer may be a superlattice structure, the material of which comprises a superlattice structure composed of aluminum gallium nitride (AlGaN) and gallium nitride (GaN), or Superlattice structure composed of aluminum gallium nitride (AlxGaN) and aluminum gallium nitride (AlyGaN), or superlattice structure composed of aluminum gallium nitride (AlGaN) and aluminum indium gallium nitride (InAlGaN) Where x is not equal to y and the superlattice structure described above is less than 20 pairs.
在本發明的一實施例中，上述的高濃度電洞層可由氮化鎵(GaN)或是氮化鋁鎵(AlGaN)所構成，上述的高濃度電洞層的鎂摻雜濃度(concentration)高於上述的P側應力釋放層的鎂摻雜濃度以及上述的電子阻擋層的鎂摻雜濃度。In an embodiment of the invention, the high-concentration hole layer may be composed of gallium nitride (GaN) or aluminum gallium nitride (AlGaN), and the magnesium concentration of the high-concentration hole layer is concentrated. It is higher than the magnesium doping concentration of the P-side stress releasing layer described above and the magnesium doping concentration of the above-described electron blocking layer.
在本發明的一實施例中，上述的高濃度電洞層的鎂(Mg)摻雜濃度高於1x1019 (Atoms/cm3 )。In an embodiment of the invention, the high concentration hole layer has a magnesium (Mg) doping concentration higher than 1 x 10 19 (Atoms/cm 3 ).
在本發明的一實施例中，上述的電子阻擋層可由氮化鋁鎵(AlGaN)所構成，上述的電子阻擋層的鋁成份百分比高於上述的P側應力釋放層的鋁成份百分比以及高於上述的高濃度電洞層的鋁成份百分比。In an embodiment of the invention, the electron blocking layer may be composed of aluminum gallium nitride (AlGaN), and the percentage of the aluminum component of the electron blocking layer is higher than the percentage of the aluminum component of the P-side stress releasing layer and higher than The percentage of aluminum component of the high concentration hole layer described above.
在本發明的一實施例中，上述的穿隧接面更包括中間半導體，設置於上述的重摻雜P型(P+)氮化物半導體及上述的重摻雜N型(N+)氮化物半導體之間。In an embodiment of the invention, the tunneling junction further includes an intermediate semiconductor disposed on the heavily doped P-type (P+) nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor. between.
在本發明的一實施例中，上述的高濃度電洞層的鎂(Mg)摻雜濃度高於1x1019 (Atoms/cm3 )且上述的高濃度電洞層的鋁成份百分比低於上述的電子阻擋層的鋁成份百分比。In an embodiment of the invention, the high concentration hole layer has a magnesium (Mg) doping concentration higher than 1×10 19 (Atoms/cm 3 ) and the high concentration hole layer has a lower aluminum component percentage than the above. The percentage of aluminum component of the electron blocking layer.
在本發明的一實施例中，上述的第一N型氮化物半導體包括N側第一應力釋放層、N側第二應力釋放層、低濃度電子層以及N型歐姆接觸層。其中配置於最接近上述的第二阻擋層為上述的N側第一應力釋放層，配置於最遠離述上述的第二阻擋層為上述的N型歐姆接觸層，上述的低濃度電子層以及上述的第二應力釋放層依序堆疊於上述的N型歐姆接觸層上方，上述的低濃度電子層被N型歐姆接觸層及上述的N側第二應力釋放層所夾住。In an embodiment of the invention, the first N-type nitride semiconductor includes an N-side first stress relief layer, an N-side second stress relief layer, a low concentration electron layer, and an N-type ohmic contact layer. The second barrier layer disposed closest to the above is the N-side first stress relief layer, and the second barrier layer farthest from the above is the N-type ohmic contact layer, the low-concentration electron layer and the above The second stress relief layer is sequentially stacked over the N-type ohmic contact layer, and the low-concentration electron layer is sandwiched by the N-type ohmic contact layer and the N-side second stress relief layer.
在本發明的一實施例中，上述的N側第一應力釋放層可為超晶格結構，其材料包含氮化銦鎵(InGaN)以及氮化鎵(GaN)所構成的超晶格結構，或是由氮化銦鎵(Inx GaN))以及氮化銦鎵(Iny GaN)所構成的超晶格結構，其中x不等於y，上述的超晶格結構小於20對。In an embodiment of the invention, the N-side first stress relief layer may be a superlattice structure, and the material thereof comprises a superlattice structure composed of indium gallium nitride (InGaN) and gallium nitride (GaN). Or a superlattice structure composed of indium gallium nitride (In x GaN) and indium gallium nitride (In y GaN), wherein x is not equal to y, and the superlattice structure described above is less than 20 pairs.
在本發明的一實施例中，上述的N側第二應力釋放層可為超晶格結構，其材料包含氮化銦鎵(InGaN)以及氮化鎵(GaN)所構成的超晶格結構，或是由氮化銦鎵(Inx GaN))以及氮化銦鎵(Iny GaN)所構成的超晶格結構，其中x不等於y，上述的超晶格結構小於20對。In an embodiment of the invention, the N-side second stress relief layer may be a superlattice structure, and the material thereof comprises a superlattice structure composed of indium gallium nitride (InGaN) and gallium nitride (GaN). Or a superlattice structure composed of indium gallium nitride (In x GaN) and indium gallium nitride (In y GaN), wherein x is not equal to y, and the superlattice structure described above is less than 20 pairs.
在本發明的一實施例中，上述的N側第一應力釋放層的銦成份百分比高於上述的N側第二應力釋放層的銦成份百分比。In an embodiment of the invention, the percentage of indium component of the N-side first stress-relieving layer is higher than the percentage of the indium component of the N-side second stress-relieving layer.
在本發明的一實施例中，上述的N型氮化物半導體，上述的低濃度電子層可由氮化鎵(GaN)、氮化銦鎵(InGaN)、氮化鋁鎵(AlGaN)或氮化銦鋁鎵(InAlGaN)所構成，上述的低濃度電子層的矽摻雜濃度低於上述的N型歐姆接觸層的矽摻雜濃度。In an embodiment of the invention, the N-type nitride semiconductor, the low-concentration electron layer may be gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN) or indium nitride. The aluminum gallium (InAlGaN) is composed of the above-mentioned low-concentration electron layer having a germanium doping concentration lower than that of the above-described N-type ohmic contact layer.
在本發明的一實施例中，上述的低濃度電子層的矽摻雜濃度低於1x1018 (Atoms/cm3 )。In an embodiment of the invention, the low concentration electron layer has a germanium doping concentration of less than 1 x 10 18 (Atoms/cm 3 ).
在本發明的一實施例中，上述的N型歐姆接觸層可由氮化鎵(GaN)、氮化銦鎵(InGaN)、氮化鋁鎵(AlGaN)或氮化銦鋁鎵(InAlGaN)所構成，上述的N型歐姆接觸層的矽摻雜濃度高於上述的N側第一應力釋放層的矽摻雜濃度、上述的N側第二應力釋放層的矽摻雜濃度及上述的低濃度電子層的矽摻雜濃度。In an embodiment of the invention, the N-type ohmic contact layer may be formed of gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN) or indium aluminum gallium nitride (InAlGaN). The cerium doping concentration of the N-type ohmic contact layer is higher than the cerium doping concentration of the N-side first stress-relieving layer, the cerium doping concentration of the N-side second stress-relieving layer, and the low-concentration electrons described above. The erbium doping concentration of the layer.
在本發明的一實施例中，上述的P側應力釋放層的上述的超晶格結構小於10對。In an embodiment of the invention, the super-lattice structure of the P-side stress relief layer is less than 10 pairs.
在本發明的一實施例中，上述的N側第一應力釋放層的上述的超晶格結構小於10對。In an embodiment of the invention, the above-described superlattice structure of the N-side first stress relief layer is less than 10 pairs.
在本發明的一實施例中，上述的第一N側第二應力釋放層的上述的超晶格結構小於10對。In an embodiment of the invention, the super-lattice structure of the first N-side second stress relief layer is less than 10 pairs.
在本發明的一實施例中，上述的第一N型電極的材料包括Ag、Al、Ni、Rh、Au、Cu、Ti、Pt、Pd、Mo、Cr、W或上述金屬的合金。In an embodiment of the invention, the material of the first N-type electrode includes Ag, Al, Ni, Rh, Au, Cu, Ti, Pt, Pd, Mo, Cr, W or an alloy of the above metals.
在本發明的一實施例中，上述的N型高反射歐姆電極包括Ag、Al、Ni、Rh、Au、Cu、Ti、Pt、Pd、Mo、Cr、W或上述金屬的合金。In an embodiment of the invention, the N-type high reflection ohmic electrode includes Ag, Al, Ni, Rh, Au, Cu, Ti, Pt, Pd, Mo, Cr, W or an alloy of the above metals.
在本發明的一實施例中，上述的第二N型電極包括Ag、Al、Ni、Rh、Au、Cu、Ti、Pt、Pd、Mo、Cr、W或上述金屬的合金。In an embodiment of the invention, the second N-type electrode includes Ag, Al, Ni, Rh, Au, Cu, Ti, Pt, Pd, Mo, Cr, W or an alloy of the above metals.
在本發明的一實施例中，上述的第一焊接金屬層材料包含Ag、Al、Ni、Rh、Au、Cu、Ti、Pt、Pd、Mo、Cr、W、Sn、銦(In)或上述金屬的合金。In an embodiment of the invention, the first solder metal layer material comprises Ag, Al, Ni, Rh, Au, Cu, Ti, Pt, Pd, Mo, Cr, W, Sn, indium (In) or the above An alloy of metals.
在本發明的一實施例中，上述的第二焊接金屬層材料包含Ag、Al、Ni、Rh、Au、Cu、Ti、Pt、Pd、Mo、Cr、W、Sn、In或上述金屬的合金。In an embodiment of the invention, the second solder metal layer material comprises Ag, Al, Ni, Rh, Au, Cu, Ti, Pt, Pd, Mo, Cr, W, Sn, In or an alloy of the above metals. .
在本發明的一實施例中，上述的接合基板包含純金屬基板、銅基板、鎢基板、鋁基板、合金基板、銅鎢基板、陶瓷基板、氧化鋁基板、矽基板、或碳化矽基板。In an embodiment of the invention, the bonding substrate includes a pure metal substrate, a copper substrate, a tungsten substrate, an aluminum substrate, an alloy substrate, a copper tungsten substrate, a ceramic substrate, an alumina substrate, a germanium substrate, or a tantalum carbide substrate.
在本發明的一實施例中，上述的接合基板的熱膨脹係數高於或等於上述的第一N型氮化物半導體的熱膨脹係數。In an embodiment of the invention, the bonding substrate has a thermal expansion coefficient higher than or equal to a thermal expansion coefficient of the first N-type nitride semiconductor.
在本發明的一實施例中，上述的接合基板的熱膨脹係數低於或等於上述的第一N型氮化物半導體的熱膨脹係數。In an embodiment of the invention, the bonded substrate has a thermal expansion coefficient lower than or equal to a thermal expansion coefficient of the first N-type nitride semiconductor.
在本發明的一實施例中，上述的第一N型氮化物半導體具有表面粗化結構，增加光取出效率。In an embodiment of the invention, the first N-type nitride semiconductor has a surface roughening structure to increase light extraction efficiency.
在本發明的一實施例中，上述的高反射絕緣層由多個介電材料對(pair)組成，上述的多個介電材料對包括多個第一介電對以及多個第二介電對。In an embodiment of the invention, the high reflective insulating layer is composed of a plurality of pairs of dielectric materials, and the plurality of dielectric material pairs include a plurality of first dielectric pairs and a plurality of second dielectrics. Correct.
在本發明的一實施例中，上述的第一介電對包括第一材料層以及第二材料層。其中上述的第一材料層的介電係數大於上述的第二材料層的介電係數。In an embodiment of the invention, the first dielectric pair includes a first material layer and a second material layer. Wherein the dielectric constant of the first material layer is greater than the dielectric constant of the second material layer.
在本發明的一實施例中，上述的第一材料層以及上述的第二材料層的光學厚度小於四分之一的波長，上述的波長為上述的氮化物半導體量子井發光結構所發出的波長。In an embodiment of the invention, the first material layer and the second material layer have an optical thickness of less than a quarter of a wavelength, and the wavelength is a wavelength emitted by the nitride semiconductor quantum well emitting structure. .
在本發明的一實施例中，上述的第二介電對包括第一材料層以及第二材料層，其中上述的第一材料層的介電係數大於上述的第二材料層的介電係數。In an embodiment of the invention, the second dielectric pair includes a first material layer and a second material layer, wherein the first material layer has a dielectric constant greater than a dielectric constant of the second material layer.
在本發明的一實施例中，上述的第一材料層的光學厚度小於四分之一的波長，上述的第二材料層的光學厚度大於四分之一的波長，上述的波長為上述的氮化物半導體量子井發光結構所發出的波長。In an embodiment of the invention, the first material layer has an optical thickness of less than a quarter of a wavelength, and the second material layer has an optical thickness greater than a quarter of a wavelength, wherein the wavelength is the nitrogen The wavelength emitted by the quantum structure of a quantum well.
在本發明的一實施例中，上述的氮化物半導體元件設置於封裝載體以及封裝基板上，其中上述的封裝基板包括電路板以及二個銲墊。上述的二個銲墊設置於上述的電路板上。其中上述的封裝載體包括支架或載板、二個導電引腳、樹脂、二個導電材料、透明膠以及螢光粉。上述的支架或上述的載板設置於上述的電路板上。上述的二個導電引腳設置於上述的支架或上述的載板上，用以與上述的二個銲墊電性連接，其中上述的氮化物半導體元件設置於上述的二個導電引腳上，其中上述的第一N型電極及上述的第二N型電極並與上述的二個導電引腳對應地電性連接。上述的樹脂設置於上述的支架或上述的載板上，並用以容納上述的氮化物半導體元件及上述的二個導電引腳。上述的二個導電材料用以電性連接上述的上述的氮化物半導體元件的上述的第一N型電極及上述的第二N型電極以及上述的二個導電引腳。上述的透明膠用以包覆上述的上述的氮化物半導體元件及上述的二個導電引腳。上述的螢光粉用以填入於上述的透明膠中。In an embodiment of the invention, the nitride semiconductor device is disposed on a package carrier and a package substrate, wherein the package substrate comprises a circuit board and two pads. The above two pads are disposed on the above circuit board. The package carrier described above comprises a bracket or a carrier, two conductive pins, a resin, two conductive materials, a transparent glue and a phosphor powder. The above bracket or the above carrier is provided on the above circuit board. The two conductive pins are disposed on the bracket or the carrier board for electrically connecting to the two solder pads, wherein the nitride semiconductor component is disposed on the two conductive pins. The first N-type electrode and the second N-type electrode are electrically connected to the two conductive pins. The above resin is disposed on the above-mentioned bracket or the above-mentioned carrier, and is for accommodating the above-described nitride semiconductor device and the above two conductive pins. The two conductive materials are used to electrically connect the first N-type electrode and the second N-type electrode of the nitride semiconductor device described above and the two conductive leads. The above transparent adhesive is used to coat the above-described nitride semiconductor device and the above two conductive pins. The above phosphor powder is used to fill in the above transparent glue.
在本發明的一實施例中，上述的螢光粉係由具高穩定發光特性的材料所製成，包含石榴石系(Garnet)、硫化物(Sulfate)、氮化物(Nitrate)、矽酸鹽(Silicate)、鋁酸鹽(Aluminate)或上述材料的任意組合，其發光波長約為300nm至700nm，其中上述的螢光粉的粒徑為1~25μm，其中上述的氮化物半導體元件所產生的一部份的光線可以激發上述的螢光粉，使得上述的螢光粉產生較長波長的光線，上述的氮化物半導體元件的剩餘一部份未被上述的螢光粉轉換的光線與上述的螢光粉產生的光線可以混合成白光。In an embodiment of the invention, the phosphor powder is made of a material having high stable luminescent properties, and includes Garnet, Sulfate, Nitrate, and Citrate. (Silicate), aluminate (Aluminate) or any combination of the above materials, having an emission wavelength of about 300 nm to 700 nm, wherein the above-mentioned phosphor powder has a particle diameter of 1 to 25 μm, wherein the above-described nitride semiconductor device is produced. A portion of the light illuminates the phosphor powder to cause the phosphor powder to generate a longer wavelength of light, and the remaining portion of the nitride semiconductor device is not converted by the phosphor powder and the above The light produced by the phosphor can be mixed into white light.
在本發明的一實施例中，上述的導電材料包含銲線、金、銀、銅、鋁、或是混合材料。In an embodiment of the invention, the conductive material comprises a bonding wire, gold, silver, copper, aluminum, or a mixed material.
在本發明的一實施例中，上述的透明膠材包括環氧樹脂。In an embodiment of the invention, the transparent adhesive material comprises an epoxy resin.
在本發明的一實施例中，上述的導電引腳可為纯金屬材料、金、銀、銅、鋁、或低熔點金屬合金、金錫合金、錫、鉍或錫鉍合金。In an embodiment of the invention, the conductive pins may be pure metal materials, gold, silver, copper, aluminum, or low melting point metal alloys, gold tin alloys, tin, antimony or tin antimony alloys.
在本發明的一實施例中，上述的第二N型氮化物半導體及上述的重摻雜N型(N+)氮化物半導體不會吸收上述的氮化物半導體量子井發光結構所發出光線。In an embodiment of the invention, the second N-type nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor do not absorb light emitted by the nitride semiconductor quantum well light-emitting structure.
在本發明的一實施例中，上述的第二N型氮化物半導體及上述的重摻雜N型(N+)氮化物半導體的能隙大於上述的氮化物半導體量子井發光結構的能隙。In an embodiment of the invention, the energy gap of the second N-type nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor is larger than the energy gap of the nitride semiconductor quantum well light-emitting structure.
在本發明的一實施例中，上述的多個氮化物半導體元件係可電性串聯而形成氮化物半導體高壓元件。In an embodiment of the invention, the plurality of nitride semiconductor elements are electrically connected in series to form a nitride semiconductor high voltage element.
在本發明的一實施例中，上述的氮化物半導體元件可以發出UV光線、藍色光線或綠色光線。In an embodiment of the invention, the nitride semiconductor device may emit UV light, blue light or green light.
在本發明的一實施例中，上述的氮化物半導體元件可以應用於燈絲(Filament)產品。In an embodiment of the invention, the nitride semiconductor device described above can be applied to a filament product.
在本發明的一實施例中，上述的氮化物半導體元件可以應用於COB(Chip on Board)產品。In an embodiment of the invention, the nitride semiconductor device described above can be applied to a COB (Chip on Board) product.
在本發明的一實施例中，上述的氮化物半導體元件可以應用於雷射二極體(Laser Diode)產品。In an embodiment of the invention, the nitride semiconductor device described above can be applied to a laser diode product.
在本發明的一實施例中，上述的氮化物半導體元件可以應用於發光二極體(Light Emitting Diode)產品。In an embodiment of the invention, the nitride semiconductor device described above can be applied to a Light Emitting Diode product.
本發明提供一種氮化物半導體元件，其包括基板、緩衝層、第一N型氮化物半導體、氮化物半導體量子井發光結構、P型氮化物半導體、穿隧接面以及第二N型氮化物半導體。上述的基板具有相對的第一面及第二面。上述的緩衝層設置於上述的基板的上述的第一面上。上述的第一N型氮化物半導體設置於上述的緩衝層上。上述的氮化物半導體量子井發光結構設置於上述的第一N型氮化物半導體上。上述的P型氮化物半導體設置於上述的氮化物半導體量子井發光結構上。上述的穿隧接面(Tunnel Junction)設置於上述的氮化物半導體量子井發光結構上。上述的穿隧接面包括重摻雜P型(P+)氮化物半導體以及重摻雜N型(N+)氮化物半導體。上述的重摻雜P型(P+)氮化物半導體設置於上述的氮化物半導體量子井發光結構上。上述的重摻雜N型(N+)氮化物半導體設置於上述的重摻雜P型氮化物半導體上。上述的第二N型氮化物半導體，設置於上述的穿隧接面的上述的重摻雜N型氮化物半導體上。其中上述的氮化物半導體量子井發光結構具有多個井層和多個阻擋層，上述的多個阻擋層包含配置於最接近上述的P型氮化物半導體位置的第一阻擋層、配置於最接近上述的第一N型氮化物半導體位置的第二阻擋層以及多個第三阻擋層，其中上述的多個第三阻擋層被上述的多個井層夾住，其中上述的第一阻擋層的厚度小於上述的第二阻擋層的厚度。The present invention provides a nitride semiconductor device including a substrate, a buffer layer, a first N-type nitride semiconductor, a nitride semiconductor quantum well light-emitting structure, a P-type nitride semiconductor, a tunnel junction, and a second N-type nitride semiconductor . The substrate has opposite first and second faces. The buffer layer is provided on the first surface of the substrate described above. The first N-type nitride semiconductor described above is provided on the buffer layer described above. The nitride semiconductor quantum well light-emitting structure described above is provided on the first N-type nitride semiconductor described above. The above-described P-type nitride semiconductor is provided on the above-described nitride semiconductor quantum well light-emitting structure. The above tunnel junction is disposed on the nitride semiconductor quantum well light-emitting structure described above. The tunneling junction described above includes a heavily doped P-type (P+) nitride semiconductor and a heavily doped N-type (N+) nitride semiconductor. The above heavily doped P-type (P+) nitride semiconductor is provided on the above-described nitride semiconductor quantum well light-emitting structure. The above heavily doped N-type (N+) nitride semiconductor is provided on the above-described heavily doped P-type nitride semiconductor. The second N-type nitride semiconductor described above is provided on the above-described heavily doped N-type nitride semiconductor on the tunnel junction surface. Wherein the nitride semiconductor quantum well light-emitting structure has a plurality of well layers and a plurality of barrier layers, and the plurality of barrier layers include a first barrier layer disposed at a position closest to the P-type nitride semiconductor, and disposed closest to a second barrier layer of the first N-type nitride semiconductor position and a plurality of third barrier layers, wherein the plurality of third barrier layers are sandwiched by the plurality of well layers, wherein the first barrier layer The thickness is smaller than the thickness of the second barrier layer described above.
在本發明的一實施例中，上述的重摻雜P型半導體層的能隙越靠近上述的P型氮化物半導體越高，上述的重摻雜N型氮化物半導體層的能隙越靠近上述的第二N型氮化物半導體越高。In an embodiment of the present invention, the closer the energy gap of the heavily doped P-type semiconductor layer is to the P-type nitride semiconductor, the closer the energy gap of the heavily doped N-type nitride semiconductor layer is to the above. The higher the second N-type nitride semiconductor.
在本發明的一實施例中，上述的重摻雜P型半導體層的厚度約為1nm～100nm，上述的重摻雜N型氮化物半導體層的厚度約為1nm～100nm。In an embodiment of the invention, the heavily doped P-type semiconductor layer has a thickness of about 1 nm to 100 nm, and the heavily doped N-type nitride semiconductor layer has a thickness of about 1 nm to 100 nm.
在本發明的一實施例中，上述的第二N型氮化物半導體及上述的重摻雜N型(N+)氮化物半導體不會吸收上述的氮化物半導體量子井發光結構所發出光線。In an embodiment of the invention, the second N-type nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor do not absorb light emitted by the nitride semiconductor quantum well light-emitting structure.
在本發明的一實施例中，上述的第二N型氮化物半導體及上述的重摻雜N型(N+)氮化物半導體的能隙大於上述的氮化物半導體量子井發光結構的能隙。In an embodiment of the invention, the energy gap of the second N-type nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor is larger than the energy gap of the nitride semiconductor quantum well light-emitting structure.
在本發明的一實施例中，上述的多個氮化物半導體元件係可電性串聯而形成氮化物半導體高壓元件。In an embodiment of the invention, the plurality of nitride semiconductor elements are electrically connected in series to form a nitride semiconductor high voltage element.
在本發明的一實施例中，上述的氮化物半導體元件可以發出UV光線、藍色光線或綠色光線。In an embodiment of the invention, the nitride semiconductor device may emit UV light, blue light or green light.
在本發明的一實施例中，上述的氮化物半導體元件可以應用於燈絲(Filament)產品。In an embodiment of the invention, the nitride semiconductor device described above can be applied to a filament product.
在本發明的一實施例中，上述的氮化物半導體元件可以應用於COB(Chip on Board)產品。In an embodiment of the invention, the nitride semiconductor device described above can be applied to a COB (Chip on Board) product.
在本發明的一實施例中，上述的氮化物半導體元件可以應用於雷射二極體(Laser Diode)產品。In an embodiment of the invention, the nitride semiconductor device described above can be applied to a laser diode product.
在本發明的一實施例中，上述的氮化物半導體元件可以應用於發光二極體(Light Emitting Diode)產品。In an embodiment of the invention, the nitride semiconductor device described above can be applied to a Light Emitting Diode product.
本發明提供一種氮化物半導體元件，其包括基板、緩衝層、第一N型氮化物半導體、氮化物半導體量子井發光結構、P型氮化物半導體、穿隧接面(Tunnel Junction)以及第二N型氮化物半導體。上述的基板具有相對的第一面及第二面。上述的緩衝層設置於上述的基板的上述的第一面上。上述的第一N型氮化物半導體設置於上述的緩衝層上。上述的氮化物半導體量子井發光結構設置於上述的第一N型氮化物半導體上。上述的P型氮化物半導體設置於上述的氮化物半導體量子井發光結構上。上述的穿隧接面(Tunnel Junction)設置於上述的氮化物半導體量子井發光結構上。上述的穿隧接面包括重摻雜P型(P+)氮化物半導體以及重摻雜N型(N+)氮化物半導體。上述的重摻雜P型(P+)氮化物半導體設置於上述的氮化物半導體量子井發光結構上。上述的重摻雜N型(N+)氮化物半導體設置於上述的重摻雜P型氮化物半導體上。上述的第二N型氮化物半導體設置於上述的穿隧接面的上述的重摻雜N型氮化物半導體上。其中上述的氮化物半導體量子井發光結構具有多個井層和多個阻擋層，上述的多個阻擋層包含配置於最接近上述的P型氮化物半導體位置的第一阻擋層、配置於最接近上述的第一N型氮化物半導體位置的第二阻擋層以及多個第三阻擋層，其中上述的多個第三阻擋層被上述的多個井層夾住，其中上述的第一阻擋層的厚度小於上述的第三阻擋層的厚度。The present invention provides a nitride semiconductor device including a substrate, a buffer layer, a first N-type nitride semiconductor, a nitride semiconductor quantum well light emitting structure, a P-type nitride semiconductor, a tunnel junction, and a second N Type nitride semiconductor. The substrate has opposite first and second faces. The buffer layer is provided on the first surface of the substrate described above. The first N-type nitride semiconductor described above is provided on the buffer layer described above. The nitride semiconductor quantum well light-emitting structure described above is provided on the first N-type nitride semiconductor described above. The above-described P-type nitride semiconductor is provided on the above-described nitride semiconductor quantum well light-emitting structure. The above tunnel junction is disposed on the nitride semiconductor quantum well light-emitting structure described above. The tunneling junction described above includes a heavily doped P-type (P+) nitride semiconductor and a heavily doped N-type (N+) nitride semiconductor. The above heavily doped P-type (P+) nitride semiconductor is provided on the above-described nitride semiconductor quantum well light-emitting structure. The above heavily doped N-type (N+) nitride semiconductor is provided on the above-described heavily doped P-type nitride semiconductor. The second N-type nitride semiconductor is provided on the above-described heavily doped N-type nitride semiconductor on the tunnel junction surface. Wherein the nitride semiconductor quantum well light-emitting structure has a plurality of well layers and a plurality of barrier layers, and the plurality of barrier layers include a first barrier layer disposed at a position closest to the P-type nitride semiconductor, and disposed closest to a second barrier layer of the first N-type nitride semiconductor position and a plurality of third barrier layers, wherein the plurality of third barrier layers are sandwiched by the plurality of well layers, wherein the first barrier layer The thickness is less than the thickness of the third barrier layer described above.
在本發明的一實施例中，上述的重摻雜P型半導體層的能隙越靠近上述的P型氮化物半導體越高，上述的重摻雜N型氮化物半導體層的能隙越靠近上述的第二N型氮化物半導體越高。In an embodiment of the present invention, the closer the energy gap of the heavily doped P-type semiconductor layer is to the P-type nitride semiconductor, the closer the energy gap of the heavily doped N-type nitride semiconductor layer is to the above. The higher the second N-type nitride semiconductor.
在本發明的一實施例中，上述的重摻雜P型半導體層的厚度約為1nm～100nm，上述的重摻雜N型氮化物半導體層的厚度約為1nm～100nm。In an embodiment of the invention, the heavily doped P-type semiconductor layer has a thickness of about 1 nm to 100 nm, and the heavily doped N-type nitride semiconductor layer has a thickness of about 1 nm to 100 nm.
在本發明的一實施例中，上述的第二N型氮化物半導體及上述的重摻雜N型(N+)氮化物半導體不會吸收上述的氮化物半導體量子井發光結構所發出光線。In an embodiment of the invention, the second N-type nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor do not absorb light emitted by the nitride semiconductor quantum well light-emitting structure.
在本發明的一實施例中，上述的第二N型氮化物半導體及上述的重摻雜N型(N+)氮化物半導體的能隙大於上述的氮化物半導體量子井發光結構的能隙。In an embodiment of the invention, the energy gap of the second N-type nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor is larger than the energy gap of the nitride semiconductor quantum well light-emitting structure.
在本發明的一實施例中，上述的多個氮化物半導體元件係可電性串聯而形成氮化物半導體高壓元件。In an embodiment of the invention, the plurality of nitride semiconductor elements are electrically connected in series to form a nitride semiconductor high voltage element.
在本發明的一實施例中，上述的氮化物半導體元件可以發出UV光線、藍色光線或綠色光線。In an embodiment of the invention, the nitride semiconductor device may emit UV light, blue light or green light.
在本發明的一實施例中，上述的氮化物半導體元件可以應用於燈絲(Filament)產品。In an embodiment of the invention, the nitride semiconductor device described above can be applied to a filament product.
在本發明的一實施例中，上述的氮化物半導體元件可以應用於COB(Chip on Board)產品。In an embodiment of the invention, the nitride semiconductor device described above can be applied to a COB (Chip on Board) product.
在本發明的一實施例中，上述的氮化物半導體元件可以應用於雷射二極體(Laser Diode)產品。In an embodiment of the invention, the nitride semiconductor device described above can be applied to a laser diode product.
在本發明的一實施例中，上述的氮化物半導體元件可以應用於發光二極體(Light Emitting Diode)產品。In an embodiment of the invention, the nitride semiconductor device described above can be applied to a Light Emitting Diode product.
本發明提供一種氮化物半導體元件，其包括第一N型電極、第一N型氮化物半導體、氮化物半導體量子井發光結構、P型氮化物半導體、穿隧接面(Tunnel Junction)、第二N型氮化物半導體、高反射絕緣層、N型高反射歐姆電極、第一焊接金屬層、第二焊接金屬層、接合基板以及第二N型電極。上述的第一N型氮化物半導體設置於上述的第一N型電極上。上述的氮化物半導體量子井發光結構設置於上述的第一N型氮化物半導體上。上述的P型氮化物半導體設置於上述的氮化物半導體量子井發光結構上。上述的穿隧接面(Tunnel Junction)設置於上述的氮化物半導體量子井發光結構上。上述的穿隧接面包括重摻雜P型(P+)氮化物半導體以及重摻雜N型(N+)氮化物半導體。上述的重摻雜P型(P+)氮化物半導體設置於上述的氮化物半導體量子井發光結構上。上述的重摻雜N型(N+)氮化物半導體設置於上述的重摻雜P型氮化物半導體上。上述的第二N型氮化物半導體設置於上述的穿隧接面的上述的重摻雜N型氮化物半導體上。上述的高反射絕緣層設置於上述的第二N型氮化物半導體上，並暴露出部份的上述的第二N型氮化物半導體。上述的N型高反射歐姆電極設置於上述的第二N型氮化物半導體上，並覆蓋上述的高反射絕緣層及上述的第二N型氮化物半導體。上述的第一焊接金屬層設置於上述的N型高反射歐姆電極上。上述的第二焊接金屬層設置於上述的第一焊接金屬層上。上述的接合基板設置於上述的第二焊接金屬層上，並與上述的第一焊接金屬層電性連接。上述的第二N型電極設置於上述的接合基板上，並與上述的接合基板電性連接。其中上述的氮化物半導體量子井發光結構具有多個井層和多個阻擋層，上述的多個阻擋層包含配置於最接近上述的P型氮化物半導體位置的第一阻擋層、配置於最接近上述的第一N型氮化物半導體位置的第二阻擋層以及多個第三阻擋層，其中上述的多個第三阻擋層被上述的多個井層夾住，其中上述的第一阻擋層的厚度小於上述的第二阻擋層的厚度。The present invention provides a nitride semiconductor device including a first N-type electrode, a first N-type nitride semiconductor, a nitride semiconductor quantum well light-emitting structure, a P-type nitride semiconductor, a tunnel junction, and a second An N-type nitride semiconductor, a highly reflective insulating layer, an N-type highly reflective ohmic electrode, a first solder metal layer, a second solder metal layer, a bonding substrate, and a second N-type electrode. The first N-type nitride semiconductor described above is provided on the first N-type electrode described above. The nitride semiconductor quantum well light-emitting structure described above is provided on the first N-type nitride semiconductor described above. The above-described P-type nitride semiconductor is provided on the above-described nitride semiconductor quantum well light-emitting structure. The above tunnel junction is disposed on the nitride semiconductor quantum well light-emitting structure described above. The tunneling junction described above includes a heavily doped P-type (P+) nitride semiconductor and a heavily doped N-type (N+) nitride semiconductor. The above heavily doped P-type (P+) nitride semiconductor is provided on the above-described nitride semiconductor quantum well light-emitting structure. The above heavily doped N-type (N+) nitride semiconductor is provided on the above-described heavily doped P-type nitride semiconductor. The second N-type nitride semiconductor is provided on the above-described heavily doped N-type nitride semiconductor on the tunnel junction surface. The high-reflection insulating layer is disposed on the second N-type nitride semiconductor and exposes a portion of the second N-type nitride semiconductor. The N-type high-reflection ohmic electrode is provided on the second N-type nitride semiconductor and covers the high-reflection insulating layer and the second N-type nitride semiconductor. The first solder metal layer described above is disposed on the N-type high reflection ohmic electrode described above. The second solder metal layer is disposed on the first solder metal layer. The bonding substrate is provided on the second solder metal layer and electrically connected to the first solder metal layer. The second N-type electrode is provided on the bonding substrate and electrically connected to the bonding substrate. Wherein the nitride semiconductor quantum well light-emitting structure has a plurality of well layers and a plurality of barrier layers, and the plurality of barrier layers include a first barrier layer disposed at a position closest to the P-type nitride semiconductor, and disposed closest to a second barrier layer of the first N-type nitride semiconductor position and a plurality of third barrier layers, wherein the plurality of third barrier layers are sandwiched by the plurality of well layers, wherein the first barrier layer is The thickness is smaller than the thickness of the second barrier layer described above.
在本發明的一實施例中，上述的重摻雜P型半導體層的能隙越靠近上述的P型氮化物半導體越高，上述的重摻雜N型氮化物半導體層的能隙越靠近上述的第二N型氮化物半導體越高。In an embodiment of the present invention, the closer the energy gap of the heavily doped P-type semiconductor layer is to the P-type nitride semiconductor, the closer the energy gap of the heavily doped N-type nitride semiconductor layer is to the above. The higher the second N-type nitride semiconductor.
在本發明的一實施例中，上述的重摻雜P型半導體層的厚度約為1nm～100nm，上述的重摻雜N型氮化物半導體層的厚度約為1nm～100nm。In an embodiment of the invention, the heavily doped P-type semiconductor layer has a thickness of about 1 nm to 100 nm, and the heavily doped N-type nitride semiconductor layer has a thickness of about 1 nm to 100 nm.
在本發明的一實施例中，上述的第二N型氮化物半導體及上述的重摻雜N型(N+)氮化物半導體不會吸收上述的氮化物半導體量子井發光結構所發出光線。In an embodiment of the invention, the second N-type nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor do not absorb light emitted by the nitride semiconductor quantum well light-emitting structure.
在本發明的一實施例中，上述的第二N型氮化物半導體及上述的重摻雜N型(N+)氮化物半導體的能隙大於上述的氮化物半導體量子井發光結構的能隙。In an embodiment of the invention, the energy gap of the second N-type nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor is larger than the energy gap of the nitride semiconductor quantum well light-emitting structure.
在本發明的一實施例中，上述的多個氮化物半導體元件係可電性串聯而形成氮化物半導體高壓元件。In an embodiment of the invention, the plurality of nitride semiconductor elements are electrically connected in series to form a nitride semiconductor high voltage element.
在本發明的一實施例中，上述的氮化物半導體元件可以發出UV光線、藍色光線或綠色光線。In an embodiment of the invention, the nitride semiconductor device may emit UV light, blue light or green light.
在本發明的一實施例中，上述的氮化物半導體元件可以應用於燈絲(Filament)產品。In an embodiment of the invention, the nitride semiconductor device described above can be applied to a filament product.
在本發明的一實施例中，上述的氮化物半導體元件可以應用於COB(Chip on Board)產品。In an embodiment of the invention, the nitride semiconductor device described above can be applied to a COB (Chip on Board) product.
在本發明的一實施例中，上述的氮化物半導體元件可以應用於雷射二極體(Laser Diode)產品。In an embodiment of the invention, the nitride semiconductor device described above can be applied to a laser diode product.
在本發明的一實施例中，上述的氮化物半導體元件可以應用於發光二極體(Light Emitting Diode)產品。In an embodiment of the invention, the nitride semiconductor device described above can be applied to a Light Emitting Diode product.
本發明提供一種氮化物半導體元件，其包括第一N型電極、第一N型氮化物半導體、氮化物半導體量子井發光結構、P型氮化物半導體、穿隧接面(Tunnel Junction)、第二N型氮化物半導體、高反射絕緣層、N型高反射歐姆電極、第一焊接金屬層、第二焊接金屬層、接合基板以及第二N型電極。上述的第一N型氮化物半導體設置於上述的第一N型電極上。上述的氮化物半導體量子井發光結構設置於上述的第一N型氮化物半導體上。上述的P型氮化物半導體設置於上述的氮化物半導體量子井發光結構上。上述的穿隧接面(Tunnel Junction)設置於上述的氮化物半導體量子井發光結構上。上述的穿隧接面包括重摻雜P型(P+)氮化物半導體以及重摻雜N型(N+)氮化物半導體。上述的重摻雜P型(P+)氮化物半導體設置於上述的氮化物半導體量子井發光結構上。上述的重摻雜N型(N+)氮化物半導體設置於上述的重摻雜P型氮化物半導體上。上述的第二N型氮化物半導體設置於上述的穿隧接面的上述的重摻雜N型氮化物半導體上。上述的高反射絕緣層設置於上述的第二N型氮化物半導體上，並暴露出部份的上述的第二N型氮化物半導體。上述的N型高反射歐姆電極設置於上述的第二N型氮化物半導體上，並覆蓋上述的高反射絕緣層及上述的第二N型氮化物半導體。上述的第一焊接金屬層設置於上述的N型高反射歐姆電極上。上述的第二焊接金屬層設置於上述的第一焊接金屬層上。上述的接合基板設置於上述的第二焊接金屬層上，並與上述的第一焊接金屬層電性連接。上述的第二N型電極設置上述的接合基板上，並與上述的接合基板電性連接。其中上述的氮化物半導體量子井發光結構具有多個井層和多個阻擋層，上述的多個阻擋層包含配置於最接近上述的P型氮化物半導體位置的第一阻擋層、配置於最接近上述的第一N型氮化物半導體位置的第二阻擋層以及多個第三阻擋層，其中上述的多個第三阻擋層被上述的多個井層夾住，其中上述的第一阻擋層的厚度小於上述的第三阻擋層的厚度。The present invention provides a nitride semiconductor device including a first N-type electrode, a first N-type nitride semiconductor, a nitride semiconductor quantum well light-emitting structure, a P-type nitride semiconductor, a tunnel junction, and a second An N-type nitride semiconductor, a highly reflective insulating layer, an N-type highly reflective ohmic electrode, a first solder metal layer, a second solder metal layer, a bonding substrate, and a second N-type electrode. The first N-type nitride semiconductor described above is provided on the first N-type electrode described above. The nitride semiconductor quantum well light-emitting structure described above is provided on the first N-type nitride semiconductor described above. The above-described P-type nitride semiconductor is provided on the above-described nitride semiconductor quantum well light-emitting structure. The above tunnel junction is disposed on the nitride semiconductor quantum well light-emitting structure described above. The tunneling junction described above includes a heavily doped P-type (P+) nitride semiconductor and a heavily doped N-type (N+) nitride semiconductor. The above heavily doped P-type (P+) nitride semiconductor is provided on the above-described nitride semiconductor quantum well light-emitting structure. The above heavily doped N-type (N+) nitride semiconductor is provided on the above-described heavily doped P-type nitride semiconductor. The second N-type nitride semiconductor is provided on the above-described heavily doped N-type nitride semiconductor on the tunnel junction surface. The high-reflection insulating layer is disposed on the second N-type nitride semiconductor and exposes a portion of the second N-type nitride semiconductor. The N-type high-reflection ohmic electrode is provided on the second N-type nitride semiconductor and covers the high-reflection insulating layer and the second N-type nitride semiconductor. The first solder metal layer described above is disposed on the N-type high reflection ohmic electrode described above. The second solder metal layer is disposed on the first solder metal layer. The bonding substrate is provided on the second solder metal layer and electrically connected to the first solder metal layer. The second N-type electrode is provided on the above-described bonding substrate, and is electrically connected to the bonding substrate described above. Wherein the nitride semiconductor quantum well light-emitting structure has a plurality of well layers and a plurality of barrier layers, and the plurality of barrier layers include a first barrier layer disposed at a position closest to the P-type nitride semiconductor, and disposed closest to a second barrier layer of the first N-type nitride semiconductor position and a plurality of third barrier layers, wherein the plurality of third barrier layers are sandwiched by the plurality of well layers, wherein the first barrier layer The thickness is less than the thickness of the third barrier layer described above.
在本發明的一實施例中，上述的重摻雜P型半導體層的能隙越靠近上述的P型氮化物半導體越高，上述的重摻雜N型氮化物半導體層的能隙越靠近上述的第二N型氮化物半導體越高。In an embodiment of the present invention, the closer the energy gap of the heavily doped P-type semiconductor layer is to the P-type nitride semiconductor, the closer the energy gap of the heavily doped N-type nitride semiconductor layer is to the above. The higher the second N-type nitride semiconductor.
在本發明的一實施例中，上述的重摻雜P型半導體層的厚度約為1nm～100nm，上述的重摻雜N型氮化物半導體層的厚度約為1nm～100nm。In an embodiment of the invention, the heavily doped P-type semiconductor layer has a thickness of about 1 nm to 100 nm, and the heavily doped N-type nitride semiconductor layer has a thickness of about 1 nm to 100 nm.
在本發明的一實施例中，上述的第二N型氮化物半導體及上述的重摻雜N型(N+)氮化物半導體不會吸收上述的氮化物半導體量子井發光結構所發出光線。In an embodiment of the invention, the second N-type nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor do not absorb light emitted by the nitride semiconductor quantum well light-emitting structure.
在本發明的一實施例中，上述的第二N型氮化物半導體及上述的重摻雜N型(N+)氮化物半導體的能隙大於上述的氮化物半導體量子井發光結構的能隙。In an embodiment of the invention, the energy gap of the second N-type nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor is larger than the energy gap of the nitride semiconductor quantum well light-emitting structure.
在本發明的一實施例中，上述的多個氮化物半導體元件係可電性串聯而形成氮化物半導體高壓元件。In an embodiment of the invention, the plurality of nitride semiconductor elements are electrically connected in series to form a nitride semiconductor high voltage element.
在本發明的一實施例中，上述的氮化物半導體元件可以發出UV光線、藍色光線或綠色光線。In an embodiment of the invention, the nitride semiconductor device may emit UV light, blue light or green light.
在本發明的一實施例中，上述的氮化物半導體元件可以應用於燈絲(Filament)產品。In an embodiment of the invention, the nitride semiconductor device described above can be applied to a filament product.
在本發明的一實施例中，上述的氮化物半導體元件可以應用於COB(Chip on Board)產品。In an embodiment of the invention, the nitride semiconductor device described above can be applied to a COB (Chip on Board) product.
在本發明的一實施例中，上述的氮化物半導體元件可以應用於雷射二極體(Laser Diode)產品。In an embodiment of the invention, the nitride semiconductor device described above can be applied to a laser diode product.
在本發明的一實施例中，上述的氮化物半導體元件可以應用於發光二極體(Light Emitting Diode)產品。In an embodiment of the invention, the nitride semiconductor device described above can be applied to a Light Emitting Diode product.
本發明提供一種氮化物半導體元件的製造方法，包括下列步驟。形成半導體晶圓。以隱形雷射方式切割上述的半導體晶圓，形成如上述任一實施例中的氮化物半導體元件。The present invention provides a method of fabricating a nitride semiconductor device comprising the following steps. Forming a semiconductor wafer. The semiconductor wafer is cut in a stealth laser manner to form a nitride semiconductor device according to any of the above embodiments.
本發明提供一種封裝結構，其包括電路板、支架或載板以及如上述任一實施例中的氮化物半導體元件。上述的支架或上述的載板設置於上述的電路板上。上述的氮化物半導體元件設置於上述的支架或上述的載板上。The present invention provides a package structure comprising a circuit board, a bracket or a carrier and a nitride semiconductor component as in any of the above embodiments. The above bracket or the above carrier is provided on the above circuit board. The nitride semiconductor device described above is provided on the above-described holder or the above-described carrier.
在本發明的一實施例中，上述的封裝結構更包括透明膠，覆蓋如上述任一實施例中的氮化物半導體元件。In an embodiment of the invention, the package structure further includes a transparent adhesive covering the nitride semiconductor device of any of the above embodiments.
在本發明的一實施例中，上述的封裝結構更包括螢光粉，填入於上述的透明膠內。In an embodiment of the invention, the package structure further comprises a phosphor powder filled in the transparent glue.
在本發明的一實施例中，上述的螢光粉的濃度係均勻分佈於上述的透明膠內。In an embodiment of the invention, the concentration of the phosphor powder is uniformly distributed in the transparent paste.
在本發明的一實施例中，上述的螢光粉的濃度係不均勻分佈於上述的透明膠內。In an embodiment of the invention, the concentration of the phosphor powder is unevenly distributed in the transparent paste.
在本發明的一實施例中，上述的螢光粉的濃度係由如上述任一實施例中的氮化物半導體元件的表面往上述的透明膠的表面逐漸增加。In an embodiment of the invention, the concentration of the phosphor powder is gradually increased from the surface of the nitride semiconductor element in any of the above embodiments to the surface of the transparent paste.
在本發明的一實施例中，上述的螢光粉的濃度係由如上述任一實施例中的氮化物半導體元件的表面往上述的透明膠的表面逐漸減少。In an embodiment of the invention, the concentration of the phosphor powder is gradually reduced from the surface of the nitride semiconductor element in any of the above embodiments to the surface of the transparent paste.
在本發明的一實施例中，上述的螢光粉係由具高穩定發光特性的材料所製成，包含石榴石系(Garnet)、硫化物(Sulfate)、氮化物(Nitrate)、矽酸鹽(Silicate)、鋁酸鹽(Aluminate)或上述材料的任意組合，其發光波長約為300nm至700nm，其中上述的螢光粉的粒徑為1~25μm，其中上述的氮化物半導體元件所產生的一部份的光線可以激發上述的螢光粉，使得上述的螢光粉產生較長波長的光線，上述的氮化物半導體元件的剩餘一部份未被上述的螢光粉轉換的光線與上述的螢光粉產生的光線可以混合成白光。In an embodiment of the invention, the phosphor powder is made of a material having high stable luminescent properties, and includes Garnet, Sulfate, Nitrate, and Citrate. (Silicate), aluminate (Aluminate) or any combination of the above materials, having an emission wavelength of about 300 nm to 700 nm, wherein the above-mentioned phosphor powder has a particle diameter of 1 to 25 μm, wherein the above-described nitride semiconductor device is produced. A portion of the light illuminates the phosphor powder to cause the phosphor powder to generate a longer wavelength of light, and the remaining portion of the nitride semiconductor device is not converted by the phosphor powder and the above The light produced by the phosphor can be mixed into white light.
本發明提供一種氮化物半導體高壓元件，其包括電路板以及多個氮化物半導體元件。上述的多個氮化物半導體元件設置於上述的電路板上並相互電性串聯。其中各個上述的多個氮化物半導體元件包括第一N型氮化物半導體、氮化物半導體量子井發光結構、P型氮化物半導體、穿隧接面(Tunnel Junction)、第二N型氮化物半導體、第一N型電極以及第二N型電極。上述的第一N型氮化物半導體設置於上述的電路板上。上述的氮化物半導體量子井發光結構設置於上述的第一N型氮化物半導體上。上述的P型氮化物半導體設置於上述的氮化物半導體量子井發光結構上。上述的穿隧接面(Tunnel Junction)設置於上述的氮化物半導體量子井發光結構上。上述的穿隧接面包括重摻雜P型(P+)氮化物半導體以及重摻雜N型(N+)氮化物半導體。上述的重摻雜P型(P+)氮化物半導體設置於上述的氮化物半導體量子井發光結構上。上述的重摻雜N型(N+)氮化物半導體設置於上述的重摻雜P型氮化物半導體上。上述的第二N型氮化物半導體設置於上述的穿隧接面的上述的重摻雜N型氮化物半導體上。上述的第一N型電極設置於上述的第一N型氮化物半導體的一側。上述的第二N型電極設置於上述的第二N型氮化物半導體上。其中上述的多個氮化物半導體元件的其中之一的上述的第一N型電極係與其他的上述的多個氮化物半導體元件的其中之一的上述的P型氮化物半導體電性連接。The present invention provides a nitride semiconductor high voltage device including a circuit board and a plurality of nitride semiconductor elements. The plurality of nitride semiconductor elements described above are provided on the above-described circuit board and electrically connected in series. Each of the plurality of nitride semiconductor elements described above includes a first N-type nitride semiconductor, a nitride semiconductor quantum well light-emitting structure, a P-type nitride semiconductor, a tunnel junction, a second N-type nitride semiconductor, A first N-type electrode and a second N-type electrode. The first N-type nitride semiconductor described above is provided on the above-described circuit board. The nitride semiconductor quantum well light-emitting structure described above is provided on the first N-type nitride semiconductor described above. The above-described P-type nitride semiconductor is provided on the above-described nitride semiconductor quantum well light-emitting structure. The above tunnel junction is disposed on the nitride semiconductor quantum well light-emitting structure described above. The tunneling junction described above includes a heavily doped P-type (P+) nitride semiconductor and a heavily doped N-type (N+) nitride semiconductor. The above heavily doped P-type (P+) nitride semiconductor is provided on the above-described nitride semiconductor quantum well light-emitting structure. The above heavily doped N-type (N+) nitride semiconductor is provided on the above-described heavily doped P-type nitride semiconductor. The second N-type nitride semiconductor is provided on the above-described heavily doped N-type nitride semiconductor on the tunnel junction surface. The first N-type electrode is provided on one side of the first N-type nitride semiconductor. The second N-type electrode is provided on the second N-type nitride semiconductor. The first N-type electrode of one of the plurality of nitride semiconductor elements described above is electrically connected to the P-type nitride semiconductor of one of the other plurality of nitride semiconductor elements.
在本發明的一實施例中，上述的重摻雜P型半導體層的能隙越靠近上述的P型氮化物半導體越高，上述的重摻雜N型氮化物半導體層的能隙越靠近上述的第二N型氮化物半導體越高。In an embodiment of the present invention, the closer the energy gap of the heavily doped P-type semiconductor layer is to the P-type nitride semiconductor, the closer the energy gap of the heavily doped N-type nitride semiconductor layer is to the above. The higher the second N-type nitride semiconductor.
在本發明的一實施例中，上述的重摻雜P型半導體層的厚度約為1nm～100nm，上述的重摻雜N型氮化物半導體層的厚度約為1nm～100nm。In an embodiment of the invention, the heavily doped P-type semiconductor layer has a thickness of about 1 nm to 100 nm, and the heavily doped N-type nitride semiconductor layer has a thickness of about 1 nm to 100 nm.
在本發明的一實施例中，上述的穿隧接面更包括中間半導體，設置於上述的重摻雜P型(P+)氮化物半導體及上述的重摻雜N型(N+)氮化物半導體之間，上述的中間半導體相對於上述的重摻雜P型(P+)氮化物半導體及上述的重摻雜N型(N+)氮化物半導體形成異質接面，以建立極化場，使得上述的重摻雜P型(P+)氮化物半導體的價帶及上述的重摻雜N型(N+)氮化物半導體的導帶相互對應。In an embodiment of the invention, the tunneling junction further includes an intermediate semiconductor disposed on the heavily doped P-type (P+) nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor. The intermediate semiconductor is formed into a heterojunction with respect to the above-mentioned heavily doped P-type (P+) nitride semiconductor and the above-mentioned heavily doped N-type (N+) nitride semiconductor to establish a polarization field, so that the above-mentioned weight The valence band of the doped P-type (P+) nitride semiconductor and the conduction band of the above-described heavily doped N-type (N+) nitride semiconductor correspond to each other.
在本發明的一實施例中，上述的重摻雜P型(P+)氮化物半導體及上述的重摻雜N型(N+)氮化物半導體的至少一者的能隙大於上述的氮化物半導體量子井發光結構的能隙。In an embodiment of the invention, at least one of the heavily doped P-type (P+) nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor has a larger energy gap than the nitride semiconductor quantum The energy gap of the well-emitting structure.
在本發明的一實施例中，上述的中間半導體包含氮化鋁鎵(AlGaN)、氮化鎵(GaN)、氮化銦鎵(InGaN)或氮化銦鋁鎵(InAlGaN)。In an embodiment of the invention, the intermediate semiconductor comprises aluminum gallium nitride (AlGaN), gallium nitride (GaN), indium gallium nitride (InGaN) or indium aluminum gallium nitride (InAlGaN).
在本發明的一實施例中，上述的中間半導體具有內部帶穿隧阻擋層(inter band tunnel barrier)，上述的重摻雜P型(P+)氮化物半導體具有P型空乏阻擋層(P-depletion barrier)，上述的重摻雜N型(N+)氮化物半導體具有N型空乏阻擋層(N-depletion barrier)。In an embodiment of the invention, the intermediate semiconductor has an internal band gap barrier, and the heavily doped P-type (P+) nitride semiconductor has a P-type depletion barrier (P-depletion). Barrier), the above heavily doped N-type (N+) nitride semiconductor has an N-depletion barrier.
在本發明的一實施例中，上述的中間半導體的厚度約為0.5nm～10nm。In an embodiment of the invention, the intermediate semiconductor has a thickness of about 0.5 nm to 10 nm.
在本發明的一實施例中，上述的中間半導體具有側面材料能隙波動(lateral material energy bandgap fluctuations)，其包含多個低及高能隙區域(low and high bandgap regions)。In an embodiment of the invention, the intermediate semiconductor has lateral material energy bandgaps, which includes a plurality of low and high band gap regions.
在本發明的一實施例中，上述的多個氮化物半導體單元係可以被一透明膠覆蓋，且上述的透明膠包含一螢光粉。In an embodiment of the invention, the plurality of nitride semiconductor units may be covered by a transparent adhesive, and the transparent adhesive comprises a phosphor.
在本發明的一實施例中，上述的螢光粉的濃度係均勻分佈於上述的透明膠內。In an embodiment of the invention, the concentration of the phosphor powder is uniformly distributed in the transparent paste.
在本發明的一實施例中，上述的螢光粉的濃度係不均勻分佈於上述的透明膠內。In an embodiment of the invention, the concentration of the phosphor powder is unevenly distributed in the transparent paste.
在本發明的一實施例中，上述的螢光粉的濃度係由上述的氮化物半導體單元的表面往上述的透明膠的表面逐漸增加。In an embodiment of the invention, the concentration of the phosphor powder is gradually increased from the surface of the nitride semiconductor unit to the surface of the transparent paste.
在本發明的一實施例中，上述的螢光粉的濃度係由上述的氮化物半導體單元的表面往上述的透明膠的表面逐漸減少。In an embodiment of the invention, the concentration of the phosphor powder is gradually decreased from the surface of the nitride semiconductor unit to the surface of the transparent paste.
在本發明的一實施例中，上述的螢光粉係由具高穩定發光特性的材料所製成，包含石榴石系(Garnet)、硫化物(Sulfate)、氮化物(Nitrate)、矽酸鹽(Silicate)、鋁酸鹽(Aluminate)或上述材料的任意組合，其發光波長約為300nm至700nm，其中上述的螢光粉的粒徑為1~25μm，其中上述的氮化物半導體元件所產生的一部份的光線可以激發上述的螢光粉，使得上述的螢光粉產生較長波長的光線，上述的氮化物半導體元件的剩餘一部份未被上述的螢光粉轉換的光線與上述的螢光粉產生的光線可以混合成白光。In an embodiment of the invention, the phosphor powder is made of a material having high stable luminescent properties, and includes Garnet, Sulfate, Nitrate, and Citrate. (Silicate), aluminate (Aluminate) or any combination of the above materials, having an emission wavelength of about 300 nm to 700 nm, wherein the above-mentioned phosphor powder has a particle diameter of 1 to 25 μm, wherein the above-described nitride semiconductor device is produced. A portion of the light illuminates the phosphor powder to cause the phosphor powder to generate a longer wavelength of light, and the remaining portion of the nitride semiconductor device is not converted by the phosphor powder and the above The light produced by the phosphor can be mixed into white light.
在本發明的一實施例中，上述的氮化物半導體量子井發光結構具有多個井層和多個阻擋層，上述的多個阻擋層包含配置於最接近上述的P型氮化物半導體位置的第一阻擋層、配置於最接近上述的第一N型氮化物半導體位置的第二阻擋層以及多個第三阻擋層，其中上述的多個第三阻擋層被上述的多個井層夾住，其中上述的第二阻擋層的厚度大於上述的第一阻擋層的厚度，第三阻擋層的厚度大於上述的第一阻擋層的厚度，第二阻擋層的厚度大於或是等於上述的第三阻擋層的厚度。In an embodiment of the invention, the nitride semiconductor quantum well light-emitting structure has a plurality of well layers and a plurality of barrier layers, and the plurality of barrier layers include a portion disposed closest to the position of the P-type nitride semiconductor. a barrier layer, a second barrier layer disposed at a position closest to the first N-type nitride semiconductor region, and a plurality of third barrier layers, wherein the plurality of third barrier layers are sandwiched by the plurality of well layers Wherein the thickness of the second barrier layer is greater than the thickness of the first barrier layer, the thickness of the third barrier layer is greater than the thickness of the first barrier layer, and the thickness of the second barrier layer is greater than or equal to the third barrier The thickness of the layer.
在本發明的一實施例中，上述的氮化物半導體量子井發光結構具有多個井層和多個阻擋層，上述的多個阻擋層包含配置於最接近上述的P型氮化物半導體位置的第一阻擋層、配置於最接近上述的第一N型氮化物半導體位置的第二阻擋層以及多個第三阻擋層，其中上述的多個第三阻擋層被上述的多個井層夾住，其中上述的第二阻擋層的厚度大於上述的第一阻擋層的厚度，第三阻擋層的厚度大於上述的第一阻擋層的厚度，上述的第二阻擋層的厚度小於或是等於上述的第三阻擋層的厚度。In an embodiment of the invention, the nitride semiconductor quantum well light-emitting structure has a plurality of well layers and a plurality of barrier layers, and the plurality of barrier layers include a portion disposed closest to the position of the P-type nitride semiconductor. a barrier layer, a second barrier layer disposed at a position closest to the first N-type nitride semiconductor region, and a plurality of third barrier layers, wherein the plurality of third barrier layers are sandwiched by the plurality of well layers Wherein the thickness of the second barrier layer is greater than the thickness of the first barrier layer, the thickness of the third barrier layer is greater than the thickness of the first barrier layer, and the thickness of the second barrier layer is less than or equal to the above The thickness of the three barrier layers.
在本發明的一實施例中，上述的第一N型氮化物半導體及上述的第二N型氮化物半導體的至少一者具有粗糙表面，用以增加上述的氮化物半導體元件的出光效果。In an embodiment of the invention, at least one of the first N-type nitride semiconductor and the second N-type nitride semiconductor has a rough surface for increasing the light-emitting effect of the nitride semiconductor device.
本發明提供一種氮化物半導體高壓元件，其包括電路板以及多個氮化物半導體元件。上述的多個氮化物半導體元件設置於上述的電路板上並相互電性串聯。其中各個上述的多個氮化物半導體元件包括第一N型電極、第一N型氮化物半導體、氮化物半導體量子井發光結構、P型氮化物半導體、穿隧接面(Tunnel Junction)、第二N型氮化物半導體、高反射絕緣層、N型高反射歐姆電極、第一焊接金屬層、第二焊接金屬層、接合基板以及第二N型電極。上述的第一N型氮化物半導體設置於上述的第一N型電極上。上述的氮化物半導體量子井發光結構設置於上述的第一N型氮化物半導體上。上述的P型氮化物半導體設置於上述的氮化物半導體量子井發光結構上。上述的穿隧接面(Tunnel Junction)設置於上述的氮化物半導體量子井發光結構上。上述的穿隧接面包括重摻雜P型(P+)氮化物半導體以及重摻雜N型(N+)氮化物半導體。上述的重摻雜P型(P+)氮化物半導體設置於上述的氮化物半導體量子井發光結構上。上述的重摻雜N型(N+)氮化物半導體設置於上述的重摻雜P型氮化物半導體上。上述的第二N型氮化物半導體設置於上述的穿隧接面的上述的重摻雜N型氮化物半導體上。上述的高反射絕緣層設置於上述的第二N型氮化物半導體上，並暴露出部份的上述的第二N型氮化物半導體。上述的N型高反射歐姆電極設置於上述的第二N型氮化物半導體上，並覆蓋上述的高反射絕緣層及上述的第二N型氮化物半導體。上述的第一焊接金屬層設置於上述的N型高反射歐姆電極上。上述的第二焊接金屬層設置於上述的第一焊接金屬層上。上述的接合基板設置於上述的第二焊接金屬層上，並與上述的第一焊接金屬層電性連接。上述的第二N型電極設置上述的接合基板上，並與上述的接合基板電性連接。其中上述的多個氮化物半導體元件的其中之一的上述的第一N型電極係與其他的上述的多個氮化物半導體元件的其中之一的上述的P型氮化物半導體電性連接。The present invention provides a nitride semiconductor high voltage device including a circuit board and a plurality of nitride semiconductor elements. The plurality of nitride semiconductor elements described above are provided on the above-described circuit board and electrically connected in series. Each of the plurality of nitride semiconductor elements includes a first N-type electrode, a first N-type nitride semiconductor, a nitride semiconductor quantum well light-emitting structure, a P-type nitride semiconductor, a tunnel junction, and a second An N-type nitride semiconductor, a highly reflective insulating layer, an N-type highly reflective ohmic electrode, a first solder metal layer, a second solder metal layer, a bonding substrate, and a second N-type electrode. The first N-type nitride semiconductor described above is provided on the first N-type electrode described above. The nitride semiconductor quantum well light-emitting structure described above is provided on the first N-type nitride semiconductor described above. The above-described P-type nitride semiconductor is provided on the above-described nitride semiconductor quantum well light-emitting structure. The above tunnel junction is disposed on the nitride semiconductor quantum well light-emitting structure described above. The tunneling junction described above includes a heavily doped P-type (P+) nitride semiconductor and a heavily doped N-type (N+) nitride semiconductor. The above heavily doped P-type (P+) nitride semiconductor is provided on the above-described nitride semiconductor quantum well light-emitting structure. The above heavily doped N-type (N+) nitride semiconductor is provided on the above-described heavily doped P-type nitride semiconductor. The second N-type nitride semiconductor is provided on the above-described heavily doped N-type nitride semiconductor on the tunnel junction surface. The high-reflection insulating layer is disposed on the second N-type nitride semiconductor and exposes a portion of the second N-type nitride semiconductor. The N-type high-reflection ohmic electrode is provided on the second N-type nitride semiconductor and covers the high-reflection insulating layer and the second N-type nitride semiconductor. The first solder metal layer described above is disposed on the N-type high reflection ohmic electrode described above. The second solder metal layer is disposed on the first solder metal layer. The bonding substrate is provided on the second solder metal layer and electrically connected to the first solder metal layer. The second N-type electrode is provided on the above-described bonding substrate, and is electrically connected to the bonding substrate described above. The first N-type electrode of one of the plurality of nitride semiconductor elements described above is electrically connected to the P-type nitride semiconductor of one of the other plurality of nitride semiconductor elements.
在本發明的一實施例中，上述的重摻雜P型半導體層的能隙越靠近上述的P型氮化物半導體越高，上述的重摻雜N型氮化物半導體層的能隙越靠近上述的第二N型氮化物半導體越高。In an embodiment of the present invention, the closer the energy gap of the heavily doped P-type semiconductor layer is to the P-type nitride semiconductor, the closer the energy gap of the heavily doped N-type nitride semiconductor layer is to the above. The higher the second N-type nitride semiconductor.
在本發明的一實施例中，上述的重摻雜P型半導體層的厚度約為1nm～100nm，上述的重摻雜N型氮化物半導體層的厚度約為1nm～100nm。In an embodiment of the invention, the heavily doped P-type semiconductor layer has a thickness of about 1 nm to 100 nm, and the heavily doped N-type nitride semiconductor layer has a thickness of about 1 nm to 100 nm.
在本發明的一實施例中，上述的穿隧接面更包括中間半導體，設置於上述的重摻雜P型(P+)氮化物半導體及上述的重摻雜N型(N+)氮化物半導體之間，上述的中間半導體相對於上述的重摻雜P型(P+)氮化物半導體及上述的重摻雜N型(N+)氮化物半導體形成異質接面，以建立極化場，使得上述的重摻雜P型(P+)氮化物半導體的價帶及上述的重摻雜N型(N+)氮化物半導體的導帶相互對應。In an embodiment of the invention, the tunneling junction further includes an intermediate semiconductor disposed on the heavily doped P-type (P+) nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor. The intermediate semiconductor is formed into a heterojunction with respect to the above-mentioned heavily doped P-type (P+) nitride semiconductor and the above-mentioned heavily doped N-type (N+) nitride semiconductor to establish a polarization field, so that the above-mentioned weight The valence band of the doped P-type (P+) nitride semiconductor and the conduction band of the above-described heavily doped N-type (N+) nitride semiconductor correspond to each other.
在本發明的一實施例中，上述的重摻雜P型(P+)氮化物半導體及上述的重摻雜N型(N+)氮化物半導體的至少一者的能隙大於上述的氮化物半導體量子井發光結構的能隙。In an embodiment of the invention, at least one of the heavily doped P-type (P+) nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor has a larger energy gap than the nitride semiconductor quantum The energy gap of the well-emitting structure.
在本發明的一實施例中，上述的中間半導體包含氮化鋁鎵(AlGaN)、氮化鎵(GaN)、氮化銦鎵(InGaN)或氮化銦鋁鎵(InAlGaN)。In an embodiment of the invention, the intermediate semiconductor comprises aluminum gallium nitride (AlGaN), gallium nitride (GaN), indium gallium nitride (InGaN) or indium aluminum gallium nitride (InAlGaN).
在本發明的一實施例中，上述的中間半導體具有內部帶穿隧阻擋層(inter band tunnel barrier)，上述的重摻雜P型(P+)氮化物半導體具有P型空乏阻擋層(P-depletion barrier)，上述的重摻雜N型(N+)氮化物半導體具有N型空乏阻擋層(N-depletion barrier)。In an embodiment of the invention, the intermediate semiconductor has an internal band gap barrier, and the heavily doped P-type (P+) nitride semiconductor has a P-type depletion barrier (P-depletion). Barrier), the above heavily doped N-type (N+) nitride semiconductor has an N-depletion barrier.
在本發明的一實施例中，上述的中間半導體的厚度約為0.5nm～10nm。In an embodiment of the invention, the intermediate semiconductor has a thickness of about 0.5 nm to 10 nm.
在本發明的一實施例中，上述的中間半導體具有側面材料能隙波動(lateral material energy bandgap fluctuations)，其包含多個低及高能隙區域(low and high bandgap regions)。In an embodiment of the invention, the intermediate semiconductor has lateral material energy bandgaps, which includes a plurality of low and high band gap regions.
在本發明的一實施例中，上述的多個氮化物半導體單元係可以被一透明膠覆蓋，且上述的透明膠包含一螢光粉。In an embodiment of the invention, the plurality of nitride semiconductor units may be covered by a transparent adhesive, and the transparent adhesive comprises a phosphor.
在本發明的一實施例中，上述的螢光粉的濃度係均勻分佈於上述的透明膠內。In an embodiment of the invention, the concentration of the phosphor powder is uniformly distributed in the transparent paste.
在本發明的一實施例中，上述的螢光粉的濃度係不均勻分佈於上述的透明膠內。In an embodiment of the invention, the concentration of the phosphor powder is unevenly distributed in the transparent paste.
在本發明的一實施例中，上述的螢光粉的濃度係由上述的氮化物半導體單元的表面往上述的透明膠的表面逐漸增加。In an embodiment of the invention, the concentration of the phosphor powder is gradually increased from the surface of the nitride semiconductor unit to the surface of the transparent paste.
在本發明的一實施例中，上述的螢光粉的濃度係由上述的氮化物半導體單元的表面往上述的透明膠的表面逐漸減少。In an embodiment of the invention, the concentration of the phosphor powder is gradually decreased from the surface of the nitride semiconductor unit to the surface of the transparent paste.
在本發明的一實施例中，上述的螢光粉係由具高穩定發光特性的材料所製成，包含石榴石系(Garnet)、硫化物(Sulfate)、氮化物(Nitrate)、矽酸鹽(Silicate)、鋁酸鹽(Aluminate)或上述材料的任意組合，其發光波長約為300nm至700nm，其中上述的螢光粉的粒徑為1~25μm，其中上述的氮化物半導體元件所產生的一部份的光線可以激發上述的螢光粉，使得上述的螢光粉產生較長波長的光線，上述的氮化物半導體元件的剩餘一部份未被上述的螢光粉轉換的光線與上述的螢光粉產生的光線可以混合成白光。In an embodiment of the invention, the phosphor powder is made of a material having high stable luminescent properties, and includes Garnet, Sulfate, Nitrate, and Citrate. (Silicate), aluminate (Aluminate) or any combination of the above materials, having an emission wavelength of about 300 nm to 700 nm, wherein the above-mentioned phosphor powder has a particle diameter of 1 to 25 μm, wherein the above-described nitride semiconductor device is produced. A portion of the light illuminates the phosphor powder to cause the phosphor powder to generate a longer wavelength of light, and the remaining portion of the nitride semiconductor device is not converted by the phosphor powder and the above The light produced by the phosphor can be mixed into white light.
在本發明的一實施例中，上述的氮化物半導體量子井發光結構具有多個井層和多個阻擋層，上述的多個阻擋層包含配置於最接近上述的P型氮化物半導體位置的第一阻擋層、配置於最接近上述的第一N型氮化物半導體位置的第二阻擋層以及多個第三阻擋層，其中上述的多個第三阻擋層被上述的多個井層夾住，其中上述的第二阻擋層的厚度大於上述的第一阻擋層的厚度，第三阻擋層的厚度大於上述的第一阻擋層的厚度，第二阻擋層的厚度大於或是等於上述的第三阻擋層的厚度。In an embodiment of the invention, the nitride semiconductor quantum well light-emitting structure has a plurality of well layers and a plurality of barrier layers, and the plurality of barrier layers include a portion disposed closest to the position of the P-type nitride semiconductor. a barrier layer, a second barrier layer disposed at a position closest to the first N-type nitride semiconductor region, and a plurality of third barrier layers, wherein the plurality of third barrier layers are sandwiched by the plurality of well layers Wherein the thickness of the second barrier layer is greater than the thickness of the first barrier layer, the thickness of the third barrier layer is greater than the thickness of the first barrier layer, and the thickness of the second barrier layer is greater than or equal to the third barrier The thickness of the layer.
在本發明的一實施例中，上述的氮化物半導體量子井發光結構具有多個井層和多個阻擋層，上述的多個阻擋層包含配置於最接近上述的P型氮化物半導體位置的第一阻擋層、配置於最接近上述的第一N型氮化物半導體位置的第二阻擋層以及多個第三阻擋層，其中上述的多個第三阻擋層被上述的多個井層夾住，其中上述的第二阻擋層的厚度大於上述的第一阻擋層的厚度，第三阻擋層的厚度大於上述的第一阻擋層的厚度，上述的第二阻擋層的厚度小於或是等於上述的第三阻擋層的厚度。In an embodiment of the invention, the nitride semiconductor quantum well light-emitting structure has a plurality of well layers and a plurality of barrier layers, and the plurality of barrier layers include a portion disposed closest to the position of the P-type nitride semiconductor. a barrier layer, a second barrier layer disposed at a position closest to the first N-type nitride semiconductor region, and a plurality of third barrier layers, wherein the plurality of third barrier layers are sandwiched by the plurality of well layers Wherein the thickness of the second barrier layer is greater than the thickness of the first barrier layer, the thickness of the third barrier layer is greater than the thickness of the first barrier layer, and the thickness of the second barrier layer is less than or equal to the above The thickness of the three barrier layers.
在本發明的一實施例中，上述的第一N型氮化物半導體及上述的第二N型氮化物半導體的至少一者具有粗糙表面，用以增加上述的氮化物半導體元件的出光效果。In an embodiment of the invention, at least one of the first N-type nitride semiconductor and the second N-type nitride semiconductor has a rough surface for increasing the light-emitting effect of the nitride semiconductor device.
本發明提供一種氮化物半導體元件，其包括基板、緩衝層、第一N型氮化物半導體、氮化物半導體量子井發光結構、P型氮化物半導體、穿隧接面(Tunnel Junction)以及第二N型氮化物半導體。上述的基板具有相對的第一面及第二面。上述的緩衝層設置於上述的基板的上述的第一面上。上述的第一N型氮化物半導體設置於上述的緩衝層上。上述的氮化物半導體量子井發光結構設置於上述的第一N型氮化物半導體上。上述的P型氮化物半導體設置於上述的氮化物半導體量子井發光結構上。其中上述的P型氮化物半導體包括、P側應力釋放層、高濃度電洞層以及電子阻擋層。上述的穿隧接面(Tunnel Junction)設置於上述的氮化物半導體量子井發光結構上。上述的穿隧接面包括重摻雜P型(P+)氮化物半導體以及重摻雜N型(N+)氮化物半導體。上述的重摻雜P型(P+)氮化物半導體設置於上述的氮化物半導體量子井發光結構上。上述的重摻雜N型(N+)氮化物半導體設置於上述的重摻雜P型氮化物半導體上。上述的第二N型氮化物半導體設置於上述的穿隧接面的上述的重摻雜N型氮化物半導體上。其中上述的氮化物半導體量子井發光結構具有多個井層和多個阻擋層，上述的多個阻擋層包含配置於最接近上述的P型氮化物半導體位置的第一阻擋層、配置於最接近上述的第一N型氮化物半導體位置的第二阻擋層以及多個第三阻擋層，其中上述的多個第三阻擋層被上述的多個井層夾住，其中配置於最接近上述的第一阻擋層為上述的P側應力釋放層，配置於最遠離上述的第一阻擋層為上述的電子阻擋層，上述的高濃度電洞層被上述的P側應力釋放層以及上述的電子阻擋層所夾住。The present invention provides a nitride semiconductor device including a substrate, a buffer layer, a first N-type nitride semiconductor, a nitride semiconductor quantum well light emitting structure, a P-type nitride semiconductor, a tunnel junction, and a second N Type nitride semiconductor. The substrate has opposite first and second faces. The buffer layer is provided on the first surface of the substrate described above. The first N-type nitride semiconductor described above is provided on the buffer layer described above. The nitride semiconductor quantum well light-emitting structure described above is provided on the first N-type nitride semiconductor described above. The above-described P-type nitride semiconductor is provided on the above-described nitride semiconductor quantum well light-emitting structure. The P-type nitride semiconductor described above includes a P-side stress releasing layer, a high-concentration hole layer, and an electron blocking layer. The above tunnel junction is disposed on the nitride semiconductor quantum well light-emitting structure described above. The tunneling junction described above includes a heavily doped P-type (P+) nitride semiconductor and a heavily doped N-type (N+) nitride semiconductor. The above heavily doped P-type (P+) nitride semiconductor is provided on the above-described nitride semiconductor quantum well light-emitting structure. The above heavily doped N-type (N+) nitride semiconductor is provided on the above-described heavily doped P-type nitride semiconductor. The second N-type nitride semiconductor is provided on the above-described heavily doped N-type nitride semiconductor on the tunnel junction surface. Wherein the nitride semiconductor quantum well light-emitting structure has a plurality of well layers and a plurality of barrier layers, and the plurality of barrier layers include a first barrier layer disposed at a position closest to the P-type nitride semiconductor, and disposed closest to a second barrier layer of the first N-type nitride semiconductor position and a plurality of third barrier layers, wherein the plurality of third barrier layers are sandwiched by the plurality of well layers, wherein the first layer is disposed closest to the first a barrier layer is the above-mentioned P-side stress releasing layer, and the first barrier layer farthest from the above is the above-mentioned electron blocking layer, and the high-concentration hole layer is the P-side stress releasing layer and the electron blocking layer described above. Caught.
在本發明的一實施例中，上述的P側應力釋放層可為超晶格結構，其材料包含氮化鋁鎵(AlGaN)以及氮化鎵(GaN)所構成的超晶格結構，或是由氮化鋁鎵(Alx GaN)以及氮化鋁鎵(Aly GaN)所構成的超晶格結構，或是由氮化鋁鎵(AlGaN)以及氮化鋁銦鎵(InAlGaN)所構成的超晶格結構，其中，x不等於y，上述的超晶格結構小於20對。In an embodiment of the invention, the P-side stress relief layer may be a superlattice structure, the material of which comprises a superlattice structure composed of aluminum gallium nitride (AlGaN) and gallium nitride (GaN), or a superlattice structure composed of aluminum gallium nitride (Al x GaN) and aluminum gallium nitride (Al y GaN), or composed of aluminum gallium nitride (AlGaN) and aluminum indium gallium nitride (InAlGaN) A superlattice structure in which x is not equal to y and the superlattice structure described above is less than 20 pairs.
在本發明的一實施例中，上述的高濃度電洞層可由氮化鎵(GaN)或是氮化鋁鎵(AlGaN)所構成，上述的高濃度電洞層的鎂摻雜濃度(concentration)高於上述的P側應力釋放層的鎂摻雜濃度以及上述的電子阻擋層的鎂摻雜濃度。In an embodiment of the invention, the high-concentration hole layer may be composed of gallium nitride (GaN) or aluminum gallium nitride (AlGaN), and the magnesium concentration of the high-concentration hole layer is concentrated. It is higher than the magnesium doping concentration of the P-side stress releasing layer described above and the magnesium doping concentration of the above-described electron blocking layer.
在本發明的一實施例中，上述的高濃度電洞層的鎂(Mg)摻雜濃度高於1x1019 (Atoms/cm3 )。In an embodiment of the invention, the high concentration hole layer has a magnesium (Mg) doping concentration higher than 1 x 10 19 (Atoms/cm 3 ).
在本發明的一實施例中，上述的電子阻擋層可由氮化鋁鎵(AlGaN)所構成，上述的電子阻擋層的鋁成份百分比高於上述的P側應力釋放層的鋁成份百分比以及高於上述的高濃度電洞層的鋁成份百分比。In an embodiment of the invention, the electron blocking layer may be composed of aluminum gallium nitride (AlGaN), and the percentage of the aluminum component of the electron blocking layer is higher than the percentage of the aluminum component of the P-side stress releasing layer and higher than The percentage of aluminum component of the high concentration hole layer described above.
在本發明的一實施例中，上述的穿隧接面更包括中間半導體，設置於上述的重摻雜P型(P+)氮化物半導體及上述的重摻雜N型(N+)氮化物半導體之間。In an embodiment of the invention, the tunneling junction further includes an intermediate semiconductor disposed on the heavily doped P-type (P+) nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor. between.
在本發明的一實施例中，上述的高濃度電洞層的鎂(Mg)摻雜濃度高於1x1019 (Atoms/cm3 )，且上述的高濃度電洞層的鋁成份百分比低於上述的電子阻擋層的鋁成份百分比。In an embodiment of the invention, the high concentration hole layer has a magnesium (Mg) doping concentration higher than 1×10 19 (Atoms/cm 3 ), and the high concentration hole layer has a lower aluminum component percentage than the above. The percentage of aluminum component of the electronic barrier layer.
在本發明的一實施例中，上述的第二N型氮化物半導體及上述的重摻雜N型(N+)氮化物半導體不會吸收上述的氮化物半導體量子井發光結構所發出光線。In an embodiment of the invention, the second N-type nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor do not absorb light emitted by the nitride semiconductor quantum well light-emitting structure.
在本發明的一實施例中，上述的第二N型氮化物半導體及上述的重摻雜N型(N+)氮化物半導體的能隙大於上述的氮化物半導體量子井發光結構的能隙。In an embodiment of the invention, the energy gap of the second N-type nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor is larger than the energy gap of the nitride semiconductor quantum well light-emitting structure.
在本發明的一實施例中，上述的多個氮化物半導體元件係可電性串聯而形成氮化物半導體高壓元件。In an embodiment of the invention, the plurality of nitride semiconductor elements are electrically connected in series to form a nitride semiconductor high voltage element.
在本發明的一實施例中，上述的氮化物半導體元件可以發出UV光線、藍色光線或綠色光線。In an embodiment of the invention, the nitride semiconductor device may emit UV light, blue light or green light.
在本發明的一實施例中，上述的氮化物半導體元件可以應用於燈絲(Filament)產品。In an embodiment of the invention, the nitride semiconductor device described above can be applied to a filament product.
在本發明的一實施例中，上述的氮化物半導體元件可以應用於COB(Chip on Board)產品。In an embodiment of the invention, the nitride semiconductor device described above can be applied to a COB (Chip on Board) product.
在本發明的一實施例中，上述的氮化物半導體元件可以應用於雷射二極體(Laser Diode)產品。In an embodiment of the invention, the nitride semiconductor device described above can be applied to a laser diode product.
在本發明的一實施例中，上述的氮化物半導體元件可以應用於發光二極體(Light Emitting Diode)產品。In an embodiment of the invention, the nitride semiconductor device described above can be applied to a Light Emitting Diode product.
本發明提供一種氮化物半導體元件，其包括基板、緩衝層、第一N型氮化物半導體、氮化物半導體量子井發光結構、P型氮化物半導體、穿隧接面(Tunnel Junction)以及第二N型氮化物半導體。上述的基板具有相對的第一面及第二面。上述的緩衝層設置於上述的基板的上述的第一面上。上述的第一N型氮化物半導體，設置於上述的緩衝層上。其中上述的第一N型氮化物半導體包括N側第一應力釋放層、N側第二應力釋放層、低濃度電子層以及N型歐姆接觸層。上述的氮化物半導體量子井發光結構設置於上述的第一N型氮化物半導體上。上述的P型氮化物半導體設置於上述的氮化物半導體量子井發光結構上。上述的穿隧接面(Tunnel Junction)設置於上述的氮化物半導體量子井發光結構上。上述的穿隧接面包括重摻雜P型(P+)氮化物半導體以及重摻雜N型(N+)氮化物半導體。上述的重摻雜P型(P+)氮化物半導體，設置於上述的氮化物半導體量子井發光結構上。上述的重摻雜N型(N+)氮化物半導體，設置於上述的重摻雜P型氮化物半導體上。上述的第二N型氮化物半導體，設置於上述的穿隧接面的上述的重摻雜N型氮化物半導體上。其中上述的氮化物半導體量子井發光結構具有多個井層和多個阻擋層，上述的多個阻擋層包含配置於最接近上述的P型氮化物半導體位置的第一阻擋層、配置於最接近上述的第一N型氮化物半導體位置的第二阻擋層以及多個第三阻擋層，其中上述的多個第三阻擋層被上述的多個井層夾住，其中配置於最接近上述的第二阻擋層為上述的N側第一應力釋放層，配置於最遠離述上述的第二阻擋層為上述的N型歐姆接觸層，上述的低濃度電子層以及上述的第二應力釋放層依序堆疊於上述的N型歐姆接觸層上方，上述的低濃度電子層被上述的N型歐姆接觸層及上述的N側第二應力釋放層所夾住。The present invention provides a nitride semiconductor device including a substrate, a buffer layer, a first N-type nitride semiconductor, a nitride semiconductor quantum well light emitting structure, a P-type nitride semiconductor, a tunnel junction, and a second N Type nitride semiconductor. The substrate has opposite first and second faces. The buffer layer is provided on the first surface of the substrate described above. The first N-type nitride semiconductor described above is provided on the above buffer layer. The first N-type nitride semiconductor described above includes an N-side first stress releasing layer, an N-side second stress releasing layer, a low-concentration electron layer, and an N-type ohmic contact layer. The nitride semiconductor quantum well light-emitting structure described above is provided on the first N-type nitride semiconductor described above. The above-described P-type nitride semiconductor is provided on the above-described nitride semiconductor quantum well light-emitting structure. The above tunnel junction is disposed on the nitride semiconductor quantum well light-emitting structure described above. The tunneling junction described above includes a heavily doped P-type (P+) nitride semiconductor and a heavily doped N-type (N+) nitride semiconductor. The above heavily doped P-type (P+) nitride semiconductor is provided on the above-described nitride semiconductor quantum well light-emitting structure. The above heavily doped N-type (N+) nitride semiconductor is provided on the above-described heavily doped P-type nitride semiconductor. The second N-type nitride semiconductor described above is provided on the above-described heavily doped N-type nitride semiconductor on the tunnel junction surface. Wherein the nitride semiconductor quantum well light-emitting structure has a plurality of well layers and a plurality of barrier layers, and the plurality of barrier layers include a first barrier layer disposed at a position closest to the P-type nitride semiconductor, and disposed closest to a second barrier layer of the first N-type nitride semiconductor position and a plurality of third barrier layers, wherein the plurality of third barrier layers are sandwiched by the plurality of well layers, wherein the first layer is disposed closest to the first The second barrier layer is the N-side first stress relief layer, and the second barrier layer farthest from the above is the N-type ohmic contact layer, and the low-concentration electron layer and the second stress-relieving layer are sequentially arranged. Stacked above the N-type ohmic contact layer, the low-concentration electron layer is sandwiched by the N-type ohmic contact layer and the N-side second stress-relieving layer.
在本發明的一實施例中，上述的N側第一應力釋放層可為超晶格結構，其材料包含氮化銦鎵(InGaN)以及氮化鎵(GaN)所構成的超晶格結構，或是由氮化銦鎵(Inx GaN)以及氮化銦鎵(Iny GaN)所構成的超晶格結構，其中x不等於y，上述的超晶格結構小於20對。In an embodiment of the invention, the N-side first stress relief layer may be a superlattice structure, and the material thereof comprises a superlattice structure composed of indium gallium nitride (InGaN) and gallium nitride (GaN). Or a superlattice structure composed of indium gallium nitride (In x GaN) and indium gallium nitride (In y GaN), wherein x is not equal to y, and the superlattice structure described above is less than 20 pairs.
在本發明的一實施例中，上述的N側第二應力釋放層可為超晶格結構，其材料包含氮化銦鎵(InGaN)以及氮化鎵(GaN)所構成的超晶格結構，或是由氮化銦鎵(Inx GaN))以及氮化銦鎵(Iny GaN)所構成的超晶格結構，其中x不等於y，上述的超晶格結構小於20對。In an embodiment of the invention, the N-side second stress relief layer may be a superlattice structure, and the material thereof comprises a superlattice structure composed of indium gallium nitride (InGaN) and gallium nitride (GaN). Or a superlattice structure composed of indium gallium nitride (In x GaN) and indium gallium nitride (In y GaN), wherein x is not equal to y, and the superlattice structure described above is less than 20 pairs.
在本發明的一實施例中，上述的N側第一應力釋放層的銦成份百分比高於上述的N側第二應力釋放層的銦成份百分比。In an embodiment of the invention, the percentage of indium component of the N-side first stress-relieving layer is higher than the percentage of the indium component of the N-side second stress-relieving layer.
在本發明的一實施例中，上述的低濃度電子層可由氮化鎵(GaN)、氮化銦鎵(InGaN)、氮化鋁鎵(AlGaN)或氮化銦鋁鎵(InAlGaN)所構成，上述的低濃度電子層的矽摻雜濃度低於上述的N型歐姆接觸層的矽摻雜濃度。In an embodiment of the invention, the low-concentration electron layer may be formed of gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), or indium aluminum gallium nitride (InAlGaN). The above-mentioned low-concentration electron layer has a germanium doping concentration lower than that of the above-described N-type ohmic contact layer.
在本發明的一實施例中，上述的低濃度電子層的矽摻雜濃度低於1x1018 (Atoms/cm3 )。In an embodiment of the invention, the low concentration electron layer has a germanium doping concentration of less than 1 x 10 18 (Atoms/cm 3 ).
在本發明的一實施例中，上述的N型歐姆接觸層可由氮化鎵(GaN)、氮化銦鎵(InGaN)、氮化鋁鎵(AlGaN)或氮化銦鋁鎵(InAlGaN)所構成，上述的N型歐姆接觸層的矽摻雜濃度高於上述的N側第一應力釋放層的矽摻雜濃度、上述的N側第二應力釋放層的矽摻雜濃度及上述的低濃度電子層的矽摻雜濃度。In an embodiment of the invention, the N-type ohmic contact layer may be formed of gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN) or indium aluminum gallium nitride (InAlGaN). The cerium doping concentration of the N-type ohmic contact layer is higher than the cerium doping concentration of the N-side first stress-relieving layer, the cerium doping concentration of the N-side second stress-relieving layer, and the low-concentration electrons described above. The erbium doping concentration of the layer.
在本發明的一實施例中，上述的第二N型氮化物半導體及上述的重摻雜N型(N+)氮化物半導體不會吸收上述的氮化物半導體量子井發光結構所發出光線。In an embodiment of the invention, the second N-type nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor do not absorb light emitted by the nitride semiconductor quantum well light-emitting structure.
在本發明的一實施例中，上述的第二N型氮化物半導體及上述的重摻雜N型(N+)氮化物半導體的能隙大於上述的氮化物半導體量子井發光結構的能隙。In an embodiment of the invention, the energy gap of the second N-type nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor is larger than the energy gap of the nitride semiconductor quantum well light-emitting structure.
在本發明的一實施例中，上述的多個氮化物半導體元件係可電性串聯而形成氮化物半導體高壓元件。In an embodiment of the invention, the plurality of nitride semiconductor elements are electrically connected in series to form a nitride semiconductor high voltage element.
在本發明的一實施例中，上述的氮化物半導體元件可以發出UV光線、藍色光線或綠色光線。In an embodiment of the invention, the nitride semiconductor device may emit UV light, blue light or green light.
在本發明的一實施例中，上述的氮化物半導體元件可以應用於燈絲(Filament)產品。In an embodiment of the invention, the nitride semiconductor device described above can be applied to a filament product.
在本發明的一實施例中，上述的氮化物半導體元件可以應用於COB(Chip on Board)產品。In an embodiment of the invention, the nitride semiconductor device described above can be applied to a COB (Chip on Board) product.
在本發明的一實施例中，上述的氮化物半導體元件可以應用於雷射二極體(Laser Diode)產品。In an embodiment of the invention, the nitride semiconductor device described above can be applied to a laser diode product.
在本發明的一實施例中，上述的氮化物半導體元件可以應用於發光二極體(Light Emitting Diode)產品。In an embodiment of the invention, the nitride semiconductor device described above can be applied to a Light Emitting Diode product.
在本發明的一實施例中，基於穿隧接面(Tunnel Junction)的結構，可以省略之後電流阻擋層(Current Blocking Layer, CBL)及透明導電層(Transparent Conductive Layer, TCL)的結構及製程，一樣可以達到電流均勻分佈以及發光效率提昇的效果。In an embodiment of the present invention, the structure and process of the Current Blocking Layer (CBL) and the Transparent Conductive Layer (TCL) may be omitted based on the tunnel junction structure. The same effect of uniform current distribution and luminous efficiency can be achieved.
基於上述，本發明的氮化物半導體元件，其可以提昇發光效率及改善製程良率。本發明的氮化物半導體元件的製造方法可用以製作上述的氮化物半導體元件。本發明的封裝結構可應用於上述的氮化物半導體元件。Based on the above, the nitride semiconductor device of the present invention can improve luminous efficiency and improve process yield. The method for producing a nitride semiconductor device of the present invention can be used to fabricate the above-described nitride semiconductor device. The package structure of the present invention can be applied to the above-described nitride semiconductor device.
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the invention will be apparent from the following description.
圖1是依照本發明的第一實施例的一種氮化物半導體元件的剖面示意圖。本實施例的氮化物半導體元件100包括P型氮化物半導體101、N型氮化物半導體102、氮化物半導體量子井發光結構103、基板104以及緩衝層105。氮化物半導體量子井發光結構103位於P型氮化物半導體101以及N型氮化物半導體102之間。基板104具有相對的第一面104A以及第二面104B。緩衝層105位於N型氮化物半導體102以及基板104的第一面104A之間。氮化物半導體量子井發光結構103具有多個井層103A以及多個阻擋層103B。多個阻擋層103B包括一個配置於最接近P型氮化物半導體101位置的第一阻擋層103B1、一個配置於最接近N型氮化物半導體102位置的第二阻擋層103B2以及至少一個第三阻擋層103B3。在圖1所繪示的實施例中，第三阻擋層103B3的數量是以一個為例，但本發明對於第三阻擋層103B3的數量並不加以限制。第三阻擋層103B3的相對兩端分別被對應的兩個井層103A夾住。換言之，多個井層103A以及各個多個阻擋層103B彼此交錯配置。第一阻擋層103B1的厚度小於100埃(Å)。具體而言，本實施例的氮化物半導體元件100可以為具有水平(horizontal)結構的發光二極體元件(light emission diode；LED)。BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic cross-sectional view showing a nitride semiconductor device in accordance with a first embodiment of the present invention. The nitride semiconductor device 100 of the present embodiment includes a P-type nitride semiconductor 101, an N-type nitride semiconductor 102, a nitride semiconductor quantum well light-emitting structure 103, a substrate 104, and a buffer layer 105. The nitride semiconductor quantum well light emitting structure 103 is located between the P-type nitride semiconductor 101 and the N-type nitride semiconductor 102. The substrate 104 has opposing first and second faces 104A, 104B. The buffer layer 105 is located between the N-type nitride semiconductor 102 and the first surface 104A of the substrate 104. The nitride semiconductor quantum well light emitting structure 103 has a plurality of well layers 103A and a plurality of barrier layers 103B. The plurality of barrier layers 103B include a first barrier layer 103B1 disposed at a position closest to the P-type nitride semiconductor 101, a second barrier layer 103B2 disposed at a position closest to the N-type nitride semiconductor 102, and at least one third barrier layer 103B3. In the embodiment illustrated in FIG. 1, the number of the third barrier layers 103B3 is exemplified by one, but the present invention does not limit the number of the third barrier layers 103B3. The opposite ends of the third barrier layer 103B3 are respectively sandwiched by the corresponding two well layers 103A. In other words, the plurality of well layers 103A and the respective plurality of barrier layers 103B are alternately arranged with each other. The first barrier layer 103B1 has a thickness of less than 100 Å. Specifically, the nitride semiconductor device 100 of the present embodiment may be a light emitting diode (LED) having a horizontal structure.
在一些實施例中，第二阻擋層103B2的厚度可以大於第一阻擋層103B1的厚度，但本發明不限於此。In some embodiments, the thickness of the second barrier layer 103B2 may be greater than the thickness of the first barrier layer 103B1, but the invention is not limited thereto.
在一些實施例中，第三阻擋層103B3的厚度可以大於第一阻擋層103B1的厚度，但本發明不限於此。In some embodiments, the thickness of the third barrier layer 103B3 may be greater than the thickness of the first barrier layer 103B1, but the invention is not limited thereto.
在一些實施例中，第一阻擋層103B1之厚度可以小於50埃(Å)，但本發明不限於此。In some embodiments, the thickness of the first barrier layer 103B1 may be less than 50 angstroms (Å), but the invention is not limited thereto.
在本實施例中，對於氮化物半導體元件100的氮化物半導體(例如可以包括：P型氮化物半導體101、N型氮化物半導體102及/或氮化物半導體量子井發光結構103)而言，前述得氮化物半導體可以包括氮化鎵(GaN)、氮化鋁(AlN)、氮化銦(InN)或為上述混晶的氮化鎵系化合物半導體(Inx Aly Ga1-x-y N，0≦x，0≦y，x+y≦1)。除此之外，亦可以在對上述的氮化物半導體進行IIIA族元素(例如：硼(B))或VA族元素(例如：磷(P)、砷(As))摻雜，以將一部分的氮置換，而形成氮化鎵系化合物的混晶(mixed crystal)。In the present embodiment, for the nitride semiconductor of the nitride semiconductor device 100 (for example, the P-type nitride semiconductor 101, the N-type nitride semiconductor 102, and/or the nitride semiconductor quantum well light-emitting structure 103 may be included), the foregoing The nitride semiconductor may include gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), or a gallium nitride compound semiconductor (In x Al y Ga 1-xy N, 0) ≦x,0≦y,x+y≦1). In addition, a group IIIA element (for example, boron (B)) or a group VA element (for example, phosphorus (P), arsenic (As)) may be doped to the above nitride semiconductor to have a part of The nitrogen is replaced to form a mixed crystal of a gallium nitride-based compound.
在本實施例中氮化物半導體量子井發光結構103可以具有多重量子井(multiple quantum well；MQW)構造或單一量子井(single quantum well；SQW)構造，於本發明不加以限制。在一些實施例中，可以是形成多重量子井構造，以可提升輸出或降低振盪臨界值。除此之外，可以將多個井層103A以及多個阻擋層103B交錯層疊交錯配置，以形成具有層疊結構(stacked structure)的量子井構造。此外，就前述的層疊構造而言，可以是將阻擋層103B夾入對應的兩個井層103A中，以形成層疊構造。In this embodiment, the nitride semiconductor quantum well light-emitting structure 103 may have a multiple quantum well (MQW) structure or a single quantum well (SQW) structure, which is not limited in the present invention. In some embodiments, multiple quantum well configurations may be formed to increase the output or reduce the oscillation threshold. In addition to this, a plurality of well layers 103A and a plurality of barrier layers 103B may be alternately stacked in a staggered configuration to form a quantum well structure having a stacked structure. Further, in the above-described laminated structure, the barrier layer 103B may be sandwiched between the corresponding two well layers 103A to form a laminated structure.
在單一量子井構造中，可以是在P型氮化物半導體101層的一側與N型氮化物半導體102層的一側分別具有至少一層阻擋層103B，以夾住井層103A。In a single quantum well configuration, at least one barrier layer 103B may be provided on one side of the P-type nitride semiconductor 101 layer and one side of the N-type nitride semiconductor 102 layer to sandwich the well layer 103A.
在多重量子井構造中，可以具有多個多個井層103A以及多個阻擋層103B，且多個井層103A以及多個阻擋層103B交錯層疊交錯配置，以夾住各個井層103A。In the multiple quantum well configuration, there may be a plurality of well layers 103A and a plurality of barrier layers 103B, and the plurality of well layers 103A and the plurality of barrier layers 103B are alternately stacked in a staggered configuration to sandwich the respective well layers 103A.
在其他實施例中，量子井構造也可以具有其他的形態，於本發明不加以限制。In other embodiments, the quantum well configuration may have other configurations, which are not limited in the present invention.
在一些實施例中，前述的多重量子井構造可以是在P型氮化物半導體101層的一側具有至少一層阻擋層103B(即，第一阻擋層103B1)，N型氮化物半導體102層的一側分別具有至少一層阻擋層103B(即，第二阻擋層103B2)，且第一阻擋層103B1以及第二阻擋層103B2之間具有至少一個阻擋層103B(即，第三阻擋層103B3)，以夾住多個井層103A。第一阻擋層103B1、第二阻擋層103B2以及第三阻擋層103B3分別為不同的膜層。換言之，氮化物半導體量子井發光結構103的相對的最外兩側可以分別為第一阻擋層103B1以及第二阻擋層103B2。In some embodiments, the foregoing multiple quantum well configuration may have at least one barrier layer 103B (ie, first barrier layer 103B1) on one side of the P-type nitride semiconductor 101 layer, and one of the N-type nitride semiconductor 102 layers. The sides respectively have at least one barrier layer 103B (ie, the second barrier layer 103B2), and at least one barrier layer 103B (ie, the third barrier layer 103B3) between the first barrier layer 103B1 and the second barrier layer 103B2 is sandwiched Live multiple layers 103A. The first barrier layer 103B1, the second barrier layer 103B2, and the third barrier layer 103B3 are respectively different film layers. In other words, the opposite outermost sides of the nitride semiconductor quantum well light emitting structure 103 may be the first barrier layer 103B1 and the second barrier layer 103B2, respectively.
除此之外，在多重量子井構造中，被不同的井層103A所夾入的阻擋層103B並不限於是一層(例如：第一井層103A/阻擋層103B/第二井層103A)。在一些實施例中，也可以於不同的井層103A之間，將兩層或兩層以上的多個阻擋層103B夾入(例如：第一井層103A/第一阻擋層103B1/第二阻擋層103B2/第二井層103A)，且前述多個阻擋層103B之間的成分或雜質摻雜量可以彼此不同。In addition, in the multiple quantum well configuration, the barrier layer 103B sandwiched by the different well layers 103A is not limited to being one layer (for example, the first well layer 103A/barrier layer 103B/second well layer 103A). In some embodiments, two or more layers of the plurality of barrier layers 103B may also be sandwiched between different well layers 103A (eg, first well layer 103A/first barrier layer 103B1/second barrier) The layer 103B2 / the second well layer 103A), and the composition or impurity doping amount between the foregoing plurality of barrier layers 103B may be different from each other.
在本實施例中，井層103A可以是含有銦的氮化物半導體層。舉例而言，井層103A的成分可以為Inα Ga1-α N(0＜α≦1)或InAlGaN。如此一來，可以形成具有良好發光或振盪的井層103A。另外，井層103A中銦的混晶比也可以使氮化物半導體量子井發光結構103具有對應的發光波長。在一些實施例中，井層103A的成分也可以為不含銦的氮化物半導體，例如：AlGaN、GaN等，於本發明不限於此。In the present embodiment, the well layer 103A may be a nitride semiconductor layer containing indium. For example, the composition of the well layer 103A may be In α Ga 1-α N (0<α≦1) or InAlGaN. As a result, the well layer 103A having good luminescence or oscillation can be formed. In addition, the mixed crystal ratio of indium in the well layer 103A may also cause the nitride semiconductor quantum well light-emitting structure 103 to have a corresponding light-emitting wavelength. In some embodiments, the composition of the well layer 103A may also be a nitride semiconductor containing no indium, such as AlGaN, GaN, etc., and the invention is not limited thereto.
本發明對於井層103A的膜厚及數量並不加以限制。在一些實施例中，井層103A的膜厚可以是10埃以上以及300埃以下的範圍。一般而言，井層103A的膜厚於20埃以上以及200埃以下的範圍內，可以降低氮化物半導體元件100的正向電壓(Forward Voltage；Vf)及/或臨界電流(Critical Current)的密度。The present invention does not limit the film thickness and number of the well layer 103A. In some embodiments, the film thickness of the well layer 103A may be in the range of 10 angstroms or more and 300 angstroms or less. In general, the film thickness of the well layer 103A is in the range of 20 angstroms or more and 200 angstroms or less, and the forward voltage (Vf) and/or the critical current density of the nitride semiconductor device 100 can be lowered. .
就製程而言，於長晶(crystal growth)的過程中，井層103A的膜厚於20埃以上可以提升膜層的均勻度(uniformity)，且井層103A的膜厚於200埃以下可以降低晶格缺陷(crystal defect)。並且，井層103A的數量可以是1以上。一般而言，若井層103A的數量為4以上時，則會對應的使氮化物半導體量子井發光結構103的各層的膜厚變厚，而進一步增加氮化物半導體量子井發光結構103的整體厚度，因而導致正向電壓上升。在一些實施例中，可以使井層103A的膜厚為100埃以下的範圍，因而可以進一步降低氮化物半導體量子井發光結構103的整體厚度。In the process of crystal growth, in the process of crystal growth, the film thickness of the well layer 103A is higher than 20 angstroms to increase the uniformity of the film layer, and the film thickness of the well layer 103A can be lowered below 200 angstroms. Crystal defect. Also, the number of well layers 103A may be 1 or more. In general, when the number of the well layers 103A is 4 or more, the film thickness of each layer of the nitride semiconductor quantum well light-emitting structure 103 is increased correspondingly, and the overall thickness of the nitride semiconductor quantum well light-emitting structure 103 is further increased. This causes the forward voltage to rise. In some embodiments, the film thickness of the well layer 103A may be made to be in the range of 100 angstroms or less, and thus the overall thickness of the nitride semiconductor quantum well light-emitting structure 103 may be further reduced.
於本發明中對於井層103A的摻雜並不加以限制。一般而言，若井層103A為含有銦的氮化物半導體，則若N型雜質的摻雜濃度增加，則可能會降低井層103A的有結晶性(crystallinity)。因此，可以降低井層103A的N型雜質的摻雜濃度，以提升井層103A的結晶性，而可以進一步提升氮化物半導體元件100的品質。The doping of the well layer 103A is not limited in the present invention. In general, if the well layer 103A is a nitride semiconductor containing indium, if the doping concentration of the N-type impurity is increased, the crystallinity of the well layer 103A may be lowered. Therefore, the doping concentration of the N-type impurity of the well layer 103A can be lowered to enhance the crystallinity of the well layer 103A, and the quality of the nitride semiconductor device 100 can be further improved.
舉例而言，在一般的半導體製程中，若N型雜質的摻雜濃度為5×1016 atoms/cm3 以下，則可以視為不具有N型雜質。除此之外，若N型雜質的摻雜濃度是在1×1018 atoms/cm3 以下以及5×1016 atoms/cm3 以上的範圍內，則可具有良好的結晶性且可以提升載子濃度(carrier concentration)，而可降低氮化物半導體元件100的正向電壓及/或臨界電流的密度。For example, in a general semiconductor process, if the doping concentration of the N-type impurity is 5 × 10 16 atoms/cm 3 or less, it can be considered that there is no N-type impurity. In addition, if the doping concentration of the N-type impurity is in the range of 1×10 18 atoms/cm 3 or less and 5×10 16 atoms/cm 3 or more, the crystallinity can be improved and the carrier can be lifted. The carrier concentration reduces the forward voltage and/or the critical current density of the nitride semiconductor device 100.
在一些實施例中，井層103A的N型雜質的摻雜濃度可以實質上小於或等於阻擋層103B的N型雜質的摻雜濃度。就製程上而言，相較於形成阻擋層103B的步驟，可以於形成井層103A的步驟中，摻入較少的N型雜質。或是，在形成阻擋層103B的步驟中摻入N型雜質，而在形成井層103A的步驟中不摻入N型雜質。如此一來，可以提升井層103A的發光再結合(radiative recombination)，而可進一步提升氮化物半導體元件100的發光效率。In some embodiments, the doping concentration of the N-type impurity of the well layer 103A may be substantially less than or equal to the doping concentration of the N-type impurity of the barrier layer 103B. In terms of the process, less N-type impurities may be incorporated in the step of forming the well layer 103A than the step of forming the barrier layer 103B. Alternatively, the N-type impurity is doped in the step of forming the barrier layer 103B, and the N-type impurity is not incorporated in the step of forming the well layer 103A. In this way, the light recombination of the well layer 103A can be improved, and the luminous efficiency of the nitride semiconductor device 100 can be further improved.
一般而言，上述的雜質方式的發光元件可以降低其正向電壓及/或臨界電流的密度而具有良好的品質。此時，也可以使井層103A、阻擋層103B以無摻雜生長而構成氮化物半導體量子井發光結構103的一部分。In general, the above-described impurity-type light-emitting element can have a good quality by reducing the density of its forward voltage and/or critical current. At this time, the well layer 103A and the barrier layer 103B may be formed as part of the nitride semiconductor quantum well light-emitting structure 103 without doping growth.
在一些實施例中，井層103A可以實質上不含N型雜質，而可以促進在井層103A內的載子再結合(recombination)，以提升井層103A的發光再結合，而可進一步提升氮化物半導體元件100的發光效率。換言之，若井層103A具有N型雜質，則由於井層103A的載子濃度較高，所以可能降低井層103A的發光再結合的機率，而使得在一定輸出下產生驅動電流(driving circuit)上升，而可能降低氮化物半導體元件100的可靠性(reliability)或元件壽命(life time)。因此，上述的雜質方式可以使井層103A的N型雜質濃度為1×1018 atoms/cm3 以下，而可得到可高輸出且穩定驅動的氮化物半導體元件100。一般而言，井層103A的N型雜質濃度可以是無摻雜或成為實質上不含N型雜質。In some embodiments, the well layer 103A may be substantially free of N-type impurities, and may facilitate carrier recombination within the well layer 103A to enhance luminescence recombination of the well layer 103A, thereby further enhancing nitrogen. The luminous efficiency of the semiconductor device 100. In other words, if the well layer 103A has an N-type impurity, since the carrier concentration of the well layer 103A is high, the probability of light-emitting recombination of the well layer 103A may be lowered, so that a driving circuit rises at a certain output, It is possible to reduce the reliability or life time of the nitride semiconductor device 100. Therefore, in the above-described impurity method, the N-type impurity concentration of the well layer 103A can be 1 × 10 18 atoms/cm 3 or less, and the nitride semiconductor device 100 which can be driven with high output and stably driven can be obtained. In general, the N-type impurity concentration of the well layer 103A may be undoped or substantially free of N-type impurities.
在氮化物半導體元件100作為雷射元件的使用方式之下，若井層103A具有N型雜質則可能會使雷射光的峰值波長的光譜寬度變寬，或使因為井層103A內的結晶性降低而降低雷射元件的元件壽命。因此，上述的雜質方式可以使井層103A的N型雜質濃度為1×1017 atoms/cm3 以提升氮化物半導體元件100的可靠性(reliability)或元件壽命(life time)。Under the use of the nitride semiconductor device 100 as a laser device, if the well layer 103A has an N-type impurity, the spectral width of the peak wavelength of the laser light may be broadened, or the crystallinity in the well layer 103A may be lowered. Reduce the component life of the laser component. Therefore, the above impurity method can make the N-type impurity concentration of the well layer 103A 1 × 10 17 atoms/cm 3 to improve the reliability or the life time of the nitride semiconductor device 100.
在本實施例中，相較於井層103A的銦混晶比，可以使阻擋層103B為具有較低銦混晶含銦氮化物半導體，但本發明不限於此。在一些實施例中，阻擋層103B也可以為含有氮化鎵、鋁的氮化物的半導體等。舉例而言，阻擋層103B的材質可以為Inβ Alγ Ga1- γ N(0≦β≦1，0≦γ≦1)、Inβ Ga1- β N(0≦β＜1，α＞β)、GaN或Alγ Ga1- γ N(0＜γ≦1)。In the present embodiment, the barrier layer 103B may have a lower indium mixed crystal indium-containing nitride semiconductor than the indium mixed crystal ratio of the well layer 103A, but the present invention is not limited thereto. In some embodiments, the barrier layer 103B may also be a semiconductor containing a nitride of gallium nitride, aluminum, or the like. For example, the material of the barrier layer 103B may be In β Al γ Ga 1- γ N(0≦β≦1, 0≦γ≦1), In β Ga 1- β N (0≦β<1, α> β), GaN or Al γ Ga 1- γ N (0<γ≦1).
值得注意的是，在作為最底層的阻擋層103B(如：下部阻擋層103B或第二阻擋層103B2)時，一般而言可以使用不含鋁的氮化物半導體。舉例而言，最底層的阻擋層103B(如：下部阻擋層103B或第二阻擋層103B2)的材質可以為Inβ Ga1- β N(0≦β＜1，α＞β)或GaN。如此一來，可以避免後續形成於其上且含有In氮化物的井層103A直接形成於含有鋁的氮化物半導體(如：Inβ Alγ Ga1- γ N或Alγ Ga1- γ N)上，而降低井層103A的結晶性。除此之外，可以使阻擋層103B的帶隙大於井層103A的帶隙，而可適宜地調整阻擋層103B及/或井層103A的組成成分。It is to be noted that, in the case of the lowermost barrier layer 103B (e.g., the lower barrier layer 103B or the second barrier layer 103B2), a nitride semiconductor containing no aluminum can be generally used. For example, the material of the bottommost barrier layer 103B (eg, the lower barrier layer 103B or the second barrier layer 103B2) may be In β Ga 1- β N (0≦β<1, α>β) or GaN. In this way, the well layer 103A formed thereon and containing the In nitride can be prevented from being directly formed on the nitride semiconductor containing aluminum (eg, In β Al γ Ga 1- γ N or Al γ Ga 1- γ N). Above, the crystallinity of the well layer 103A is lowered. In addition to this, the band gap of the barrier layer 103B may be made larger than the band gap of the well layer 103A, and the composition of the barrier layer 103B and/or the well layer 103A may be appropriately adjusted.
另外，除了上部阻擋層103B(即，較接近P型氮化物半導體101的阻擋層103B，例如為第一阻擋層103B1)之外，本發明對於其餘的阻擋層103B(如：第二阻擋層103B2及/或第三阻擋層103B3)的N型雜質的摻雜濃度並不加以限制。一般而言，具有N型雜質的阻擋層103B其N型雜質的摻雜濃度可以為5×1016 atoms/cm3 至1×1020 atoms /cm3 。In addition, the present invention is for the remaining barrier layer 103B (eg, the second barrier layer 103B2 except for the upper barrier layer 103B (ie, the barrier layer 103B closer to the P-type nitride semiconductor 101, such as the first barrier layer 103B1). The doping concentration of the N-type impurity of the third barrier layer 103B3) is not limited. In general, the barrier layer 103B having an N-type impurity may have a doping concentration of the N-type impurity of 5 × 10 16 atoms / cm 3 to 1 × 10 20 atoms / cm 3 .
在用於一般發光二極體的氮化物半導體元件100中，前述的N型雜質的摻雜濃度可以為5×1016 atoms /cm3 至2×1018 atoms /cm3 。並且，在用於高輸出發光二極體的氮化物半導體元件100中，前述的N型雜質的摻雜濃度可以為5×1017 atoms /cm3 至1×1020 atoms /cm3 ，且可以進一步為1×1018 atoms /cm3 至5×1019 atoms /cm3 。In the nitride semiconductor device 100 for a general light-emitting diode, the aforementioned N-type impurity may have a doping concentration of 5 × 10 16 atoms /cm 3 to 2 × 10 18 atoms / cm 3 . Further, in the nitride semiconductor device 100 for a high-output light-emitting diode, the aforementioned N-type impurity may have a doping concentration of 5 × 10 17 atoms /cm 3 to 1 × 10 20 atoms / cm 3 and may Further, it is 1 × 10 18 atoms / cm 3 to 5 × 10 19 atoms / cm 3 .
在阻擋層103B具有高濃度的N型雜質摻雜濃度時，可以使井層103A實質上為不具有N型雜質的摻雜。在用於不同的發光二極體的氮化物半導體元件100中，可以為了要提升驅動電流而得到高的輸出，而使的N型雜質的摻雜濃度增加，以進一步提升載子濃度。因此，在用於前述的一般發光二極體的氮化物半導體元件100中，可以在部分的第二阻擋層103B2及/或第三阻擋層103B3中摻雜入N型雜質，或是不摻雜入N型雜質，於本發明不加以限制。When the barrier layer 103B has a high concentration of the N-type impurity doping concentration, the well layer 103A can be made substantially doped without an N-type impurity. In the nitride semiconductor device 100 for different light-emitting diodes, a high output can be obtained in order to increase the driving current, and the doping concentration of the N-type impurity is increased to further increase the carrier concentration. Therefore, in the nitride semiconductor device 100 used for the foregoing general light-emitting diode, an N-type impurity may be doped in a portion of the second barrier layer 103B2 and/or the third barrier layer 103B3, or may be undoped. The N-type impurity is not limited in the present invention.
在本實施例中，阻擋層103B的膜厚可以小於或等於500埃，但本發明不限於此。在一些實施例中，阻擋層103B的膜厚與井層103A的膜厚可以基本上相同，也就是阻擋層103B的膜厚可以為10埃至300埃的範圍。In the present embodiment, the film thickness of the barrier layer 103B may be less than or equal to 500 angstroms, but the invention is not limited thereto. In some embodiments, the film thickness of the barrier layer 103B may be substantially the same as the film thickness of the well layer 103A, that is, the film thickness of the barrier layer 103B may range from 10 angstroms to 300 angstroms.
在一些實施例中，阻擋層103B也可以具有P型摻雜。就具有P型摻雜的阻擋層103B而言，其P型雜質的摻雜濃度可以為為5×1016 atoms /cm3 至1×1020 atoms /cm3 。在一些實施例中，前述的P型雜質的摻雜濃度可以為5×1016 atoms /cm3 至1×1018 atoms /cm3 。若前述的P型雜質的摻雜濃度超過1×1020 atoms /cm3 ，則即使增加p型雜質的摻雜濃度，載子濃度也幾乎不會變化，反而會因為過量的雜質而造成的結晶性惡化，而導致光的散射作用增加，而進一步降低氮化物半導體量子井發光結構103的發光效率。並且，若前述的P型雜質的摻雜濃度低於1×1018 atoms/cm3 ，則可抑制前述因為雜質增加所造成的發光效率降低的因素，並可以使氮化物半導體量子井發光結構103內的載子濃度穩定。此外，就P型雜質的摻雜量而言，一般而言至少會具有些微的P型雜質摻雜量。In some embodiments, the barrier layer 103B can also have a P-type doping. For the barrier layer 103B having a P-type doping, the doping concentration of the P-type impurity may be 5 × 10 16 atoms / cm 3 to 1 × 10 20 atoms / cm 3 . In some embodiments, the aforementioned P-type impurity may have a doping concentration of 5×10 16 atoms /cm 3 to 1×10 18 atoms /cm 3 . If the doping concentration of the aforementioned P-type impurity exceeds 1 × 10 20 atoms /cm 3 , even if the doping concentration of the p-type impurity is increased, the carrier concentration hardly changes, but crystals due to excessive impurities are caused. The deterioration of the property causes an increase in the scattering effect of light, and further reduces the luminous efficiency of the nitride semiconductor quantum well light-emitting structure 103. Further, if the doping concentration of the P-type impurity is less than 1 × 10 18 atoms/cm 3 , the above-described factor of deterioration in luminous efficiency due to an increase in impurities can be suppressed, and the nitride semiconductor quantum well light-emitting structure 103 can be made. The concentration of the carrier inside is stable. Further, in terms of the doping amount of the P-type impurity, generally, there is at least a slight amount of P-type impurity doping.
在本實施例中，P型氮化物半導體101位置的阻擋層103B(即，第一阻擋層103B1)可以無摻雜N型雜質、實質上無摻雜(即，雜質濃度小於5×1016 atoms/cm3 )N型雜質或摻雜P型雜質，且第一阻擋層103B1的厚度小於100埃。如此一來，可以提升來自於P型氮化物半導體101的載子注入效率(injection efficiency)，而可進一步提升氮化物半導體元件100的發光效率。In the present embodiment, the barrier layer 103B at the position of the P-type nitride semiconductor 101 (ie, the first barrier layer 103B1) may be undoped with N-type impurities and substantially undoped (ie, the impurity concentration is less than 5×10 16 atoms). /cm 3 ) N-type impurity or doped P-type impurity, and the thickness of the first barrier layer 103B1 is less than 100 angstroms. As a result, the implantation efficiency from the P-type nitride semiconductor 101 can be improved, and the luminous efficiency of the nitride semiconductor device 100 can be further improved.
在一些實施例中，P型氮化物半導體101可以包括P側應力釋放層101A、高濃度電洞層101B、電子阻擋層101C以及P型歐姆接觸層101D，且自第一阻擋層103B1向遠離於第一阻擋層103B1的方向上依序為P側應力釋放層101A、高濃度電洞層101B、電子阻擋層101C以及P型歐姆接觸層101D。In some embodiments, the P-type nitride semiconductor 101 may include a P-side stress releasing layer 101A, a high-concentration hole layer 101B, an electron blocking layer 101C, and a P-type ohmic contact layer 101D, and is away from the first barrier layer 103B1. The direction of the first barrier layer 103B1 is, in order, the P-side stress releasing layer 101A, the high-concentration hole layer 101B, the electron blocking layer 101C, and the P-type ohmic contact layer 101D.
P側應力釋放層101A可以為超晶格(super lattice)結構。超晶格結構的材料可以包含氮化鋁鎵(AlGaN)以及氮化鎵(GaN)所構成的超晶格結構，或是由氮化鋁鎵(Alx GaN)以及氮化鋁鎵(Aly GaN)所構成的超晶格結構，或是由氮化鋁鎵(AlGaN)以及氮化鋁銦鎵(InAlGaN)所構成的超晶格結構，於本發明不加以限制。除此之外，前述的超晶格結構的對數可以小於20對，但本發明不限於此。在一些實施例中，前述的超晶格結構的對數也可以小於10對。The P-side stress relief layer 101A may be a super lattice structure. The superlattice structure material may include a superlattice structure composed of aluminum gallium nitride (AlGaN) and gallium nitride (GaN), or aluminum gallium nitride (Al x GaN) and aluminum gallium nitride (Al y) The superlattice structure composed of GaN) or a superlattice structure composed of aluminum gallium nitride (AlGaN) and aluminum indium gallium nitride (InAlGaN) is not limited in the present invention. In addition to this, the logarithm of the aforementioned superlattice structure may be less than 20 pairs, but the invention is not limited thereto. In some embodiments, the aforementioned superlattice structure may also have a logarithm of less than 10 pairs.
高濃度電洞層101B可以由氮化鎵(GaN)或是氮化鋁鎵(AlGaN)所構成，高濃度電洞層101B的鎂摻雜濃度(concentration)高於P側應力釋放層101A的鎂摻雜濃度以及電子阻擋層101C的鎂摻雜濃度。舉例而言，高濃度電洞層101B的鎂(Mg)摻雜濃度可以高於1x1019 (Atoms/cm3 )。The high concentration hole layer 101B may be composed of gallium nitride (GaN) or aluminum gallium nitride (AlGaN), and the magnesium concentration of the high concentration hole layer 101B is higher than that of the P side stress release layer 101A. The doping concentration and the magnesium doping concentration of the electron blocking layer 101C. For example, the high concentration hole layer 101B may have a magnesium (Mg) doping concentration higher than 1×10 19 (Atoms/cm 3 ).
電子阻擋層101C可以由氮化鋁鎵(AlGaN)所構成，電子阻擋層101C的鋁成份百分比高於P側應力釋放層101A的鋁成份百分比以及高於高濃度電洞層101B的鋁成份百分比。在一些實施例中，高濃度電洞層101B的鋁成份百分比低於電子阻擋層101C的鋁成份百分比，但本發明不限於此。The electron blocking layer 101C may be composed of aluminum gallium nitride (AlGaN), and the aluminum component percentage of the electron blocking layer 101C is higher than the aluminum component percentage of the P side stress releasing layer 101A and the aluminum component percentage higher than the high concentration hole layer 101B. In some embodiments, the aluminum component percentage of the high concentration hole layer 101B is lower than the aluminum component percentage of the electron blocking layer 101C, but the invention is not limited thereto.
P型歐姆接觸層101D可以由氮化鎵(GaN)所構成，P型歐姆接觸層101D的鎂摻雜濃度高於電子阻擋層101C的鎂摻雜濃度。The P-type ohmic contact layer 101D may be composed of gallium nitride (GaN), and the magnesium doping concentration of the P-type ohmic contact layer 101D is higher than the magnesium doping concentration of the electron blocking layer 101C.
在一些實施例中，N型氮化物半導體102可以包括N側第一應力釋放層102A、N側第二應力釋放層102B、低濃度電子層102C以及N型歐姆接觸層102D。且自第二阻擋層103B2向遠離於第二阻擋層103B2的方向上依序為N側第一應力釋放層102A、N側第二應力釋放層102B、低濃度電子層102C以及N型歐姆接觸層102D。In some embodiments, the N-type nitride semiconductor 102 may include an N-side first stress relief layer 102A, an N-side second stress relief layer 102B, a low concentration electron layer 102C, and an N-type ohmic contact layer 102D. And from the second barrier layer 103B2 in a direction away from the second barrier layer 103B2, the N-side first stress relief layer 102A, the N-side second stress release layer 102B, the low-concentration electron layer 102C, and the N-type ohmic contact layer. 102D.
N側第一應力釋放層102A及/或N側第二應力釋放層102B可以為超晶格結構可以為超晶格(super lattice)結構。超晶格結構的材料可以包含氮化鋁鎵(AlGaN)以及氮化鎵(GaN)所構成的超晶格結構，或是由氮化鋁鎵(Alx GaN)以及氮化鋁鎵(Aly GaN)所構成的超晶格結構，或是由氮化鋁鎵(AlGaN)以及氮化鋁銦鎵(InAlGaN)所構成的超晶格結構，於本發明不加以限制。除此之外，前述的超晶格結構的對數可以小於20對，但本發明不限於此。在一些實施例中，前述的超晶格結構的對數也可以小於10對。The N-side first stress relief layer 102A and/or the N-side second stress relief layer 102B may be a superlattice structure which may be a super lattice structure. The superlattice structure material may include a superlattice structure composed of aluminum gallium nitride (AlGaN) and gallium nitride (GaN), or aluminum gallium nitride (Al x GaN) and aluminum gallium nitride (Al y) The superlattice structure composed of GaN) or a superlattice structure composed of aluminum gallium nitride (AlGaN) and aluminum indium gallium nitride (InAlGaN) is not limited in the present invention. In addition to this, the logarithm of the aforementioned superlattice structure may be less than 20 pairs, but the invention is not limited thereto. In some embodiments, the aforementioned superlattice structure may also have a logarithm of less than 10 pairs.
N側第一應力釋放層102A的銦(Indium)成份百分比高於N側第二應力釋放層102B的銦成份百分比。The percentage of the indium component of the N-side first stress-relieving layer 102A is higher than the percentage of the indium component of the N-side second stress-relieving layer 102B.
低濃度電子層102C可以由氮化鎵(GaN)、氮化銦鎵(InGaN)或是氮化鋁鎵(AlGaN)所構成。在一些實施例中，低濃度電子層102C的矽摻雜濃度低於N型歐姆接觸層102D的矽摻雜濃度，但本發明不限於此。舉例而言，低濃度電子層102C的矽(Si)摻雜濃度可以低於1x1018 (Atoms/cm3 )。The low concentration electron layer 102C may be composed of gallium nitride (GaN), indium gallium nitride (InGaN), or aluminum gallium nitride (AlGaN). In some embodiments, the germanium doping concentration of the low concentration electron layer 102C is lower than the germanium doping concentration of the n-type ohmic contact layer 102D, but the invention is not limited thereto. For example, the low concentration electron layer 102C may have a cerium (Si) doping concentration of less than 1 x 10 18 (Atoms/cm 3 ).
N型歐姆接觸層102D可以由氮化鎵(GaN) 、氮化銦鎵(InGaN)或是氮化鋁鎵(AlGaN)所構成。在一些實施例中，N型歐姆接觸層102D的矽摻雜濃度高於N側第一應力釋放層102A、N側第二應力釋放層102B以及低濃度電子層102C，但本發明不限於此。The N-type ohmic contact layer 102D may be composed of gallium nitride (GaN), indium gallium nitride (InGaN), or aluminum gallium nitride (AlGaN). In some embodiments, the erbium doping concentration of the N-type ohmic contact layer 102D is higher than the N-side first stress-relieving layer 102A, the N-side second stress-relieving layer 102B, and the low-concentration electron layer 102C, but the invention is not limited thereto.
基板104的材質可以包含III-V族(例如：GaN)、IV族(例如：Si)、II-VI族(例如：CdS、CdTe、ZnS)的元素與合金、氧化鋅(ZnO)、尖晶石(spinel)、氮化鎵(GaN) 、藍寶石(sapphire)或矽(Si)。The material of the substrate 104 may include elements and alloys of group III-V (for example, GaN), group IV (for example, Si), group II-VI (for example, CdS, CdTe, ZnS), zinc oxide (ZnO), and spinel. Spirel, gallium nitride (GaN), sapphire or bismuth (Si).
基板104的第一面104A包括成長表面104A1以及多個位於該成長表面104A1上的微結構104A2。在一些實施例中，微結構104A2具有非圓滑之蝕刻側面。舉例而言，成長表面104A1的表面粗糙度可以低於10埃(Å)，或是微結構104A2的表面粗糙度低於10埃(Å)。在一些實施例中，基板104的第二面104B的粗糙度大於成長表面104A1的粗糙度以及微結構104A2的表面粗糙度。The first side 104A of the substrate 104 includes a growth surface 104A1 and a plurality of microstructures 104A2 located on the growth surface 104A1. In some embodiments, microstructures 104A2 have non-smooth etched sides. For example, the surface roughness of the growth surface 104A1 may be less than 10 angstroms (Å), or the surface roughness of the microstructure 104A2 may be less than 10 angstroms (Å). In some embodiments, the roughness of the second face 104B of the substrate 104 is greater than the roughness of the growth surface 104A1 and the surface roughness of the microstructure 104A2.
在一些實施例中，微結構104A2可以為週期性的突出結構，且前數週期性的突出結構可以具有對應的高度104D、寬度104E以及底面間距104F。高度104D可以介於1微米至3微米之間。寬度104E介於1微米至3微米之間。底面間距104F介於0.1微米至3微米之間。In some embodiments, the microstructures 104A2 can be periodic protruding structures, and the pre-periodic protruding structures can have corresponding heights 104D, widths 104E, and bottom surface spacings 104F. Height 104D can be between 1 micron and 3 microns. The width 104E is between 1 micron and 3 microns. The bottom surface spacing 104F is between 0.1 microns and 3 microns.
舉例而言，微結構104A2的外型可以為半球體(hemisphere)、錐體(cone)、截頭錐體(truncated-cone)、金字塔(pyramid)、截頭金字塔(truncated-pyramid)、方柱(square pillar)、圓桶(cylinder)或其他適宜的週期性突出結構104C，於本發明不加以限制。For example, the microstructure of the microstructure 104A2 may be a hemisphere, a cone, a truncated-cone, a pyramid, a truncated-pyramid, a square pillar. (square pillar), cylinder or other suitable periodic protruding structure 104C, which is not limited in the present invention.
在一些實施例中，緩衝層105可以包括第一緩衝層105A以及第二緩衝層105B。第一緩衝層105A可以與微結構104A2共形設置(conformal)。第二緩衝層105B位於第一緩衝層105A上，且第二緩衝層105B相對於第一緩衝層105A的一面可以為一平坦面，以使後續形成的膜層(如：N型歐姆接觸層102D)可以位於第二緩衝層105B的平坦面上。In some embodiments, the buffer layer 105 can include a first buffer layer 105A and a second buffer layer 105B. The first buffer layer 105A can be conformally formed with the microstructures 104A2. The second buffer layer 105B is located on the first buffer layer 105A, and the second buffer layer 105B may be a flat surface with respect to one surface of the first buffer layer 105A, so as to form a subsequently formed film layer (eg, an N-type ohmic contact layer 102D). ) may be located on a flat surface of the second buffer layer 105B.
在本實施例中，氮化物半導體元件100可以更包括平台結構106、N型電極107、電流阻擋層108、透明導電層109、P型電極110、絕緣層111以及高反射絕緣層112。平台結構106露出部分的N型歐姆接觸層102D。N型電極107與N型歐姆接觸層102D電性連接。電流阻擋層108與P型歐姆接觸層101D直接接觸。透明導電層109覆蓋電流阻擋層108且與P型歐姆接觸層101D直接接觸。P型電極110位於透明導電層109之上方，並藉由透明導電層109以與P型歐姆接觸層101D電性連接。絕緣層111覆蓋N型電極107、P型電極110以及平台結構106的側壁。高反射絕緣層112位於基板104的第二面104B。In the present embodiment, the nitride semiconductor device 100 may further include a terrace structure 106, an N-type electrode 107, a current blocking layer 108, a transparent conductive layer 109, a P-type electrode 110, an insulating layer 111, and a highly reflective insulating layer 112. The platform structure 106 exposes a portion of the N-type ohmic contact layer 102D. The N-type electrode 107 is electrically connected to the N-type ohmic contact layer 102D. The current blocking layer 108 is in direct contact with the P-type ohmic contact layer 101D. The transparent conductive layer 109 covers the current blocking layer 108 and is in direct contact with the P-type ohmic contact layer 101D. The P-type electrode 110 is located above the transparent conductive layer 109 and is electrically connected to the P-type ohmic contact layer 101D by the transparent conductive layer 109. The insulating layer 111 covers the N-type electrode 107, the P-type electrode 110, and the sidewall of the land structure 106. The highly reflective insulating layer 112 is located on the second side 104B of the substrate 104.
在一些實施例中，高反射絕緣層112可以由多個介電材料對(pair)所組成。前述的多個介電材料對可以包括多個第一介電對112A以及多個第二介電對112B。第一介電對112A及/或第二介電對112B可以包括第一材料層112C以及第二材料層112D，其中第一材料層112C的介電係數大於第二材料層112D的介電係數。In some embodiments, the highly reflective insulating layer 112 can be comprised of a plurality of pairs of dielectric materials. The plurality of dielectric material pairs described above may include a plurality of first dielectric pairs 112A and a plurality of second dielectric pairs 112B. The first dielectric pair 112A and/or the second dielectric pair 112B can include a first material layer 112C and a second material layer 112D, wherein the dielectric constant of the first material layer 112C is greater than the dielectric constant of the second material layer 112D.
在一些實施例中，第一材料層112C及/或第二材料層112D的光學厚度小於四方之一的波長(波長/4)，且前述的波長基本上為氮化物半導體量子井發光結構103所發出之光的波長。In some embodiments, the optical thickness of the first material layer 112C and/or the second material layer 112D is less than a wavelength of one of the squares (wavelength / 4), and the aforementioned wavelength is substantially the nitride semiconductor quantum well light emitting structure 103 The wavelength of the emitted light.
在一些實施例中，高反射絕緣層112的材料可以包括氧化物、氮化物、及/或至少包含矽(Si)、鈦(Ti)、鋯(Zr)、鈮(Nb)、鉭(Ta)或鋁(Al)元素所組成的氧化物或氮化物，於本發明不限於此。In some embodiments, the material of the highly reflective insulating layer 112 may include an oxide, a nitride, and/or at least bismuth (Si), titanium (Ti), zirconium (Zr), niobium (Nb), tantalum (Ta). An oxide or a nitride composed of an aluminum (Al) element is not limited thereto.
在一些實施例中，透明導電層109的材料可以包括銦錫氧化物(Indium Tin Oxide；ITO)、銦鋅氧化物(indium zinc oxide；IZO)、氧化鋅（Zinc Oxide；ZnO）或氧化鋅鋁(Aluminum Zinc Oxide；AZO)，於本發明不限於此。In some embodiments, the material of the transparent conductive layer 109 may include Indium Tin Oxide (ITO), indium zinc oxide (IZO), zinc oxide (Zinc Oxide; ZnO), or zinc aluminum oxide. (Aluminum Zinc Oxide; AZO), the invention is not limited thereto.
在一些實施例中，絕緣層111的材料可以包括氧化矽(SiOX )、氮化矽(SiNX )、聚醯亞胺(Polyimide)、或其他高分子材料，於本發明不限於此。In some embodiments, the material of the insulating layer 111 may comprise silicon oxide (SiO X), silicon nitride (SiN X), polyimide (Polyimide), or other polymer material, the present invention is not limited thereto.
在一些實施例中，N型電極107及/或P型電極110的材料可以包括銀(Ag)、鋁(Al)、鎳(Ni)、銠(Rh)、金(Au)、銅(Cu)、鈦(Ti)、鉑(Pt)、鈀(Pd)、鉬(Mo)、鉻(Cr)、鎢(W)、其他適宜的金屬及/或上述金屬之合金，於本發明不限於此。In some embodiments, the material of the N-type electrode 107 and/or the P-type electrode 110 may include silver (Ag), aluminum (Al), nickel (Ni), rhenium (Rh), gold (Au), copper (Cu). Titanium (Ti), platinum (Pt), palladium (Pd), molybdenum (Mo), chromium (Cr), tungsten (W), other suitable metals, and/or alloys of the above metals are not limited thereto.
圖2是依照本發明的第二實施例的一種氮化物半導體元件200的剖面示意圖。第二實施例的氮化物半導體元件200與圖1的氮化物半導體元件100類似，本實施例採用圖2針對氮化物半導體元件200進行描述。值得注意的是，在圖2中，相同或相似的標號表示相同或相似的構件，故針對圖1中說明過的構件於此不再贅述。2 is a schematic cross-sectional view of a nitride semiconductor device 200 in accordance with a second embodiment of the present invention. The nitride semiconductor device 200 of the second embodiment is similar to the nitride semiconductor device 100 of FIG. 1, and the present embodiment is described with respect to the nitride semiconductor device 200 using FIG. It is noted that in FIG. 2, the same or similar reference numerals denote the same or similar components, and thus the components described in FIG. 1 will not be described again.
請參照圖2，第二實施例的氮化物半導體元件200與圖1的氮化物半導體元件100類似，兩者的差異在於：本實施例的氮化物半導體元件200更包括P型高反射歐姆電極225、第一焊接金屬層221、第二焊接金屬層222、接合基板223以及基板電極224。在本實施例中，高反射絕緣層212的組成可以類似於前述實施例(如：第一實施例)的高反射絕緣層112。P型高反射歐姆電極225覆蓋於高反射絕緣層212以及P型氮化物半導體101上，並且與P型氮化物半導體101電性連接。第一焊接金屬層221覆蓋於P型高反射歐姆電極225上，並且與P型氮化物半導體101電性連接。第二焊接金屬層222覆蓋於第一焊接金屬層221上，並且與P型氮化物半導體101電性連接。接合基板223覆蓋於第二焊接金屬層222上，並且與P型氮化物半導體101電性連接。基板電極224覆蓋於接合基板223上，並且與P型氮化物半導體101電性連接。具體而言，本實施例的氮化物半導體元件100可以為具有垂直(vertical)結構的發光二極體元件。Referring to FIG. 2, the nitride semiconductor device 200 of the second embodiment is similar to the nitride semiconductor device 100 of FIG. 1, and the difference is that the nitride semiconductor device 200 of the present embodiment further includes a P-type high reflection ohmic electrode 225. The first solder metal layer 221, the second solder metal layer 222, the bonding substrate 223, and the substrate electrode 224. In the present embodiment, the composition of the highly reflective insulating layer 212 may be similar to the highly reflective insulating layer 112 of the foregoing embodiment (e.g., the first embodiment). The P-type high reflection ohmic electrode 225 covers the high reflection insulating layer 212 and the P type nitride semiconductor 101, and is electrically connected to the P type nitride semiconductor 101. The first solder metal layer 221 covers the P-type high reflection ohmic electrode 225 and is electrically connected to the P-type nitride semiconductor 101. The second solder metal layer 222 covers the first solder metal layer 221 and is electrically connected to the P-type nitride semiconductor 101. The bonding substrate 223 covers the second solder metal layer 222 and is electrically connected to the P-type nitride semiconductor 101. The substrate electrode 224 is overlaid on the bonding substrate 223 and electrically connected to the P-type nitride semiconductor 101. Specifically, the nitride semiconductor device 100 of the present embodiment may be a light emitting diode element having a vertical structure.
在一些實施例中，P型高反射歐姆電極225以及基板電極224的材料可以類似於N型電極107及/或前述實施例的P型電極110的材料，於本發明不限於此。In some embodiments, the material of the P-type highly reflective ohmic electrode 225 and the substrate electrode 224 may be similar to the material of the N-type electrode 107 and/or the P-type electrode 110 of the foregoing embodiment, and the invention is not limited thereto.
在一些實施例中，第一焊接金屬層221及/或第二焊接金屬層222的材料可以包括銀(Ag)、鋁(Al)、鎳(Ni)、銠(Rh)、金(Au)、銅(Cu)、鈦(Ti)、鉑(Pt)、鈀(Pd)、鉬(Mo)、鉻(Cr)、鎢(W)、錫(Sn)其他適宜的金屬及/或上述金屬之合金，於本發明不限於此。In some embodiments, the material of the first solder metal layer 221 and/or the second solder metal layer 222 may include silver (Ag), aluminum (Al), nickel (Ni), rhenium (Rh), gold (Au), Copper (Cu), titanium (Ti), platinum (Pt), palladium (Pd), molybdenum (Mo), chromium (Cr), tungsten (W), tin (Sn) other suitable metals and / or alloys of the above metals The invention is not limited thereto.
圖3是依照本發明的第三實施例的一種氮化物半導體元件300的剖面示意圖。第三實施例的氮化物半導體元件300與圖1的氮化物半導體元件100類似，本實施例採用圖3針對氮化物半導體元件300進行描述。值得注意的是，在圖3中，相同或相似的標號表示相同或相似的構件，故針對圖1中說明過的構件於此不再贅述。3 is a cross-sectional view of a nitride semiconductor device 300 in accordance with a third embodiment of the present invention. The nitride semiconductor device 300 of the third embodiment is similar to the nitride semiconductor device 100 of FIG. 1, and the present embodiment is described with respect to the nitride semiconductor device 300 using FIG. It is to be noted that in FIG. 3, the same or similar reference numerals denote the same or similar components, and thus the components described in FIG. 1 will not be described again.
請參照圖3，第三實施例的氮化物半導體元件300與圖1的氮化物半導體元件100類似，兩者的差異在於：本實施例的氮化物半導體元件100更包括第一銲墊層321、第二銲墊層322、第一連接電極323以及第二連接電極324。在本實施例中，高反射絕緣層312的組成可以類似於前述實施例(如：第一實施例)的高反射絕緣層112。第一銲墊層321與N型電極107電性連接。第二銲墊層322與P型電極110電性連接。第一連接電極323與第一銲墊層321電性連接。第二連接電極324與第二銲墊層322電性連接。具體而言，本實施例的氮化物半導體元件300可以為具有覆晶(flip chip)結構的發光二極體元件。Referring to FIG. 3, the nitride semiconductor device 300 of the third embodiment is similar to the nitride semiconductor device 100 of FIG. 1 , and the difference is that the nitride semiconductor device 100 of the present embodiment further includes a first pad layer 321 . The second pad layer 322, the first connection electrode 323, and the second connection electrode 324. In the present embodiment, the composition of the highly reflective insulating layer 312 may be similar to the highly reflective insulating layer 112 of the foregoing embodiment (e.g., the first embodiment). The first pad layer 321 is electrically connected to the N-type electrode 107. The second pad layer 322 is electrically connected to the P-type electrode 110. The first connection electrode 323 is electrically connected to the first pad layer 321 . The second connection electrode 324 is electrically connected to the second pad layer 322 . Specifically, the nitride semiconductor device 300 of the present embodiment may be a light emitting diode element having a flip chip structure.
在一些實施例中，第一連接電極323以及第二連接電極324可以分別電性連接至電路板319上的不同端點。In some embodiments, the first connection electrode 323 and the second connection electrode 324 can be electrically connected to different end points on the circuit board 319, respectively.
圖4是依照本發明的第四實施例的一種氮化物半導體元件400的剖面示意圖。第四實施例的氮化物半導體元件400與圖1的氮化物半導體元件100類似，本實施例採用圖4針對氮化物半導體元件400進行描述。值得注意的是，在圖4中，相同或相似的標號表示相同或相似的構件，故針對圖1中說明過的構件於此不再贅述。4 is a cross-sectional view showing a nitride semiconductor device 400 in accordance with a fourth embodiment of the present invention. The nitride semiconductor device 400 of the fourth embodiment is similar to the nitride semiconductor device 100 of FIG. 1, and the present embodiment is described with respect to the nitride semiconductor device 400 using FIG. It is noted that in FIG. 4, the same or similar reference numerals denote the same or similar components, and thus the components described in FIG. 1 will not be described again.
請參照圖4，第四實施例的氮化物半導體元件400與圖1的氮化物半導體元件100類似，兩者的差異在於：本實施例的氮化物半導體元件400更包括穿隧接面(Tunnel Junction)470以及第二N型氮化物半導體452。穿隧接面470包括重摻雜P型(P+)氮化物半導體401D以及重摻雜N型(N+)氮化物半導體451，或是由重摻雜P型(P+)氮化物半導體401D以及重摻雜N型(N+)氮化物半導體451所形成的接面。重摻雜P型氮化物半導體401D設置於氮化物半導體量子井發光結構103上。重摻雜N型氮化物半導體451設置於重摻雜P型氮化物半導體401D上。第二N型氮化物半導體452設置於穿隧接面470的重摻雜N型氮化物半導體451上。Referring to FIG. 4, the nitride semiconductor device 400 of the fourth embodiment is similar to the nitride semiconductor device 100 of FIG. 1, and the difference is that the nitride semiconductor device 400 of the present embodiment further includes a tunnel junction (Tunnel Junction). And a second N-type nitride semiconductor 452. The tunneling junction 470 includes a heavily doped P-type (P+) nitride semiconductor 401D and a heavily doped N-type (N+) nitride semiconductor 451, or a heavily doped P-type (P+) nitride semiconductor 401D and heavily doped A junction formed by a hetero-N-type (N+) nitride semiconductor 451. The heavily doped P-type nitride semiconductor 401D is disposed on the nitride semiconductor quantum well light-emitting structure 103. The heavily doped N-type nitride semiconductor 451 is disposed on the heavily doped P-type nitride semiconductor 401D. The second N-type nitride semiconductor 452 is disposed on the heavily doped N-type nitride semiconductor 451 of the tunnel junction 470.
在一些實施例中，重摻雜N型氮化物半導體451的能隙(Energy Bandgap)大於氮化物半導體量子井發光結構103的能隙。如此一來，重摻雜N型氮化物半導體451基本上可以不吸收氮化物半導體量子井發光結構103所發出光線。In some embodiments, the energy bandgap of the heavily doped N-type nitride semiconductor 451 is greater than the energy gap of the nitride semiconductor quantum well emitting structure 103. As such, the heavily doped N-type nitride semiconductor 451 may substantially not absorb the light emitted by the nitride semiconductor quantum well light-emitting structure 103.
在一些實施例中，重摻雜P型氮化物半導體層401D的成分或形成方式可以類似於P型歐姆接觸層101D。也就是說，重摻雜P型氮化物半導體層401D可以與P側應力釋放層101A、高濃度電洞層101B以及電子阻擋層101C構成P型氮化物半導體101。In some embodiments, the composition or formation of the heavily doped P-type nitride semiconductor layer 401D may be similar to the P-type ohmic contact layer 101D. That is, the heavily doped P-type nitride semiconductor layer 401D may constitute the P-type nitride semiconductor 101 with the P-side stress releasing layer 101A, the high-concentration hole layer 101B, and the electron blocking layer 101C.
在一些實施例中，重摻雜P型氮化物半導體層401D的能隙(Energy Bandgap)可以是越靠近P型氮化物半導體101越高，且重摻雜P型氮化物半導體層401D的厚度可以介於1奈米(namometer；nm)至100nm之間，但本發明不限於此。In some embodiments, the energy bandgap of the heavily doped P-type nitride semiconductor layer 401D may be higher toward the P-type nitride semiconductor 101, and the thickness of the heavily doped P-type nitride semiconductor layer 401D may be It is between 1 nm (nm) and 100 nm, but the invention is not limited thereto.
在一些實施例中，重摻雜N型氮化物半導體451的能隙可以是越靠近N型氮化物半導體102越高，且重摻雜N型氮化物半導體451的厚度可以介於1奈米nm至100nm之間，但本發明不限於此。In some embodiments, the energy gap of the heavily doped N-type nitride semiconductor 451 may be higher toward the N-type nitride semiconductor 102, and the thickness of the heavily doped N-type nitride semiconductor 451 may be between 1 nm nm. It is between 100 nm, but the invention is not limited thereto.
在一些實施例中，第一N型氮化物半導體102及/或第二N型氮化物半導體452可以具有粗糙表面，以提升氮化物半導體元件400之出光效果。In some embodiments, the first N-type nitride semiconductor 102 and/or the second N-type nitride semiconductor 452 may have a rough surface to enhance the light-emitting effect of the nitride semiconductor device 400.
在一些實施例中，穿隧接面470可以更包括設置於重摻雜P型氮化物半導體401D以及重摻雜N型氮化物半導體451之間的中間半導體(未繪示)。中間半導體可以具有內部帶穿隧阻擋層(inter band tunnel barrier)，重摻雜P型氮化物半導體401D可以具有P型空乏阻擋層(P-depletion barrier)，重摻雜N型氮化物半導體451可以具有N型空乏阻擋層(N-depletion barrier)。如此一來，中間半導體相對於重摻雜P型氮化物半導體401D以及重摻雜N型氮化物半導體451形成異質接面(heterojunction)，以於重摻雜P型氮化物半導體401D以及重摻雜N型氮化物半導體451之間形成極化場(polarization field)，而使重摻雜P型氮化物半導體401D的價帶以及該重摻雜N型氮化物半導體451的導帶可以彼此相互對應。In some embodiments, the tunnel junction 470 may further include an intermediate semiconductor (not shown) disposed between the heavily doped P-type nitride semiconductor 401D and the heavily doped N-type nitride semiconductor 451. The intermediate semiconductor may have an internal band gap barrier, and the heavily doped P-type nitride semiconductor 401D may have a P-depletion barrier, and the heavily doped N-type nitride semiconductor 451 may It has an N-depletion barrier. As a result, the intermediate semiconductor forms a heterojunction with respect to the heavily doped P-type nitride semiconductor 401D and the heavily doped N-type nitride semiconductor 451 to heavily dope the P-type nitride semiconductor 401D and heavily doped A polarization field is formed between the N-type nitride semiconductors 451, and the valence bands of the heavily doped P-type nitride semiconductor 401D and the conduction bands of the heavily doped N-type nitride semiconductor 451 may correspond to each other.
在一些實施例中，中間半導體的材料可以包含氮化鋁鎵(AlGaN)、氮化鎵(GaN)、氮化銦鎵(InGaN)或氮化銦鋁鎵(InAlGaN)。並且，中間半導體之厚度約為0.5nm～10nm，但本發明不限於此。In some embodiments, the material of the intermediate semiconductor may comprise aluminum gallium nitride (AlGaN), gallium nitride (GaN), indium gallium nitride (InGaN), or indium aluminum gallium nitride (InAlGaN). Further, the thickness of the intermediate semiconductor is about 0.5 nm to 10 nm, but the present invention is not limited thereto.
在一些實施例中，中間半導體具有一側面材料能隙波動(lateral material energy bandgap fluctuation)，其包含多個低能隙及高能隙區域(low bandgap and high bandgap regions)。In some embodiments, the intermediate semiconductor has a lateral material energy bandgap, which includes a plurality of low bandgap and high band gap regions.
在一些實施例中，若氮化物半導體元件400具有穿隧接面470的結構，則可以省略之後電流阻擋層(Current Blocking Layer, CBL)及透明導電層(Transparent Conductive Layer, TCL)的結構及製程，一樣可以達到電流均勻分佈以及發光效率提昇的效果。In some embodiments, if the nitride semiconductor device 400 has a tunneling junction 470 structure, the structure and process of the Current Blocking Layer (CBL) and the Transparent Conductive Layer (TCL) may be omitted. In the same way, the uniform distribution of current and the improvement of luminous efficiency can be achieved.
圖5是依照本發明的第五實施例的一種氮化物半導體元件500的剖面示意圖。第五實施例的氮化物半導體元件500與圖2的氮化物半導體元件200類似，本實施例採用圖5針對氮化物半導體元件500進行描述。值得注意的是，在圖5中，相同或相似的標號表示相同或相似的構件，故針對圖2中說明過的構件於此不再贅述。Figure 5 is a cross-sectional view showing a nitride semiconductor device 500 in accordance with a fifth embodiment of the present invention. The nitride semiconductor device 500 of the fifth embodiment is similar to the nitride semiconductor device 200 of FIG. 2, and the present embodiment will be described with respect to the nitride semiconductor device 500 using FIG. It is to be noted that in FIG. 5, the same or similar reference numerals denote the same or similar components, and thus the components described in FIG. 2 will not be described again.
請參照圖5，第五實施例的氮化物半導體元件500與圖2的氮化物半導體元件200類似，兩者的差異在於：本實施例的氮化物半導體元件500更包括穿隧接面470以及第二N型氮化物半導體452。Referring to FIG. 5, the nitride semiconductor device 500 of the fifth embodiment is similar to the nitride semiconductor device 200 of FIG. 2, and the difference is that the nitride semiconductor device 500 of the present embodiment further includes a tunnel junction surface 470 and a portion. Two N-type nitride semiconductors 452.
在本實施例中，穿隧接面470以及第二N型氮化物半導體452可以類似前述實施例(如：第四實施例)的穿隧接面470以及第二N型氮化物半導體452，故於此不加以贅述。In this embodiment, the tunnel junction 470 and the second N-type nitride semiconductor 452 can be similar to the tunnel junction 470 of the foregoing embodiment (eg, the fourth embodiment) and the second N-type nitride semiconductor 452. I will not repeat them here.
圖6是依照本發明的第六實施例的一種氮化物半導體元件600的剖面示意圖。第六實施例的氮化物半導體元件600與圖3的氮化物半導體元件300類似，本實施例採用圖6針對氮化物半導體元件600進行描述。值得注意的是，在圖6中，相同或相似的標號表示相同或相似的構件，故針對圖3中說明過的構件於此不再贅述。Figure 6 is a cross-sectional view showing a nitride semiconductor device 600 in accordance with a sixth embodiment of the present invention. The nitride semiconductor device 600 of the sixth embodiment is similar to the nitride semiconductor device 300 of FIG. 3, and the present embodiment will be described with respect to the nitride semiconductor device 600 using FIG. It is to be noted that in FIG. 6, the same or similar reference numerals denote the same or similar components, and the components described in FIG. 3 will not be described again.
請參照圖6，第六實施例的氮化物半導體元件600與圖3的氮化物半導體元件300類似，兩者的差異在於：本實施例的氮化物半導體元件600更包括穿隧接面470以及第二N型氮化物半導體452。Referring to FIG. 6, the nitride semiconductor device 600 of the sixth embodiment is similar to the nitride semiconductor device 300 of FIG. 3, and the difference is that the nitride semiconductor device 600 of the present embodiment further includes a tunnel junction 470 and a Two N-type nitride semiconductors 452.
在本實施例中，穿隧接面470以及第二N型氮化物半導體452可以類似前述實施例(如：第四實施例)的穿隧接面470以及第二N型氮化物半導體452，故於此不加以贅述。In this embodiment, the tunnel junction 470 and the second N-type nitride semiconductor 452 can be similar to the tunnel junction 470 of the foregoing embodiment (eg, the fourth embodiment) and the second N-type nitride semiconductor 452. I will not repeat them here.
圖7是依照本發明的第七實施例的一種氮化物半導體高壓元件的剖面示意圖。第七實施例的氮化物半導體高壓元件700與圖4的氮化物半導體元件400類似，本實施例採用圖7針對氮化物半導體高壓元件700進行描述。值得注意的是，在圖7中，相同或相似的標號表示相同或相似的構件，故針對圖4中說明過的構件於此不再贅述。Figure 7 is a cross-sectional view showing a nitride semiconductor high voltage device in accordance with a seventh embodiment of the present invention. The nitride semiconductor high voltage element 700 of the seventh embodiment is similar to the nitride semiconductor element 400 of FIG. 4, and the present embodiment will be described with reference to FIG. 7 for the nitride semiconductor high voltage element 700. It is to be noted that in FIG. 7, the same or similar reference numerals denote the same or similar components, and thus the components described in FIG. 4 will not be described again.
請參照圖7，第七實施例的氮化物半導體高壓元件700與圖4的氮化物半導體元件400類似，兩者的差異在於：本實施例的氮化物半導體高壓元件可以是多個如圖4的氮化物半導體元件400彼此串接而構成的氮化物半導體高壓元件700。Referring to FIG. 7, the nitride semiconductor high voltage device 700 of the seventh embodiment is similar to the nitride semiconductor device 400 of FIG. 4, and the difference is that the nitride semiconductor high voltage device of the embodiment may be a plurality of nitride semiconductor devices as shown in FIG. The nitride semiconductor high voltage element 700 is formed by connecting the nitride semiconductor elements 400 in series.
舉例而言，在本實施例中，第一氮化物半導體元件700a及/或第二氮化物半導體元件700b可以類似於圖4的氮化物半導體元件400，且第一氮化物半導體元件700a的N型氮化物半導體102可以藉由N型電極107、金屬連結760以及P型電極110以與第二氮化物半導體元件700b的P型氮化物半導體101電性連接。For example, in the present embodiment, the first nitride semiconductor device 700a and/or the second nitride semiconductor device 700b may be similar to the nitride semiconductor device 400 of FIG. 4, and the N-type of the first nitride semiconductor device 700a The nitride semiconductor 102 can be electrically connected to the P-type nitride semiconductor 101 of the second nitride semiconductor device 700b by the N-type electrode 107, the metal connection 760, and the P-type electrode 110.
在本實施例中，第一氮化物半導體元件700a的基板104與第二氮化物半導體元件700b的基板104彼此相連。也就是說，第一氮化物半導體元件700a以及第二氮化物半導體元件700b可以具有共同的基板104，但本發明不限於此。In the present embodiment, the substrate 104 of the first nitride semiconductor element 700a and the substrate 104 of the second nitride semiconductor element 700b are connected to each other. That is, the first nitride semiconductor element 700a and the second nitride semiconductor element 700b may have a common substrate 104, but the invention is not limited thereto.
圖8是依照本發明的第八實施例的一種氮化物半導體高壓元件的剖面示意圖。第八實施例的氮化物半導體高壓元件800與圖7的氮化物半導體元件700類似，本實施例採用圖8針對氮化物半導體高壓元件800進行描述。值得注意的是，在圖8中，相同或相似的標號表示相同或相似的構件，故針對圖7中說明過的構件於此不再贅述。Figure 8 is a cross-sectional view showing a nitride semiconductor high voltage device in accordance with an eighth embodiment of the present invention. The nitride semiconductor high voltage element 800 of the eighth embodiment is similar to the nitride semiconductor element 700 of FIG. 7, and the present embodiment is described with respect to the nitride semiconductor high voltage element 800 using FIG. It is noted that in FIG. 8, the same or similar reference numerals denote the same or similar components, and thus the components described in FIG. 7 will not be described again.
請參照圖8，第八實施例的氮化物半導體高壓元件800與圖7的氮化物半導體元件700類似，兩者的差異在於：本實施例的氮化物半導體高壓元件其第一氮化物半導體元件800a的基板804a與第二氮化物半導體元件800b的基板804b彼此分離。Referring to FIG. 8, the nitride semiconductor high voltage device 800 of the eighth embodiment is similar to the nitride semiconductor device 700 of FIG. 7, and the difference is that the nitride semiconductor high voltage device of the present embodiment has the first nitride semiconductor device 800a. The substrate 804a and the substrate 804b of the second nitride semiconductor element 800b are separated from each other.
圖9是依照本發明的第九實施例的一種氮化物半導體高壓元件的剖面示意圖。第九實施例的氮化物半導體高壓元件900與圖5的氮化物半導體元件500類似，本實施例採用圖9針對氮化物半導體高壓元件900進行描述。值得注意的是，在圖9中，相同或相似的標號表示相同或相似的構件，故針對圖5中說明過的構件於此不再贅述。Figure 9 is a cross-sectional view showing a nitride semiconductor high voltage device in accordance with a ninth embodiment of the present invention. The nitride semiconductor high voltage element 900 of the ninth embodiment is similar to the nitride semiconductor element 500 of FIG. 5, and the present embodiment will be described with reference to FIG. 9 for the nitride semiconductor high voltage element 900. It is to be noted that, in FIG. 9, the same or similar reference numerals denote the same or similar components, and the components described in FIG. 5 will not be described again.
請參照圖9，第九實施例的氮化物半導體高壓元件900與圖5的氮化物半導體元件500類似，兩者的差異在於：本實施例的氮化物半導體高壓元件可以是多個如圖5的氮化物半導體元件500彼此串接而構成的氮化物半導體高壓元件900。Referring to FIG. 9, the nitride semiconductor high voltage device 900 of the ninth embodiment is similar to the nitride semiconductor device 500 of FIG. 5, and the difference is that the nitride semiconductor high voltage device of the embodiment may be a plurality of nitride semiconductor devices as shown in FIG. The nitride semiconductor high voltage element 900 is formed by connecting the nitride semiconductor elements 500 in series.
舉例而言，在本實施例中，第一氮化物半導體元件900a及/或第二氮化物半導體元件900b可以類似於圖5的氮化物半導體元件500，且第一氮化物半導體元件900a的N型氮化物半導體102可以藉由N型電極107、金屬連結706以及基板電極224以與第二氮化物半導體元件900a的P型氮化物半導體101電性連接。For example, in the present embodiment, the first nitride semiconductor device 900a and/or the second nitride semiconductor device 900b may be similar to the nitride semiconductor device 500 of FIG. 5, and the N-type of the first nitride semiconductor device 900a The nitride semiconductor 102 can be electrically connected to the P-type nitride semiconductor 101 of the second nitride semiconductor device 900a by the N-type electrode 107, the metal connection 706, and the substrate electrode 224.
圖10是依照本發明的第十實施例的一種氮化物半導體高壓元件的剖面示意圖。第十實施例的氮化物半導體高壓元件1000與圖6的氮化物半導體元件600類似，本實施例採用圖10針對氮化物半導體高壓元件1000進行描述。值得注意的是，在圖10中，相同或相似的標號表示相同或相似的構件，故針對圖6中說明過的構件於此不再贅述。Figure 10 is a cross-sectional view showing a nitride semiconductor high voltage device in accordance with a tenth embodiment of the present invention. The nitride semiconductor high voltage element 1000 of the tenth embodiment is similar to the nitride semiconductor element 600 of FIG. 6, and the present embodiment will be described with reference to FIG. 10 for the nitride semiconductor high voltage element 1000. It is to be noted that in FIG. 10, the same or similar reference numerals denote the same or similar members, and thus the components explained in FIG. 6 will not be described again.
請參照圖10，第十實施例的氮化物半導體高壓元件1000與圖6的氮化物半導體元件600類似，兩者的差異在於：本實施例的氮化物半導體高壓元件可以是多個如圖6的氮化物半導體元件600彼此串接而構成的氮化物半導體高壓元件1000。Referring to FIG. 10, the nitride semiconductor high voltage device 1000 of the tenth embodiment is similar to the nitride semiconductor device 600 of FIG. 6. The difference between the two is that the nitride semiconductor high voltage device of the present embodiment may be a plurality of nitride semiconductor devices as shown in FIG. The nitride semiconductor high voltage element 1000 is formed by connecting the nitride semiconductor elements 600 in series.
舉例而言，在本實施例中，第一氮化物半導體元件1000a及/或第二氮化物半導體元件1000b可以類似於圖6的氮化物半導體元件600，且第一氮化物半導體元件1000a的N型氮化物半導體102可以藉由N型電極107、位於電路板319的金屬連結(未繪示)以及第二連接電極324以與第二氮化物半導體元件1000b的P型氮化物半導體101電性連接。For example, in the present embodiment, the first nitride semiconductor device 1000a and/or the second nitride semiconductor device 1000b may be similar to the nitride semiconductor device 600 of FIG. 6, and the N-type of the first nitride semiconductor device 1000a The nitride semiconductor 102 can be electrically connected to the P-type nitride semiconductor 101 of the second nitride semiconductor device 1000b via an N-type electrode 107, a metal connection (not shown) on the circuit board 319, and a second connection electrode 324.
圖11是依照本發明的第十一實施例的一種氮化物半導體元件的封裝結構的剖面示意圖。在本實施例中，氮化物半導體元件1100a可以為水平結構的發光二極體元件。舉例而言，氮化物半導體元件1100a可以是類似於第一實施例的氮化物半導體元件100或是類似於第四實施例的氮化物半導體元件400，但本發明不限於此。Figure 11 is a cross-sectional view showing a package structure of a nitride semiconductor device in accordance with an eleventh embodiment of the present invention. In the present embodiment, the nitride semiconductor device 1100a may be a horizontally-structured light emitting diode element. For example, the nitride semiconductor device 1100a may be a nitride semiconductor device 100 similar to the first embodiment or a nitride semiconductor device 400 similar to the fourth embodiment, but the invention is not limited thereto.
封裝結構1100包括封裝載體、封裝基板以及氮化物半導體元件1100a。氮化物半導體元件1100a設置於封裝載體以及封裝基板上。封裝基板包括電路板1119、二個銲墊1120A、1120B。二個銲墊1120A、1120B分別設置於電路板1119上且彼此分離。封裝載體包括支架1113、二個導電引腳1114A、1114B、樹脂1115、透明膠1117以及螢光粉1118。二個導電引腳1114A、1114B分別設置於該支架1113上，用以分別與二個銲墊1120A、1120B電性連接。氮化物半導體元件1100a設置於二個導電引腳1114A、1114B上，並與二個導電引腳1114A、1114B電性連接。樹脂1115設置於支架1113上，並用以容納氮化物半導體元件1100a及二個導電引腳1114A、1114B。透明膠1117用以包覆氮化物半導體元件1100a及二個導電引腳1114A、1114B。螢光粉1118用以填入於透明膠1117中。The package structure 1100 includes a package carrier, a package substrate, and a nitride semiconductor device 1100a. The nitride semiconductor device 1100a is disposed on the package carrier and the package substrate. The package substrate includes a circuit board 1119 and two pads 1120A and 1120B. The two pads 1120A, 1120B are respectively disposed on the circuit board 1119 and separated from each other. The package carrier includes a bracket 1113, two conductive pins 1114A, 1114B, a resin 1115, a transparent glue 1117, and a phosphor powder 1118. Two conductive pins 1114A and 1114B are respectively disposed on the bracket 1113 for electrically connecting the two pads 1120A and 1120B, respectively. The nitride semiconductor device 1100a is disposed on the two conductive pins 1114A and 1114B and electrically connected to the two conductive pins 1114A and 1114B. The resin 1115 is disposed on the bracket 1113 and accommodates the nitride semiconductor device 1100a and the two conductive pins 1114A and 1114B. The transparent adhesive 1117 is used to coat the nitride semiconductor device 1100a and the two conductive pins 1114A and 1114B. Fluorescent powder 1118 is used to fill the transparent adhesive 1117.
在本實施例中，封裝載體更包括二個導電材料1116。二個導電材料1116用以電性連接氮化物半導體元件1100a以及二個導電引腳1114A、1114B。In this embodiment, the package carrier further includes two conductive materials 1116. Two conductive materials 1116 are used to electrically connect the nitride semiconductor device 1100a and the two conductive pins 1114A, 1114B.
在一些實施例中，螢光粉1118係由具高穩定發光特性的材料所製成，其材料例如可以包括石榴石系(Garnet)、硫化物(Sulfate)、氮化物(Nitrate)、矽酸鹽(Silicate)、鋁酸鹽(Aluminate)或其上述材料的任意組合，但本發明不限於此。螢光粉1118的發光波長約為300nm至700nm。螢光粉1118的粒徑為1~25μm。In some embodiments, the phosphor powder 1118 is made of a material having highly stable luminescent properties, and the material thereof may include, for example, Garnet, Sulfate, Nitrate, Citrate. (Silicate), aluminate (Aluminate) or any combination thereof, but the invention is not limited thereto. The phosphor powder 1118 has an emission wavelength of about 300 nm to 700 nm. The phosphor powder 1118 has a particle diameter of 1 to 25 μm.
在一些實施例中，導電材料1116可以為銲線、金、銀、銅、鋁、銲錫或是混合材料。在本實施例中，導電材料1116是以銲線為例，但本發明不限於此。In some embodiments, the conductive material 1116 can be a wire bond, gold, silver, copper, aluminum, solder, or a hybrid material. In the present embodiment, the conductive material 1116 is exemplified by a bonding wire, but the invention is not limited thereto.
在一些實施例中，透明膠1117的材料可以包括環氧樹脂(epoxy resin)，但本發明不限於此。In some embodiments, the material of the transparent adhesive 1117 may include an epoxy resin, but the invention is not limited thereto.
在一些實施例中，導電引腳1114A、1114B的材料可以可為纯金屬材料、金、銀、銅、鋁、低熔點金屬合金、金錫合金、錫、鉍或錫鉍合金，但本發明不限於此。In some embodiments, the material of the conductive pins 1114A, 1114B may be a pure metal material, gold, silver, copper, aluminum, a low melting point metal alloy, a gold tin alloy, a tin, a tantalum or a tin tantalum alloy, but the present invention does not Limited to this.
圖12是依照本發明的第十二實施例的一種氮化物半導體元件的封裝結構的剖面示意圖。第十二實施例的封裝結構1200與圖11的封裝結構1100類似，本實施例採用圖12針對封裝結構1200進行描述。值得注意的是，在圖12中，相同或相似的標號表示相同或相似的構件，故針對圖11中說明過的構件於此不再贅述。Figure 12 is a cross-sectional view showing a package structure of a nitride semiconductor device in accordance with a twelfth embodiment of the present invention. The package structure 1200 of the twelfth embodiment is similar to the package structure 1100 of FIG. 11, and the present embodiment is described with reference to FIG. 12 for the package structure 1200. It is to be noted that in FIG. 12, the same or similar reference numerals denote the same or similar components, and the components described in FIG. 11 will not be described again.
請參照圖12，第十二實施例的封裝結構1200與圖11的封裝結構1100類似，兩者的差異在於：在本實施例中，氮化物半導體元件1200a可以為垂直結構的發光二極體元件。舉例而言，氮化物半導體元件1200a可以是類似於第二實施例的氮化物半導體元件200或是類似於第五實施例的氮化物半導體元件500，但本發明不限於此。Referring to FIG. 12, the package structure 1200 of the twelfth embodiment is similar to the package structure 1100 of FIG. 11, and the difference is that in the embodiment, the nitride semiconductor device 1200a may be a vertical structure of the LED component. . For example, the nitride semiconductor element 1200a may be a nitride semiconductor element 200 similar to the second embodiment or a nitride semiconductor element 500 similar to the fifth embodiment, but the invention is not limited thereto.
在本實施例中，封裝載體包括第一導電材料1116以及第二導電材料1116。第一導電材料1116以及第二導電材料1116可以類似於前述實施例的導電材料1116。第一導電材料1116可以為銲線，且第二導電材料1116可以為銲球(solder ball)、凸塊(bump)或類似物，但本發明不限於此。In the present embodiment, the package carrier includes a first conductive material 1116 and a second conductive material 1116. The first conductive material 1116 and the second conductive material 1116 can be similar to the conductive material 1116 of the previous embodiment. The first conductive material 1116 may be a bonding wire, and the second conductive material 1116 may be a solder ball, a bump, or the like, but the invention is not limited thereto.
圖13是依照本發明的第十三實施例的一種氮化物半導體元件100的封裝結構的剖面示意圖。第十三實施例的封裝結構1300與圖11的封裝結構1100類似，本實施例採用圖13針對封裝結構1300進行描述。值得注意的是，在圖13中，相同或相似的標號表示相同或相似的構件，故針對圖11中說明過的構件於此不再贅述。Figure 13 is a cross-sectional view showing a package structure of a nitride semiconductor device 100 in accordance with a thirteenth embodiment of the present invention. The package structure 1300 of the thirteenth embodiment is similar to the package structure 1100 of FIG. 11, and the present embodiment is described with reference to FIG. 13 for the package structure 1300. It is to be noted that in FIG. 13, the same or similar reference numerals denote the same or similar components, and the components described in FIG. 11 will not be described again.
請參照圖13，第十三實施例的封裝結構1300與圖11的封裝結構1100類似，兩者的差異在於：在本實施例中，氮化物半導體元件1300a可以為覆晶結構的發光二極體元件。舉例而言，氮化物半導體元件1300a可以是類似於第三實施例的氮化物半導體元件100300或是類似於第六實施例的氮化物半導體元件600，但本發明不限於此。Referring to FIG. 13, the package structure 1300 of the thirteenth embodiment is similar to the package structure 1100 of FIG. 11, and the difference is that in the embodiment, the nitride semiconductor device 1300a may be a flip-chip light-emitting diode. element. For example, the nitride semiconductor element 1300a may be a nitride semiconductor element 100300 similar to the third embodiment or a nitride semiconductor element 600 similar to the sixth embodiment, but the invention is not limited thereto.
在本實施例中，封裝載體更包括二個導電材料1116。導電材料1116可以類似於前述實施例的導電材料1116。在本實施例中，導電材料1116可以為銲球(solder ball)、凸塊(bump)或類似物，但本發明不限於此。In this embodiment, the package carrier further includes two conductive materials 1116. Conductive material 1116 can be similar to conductive material 1116 of the previous embodiments. In the present embodiment, the conductive material 1116 may be a solder ball, a bump or the like, but the invention is not limited thereto.
圖14是依照本發明的一種氮化物半導體元件的製造流程圖。Figure 14 is a flow chart showing the manufacture of a nitride semiconductor device in accordance with the present invention.
請參照圖14。首先，在步驟S1中，形成一半導體晶圓。接著，在步驟S2中，以隱形雷射方式(stealth dicing process)切割半導體晶圓，以形成氮化物半導體元件。Please refer to Figure 14. First, in step S1, a semiconductor wafer is formed. Next, in step S2, the semiconductor wafer is diced in a stealth dicing process to form a nitride semiconductor device.
在本實施例中，氮化物半導體元件例如是前述任一實施中的氮化物半導體元件。舉例而言，本實施例的氮化物半導體元件的製造方法可以為氮化物半導體元件100、200、300、400、500、600的製造方法，或是氮化物半導體高壓元件700、800、900、1000的製造方法，但本發明不限於此。In the present embodiment, the nitride semiconductor device is, for example, the nitride semiconductor device in any of the above embodiments. For example, the method of fabricating the nitride semiconductor device of the present embodiment may be a method of fabricating the nitride semiconductor device 100, 200, 300, 400, 500, 600, or a nitride semiconductor high voltage device 700, 800, 900, 1000. Manufacturing method, but the invention is not limited thereto.
氮化物半導體元件可以發出UV光線、藍色光線或綠色光線。氮化物半導體元件可以應用於燈絲(Filament)產品、COB(Chip on Board)產品、雷射二極體(Laser Diode)產品或發光二極體(Light Emitting Diode)產品。The nitride semiconductor component can emit UV light, blue light, or green light. The nitride semiconductor device can be applied to a Filament product, a COB (Chip on Board) product, a Laser Diode product, or a Light Emitting Diode product.
綜上所述，本發明的氮化物半導體元件，其可以提昇發光效率及改善製程良率。本發明的氮化物半導體元件的製造方法，可用以製作上述的氮化物半導體元件。本發明的封裝結構，可應用於上述的氮化物半導體元件。As described above, the nitride semiconductor device of the present invention can improve luminous efficiency and improve process yield. The method for producing a nitride semiconductor device of the present invention can be used to fabricate the above-described nitride semiconductor device. The package structure of the present invention can be applied to the above-described nitride semiconductor device.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.
100、200、300、400、500、600、1100a、1200a、1300a‧‧‧氮化物半導體元件100, 200, 300, 400, 500, 600, 1100a, 1200a, 1300a‧‧‧ nitride semiconductor components
700、800、900、1000‧‧‧氮化物半導體高壓元件700, 800, 900, 1000‧‧‧ nitride semiconductor high voltage components
1100、1200、1300‧‧‧封裝結構1100, 1200, 1300‧‧‧ package structure
700a、800a、900a、1000a‧‧‧第一氮化物半導體元件700a, 800a, 900a, 1000a‧‧‧ first nitride semiconductor components
700b、800b、900b、1000b‧‧‧第二氮化物半導體元件700b, 800b, 900b, 1000b‧‧‧Second nitride semiconductor components
101‧‧‧P型氮化物半導體101‧‧‧P type nitride semiconductor
101A‧‧‧P側應力釋放層101A‧‧‧P side stress relief layer
101B‧‧‧高濃度電洞層101B‧‧‧High concentration hole layer
101C‧‧‧電子阻擋層101C‧‧‧Electronic barrier
101D‧‧‧P型歐姆接觸層101D‧‧‧P type ohmic contact layer
102‧‧‧N型氮化物半導體102‧‧‧N type nitride semiconductor
102A‧‧‧N側第一應力釋放層102A‧‧‧N side first stress relief layer
102B‧‧‧N側第二應力釋放層102B‧‧‧N side second stress relief layer
102C‧‧‧低濃度電子層102C‧‧‧Low concentration electron layer
102D‧‧‧N型歐姆接觸層102D‧‧‧N type ohmic contact layer
103‧‧‧氮化物半導體量子井發光結構103‧‧‧Nitrate semiconductor quantum well light-emitting structure
103A‧‧‧井層103A‧‧‧ Wells
103B‧‧‧阻擋層103B‧‧‧Block
103B1‧‧‧第一阻擋層103B1‧‧‧First barrier
103B2‧‧‧第二阻擋層103B2‧‧‧Second barrier
103B3‧‧‧第三阻擋層103B3‧‧‧ third barrier
104、804a、804b‧‧‧基板104, 804a, 804b‧‧‧ substrate
104A‧‧‧第一面104A‧‧‧ first side
104A1‧‧‧成長表面104A1‧‧‧Growth surface
104A2‧‧‧微結構104A2‧‧‧Microstructure
104B‧‧‧第二面104B‧‧‧ second side
104C‧‧‧週期性突出結構104C‧‧‧Periodic protruding structure
104D‧‧‧高度104D‧‧‧ Height
104E‧‧‧寬度104E‧‧‧Width
104F‧‧‧底面間距104F‧‧‧Bottom spacing
105‧‧‧緩衝層105‧‧‧buffer layer
105A‧‧‧第一緩衝層105A‧‧‧First buffer layer
105B‧‧‧第二緩衝層105B‧‧‧Second buffer layer
106‧‧‧平台結構106‧‧‧ platform structure
107‧‧‧N型電極107‧‧‧N type electrode
108‧‧‧電流阻擋層108‧‧‧current barrier
109‧‧‧透明導電層109‧‧‧Transparent conductive layer
110‧‧‧P型電極110‧‧‧P type electrode
111‧‧‧絕緣層111‧‧‧Insulation
112、212、312‧‧‧高反射絕緣層112, 212, 312‧‧‧ high reflective insulation
112A‧‧‧第一介電對112A‧‧‧First Dielectric Pair
112B‧‧‧第二介電對112B‧‧‧Second dielectric pair
112C‧‧‧第一材料層112C‧‧‧First material layer
112D‧‧‧第二材料層112D‧‧‧Second material layer
221‧‧‧第一焊接金屬層221‧‧‧First welded metal layer
222‧‧‧第二焊接金屬層222‧‧‧Second welding metal layer
223‧‧‧接合基板223‧‧‧ Bonding substrate
224‧‧‧基板電極224‧‧‧ substrate electrode
225‧‧‧P型高反射歐姆電極225‧‧‧P type high reflection ohmic electrode
319、1119‧‧‧電路板319, 1119‧‧‧ circuit board
321‧‧‧第一銲墊層321‧‧‧First pad layer
322‧‧‧第二銲墊層322‧‧‧Second pad
323‧‧‧第一連接電極323‧‧‧First connecting electrode
324‧‧‧第二連接電極324‧‧‧Second connection electrode
470‧‧‧穿隧接面470‧‧‧ Tunneling junction
450‧‧‧第二N型氮化物半導體450‧‧‧Second N-type nitride semiconductor
451‧‧‧重摻雜N型氮化物半導體451‧‧‧ heavily doped N-type nitride semiconductor
452‧‧‧第二N型氮化物半導體452‧‧‧Second N-type nitride semiconductor
401D‧‧‧重摻雜P型氮化物半導體401D‧‧‧ heavily doped P-type nitride semiconductor
760‧‧‧金屬連結760‧‧‧Metal links
1120A、1120B‧‧‧銲墊1120A, 1120B‧‧‧ solder pads
1113‧‧‧支架1113‧‧‧ bracket
1114A、1114B‧‧‧導電引腳1114A, 1114B‧‧‧ conductive pins
1115‧‧‧樹脂1115‧‧‧Resin
1116‧‧‧導電材料1116‧‧‧Electrical materials
1117‧‧‧透明膠1117‧‧‧Sticky adhesive
1118‧‧‧螢光粉1118‧‧‧Flame powder
S1、S2‧‧‧步驟S1, S2‧‧‧ steps
圖1是依照本發明的第一實施例的一種氮化物半導體元件的剖面示意圖。 圖2是依照本發明的第二實施例的一種氮化物半導體元件的剖面示意圖。 圖3是依照本發明的第三實施例的一種氮化物半導體元件的剖面示意圖。 圖4是依照本發明的第四實施例的一種氮化物半導體元件的剖面示意圖。 圖5是依照本發明的第五實施例的一種氮化物半導體元件的剖面示意圖。 圖6是依照本發明的第六實施例的一種氮化物半導體元件的剖面示意圖。 圖7是依照本發明的第七實施例的一種氮化物半導體高壓元件的剖面示意圖。 圖8是依照本發明的第八實施例的一種氮化物半導體高壓元件的剖面示意圖。 圖9是依照本發明的第九實施例的一種氮化物半導體高壓元件的剖面示意圖。 圖10是依照本發明的第十實施例的一種氮化物半導體高壓元件的剖面示意圖。 圖11是依照本發明的第十一實施例的一種氮化物半導體元件的封裝結構的剖面示意圖。 圖12是依照本發明的第十二實施例的一種氮化物半導體元件的封裝結構的剖面示意圖。 圖13是依照本發明的第十三實施例的一種氮化物半導體元件的封裝結構的剖面示意圖。 圖14是依照本發明的一種氮化物半導體元件的製造流程圖。BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic cross-sectional view showing a nitride semiconductor device in accordance with a first embodiment of the present invention. 2 is a schematic cross-sectional view showing a nitride semiconductor device in accordance with a second embodiment of the present invention. Figure 3 is a cross-sectional view showing a nitride semiconductor device in accordance with a third embodiment of the present invention. Figure 4 is a cross-sectional view showing a nitride semiconductor device in accordance with a fourth embodiment of the present invention. Figure 5 is a cross-sectional view showing a nitride semiconductor device in accordance with a fifth embodiment of the present invention. Figure 6 is a cross-sectional view showing a nitride semiconductor device in accordance with a sixth embodiment of the present invention. Figure 7 is a cross-sectional view showing a nitride semiconductor high voltage device in accordance with a seventh embodiment of the present invention. Figure 8 is a cross-sectional view showing a nitride semiconductor high voltage device in accordance with an eighth embodiment of the present invention. Figure 9 is a cross-sectional view showing a nitride semiconductor high voltage device in accordance with a ninth embodiment of the present invention. Figure 10 is a cross-sectional view showing a nitride semiconductor high voltage device in accordance with a tenth embodiment of the present invention. Figure 11 is a cross-sectional view showing a package structure of a nitride semiconductor device in accordance with an eleventh embodiment of the present invention. Figure 12 is a cross-sectional view showing a package structure of a nitride semiconductor device in accordance with a twelfth embodiment of the present invention. Figure 13 is a cross-sectional view showing a package structure of a nitride semiconductor device in accordance with a thirteenth embodiment of the present invention. Figure 14 is a flow chart showing the manufacture of a nitride semiconductor device in accordance with the present invention.
Claims (19)
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| KR20020021247A (en) * | 2000-09-14 | 2002-03-20 | 양계모 | III-Nitride compound semiconductor light emitting device having a tunnel junction structure |
| TW201421733A (en) * | 2012-11-19 | 2014-06-01 | Genesis Photonics Inc | Nitride semiconductor structure and semiconductor light emitting device |
| KR20160100568A (en) * | 2015-02-16 | 2016-08-24 | 엘지이노텍 주식회사 | Light emitting device, light emitting device package having the same, and light system having the same |
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