TWI667936B - Apparatus for reducing power consumption by early decoding - Google Patents

Abstract

The disclosure provides a means for reducing power consumption with early decoding. Law and equipment. It is determined whether the predetermined decoding condition is satisfied after the time unit in the transmission time interval expires. When the predetermined decoding condition is satisfied, decoding is performed on the received signal via a time unit in the transmission time interval. When the decoding is successful, the controller outputs the command signal to the radio frequency processor to set to the low power mode during the remaining time period of the transmission time interval after the time unit in the transmission time interval. When the time unit is the last time unit in the transmission time interval, the received signal is decoded via the radio frequency processor after the expiration of the last time unit of the transmission time interval, regardless of the predetermined decoding condition.

Description

Device for reducing power consumption by early decoding

The present disclosure is directed to methods and apparatus for reducing power consumption in a receiver that supports early decoding.

Wireless communication systems can be implemented based on various techniques for high speed packet data communication. One of a variety of techniques may include error correction decoding.

In a wireless communication system, the transmitter can encode and transmit information bits of the data to be transmitted in units of packets by means of an encoder, and the receiver can receive the encoded packet on the wireless channel and decode it by means of a decoder. The packet is received, thereby restoring the information bit.

The decoder may attempt to decode some of the signals in one TTI before receiving all signals for encoding corresponding to one transmission time interval (TTI). If the channel conditions are good, the receiver is more likely to successfully decode before receiving all of the signals for one TTI. In this case, the receiver can receive the signal unnecessarily in the remaining period in which the receiver has not received the signal.

The present disclosure has been made to address at least the above problems and/or disadvantages and to provide at least the advantages described herein. Accordingly, one aspect of the present disclosure provides methods and apparatus for supporting early decoding in a wireless communication system.

Another aspect of the present disclosure provides a method and apparatus for reducing power consumption in a receiver that supports early decoding.

Another aspect of the present disclosure provides a method and apparatus for controlling a receiver circuit for operation of an apparent bit error correction decoder.

Another aspect of the present disclosure provides a method and apparatus for reducing the power consumption of a wireless terminal by controlling the receiver circuitry by visually decoding success.

Another aspect of the present disclosure provides a method and apparatus for determining an early decoding time for a digital error correction decoder.

Another aspect of the present disclosure provides a method and apparatus for controlling early decoding operations of a digital error correction decoder.

102‧‧‧ frames

104‧‧‧Child frame

106‧‧‧ time slot

210‧‧‧RF Processor

220‧‧‧Baseband processor

230‧‧‧Decoder

300‧‧‧TTI

310‧‧‧Time

410‧‧‧RF Processor

420‧‧‧Baseband processor

430‧‧‧Decoder

440‧‧‧ Controller

500‧‧‧current TTI

510, 520‧‧‧ reference numbers

610, 620‧‧‧ effective code rate

705‧‧‧Target BLER

710‧‧‧ threshold TTI_LQM_TH

805, 810, 815, 820, 825, 830, 835, 840, 845 ‧ ‧ steps

900‧‧‧TTI/Transport Channel

905‧‧‧ Early decoding time

910‧‧‧Decoding time

920‧‧‧TTI/Transport Channel

925‧‧‧ Early decoding time

930‧‧‧Decoding time

1005, 1010, 1015, 1020, 1025, 1030, 1035‧ ‧ steps

1100‧‧‧Decoding timing of transport channels with TTI0=20 ms

1105‧‧‧ scheduled early decoding time

1110‧‧‧ End time

1120‧‧‧Decoding timing of transport channels with TTI1=40 ms

1125‧‧‧ scheduled early decoding time

1130‧‧‧ End time

1205‧‧‧RF Processor

1210‧‧‧Operating mode

1220‧‧‧Transport channel TrCH0

1225‧‧‧Transport channel TrCH1

1230, 1235, 1240, 1245, 1250, 1255, 1260‧‧‧ decoding time

1305‧‧‧BLER1

1310‧‧‧BLER0

1405, 1410, 1415, 1420, 1425, 1430, 1435, 1440‧ ‧ steps

TrCH0, TrCH1, TrCH3‧‧‧ delivery channel

TTI_LQM(k)‧‧‧ Link quality

TTI_LQM(k+1)‧‧‧ Link quality

TTI_LQM_TH‧‧‧Predetermined threshold

The above and other aspects, features and advantages of the present disclosure will be more apparent from the following detailed description of the appended claims.

1 is a diagram illustrating a frame structure for a wireless communication system in accordance with an embodiment of the present disclosure.

2 is a block diagram illustrating a structure of a receiver including a decoder in a wireless communication system in accordance with an embodiment of the present disclosure.

FIG. 3 is a timing chart illustrating a decoding operation of a normal decoding mode.

4 is a block diagram illustrating the structure of a receiver supporting early decoding, in accordance with an embodiment of the present invention.

FIG. 5 is a timing diagram illustrating a decoding operation of an early decoding mode in accordance with an embodiment of the present disclosure.

6A and 6B are graphs illustrating effective write rate determined based on the position of a receive time slot for each transport channel, in accordance with an embodiment of the present disclosure.

7 is a graph illustrating criteria for setting a threshold for link quality quality for evaluating channel quality for each time slot, in accordance with an embodiment of the present disclosure.

FIG. 8 is a flowchart illustrating an operation of determining early decoding in accordance with an embodiment of the present disclosure.

9 is a timing diagram illustrating an operation of determining an early decoding time in accordance with an embodiment of the present disclosure.

FIG. 10 is a flowchart illustrating an operation of determining an early decoding time in accordance with an embodiment of the present disclosure.

11 is a timing diagram illustrating the determined early decoding time in accordance with an embodiment of the present disclosure.

FIG. 12 is a timing diagram illustrating a decoding operation for a plurality of transport channels in accordance with an embodiment of the present disclosure.

13 is a graph illustrating a comparison between a normal decoding mode and an early decoding mode in terms of reception quality of a video channel environment determination, in accordance with an embodiment of the present disclosure.

14 is a flow diagram illustrating operation of enabling an early decoding mode in accordance with an embodiment of the present disclosure.

Embodiments of the present disclosure are described in detail with reference to the accompanying drawings. Same or class The components may be indicated by the same or similar reference numerals, although the components are illustrated in different drawings. Detailed descriptions of construction or processing procedures known in the art may be omitted to avoid obscuring the subject matter of the present disclosure.

The terms and expressions used in the following description and claims are not to be construed as a limitation of the The following description of the embodiments of the present disclosure is intended to be illustrative only, and is not intended to limit the scope of the disclosure as defined by the appended claims and their equivalents .

It should be understood that the singular forms "a", "the" Thus, for example, reference to "a component surface" includes reference to one or more of such surfaces.

With respect to the term "substantially", it is meant that the recited characteristics, parameters or values do not need to be accurately achieved, but rather are variations or variations (including, for example, tolerances, measurement errors, measurement accuracy limits, and those known to those skilled in the art). Other factors) may not exclude the amount of effect that the characteristic is intended to provide.

It should be understood that the combination of blocks and flowcharts in the flowcharts can be executed by computer program instructions. Since the computer program instructions can be installed in a general purpose computer, a special purpose computer or other processor of a programmable data processing device, instructions executed by a computer or other processor of the programmable data processing device can be used to execute a flowchart block. The way the functions are described. To perform the functions in a specific manner, the computer program instructions can be stored in a computer usable or computer readable memory capable of directing a computer or other programmable data processing device, such that it can be stored in a computer usable or computer readable memory. The instructions in the instructions may produce a manufacturing item that includes an instruction component for performing the functions described in the flowchart block. Computer program instructions can be equipped on a computer or He can be programmed into a data processing device, so that a computer or other programmable data processing device can be executed by generating a processing program in which a series of operating steps are performed on a computer or other programmable data processing device and executed by a computer. The instructions may provide steps for performing the functions described in the flowchart block.

Each block may represent a portion of a module, segment or code that contains one or more executable instructions for performing the specified logical function. In some alternative instances, it should be noted that the mentioned features in the blocks may be produced out of order. For example, two blocks shown in succession may be executed substantially concurrently, or a block may sometimes be performed in the reverse order.

As used herein, the term "~ unit" means a software component or a hardware component such as a field-programmable gate array (FPGA) or an application specific integrated circuit (ASIC). And the "~ unit" can perform certain tasks. However, the "~ unit" will not be limited to software or hardware. The "~unit" can be configured to reside in an addressable storage medium or can be configured to execute one or more processors. Thus, by way of example, the "~unit" can include components such as software components, object oriented software components, category components and task components, handlers, functions, attributes, programs, subroutines, fragments of code, Drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, and variables. The components and the functions provided in the "~ unit" can be combined into fewer components and "~ units", or can be subdivided into additional components and "~ units". The component and the "~ unit" may be implemented to execute one or more central processing units (CPUs) in a device or a secure multimedia card.

Although the embodiment of the disclosure is based on orthogonal frequency division multiplexing The wireless communication system of the orthogonal frequency division multiplexing (OFDM) is described in detail, but it is obvious to those skilled in the art that the subject matter of the present disclosure can be applied to have the subject matter without departing from the spirit and scope of the disclosure. Other communication systems and services like technical background and channel format.

In accordance with another aspect of the present disclosure, an apparatus for reducing power consumption using early decoding is provided. The apparatus includes a baseband processor configured to process a received signal from a radio frequency (RF) processor, a decoder configured to decode an output signal of the baseband processor, and a controller. The controller is configured to: determine whether a predetermined decoding condition is satisfied after a time unit in the transmission time interval expires; and when the predetermined decoding condition is satisfied, controlling the decoder to pass the transmission time The unit time in the interval performs decoding on the received signal; when the decoding is successful, transmitting the command signal to the RF processor to the transmission time interval after the time unit in the transmission time interval a low power mode is set during a remaining time period; and when the time unit is the last time unit of the transmission time interval, regardless of the predetermined decoding condition, the decoder is controlled to be at the transmission time interval Decoding is performed on the radio signal after the last time unit expires.

In accordance with another aspect of the present disclosure, an apparatus for reducing power consumption using early decoding is provided. The apparatus includes a baseband processor configured to process a received signal from an RF processor, a decoder configured to decode an output signal of the baseband processor, and a controller. The controller is configured to: perform decoding on the received signal via a predetermined early decoding time in a transmission time interval; when the decoding fails, control the decoder to be in the transmission time interval Decoding a received radio signal by a time unit; when the solution When the code is successful, determining whether the consecutive decoding success count including the successful decoding on the transmission time interval exceeds a predetermined threshold; and if the continuous decoding success count exceeds the predetermined threshold, the predetermined early decoding is performed Time is reduced by the single time unit.

In accordance with another aspect of the present disclosure, an apparatus for reducing power consumption using early decoding is provided. The apparatus includes an RF processor configured to receive a radio signal, a baseband processor configured to process an output signal of the RF processor, and a decoder configured to decode the base The output signal of the frequency processor; and the controller. The controller is configured to: determine, at a start time of the transmission time interval, whether at least one of a power loss gain obtainable via early decoding and a reception quality during a predetermined time period prior to the transmission time interval is Performing early decoding in the transmission time interval; controlling the decoder to perform decoding on the radio signal via a predetermined early decoding time in the transmission time interval when determining to perform the early decoding; and when the decoding Upon success, the RF processor is set to a low power mode during the remainder of the transmission time interval.

In an embodiment of the present disclosure described below, a digital error correction decoder (hereinafter referred to as a "decoder") of a wireless terminal may attempt to be in each predetermined unit before receiving all signals corresponding to one TTI. The time is decoded, and the power consumption of the wireless terminal can be reduced by controlling the receiver circuit depending on the success of decoding of each decoding.

1 is a diagram illustrating a frame structure for a wireless communication system in accordance with an embodiment of the present disclosure.

Referring to Figure 1, wireless communication between the transmitter and the receiver can be performed on the transport channel. In the downlink, the transmitter can be a base station and the receiver can be a wireless end. End machine. In the uplink, the transmitter can be a wireless terminal and the receiver can be a base station. The TTI of the transport channel may have one or more frames 102 (or consist of one or more frames). A frame 102 can have a plurality of sub-frames 104, and each of the sub-frames 104 can include a plurality of time slots 106.

In a 3rd generation partnership project (3GPP) long-term evolution (LTE), which is one of the standards for wireless communication, a frame with a length of 10 milliseconds It can be divided into 10 sub-frames each having a length of 1 millisecond, and each sub-frame can be divided into 2 time slots each having a length of 0.5 milliseconds. A sub-frame can be the smallest unit of TTI, and in the TTI, a minimum of 1 millisecond to a maximum of 40 milliseconds can be allocated for each transport channel (TrCH).

The bits that are subjected to the encoded output may be uniformly spread by a channel interleaver to a plurality of frames corresponding to one TTI. The decoder may receive a TTI signal via a baseband (BB) processor (including, for example, a demodulator) and then decode the received signal in each predetermined time unit. The time unit can be, for example, a half time slot, a time slot, or multiple time slots.

2 is a block diagram illustrating a structure of a receiver including a decoder in a wireless communication system in accordance with an embodiment of the present disclosure.

Referring to FIG. 2, the RF processor 210 can receive a radio signal via a receiving antenna, convert the received radio signal into a baseband signal, and provide the baseband signal to the BB processor 220. The BB processor 220 can process the baseband signal in accordance with a signal processing algorithm. The decoder 230 may perform channel decoding on the signal output from the BB processor 220 to correct the error, and then resume the information bits transmitted by the transmitter.

The decoder 230 can be typically via the BB processor 220 (including, for example) The demodulator) performs decoding after receiving all of the plurality of frames corresponding to one TTI. Herein, this decoding will be referred to as a normal decoding mode.

FIG. 3 is a timing chart illustrating a decoding operation of a normal decoding mode.

Referring to Figure 3, one TTI 300 includes N time slots, and the BB processor 220 (or channel estimator not depicted) can measure channel quality (e.g., link quality or signal) for the time slot of each time slot. Quality), for example, signal to interference ratio (SIR). In the normal decoding mode, decoder 230 may attempt to decode all received signals of the TTI at time 310 when the signals of the last time slot are all received, such that the decoding time may be independent of the channel quality of each time slot.

When the decoder 230 operates in the normal decoding mode, the RF processor 210 can operate in a high or normal signal quality mode (hereinafter referred to as a normal signal quality mode) to ensure good signal quality (eg, low block error). Rate; BLER)). The normal signal quality mode is operable to generate a signal having an error vector magnitude (EVM) that is, for example, above a predetermined threshold.

4 is a block diagram illustrating the structure of a receiver supporting early decoding in accordance with an embodiment of the present disclosure.

Referring to FIG. 4, the RF processor 410 can receive a radio signal via a receiving antenna, convert the received signal into a baseband signal, and provide the baseband signal to the BB processor 420. The BB processor 420 can process the baseband signal in accordance with a signal processing algorithm. The decoder 430 may perform channel decoding on the signal output from the BB processor 420 to correct the error, and then resume the information bits transmitted by the transmitter.

The decoder 430 supporting early decoding may attempt to decode in units of time slots before receiving all signals of one TTI. In this paper, this decoding will be referred to as the early decoding mode.

The decoder 430 may attempt to decode the received signal up to the early decoding time in the TTI at an early decoding time prior to the expiration of one TTI. During decoding, the signal of the unreceived time slot in the time slot constituting one TTI can be filled with the signal of "erasure (=0)" and the time slot that has been received, and the signal filled with "erasure" can be decoded. aims. If the effective code rate is low and the channel conditions are good, it is more likely to be successfully decoded, even in the case of a signal of a certain period of a TTI and a signal of the remaining period filled with "erasure", since each of the TTIs is formed. The signal quality during the unit period is relatively high. If the decoding is successful, the RF processor 410 may stop unnecessary receiving operations during a period corresponding to a time slot that has not been received in the TTI, thereby reducing power consumption.

For example, adaptive multi-rate (AMR) 12.2 kbps, which is one of the 3GPP transmission modes, uses a relatively low channel write rate during TTI, and in a good channel condition environment, voice transmission The channel is highly likely to be successfully received, even if only some time slots in the TTI are used. Since the normal decoding mode attempts to decode after receiving all of the signals of one TTI (even under good channel conditions), the RF processor 410 can operate in the normal signal quality mode during the entire time period of one TTI, resulting in a voice call. Unnecessary power consumption. Keeping the signal quality mode of the RF processor 410 high (even in the low transmission rate transport channel) can result in an unnecessary increase in the total power consumption of the terminal.

The controller 440 can operate the decoder 430 in a normal decoding mode or an early decoding mode for at least one TTI decision. After determining to operate the decoder 430 in an early decoding mode, the controller 440 can transmit the instruction signal to the RF processor 410 and/or control the BB processor 420 depending on the decoding result provided from the decoder 430 such that the RF processor 410 And/or BB processor 420 can be RF processor 410 and/or BB Processor 420 operates in a less power mode of operation (eg, a low signal quality mode or a low power mode). As an example, the low signal quality mode of RF processor 410 may allow signals having an EVM above a predetermined threshold. The RF processor 410 may maintain a low signal quality mode during a period corresponding to the remaining time slots of the TTI and return to the normal signal quality mode in the next TTI.

When the reception of the transmission channel is started, the RF processor 410 can set to the normal signal quality mode and output a high signal quality signal. When operating in the early decoding mode, decoder 430 may attempt to decode the data provided from BB processor 420 at the time indicated by controller 440 (e.g., predetermined early decoding time) or at each time slot, and report the decoding result. To controller 440. If a plurality of transport channels are set in the receiver, the decoder 430 can individually decode the signals of the plurality of transport channels in each time slot and provide the decoded results of the plurality of transport channels to the controller 440. If the decoding success is notified from the decoder 430 at a time slot other than the last time slot of one TTI, the controller 440 may transmit the instruction signal to the RF processor 410 such that the RF processor 410 during the remaining time slot of the TTI Low signal quality mode (ie, low power mode) operation. That is, the command signal instructs RF processor 410 to enter a low signal quality mode.

In an embodiment of the present disclosure, controller 440 can determine when decoder 430 will attempt early decoding (eg, early decoding time). The BB processor 420 can perform channel estimation, frequency/time synchronization, and channel compensation on the signal samples provided from the baseband signal of the RF processor 410, estimate the channel quality of the signal samples, and report the estimated channel quality to the controller 440. The channel quality can be, for example, the SIR of the signal samples for each time slot. The controller 440 can determine whether the decoder 430 will attempt early decoding at a certain time slot by using the SIR of the time slot as the link quality of the time slot. Early decoding time can be in time slot units or when a predetermined number of time slots are included The segment is determined by the unit.

In an embodiment of the present disclosure, the controller 440 may store the time when the "Cyclic Redundancy Code (CRC) is good" is reported from the decoder 430 as a decoding result in one TTI, as the next TTI. Early decoding time, and information about the early decoding time can be provided to decoder 430 in the next TTI. The decoder 430 can decode the signals that have been received up to the early decoding time indicated by the controller 440 in one TTI.

FIG. 5 is a timing diagram illustrating a decoding operation of an early decoding mode in accordance with an embodiment of the present disclosure.

Referring to FIG. 5, in the current TTI 500, the BB processor 420 can measure the SIR indicating the channel quality in units of time slots using a pilot channel or a reference channel transmitted from the base station, and report the SIR to the controller 440. In FIG. 5, the time slot SIR(k) may be the channel quality of the time slot k, or the channel quality of the signal during the time slot 0 to the time slot k. The controller 440 may derive a link quality metric (LQM) TTI_LQM(k) based on the time slot SIR(k) reported by the BB processor 420. The TTI_LQM(k) of the time slot k can be compared with the predetermined threshold TTI_LQM_TH, and the controller 440 can determine whether or not to attempt to decode the signal that has been received up to the time slot k, depending on the comparison result. The threshold may be obtained from a lookup table (where the time slots in which the decoding is attempted have different values) or may be implemented as the same constant value for the time slot in which the attempt is to be decoded. The controller 440 can calculate the link quality quality TTI_LQM based on the time slot SIR according to a predetermined algorithm, and the controller 440 can use, for example, a technique well known in the art as an algorithm.

When TTI_LQM(k) of slot k is less than TTI_LQM_TH (see reference numeral 510), controller 440 can control decoder 430 not to attempt decoding in time slot k. If the TTI_LQM(k+1) of the time slot (k+1) is greater than or equal to TTI_LQM_TH (see reference numeral 520), the controller 440 may control the decoder 430 to attempt decoding at the time slot (k+1). In this case, the early decoding time is the time slot (k+1).

The decoder 430 may decode the transport channel in the time slot indicated by the controller 440 in the TTI of the set plurality of transport channels, and report the decoding result to the controller 440. The decoding result may mean a CRC check result of the information bit, which result has been obtained as a result of the decoding. The CRC check result may be "CRC good" when the decoding is successful, and the CRC check result may be "CRC bad" in the case of decoding failure.

If the decoding results of the plurality of transport channels set in the terminal are different from each other (for example, if both the "CRC good" and the "CRC bad" of the transport channel occur in a specific time slot), the controller 440 can control the decoder. 430 attempts to decode only the transport channel in which the "CRC Bad" has occurred in the next time slot, or attempt to decode all transport channels in the next time slot. Therefore, even if the signal quality mode of the RF processor 410 remains low for a predetermined period of time, the reception quality (e.g., BLER) of the transmission channel to be received can be guaranteed to avoid performance degradation (compared to the normal decoding mode).

In an alternate embodiment of the present disclosure, the controller 440 may determine a plurality of conditions for performing decoding at each time slot before the TTI expiration for each transport channel or every predetermined number of time slots. The plurality of conditions may include conditions for a valid write rate of the transport channel. As an example, if the effective write rate of the transport channel is less than 1, then this condition can be satisfied. The plurality of conditions may include conditions for the LQM described above. The channel quality of each time slot may be the TTI_LQM determined by the pilot channel or reference channel of the time slot, and the TTI_LQM may be calculated as a valid SIR or per coded code. Mean mutual information per coded bit (MMIB). This condition can be satisfied if TTI_LQM is greater than or equal to the threshold of the target BLER corresponding to the transport channel. The plurality of conditions may include conditions for the number of remaining time slots. As an example, if the RF processor 410 can maintain the length of the time period in which the low signal quality mode is located (eg, the number of time slots from the next time slot of the time slot in which the decoding succeeded until the last time slot of the current TTI) is greater than The predetermined minimum number (=X, for example, 1), then this condition can be satisfied.

6A and 6B are graphs illustrating effective write rate determined based on the position of a receive time slot for each transport channel, in accordance with an embodiment of the present disclosure. Since the effective write rate 610 of the transport channel TrCH0 illustrated in FIG. 6A is less than the threshold (=1) from the 10th time slot, the controller 440 can determine for TrCH0 that the condition for the effective write rate will be The 10 time slots and their subsequent time slots are satisfied. Since the effective write rate 620 of the transport channel TrCH3 illustrated in FIG. 6B is less than the threshold (=1) from the 22nd slot of the total of 60 time slots, the controller 440 can determine for valid writes for TrCH3. The condition of the code rate will be satisfied in the 22nd time slot and its subsequent time slots.

7 is a graph illustrating criteria for setting a threshold for link quality quality for evaluating channel quality for each time slot, in accordance with an embodiment of the present disclosure. As illustrated, the controller 440 can set a threshold TTI_LQM_TH 710 corresponding to the target BLER 705 required by each of the delivery channels set in the receiver. The TTI_LQM-based BLER can be determined using a predetermined table, or can be determined experimentally or empirically.

FIG. 8 is a flowchart illustrating an operation of determining early decoding in accordance with an embodiment of the present disclosure. The illustrated operation can be performed, for example, as configured in FIG. The wireless terminal of the receiver is executed in each TTI.

Referring to Figure 8, in step 805, controller 440 transmits the command signal to RF processor 410 to set the normal signal quality mode. The RF processor 410 receives each time slot of a TTI in a normal signal quality mode in response to the command signal. The normal signal quality mode may have a higher EVM than the low signal quality mode described below, and may require relatively large power consumption.

In step 810, the controller 440 determines whether all of the conditions for determining early decoding are satisfied at the current time slot, or if necessary, determines whether some conditions are satisfied at each time slot of the TTI. In an embodiment of the present disclosure, the controller 440 determines whether the effective write rate of the transport channel is greater than a predetermined threshold (eg, 1) in the current time slot, and whether the link quality calculated at the current time slot is greater than or equal to Whether the threshold TTI_LQM_TH and the number of remaining time slots of the current TTI are greater than the threshold X.

If all of the above conditions are met, then in step 815, controller 440 instructs decoder 430 to decode the signals that have been received up to the current time slot in the current TTI. In an alternate embodiment of the present disclosure, if at least one of the above conditions (e.g., a condition for a valid write rate) is satisfied, the controller 440 determines to perform decoding at the current time slot.

In step 820, the controller 440 determines whether the decoding was successful for the signal received up to the current time slot, depending on the decoding result received from the decoder 430. If the report is successfully decoded, then in step 825, the controller 440 transmits the command signal to the RF processor 410 such that the RF processor 410 is in a low power mode (eg, low during the time period corresponding to the remaining time slot of the current TTT). Signal quality mode) operation. If multiple transmission channels are configured in the receiver, the decoding result may indicate multiple transmission frequencies. Whether the decoding of the channel is successful. If the decoding of all or a predetermined number of delivery channels is successful, the controller 440 transmits an instruction signal to the RF processor 410 to set the low power mode. In an alternate embodiment of the present disclosure, the controller 440 may transmit an instruction signal for stopping or deactivating the RF processor 410 instead of an indication signal indicating a low power mode during the remaining time slot of the current TTI. In another alternative embodiment of the present disclosure, if the decoding is successfully detected before the current TTI expires, the controller 440 may stop the transmission operation for the call or stop the call during the remaining period of the current TTI. Both the transfer operation and the receive operation.

In step 840, the controller 440 determines whether the currently received time slot is the last time slot of the current TTI. If the currently received time slot is the last time slot, the controller 440 terminates the operation. If the currently received time slot is not the last time slot, the controller 440 receives the next time slot in step 845 and then returns to step 810 to determine if the decoding condition of the next time slot is satisfied.

If it is determined in step 810 that the current time slot does not satisfy the early decoding condition, then in step 830, the controller 440 determines whether the currently received time slot is the last time slot of the current TTI. If the currently received time slot is the last time slot, then regardless of whether the early decoding conditions are met, in step 815, the controller 440 controls the decoder 430 to decode the signals that have been received up to the last time slot. However, if the current time slot does not satisfy the early decoding condition and is not the last time slot, then before returning to step 810 to determine early decoding of the next time slot, in step 835, the controller 440 will signal the command signal indicating the normal signal quality mode. Transfer to RF processor 410.

9 is a timing diagram illustrating an operation of determining an early decoding time in accordance with an embodiment of the present disclosure.

Referring to Figure 9, reference numeral 900 denotes a solution for a transport channel having TTI0. Code timing, and reference numeral 920 represents the decoding timing of the transport channel with TTI1. Here, TTI0 is 1/2 of TTI1. The decoder may attempt to decode at each predetermined unit time in one TTI 900 or 920. The unit time is TTI0/N, where N is a positive integer. As an example, the minimum value of TTI0/N can be a time slot.

In the case of a transport channel 900 with TTI0, the decoder can perform up to N decodings in one TTI, and in the case of a transport channel 920 with TTI1, the decoder can perform up to 2N decodings in one TTI. The minimum decoding time at which the decoder can operate can be TTI0/N; the last time of one TTI can be the decoding time 910 or 930 of the normal decoding mode; and the unit time before a TTI expires can be the early decoding times 905 and 925.

In the initial TTI, early decoding can begin at TTI0/N.

FIG. 10 is a flowchart illustrating an operation of determining an early decoding time in accordance with an embodiment of the present disclosure. The illustrated operations may be performed in each TTI by, for example, a wireless terminal having a receiver configured as in FIG.

Referring to Figure 10, in step 1005, the controller 440 directs the decoder 430 to attempt decoding at the pre-stored decoding time in the current TTI. In the first TTI, the decoding time may be a unit time for decoding (eg, a first time slot). In the TTI after the first TTI, the decoding time may be a value stored in the previous TTI.

In step 1010, the controller 440 determines whether the decoding was successful for the signal received up to the specified decoding time, depending on the decoding result received from the decoder 430. If the decoding fails, then in step 1015, decoder 430 receives the signal for the next unit time (e.g., the next time slot) and then attempts to decode. If the decoding is successful, the controller 440 proceeds to step 1020. When a plurality of transport channels are configured in the receiver, if decoding of all or a predetermined number of transport channels is successful, the controller 440 Proceed to step 1020.

In step 1020, the controller 440 measures the number of consecutive successes of decoding in the previous TTI including the current TTI (hereinafter simply referred to as "continuous decoding success count"). In step 1025, the controller 440 determines whether the continuous decoding success count exceeds the predetermined threshold D. The continuous decoding success count can be measured in units of TTI. As an example, if the decoding has succeeded consecutively during the three TTIs prior to the current TTI, the consecutive decoding success count may be four. The threshold may vary depending on the channel environment (eg, Doppler frequency, etc.). If the threshold is set to "1", the decoding time can be updated in each TTI.

If the consecutive decoding success count exceeds the threshold D, then in step 1030, the controller 440 changes the stored decoding time to a time unit time earlier than the stored decoding time TTI0/N (eg, earlier than the stored decoding). Time is a time slot). As an example, if the stored decoding time is time slot k, then in step 1030, controller 440 can change the decoding time to time slot (k-1). If the continuous decoding success count does not exceed the threshold D, then in step 1035, the controller 440 may store information about the time at which the decoder 430 was successfully decoded in the current TTI as the decoding time. The stored decoding time can be used in the next TTI.

If multiple transport channels are configured in the receiver, the operations illustrated in Figure 10 can be performed individually for each transport channel. If the write rate of a particular transport channel is changed, the controller 440 can initialize the decode time of the transport channel.

The embodiment of the present disclosure illustrated in FIG. 10 can be combined with the embodiment of the present disclosure illustrated in FIG. As an example, controller 440 may check for early decoding conditions (as in Figure 10) at each time slot (or each predetermined unit time) from the determined decoding time, rather than at the first time slot from a TTI. Every beginning The time slots determine whether the early decoding conditions are met.

In an embodiment of the present disclosure described below, the decoder determines the decoding time at which early decoding is performed in one TTI, depending on the power loss gain available through early decoding. In an embodiment of the disclosure, the decoding time may be an indicator measured by the terminal (eg, a signal to interference ratio (SIR) of the transport channel or a signal to noise ratio (signal to noise ratio; It is determined by at least one of SNR), the symbol SNR of the pilot channel, and the BLER of the transmission channel.

11 is a timing diagram illustrating the determined early decoding time in accordance with an embodiment of the present disclosure.

Referring to Fig. 11, reference numeral 1100 denotes a decoding timing of a transport channel having TTI0 = 20 msec, and the decoder can attempt to decode at the end time 1110 of one TTI in the normal decoding mode, and try to be in a TTI in the early decoding mode. The predetermined early decoding time 1105 before the expiration is decoded. Reference numeral 1120 denotes a decoding timing of a transport channel having TTI1 = 40 milliseconds, and the decoder may attempt to decode at the end time 1130 of one TTI in the normal decoding mode, and attempt to complete the TTI before the expiration of one TTI in the early decoding mode. The early decoding time 1125 is scheduled for decoding.

For example, the predetermined early decoding time 1105 may be the time at which the BB processor's output for the first 10 milliseconds (eg, one frame) has been fully passed to the decoder. Early decoding time can be changed by the controller. Assuming that the delay time for passing through the BB processor is negligible in the case of successful decoding of the signal for one frame, the controller can output the command signal to the RF processor for the next frame period of about 10 milliseconds. The operating mode of the RF processor is switched to the low signal quality mode. RF processor The operating mode can be adjusted to the normal mode at the start of the next TTI.

If the early decoding of the early decoding mode is performed on multiple transport channels having the same TTI, the controller may output the command signal to the RF processor for decoding failure (eg, CRC bad) in a predetermined number of transport channels The RF processor is adjusted to the normal signal quality mode. In this case, the decoder may perform decoding on the transmission channel whose decoding failed in the previous decoding time or all the transmission channels whose TTI expires in the decoding time of the normal decoding mode (for example, at the end time of one TTI).

FIG. 12 is a timing diagram illustrating a decoding operation for a plurality of transport channels in accordance with an embodiment of the present disclosure.

Referring to FIG. 12, at least one transport channel TrCH0 1220 having TTI=10 milliseconds and at least one transport channel TrCH1 1225 having TTI=20 milliseconds are disposed in the receiver, and the RF processor (ie, RFIC) 1205 is 10 milliseconds. The minimum TTI is the unit operation.

Reference numeral 1230 denotes a decoding time determined according to the normal decoding mode, or a decoding time when early decoding fails in the early decoding mode. Reference numeral 1235 denotes the decoding time of TrCH0 1220 in the early decoding mode, and reference numeral 1240 denotes the decoding time of TrCH1 1225 in the early decoding mode.

At the start of the TTI, the RF processor's operating mode 1210 is set to a normal signal quality mode (eg, high EVM) by a command signal sent from the controller. At decoding time 1245, if the decoding of the symbol for TrCH0 is successful, the operating mode 1210 of the RF processor can be adjusted to a low signal quality mode (eg, low EVM) by a command signal transmitted from the controller. The low signal quality mode can be maintained until the TTI expires, and the RF processor can be used at the beginning of the next TTI The command signal sent from the controller is initialized to the normal signal quality mode. Since the decoding of TrCH0 is successful at decoding time 1245, the decoder does need to decode TrCH0 at decoding time 1250.

At decoding time 1250, the decoder can separately decode the symbols of TrCH0 and TrCH1. If the decoder decodes TrCH0 has failed and the decoding TrCH1 has succeeded, the RF processor's operating mode 1210 can be maintained in the high signal quality mode by transmitting the command signal from the controller. Since the decoder decodes TrCH0 has failed, the decoder can again attempt to decode all of the signals of TrCH0 received in the TTI at decoding time 1260.

13 is a graph illustrating a comparison between a normal decoding mode and an early decoding mode in terms of reception quality of a video channel environment determination, in accordance with an embodiment of the present disclosure. Herein, the channel environment is represented by the symbol SNR and the reception quality is represented by BLER.

Referring to Figure 13, at the same symbol SNR, the BLER0 1310 for the case where the decoder attempts to decode at the end time of one TTI (i.e., the normal decoding mode) is smaller than the case where the decoder attempts to decode at the intermediate time (i.e., early Decoding mode) BLER1 1305. Therefore, the reception quality of the normal decoding mode can be degraded compared to the early decoding mode. Therefore, the controller can use various criteria to determine whether to enable the early decoding mode of the decoder.

As an example, if the reception quality of the transport channel within a certain window (or time period) satisfies certain criteria, the early decoding mode of the decoder can be enabled. As another example, the controller may be based on a block error rate of an early decoding mode (the controller has obtained the block error rate by unconditionally enabling an early decoding mode during a certain window) and based on a pre-calculated power loss gain To determine whether to continue the early decoding mode formula. The power loss gain can be calculated based, for example, on the power loss gain value due to adjusting the operating mode of the RF processor and the power loss increase value caused by the increased number of decoder decodings. As yet another example, if a burst error is detected, the early decoding mode may not be executed until the burst error is released or resolved.

14 is a flow diagram illustrating operation of enabling an early decoding mode in accordance with an embodiment of the present disclosure. The illustrated operations may be performed in each TTI of each transport channel, for example, by a wireless terminal having a receiver configured as in FIG. 4, or may be performed in each predetermined operational cycle including at least one TTI, Or it may be performed irregularly depending on the predetermined trigger condition.

Referring to Figure 14, in step 1405, controller 440 transmits an instruction signal to RF processor 410 to set RF processor 410 to a normal signal quality mode and decoder 430 to a normal decoding mode. In step 1410, controller 440 determines whether to enable the early decoding mode based on the characteristics of each of the transport channels and the power loss gain available via early decoding. If the early decoding mode is not enabled or the gain available via early decoding is extremely low or negligible, then in step 1440, the controller 440 maintains the decoder 430 in the normal decoding mode.

In an embodiment of the present disclosure, if the reception quality of the delivery channel within a previous window satisfies certain criteria, the controller 440 may determine to enable the early decoding mode. In an alternate embodiment of the present disclosure, the controller 440 can be based on a channel quality indicator provided from the BB processor 420 (eg, SNR of a data channel or pilot channel, SIR of a pilot channel, Doppler estimation, channel) A channel delay profile (CDP) detection value, etc.) is used to estimate the reception quality (eg, BLER) of the transport channel during early decoding, and it is determined whether the early decoding mode is enabled depending on the BLER. As an example, if the block error rate of the early decoding mode (the controller is already in a certain window) The controller 440 may determine to enable the early decoding mode if the block error rate is obtained during the period). As another example, the controller 440 can calculate the power loss gain based on the sum of the power loss gain value obtained by the low signal quality mode of the RF processor 410 and the power loss increase value obtained by the early decoding mode of the decoder 430. And, in the case where the power consumption gain exceeds a predetermined threshold, it is determined that the early decoding mode is enabled.

The symbol SNR that has been actually estimated from the controller 440 for the transport channel or pilot channel may be based on information (eg, a graph or table) indicating a relationship between the symbol SNR measured for the transport channel and the BLER of the early decoding mode. Calculate the block error rate for the early decoding mode. Techniques for mapping between effective SNR and BLER are well known in the art.

In an alternate embodiment of the present disclosure, if an occurrence of a burst error is detected from the wireless channel, the controller 440 can enable the early decoding mode and determine to maintain the early decoding mode until the burst error is released. In an alternate embodiment of the present disclosure, the controller 440 enables the early decoding mode based on the information indicated by the upper layer.

If controller 440 determines that the early decoding mode is enabled, then in step 1415, controller 440 operates decoder 430 in an early decoding mode. In step 1420, the decoder 430 performs decoding at a predetermined early decoding time or at an early decoding time indicated by the controller 440 in each TTI of the transport channel configured in the receiver, and will be for each transport channel. The decoding result is provided to the controller 440.

In step 1425, the controller 440 determines whether the reception quality of the delivery channel (the decoder 430 has attempted decoding for the delivery channel) satisfies a predetermined condition. As an example, if the decoding is successful for all or a predetermined number of T transport channels, the controller 440 proceeds to step 1430 to determine that the reception quality is good. At step 1430 The controller 440 transmits an instruction signal to the RF processor 410 to transmit the RF processor 410 to the low signal quality mode during a period corresponding to the remaining time slot of the current TTI. In the next TTI of the transport channel, the RF processor 410 can return to the normal signal quality mode.

If the decoder 430 fails to decode in at least one of the transport channels, or if the number of successfully decoded transport channels is less than the predetermined number T, then in step 1435, the controller 440 transmits an instruction signal to the RF processor 410 to place the RF processor. 410 remains in the high signal quality mode. In one embodiment of the present disclosure, in step 1435, controller 440 can transmit an instruction signal to RF processor 410 to adjust RF processor 410 to a high signal quality mode. The high signal quality mode may include, for example, an EVM that is higher than the low signal quality mode.

In the normal decoding mode, the decoder may attempt to decode at the end of the TTI of each transport channel, and in the early decoding mode, the decoder may attempt to decode at a time prior to the expiration of the TTI of each transport channel. In other words, the decoder can attempt to decode all or some of the transport channels at each time slot.

The embodiment of the present disclosure illustrated in FIG. 14 can be combined with at least one of the embodiments of FIGS. 8 and 10. As an example, controller 440 can determine whether an early decoding mode is enabled during the time period. If the controller 440 determines that the early decoding mode is enabled, the controller 440 can perform early decoding, as in the embodiment of FIG. 8 or 10.

In a particular aspect, various embodiments of the present disclosure can be embodied as computer readable code in a computer readable recording medium. The computer readable recording medium can be any data storage device capable of storing data readable by a computer system. An example of a computer readable recording medium may include read only memory (ROM), Memory access memory (RAM), compact disk-read only memory (CD-ROM), magnetic tape, flexible disk, optical data storage device, and carrier (eg, via the Internet) Data transmission, etc.). The computer readable recording medium can be distributed among computer systems connected to the network so that the computer readable code can be stored and executed in a distributed manner. Functional programs, code and code segments for implementing various embodiments of the present disclosure can be readily interpreted by programmers skilled in the art.

It will be appreciated that devices and methods in accordance with various embodiments of the present disclosure can be implemented by hardware, software, or a combination thereof. The software can be stored in a volatile or non-volatile storage device (for example, an erasable/rewritable ROM or the like), a memory (for example, a RAM, a memory chip, a memory device, a memory IC, or the like). Or an optical/magnetic recordable machine (or computer) readable storage medium (eg, a compact disk (CD), a digital versatile disk (DVD), a magnetic disk, a magnetic tape, or the like). A method in accordance with various embodiments of the present disclosure may be implemented by a computer or mobile terminal including a controller, a memory, a transceiver, and/or at least one antenna. It may be noted that the memory is an example of a machine readable storage medium suitable for storing one or more programs containing instructions for implementing embodiments of the present disclosure.

Accordingly, the disclosure may comprise a program comprising code for implementing a device and/or method as defined by the scope of the appended claims; and a machine (or computer) readable storage medium storing the program . The program can be carried electrically by any medium, such as a communication signal transmitted via a wired or wireless connection.

A device in accordance with various embodiments of the present disclosure can receive and store a program from a program server to which the device is connected by wire or wirelessly. The program server can be included for storing inclusions for allowing the program handling unit to perform set content protection a program of instructions of the method and also a memory for storing information necessary for the content protection method, a communication unit for performing wired/wireless communication with the graphics processing unit, and for requesting via the transceiver automatically or at the request of the graphics processing unit The control of the transfer program.

While the disclosure has been shown and described with respect to the embodiments of the present disclosure, it will be understood by those skilled in the art Various changes in form and detail are made in the context of the spirit and scope.

Claims (5)

An apparatus for utilizing early decoding to reduce power consumption, the apparatus comprising: a baseband processor configured to process a received signal from a radio frequency processor; a decoder configured to decode the baseband An output signal of the processor; and a controller configured to: determine whether a predetermined decoding condition is satisfied after expiration of a time unit in the transmission time interval; and control the decoder when the predetermined decoding condition is satisfied Decoding in an early decoding mode, wherein the decoder performs decoding on the received signal via the time unit in the transmission time interval; when the decoding is successful, transmits an instruction signal to the radio frequency processor Setting to a low power mode during a remaining time period of the transmission time interval after the time unit in the transmission time interval, wherein the low power mode includes a low error vector magnitude for the radio frequency processor, At least one of a stop of a transfer operation of a call, and a stop for transmission of a call and a reception operation; and when said time When the bit is the last time unit in the transmission time interval, regardless of the predetermined decoding condition, the decoder is controlled to wait until the last time unit after expiration of the last time unit of the transmission time interval The signal that has been received so far performs decoding. The apparatus of claim 1, wherein the predetermined decoding condition comprises at least one of: a first condition that is valid for the signal that has been received after expiration of the time unit The code rate is less than the first threshold; a second condition that is satisfied if the link quality calculated at the time unit is greater than or equal to a second threshold; and a third condition that is subsequent to the time unit in the transmission time interval The case where the number of time units is greater than the third threshold is satisfied. The apparatus of claim 1, wherein determining whether the predetermined decoding condition is satisfied comprises initializing the predetermined decoding condition at a time determined based on a decoding result of a previous transmission time interval in the transmission time interval determination. The apparatus of claim 1, wherein the controller is further configured to: at a start time of the transmission time interval, a power loss gain obtainable via early decoding, and before the transmission time interval It is determined whether at least one of the reception qualities during the predetermined period of time determines whether early decoding is performed in the transmission time interval. The apparatus of claim 1, wherein the controller is further configured to: when the decoding is unsuccessful, or when the predetermined decoding condition is not met and the time unit is not the last In time units, an instruction signal is transmitted to the radio frequency processor to maintain the current mode and receive the next time unit of the transmission time interval.