TWI667797B - Solar cell - Google Patents

Abstract

A solar cell has a battery cell, and the battery cell includes a semiconductor substrate, at least two adjacent doped regions, at least one insulating layer, at least two first electrodes, at least one first doped layer and at least one second electrode . Two adjacent doped regions extend from the first surface into part of the semiconductor substrate. The insulating layer covers two adjacent doped regions and part of the first surface of the semiconductor substrate, and the insulating layer has at least two openings, wherein the total area of the openings is A, the total area of the semiconductor substrate is B, and 2% ≦ ((A / B) × 100%) ≦ 9%. The first electrode is disposed on the insulating layer and respectively contacts a part of two adjacent doped regions through the opening. The first doped layer is disposed on the insulating layer and is located between two adjacent first electrodes. The second electrode is disposed on the first doped layer.

Description

Solar battery

The present invention relates to a photoelectric conversion device, and particularly relates to a solar cell.

Nowadays, the energy used by humans mainly comes from oil. However, due to the limited oil resources of the earth, the demand for alternative energy sources has increased day by day in recent years. Among all kinds of alternative energy sources, solar energy has become the green energy with the most development potential.

However, due to high manufacturing costs, complicated manufacturing processes, and poor photoelectric conversion efficiency, the development of solar cells still needs further breakthroughs. Therefore, how to make a solar cell with good photoelectric conversion efficiency is one of the problems that the R & D personnel urgently want to solve.

The invention provides a solar cell with good photoelectric conversion efficiency.

The solar cell of the present invention has at least one battery cell. The battery cell includes a semiconductor substrate, at least two adjacent doped regions, at least one insulating layer, at least two first electrodes, at least one first doped layer, and at least one second electrode. The semiconductor substrate has a first surface and a second surface opposite to the first surface, wherein the semiconductor substrate has a first polarity. At least two adjacent doped regions extend from the first surface into part of the semiconductor substrate, wherein the doped regions have a second polarity and are different from the first polarity. At least one insulating layer covers two adjacent doped regions and part of the first surface, and the insulating layer has at least two openings, the openings respectively expose a part of the two adjacent doped regions, wherein the area of the openings The sum is A, the total area of the semiconductor substrate is B, and 2% ≦ ((A / B) × 100%) ≦ 9%. At least two first electrodes are disposed on the insulating layer and respectively contact a part of two adjacent doped regions through the opening. At least one first doped layer is disposed on the insulating layer and is located between two adjacent first electrodes, wherein the first doped layer has a first polarity. At least one second electrode is disposed on the first doped layer.

Based on the above, in the solar cell of the embodiment of the present invention, the insulating layer covers two adjacent doped regions and part of the first surface, and the first doped layer is disposed on the insulating layer. In this way, the insulating layer can provide a field effect passivation function for the minority carriers in the doped region and the first doped layer, so that the minority carriers are not likely to recombine. In addition, at least two first electrodes are disposed on the insulating layer and respectively contact a part of two adjacent doped regions through the opening, so that the contact resistance of the first electrode and the doped regions can be reduced to improve the filling of the solar cell Fill factor (FF). In addition, the second electrode is disposed on the first doped layer between two adjacent first electrodes, so that the front side of the solar cell (ie, the second surface) will not have a metal that blocks incident light, thereby increasing the photocurrent of the solar cell (J _SC ) value.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below and described in detail in conjunction with the accompanying drawings.

The present invention will be explained more fully below with reference to the drawings of this embodiment. However, the present invention can also be embodied in various forms, and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings will be exaggerated for clarity. The same or similar reference numbers indicate the same or similar elements, and the following paragraphs will not repeat them one by one. In addition, the directional terms mentioned in the embodiments, for example: up, down, left, right, front or back, etc., are only the directions referring to the attached drawings. Therefore, the directional terminology is used to illustrate rather than limit the invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Throughout the specification, the same reference numerals denote the same elements. It should be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “connected to” another element, it can be directly on or connected to the other element, or Intermediate elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to physical and / or electrical connections. However, the electrical connection or coupling may be that there are other elements between the two elements.

As used herein, "about", "approximately", or "substantially" includes the stated value and the average value within the acceptable deviation range of the specific value determined by those of ordinary skill in the art, taking into account the measurement and the measurement in question A certain amount of related errors (ie, measurement system limitations). For example, "about" may mean within one or more standard deviations of the stated value, or within ± 30%, ± 20%, ± 10%, ± 5%. Furthermore, as used herein, "about", "approximately", or "substantially" can be based on optical properties, etching properties, or other properties to select a more acceptable range of deviation or standard deviation, rather than applying one standard deviation to all properties .

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant technology and the present invention, and will not be interpreted as idealized or excessive Formal meaning unless explicitly defined in this article.

Exemplary embodiments are described herein with reference to cross-sectional views that are schematic diagrams of idealized embodiments. Therefore, the illustrated shape change as a result of, for example, manufacturing techniques and / or tolerances can be expected. Therefore, the embodiments described herein should not be construed as being limited to the specific shapes of the regions as shown herein, but include deviations in shapes caused by manufacturing, for example. For example, an area shown or described as flat may generally have rough and / or non-linear characteristics. In addition, the acute angle shown may be round. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the precise shapes of the regions, and are not intended to limit the scope of the claims.

FIG. 1 is a schematic cross-sectional view of a solar cell according to an embodiment of the invention. Please refer to FIG. 1, the solar battery SC has at least one battery unit SCU. In order to clearly show the specific structure of the battery unit SCU, only one battery unit SCU is shown in FIG. 1 as an exemplary embodiment for description, but the present invention is not limited thereto. In other embodiments, the solar cell SC may also have multiple battery cells SCU. The battery cell SCU includes a semiconductor substrate 100, at least two adjacent doped regions 106, at least one insulating layer 108, at least two first electrodes 112, at least one first doped layer 114, and at least one second electrode 116.

The semiconductor substrate 100 has a first surface 102 and a second surface 104 opposite to the first surface 102. In some embodiments, the first surface 102 is the rear side of the solar cell SC, and the second surface 104 is the front side of the solar cell SC. As shown in FIG. 1, the light L irradiates the second surface 104 of the solar cell, so the second surface 104 is also called a light-receiving side. The semiconductor substrate 100 has a first polarity, which may be an N-type semiconductor substrate or a P-type semiconductor substrate. In some embodiments, the first polarity may be N-type. In some embodiments, the first polarity may also be P-type. For N-type or P-type dopants, please refer to the subsequent description. If the solar cell SC is an N-type solar cell, it has the advantages of good minority carrier life and no light attenuation, so it has greater efficiency improvement space and stability. In some embodiments, the material of the semiconductor substrate 100 may include gallium arsenide, germanium, silicon-containing materials, or other suitable materials, or a combination of at least two of the foregoing.

At least two adjacent doped regions 106 extend from the first surface 102 into part of the semiconductor substrate 100. Each doped region 106 has at least one first sub-region 118 and at least one second sub-region 120. In some embodiments, both adjacent doped regions 106 have a second polarity (for example, both the first sub-region 118 and the second sub-region 120 have a second polarity), and the second polarity is different from the first polarity. In this embodiment, if the first polarity can be N-type, the second polarity can be P-type, but the invention is not limited thereto. In some embodiments, if the first polarity can be P-type, the second polarity can be N-type. In some embodiments, the method of forming the doped region 106 may be a patterned ion implantation process on the semiconductor substrate 100, or other suitable methods.

At least one insulating layer 108 covers the doped region 106 and part of the first surface 102. Material of the insulating layer 108 may be silicon oxide (SiO _x), silicon nitride (SiN _x), silicon oxynitride (SiON), yttrium oxide (YO _x), or other suitable materials, or combinations of the foregoing. In some embodiments, the insulating layer 108 has at least two openings 110 that respectively expose a part of the doped region 106. For example, the opening 110 exposes at least a portion of the corresponding second sub-region 120. In some embodiments, the method for forming the insulating layer 108 may be chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable methods.

At least two first electrodes 112 are disposed on the insulating layer 108 and contact a portion of two adjacent doped regions 106 through the openings 110 respectively, so that the contact resistance of the first electrodes 112 and the doped regions 106 can be reduced to improve Solar cell fill factor (FF). The first electrode 112 may be a single-layer or multi-layer structure, and its material may be a conductor material, such as aluminum, silver, platinum, gold, copper, or other suitable materials, alloys of the above materials, or a combination of the above materials. In this embodiment, the first electrode 112 contacts the corresponding second sub-region 120 via the opening 110. It should be noted that if the area of the opening 110 is too large, the field effect passivation effect of the insulating layer 108 is reduced, and it is difficult to reduce the occurrence of minority carrier recombination. Therefore, in some embodiments, when the total area of the opening 110 is A, and the total area of the semiconductor substrate 100 is B, the opening ratio ((A / B) × 100%) is substantially greater than or equal to 2% and substantially The upper limit is less than or equal to 9% (for example: 2% ≦ ((A / B) × 100%) ≦ 9%). In this way, in addition to reducing the contact resistance of the first electrode 112 and the doped region 106, the insulating layer 108 can also provide a sufficient field effect passivation effect, so that the solar cell SC has good photoelectric conversion efficiency. In other embodiments, in the case where the aperture ratio is substantially greater than or equal to 5% and substantially less than or equal to 9% (5% ≦ ((A / B) × 100%) ≦ 9%), the solar cell SC has more Good photoelectric conversion efficiency. It should be noted that in the case where the solar cell SC has a plurality of battery cells SCU, A represents the total opening of the plurality of battery cells SCU, and B represents the total area of the semiconductor substrate SC having a plurality of battery cells SCU.

At least one first doped layer 114 is disposed on the insulating layer 108 and between two adjacent first electrodes 112, wherein the first doped layer 114 has a first polarity. In this way, the insulating layer 108 can provide a field-effect passivation function for the minority carriers in the doped region 106 and the first doped layer 114, so that it is not easy to recombine, thereby increasing the open circuit voltage (V _OC ). In some embodiments, the insulating layer 108 may serve as a tunnel oxide layer (tunnel oxide layer), where the thickness t is greater than 0 nanometers and substantially less than or equal to 10 nanometers (0 nm <t ≦ 10 nm), The probability of electrons passing through the insulating layer 108 increases, so that the photoelectric conversion efficiency of the solar cell SC can be further improved. In addition, since the doped region 106 (which has a second polarity, such as P-type), the semiconductor substrate 100 (which has a first polarity, such as N-type), and the insulating layer 108 provide a heterojunction-like (heterojunction) The structure greatly reduces the saturation current, so it can effectively improve the photoelectric conversion efficiency. In some embodiments, the first doping layer 114 may be formed by chemical vapor deposition or other suitable methods to form a semiconductor material layer on the surface of the insulating layer 108, preferably, a polysilicon layer, Then, an ion implantation process is performed on the above polysilicon layer, and the first doped layer 114 of this embodiment has N-type doping as an example, so it may include N-type dopants such as arsenic, phosphorus, antimony, and other suitable Dopant, or the aforementioned compound, or a combination of the aforementioned, but the invention is not limited thereto. In other embodiments, if the first doped layer 114 has a P-type dopant, for example, aluminum, boron, gallium, other suitable dopants, or the aforementioned compound, or a combination of the aforementioned. In other embodiments, the first doped layer 114 may also be formed on the surface of the insulating layer 108 with the first polarity directly by low pressure chemical vapor deposition (LPCVD) or other suitable methods.的 第一 不可 层 114。 The first doped layer 114. In other embodiments, the first doped layer 114 may be formed on the surface of the insulating layer 108 after the amorphous silicon layer is formed, and then the amorphous silicon layer is recrystallized by laser annealing, heating annealing, or other suitable methods Form a polysilicon layer, and then ion implantation process.

In some embodiments, the first doped layer 114 and the semiconductor substrate 100 have substantially the same polarity, and the resistance of the first doped layer 114 is smaller than the resistance of the semiconductor substrate 100. In this way, the first doped layer 114 can be used as a back side field (BSF) device to improve the open circuit voltage, thereby improving the photoelectric conversion efficiency of the solar cell SC. In addition, the doped region 106 and the first doped layer 114 and the semiconductor substrate 100 have different polarities (for example, the doped region 106 may be P-type; both the first doped layer 114 and the semiconductor substrate 100 may be N-type), It can be used as the emitter of the solar cell SC. In some embodiments, the doping concentration of the first doping layer 114 is greater than the doping concentration of the semiconductor substrate 100. In some embodiments, the first doped layer 114 includes polysilicon, which can further enhance the field effect passivation effect to improve the open circuit voltage, so that the photoelectric conversion efficiency of the solar cell SC can be improved. In addition, because the minority carrier lifetime (MCLT) of N-type doped polysilicon is greater than that of P-type doped polysilicon, and the hidden open circuit voltage (iVoc) is also higher, the passivation effect of N-type doped polysilicon is higher than that of P It is good to do polysilicon, but not limited to this.

In some embodiments, the first sub-region 118 of the doped region 106 may be adjacent to the first doped layer 114, and the second sub-region 120 thereof is far away from the first doped layer 114, preferably, the second sub-region The resistance value of 120 may be less than the resistance value of the first sub-region 118, the resistance value of the semiconductor substrate 100 and the resistance value of the first doped layer 114, and the resistance value of the first doped layer 114 is less than the resistance value of the semiconductor substrate 100. In this way, minority carriers tend to be transferred from the second sub-region 120 to the first doped layer 114 through the first sub-region 118, so that the conduction efficiency of the minority carrier can be improved by shortening the travel path of the minority carrier. In some embodiments, the first doped layer 114 does not overlap two adjacent doped regions 106, for example, the first sub-region 118 is between the second sub-region 120 and the first doped layer 114, which can be avoided The problem of poor photoelectric conversion efficiency caused by too many PN junctions.

At least one second electrode 116 is disposed on the first doped layer 114. In this way, both the first electrode 112 and the second electrode 116 are provided on the back side of the solar cell SC (for example: the first surface 102), so that the front side of the solar cell SC (for example: the second surface 104) will not block the incident The metal of the light L, in turn, enhances the photocurrent (J _SC ) value of the solar cell. The second electrode 116 may have a single-layer or multi-layer structure, and the material thereof may be a conductor material, such as aluminum, silver, platinum, gold, copper, or other suitable materials, alloys of the foregoing materials, or a combination of the foregoing materials.

In some embodiments, at least one second doped layer 122 having a first polarity (eg, having substantially the same polarity as the semiconductor substrate 100) can be selectively disposed on the second surface 104, and its resistance value is less than The resistance of the semiconductor substrate 100 (for example, the doping concentration of the second doping layer 122 is greater than the doping concentration of the semiconductor substrate 100). In this way, the second doped layer 122 can function as a front surface field (FSF) element, so that the second doped layer 122 can guide minority carriers from the FSF element into the semiconductor substrate 100, thereby enhancing The photoelectric conversion efficiency of the solar cell SC. In some embodiments, the method for forming the second doped layer 122 may be an ion implantation process on the second surface 104 of the semiconductor substrate 100. In other embodiments, the second doped layer 122 may also be formed on the second surface 104 of the semiconductor substrate 100 by CVD or other suitable methods. Furthermore, in order to increase the light incident amount of the solar cell SC, in some embodiments, a plurality of uneven microstructures may be selectively formed on the surface (eg, top surface) of the second doped layer 122 away from the semiconductor substrate 100 (As shown in Figure 1). In some embodiments, the textured microstructure can be formed by a textured process, but the invention is not limited thereto. In some embodiments, the uneven microstructure may be a suede structure.

In addition, in some embodiments, at least one reflective layer 124 can be selectively disposed on the uneven microstructure, so that the photocurrent (J _SC ) value can be increased by increasing the amount of incident light. The anti-reflection layer 124 may be a single-layer or multi-layer structure, and its materials include silicon nitride, silicon oxide, silicon oxynitride, zinc oxide, titanium oxide, indium tin oxide, indium oxide, bismuth oxide, and tin oxide ( tin oxide, zirconium oxide, hafnium oxide, antimony oxide, gadolinium oxide, or other suitable materials, or a combination of the foregoing materials.

FIG. 2 is a comparison diagram of the aperture ratio, photocurrent, and open circuit voltage of a solar cell according to an embodiment of the invention.

Referring to FIG. 2, it can be seen that as the aperture ratio is higher, the contact resistance between the first electrode 112 and the doped region 106 is lower, so the photocurrent value (unit: mA / cm ² ) is also getting higher and higher. However, when the aperture ratio is greater than about 6%, the magnitude of the photocurrent gradually decreases as the aperture ratio increases. In addition, it can be seen that as the aperture ratio is higher, the field effect passivation effect of the insulating layer 108 is lower, so the open circuit voltage (unit: V) is also getting smaller and smaller.

FIG. 3 is a comparison diagram of the aperture ratio, fill factor and conversion efficiency of a solar cell according to an embodiment of the invention.

Please refer to FIG. 3, when the aperture ratio is about 0%, the fill factor (for example: FF value, unitless) is about 78.5%; the photoelectric conversion efficiency (unitless) is about 23.7%, and the aperture ratio is about greater than At 0%, the FF value increases to approximately 81.5%, and the photoelectric conversion efficiency increases to approximately 23.9%. However, as the aperture ratio gradually increases, the FF value also gradually decreases, and the magnitude of the photoelectric conversion efficiency gradually decreases as the aperture ratio increases. When the aperture ratio is greater than about 9%, the FF value is reduced to about 78%, and the photoelectric conversion efficiency is reduced to about 23.4%, both of which are smaller than the case where the aperture ratio is about 0%. It can be seen that when the aperture ratio is substantially greater than or equal to 2% and substantially less than or equal to 9% (for example: 2% ≦ ((A / B) × 100%) ≦ 9%), the solar cell SC can have a good Photoelectric conversion efficiency. Furthermore, as shown in FIG. 3, when the aperture ratio is substantially equal to or greater than 5% and substantially equal to or less than 9%, the solar cell SC has better photoelectric conversion efficiency.

Hereinafter, the features of the present invention will be described more specifically with reference to Example 1 and Comparative Examples 1 to 3. Although the following embodiments are described, the materials used, their amounts and ratios, processing details, processing flow, etc. can be appropriately changed without exceeding the scope of the present invention. Therefore, the present invention should not be limitedly interpreted by the embodiments described below. 4 to 6 are schematic cross-sectional views of Comparative Examples 1 to 3, respectively.

Examples 1

Embodiment 1 is the solar cell of the above embodiment (as shown in FIG. 1), and its aperture ratio is about 5%. In other words, the area of the insulating layer 108 (for example, a tunnel oxide layer with a thickness of about 1 nm) accounts for about 95% of the total area of the semiconductor substrate 100.

Comparative example 1

4, the solar cell 10 of Comparative Example 1 includes an N-type semiconductor substrate 200, a P-type lightly doped region 202, a P-type heavily doped region 204, a first electrode 206, a tunneling oxide layer 208, and an N-type heavily doped The hetero-amorphous silicon layer 210, the second electrode 212, and the anti-reflection layer 214. The first electrode 206 is disposed on the light-receiving surface of the solar cell 10, which is in contact with the P-type heavily doped region 204; and the second electrode 212 is disposed on the back side of the solar cell 10, which is in contact with the N-type heavily doped amorphous silicon layer 210 contact. That is, the first electrode 206 and the second electrode 212 are respectively disposed on opposite sides of the N-type semiconductor substrate 200. In addition, the tunnel oxide layer 208 is disposed between the N-type semiconductor substrate 200 and the N-type heavily doped amorphous silicon layer 210, and the tunnel oxide layer 208 (thickness is about 1 nm) does not have an opening. That is, the aperture ratio of Comparative Example 1 is 0%, that is, the area of the tunnel oxide layer 208 accounts for 100% of the total area of the semiconductor substrate 200. The anti-reflection layer 214 is disposed on the uneven microstructure of the P-type lightly doped region 202.

Comparative example 2

5, the solar cell 20 of Comparative Example 2 includes an N-type semiconductor substrate 300, an N-type heavily doped region 302, a P-type heavily doped region 304, a first electrode 306, a second electrode 308, an oxide layer 310, a front The surface electric field element 312 and the anti-reflection layer 314. The first electrode 306 and the second electrode 308 are separately disposed on the back side of the solar cell 20, and the two are in contact with the N-type heavily doped region 302 and the P-type heavily doped region 304 in the N-type semiconductor substrate 300, respectively. An oxide layer 310 (thickness approximately 72 nm) is provided between the first electrode 306 and the second electrode 308. That is, Comparative Example 2 does not have a tunnel oxide layer. The front surface electric field element 312 is provided on the light-receiving surface of the solar cell 20, and the anti-reflection layer 314 is provided on the uneven microstructure of the front surface electric field element 312.

Comparative example 3

6, the solar cell 30 of Comparative Example 3 includes an N-type semiconductor substrate 400, a P-type heavily doped polysilicon layer 402, an N-type heavily doped polysilicon layer 404, a first electrode 406, a second electrode 408, tunneling oxidation The layer 410, the front surface electric field element 412, and the anti-reflection layer 414. The first electrode 406 and the second electrode 408 are separately disposed on the back side of the solar cell 30, and both are in contact with the N-type heavily doped polysilicon layer 404 and the P-type heavily doped polysilicon layer 402, respectively. The tunnel oxide layer 410 (thickness is about 1 nm) is disposed between the N-type semiconductor substrate 400 and the P-type heavily doped polysilicon layer 402 and the N-type heavily doped polysilicon layer 404, and the tunnel oxide layer 410 has no opening. That is, the aperture ratio of Comparative Example 3 is 0%, that is, the area of the tunnel oxide layer 410 accounts for 100% of the total area of the N-type semiconductor substrate 400. The front surface electric field element 412 is provided on the light-receiving surface of the solar cell 30, and the anti-reflection layer 414 is provided on the uneven microstructure of the front surface electric field element 412.

The photocurrent (J _SC , unit: mA / cm ² ), open circuit voltage (V _OC , unit: V) and fill factor (FF, no unit) were tested for the above Example 1 and Comparative Examples 1 to 3, The photoelectric conversion efficiency (Eff, unitless) can be obtained by Equation 1 below. The experimental results are shown in Table 1. [Formula 1]

[Table 1] Example 1 Comparative example 1 Comparative example 2 Comparative Example 3 The ratio of the area of the tunneling oxide layer to the total area of the semiconductor substrate (%) 95 100 NA 100 Photocurrent (mA / cm ² ) 42.15 41.33 42.37 42.37 Open circuit voltage (V) 0.707 0.696 0.688 0.712 Fill factor (%) 81.16 80.89 81.12 78.69 Photoelectric conversion efficiency (%) 24.2 23.26 23.65 23.75

It can be seen from Table 1 that although the photocurrent of Example 1 is slightly smaller than that of Comparative Examples 1 to 3, the open circuit voltage is greater than that of Comparative Examples 1 and 2 and is slightly smaller than that of Comparative Example 3. In addition, the fill factor of Example 1 is greater than that of Comparative Examples 1 to 3. In this way, the solar cell obtained in Example 1 still has the highest photoelectric conversion efficiency after the photoelectric conversion efficiency calculated by Equation 1.

In summary, in the solar cell of the above embodiment, the insulating layer covers two adjacent doped regions and part of the first surface, and the first doped layer is disposed on the insulating layer. In this way, the insulating layer can provide a field effect passivation function for the minority carriers in the doped region and the first doped layer, making it less likely to recombine. In addition, at least two first electrodes are disposed on the insulating layer and respectively contact a part of two adjacent doped regions through the opening, so that the contact resistance of the first electrode and the doped regions can be reduced to improve the filling of the solar cell factor. In addition, the second electrode is disposed on the first doped layer between two adjacent first electrodes, so that the front side of the solar cell (for example: the second surface) will not have a metal that blocks the incident light, thereby enhancing the light of the solar cell Current value.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

SC, 10, 20, 30: solar cell SCU: battery cell 100: semiconductor substrate 102: first surface 104: second surface 106: doped region 108: insulating layer 110: openings 112, 206, 306, 406: first Electrode 114: first doped layer 116, 212, 308, 408: second electrode 118: first sub-region 120: second sub-region 122: second doped layer 124, 214, 314, 414: anti-reflection layer 200 , 300, 400: N-type semiconductor substrate 202: P-type lightly doped region 204: P-type heavily doped region 208, 410: tunneling oxide layer 210: N-type heavily doped amorphous silicon layer 302: N-type heavily doped Impurity region 304: P-type heavily doped region 310: oxide layers 312, 412: front surface electric field elements 402: P-type heavily doped polysilicon layer 404: N-type heavily doped polysilicon layer L: light t: thickness

FIG. 1 is a schematic cross-sectional view of a solar cell according to an embodiment of the invention. FIG. 2 is a comparison diagram of the aperture ratio, photocurrent, and open circuit voltage of a solar cell according to an embodiment of the invention. FIG. 3 is a comparison diagram of the aperture ratio, fill factor and conversion efficiency of a solar cell according to an embodiment of the invention. 4 to 6 are schematic cross-sectional views of solar cells of Comparative Examples 1 to 3, respectively.

Claims (13)

A solar cell has at least one battery cell, and the at least one battery cell includes: a semiconductor substrate having a first surface and a second surface opposite to the first surface, wherein the semiconductor substrate has a first polarity; At least two adjacent doped regions extending from the first surface into part of the semiconductor substrate, wherein the doped regions all have a second polarity, and the second polarity is different from the first polarity; at least one An insulating layer covering the two adjacent doped regions and part of the first surface, and the insulating layer has at least two openings, the openings respectively expose a part of the two adjacent doped regions , Where the total area of the openings is A, the total area of the semiconductor substrate is B, and 2% ≦ ((A / B) × 100%) ≦ 9%; at least two first electrodes are provided on the insulating layer And respectively contact a part of the two adjacent doped regions through the openings; at least a first doped layer is disposed on the insulating layer and is located between the two first electrodes, wherein the first doped The impurity layer has the first polarity; and at least a second electrode, provided On the first doped layer. The solar cell as described in item 1 of the patent application scope, where 5% ≦ ((A / B) x100%) ≦ 9%. The solar cell as described in item 1 of the patent application range, wherein the resistance value of the first doped layer is less than the resistance value of the semiconductor substrate. The solar cell as described in item 1 of the patent application range, wherein the first doped layer does not overlap the two adjacent doped regions. The solar cell as described in item 1 of the patent application range, wherein the first doped layer includes polysilicon. The solar cell as described in item 1 of the patent application range, wherein the insulating layer includes an oxide layer, and the thickness of the oxide layer is t, and 0 nm <t ≦ 10 nm. The solar cell as described in item 1 of the patent application range, wherein each of the two adjacent doped regions has at least a first sub-region and at least a second sub-region, and the resistance value of the second sub-region is less than the The resistance of the first sub-region. The solar cell as described in item 7 of the patent application range, wherein the openings respectively expose at least a portion of the second sub-regions, and the first electrodes respectively contact the second sub-regions through the openings . The solar cell as described in item 7 of the patent application range, wherein the resistance values of the second sub-regions are smaller than the resistance value of the semiconductor substrate and the resistance value of the first doped layer. The solar cell as described in item 7 of the patent application range, wherein the first sub-regions are adjacent to the first doped layer, and the second sub-regions are remote from the first doped layer. The solar cell according to any one of claims 1 to 7, wherein the at least one battery cell further includes: at least one second doped layer disposed on the second surface, wherein the second The doped layer has the first polarity, and the resistance of the second doped layer is smaller than the resistance of the semiconductor substrate. The solar cell as described in item 11 of the patent application range, wherein the second doped layer has a plurality of uneven microstructures. The solar cell as recited in item 12 of the patent application range, wherein the at least one battery cell further includes: at least one anti-reflection layer disposed on the uneven microstructures.