TWI659423B - Flash memory apparatus and storage management method for flash memory - Google Patents

Abstract

A flash memory storage management method includes: providing a flash memory module, the flash memory module comprising a plurality of single-level unit data blocks and at least one multi-level unit data block; The data is classified into plural group data; performing single-level unit data writing and performing an error correction encoding operation similar to a fault-tolerant disk array to generate a corresponding check code, so as to convert the plural group data and the corresponding check code. Write to the single-level unit data blocks; when the writing of the single-level unit data blocks is completed, perform internal copying, the plural group data stored in the single-level unit data blocks, and the correspondence The check code is sequentially written into the at least one multi-level unit data block according to the storage order of the single-level unit data blocks.

Description

Flash memory device and flash memory storage management method

The present invention relates to a flash memory device, and more particularly, to a flash memory device and a storage management method that perform an error correction encoding operation similar to a fault-tolerant disk array.

Generally speaking, for a flash memory controller to perform data writing to write a single piece of data to a single-level unit data block or a multi-level unit data block, the traditional mechanism is used, for example, in a data block. On the last page of the character line, check codes corresponding to other data pages of the character line are placed, so that when a write failure occurs, the character line is open, and the character line is shorted, the corresponding check code can be used to perform Some degree of error correction, however, such a data storage rate is too low. For example, if a character line includes 8 data pages, only 7 data pages are used to store data, and another data page is used to store school data. Check the code. In this way, 1/8 of a data block will be used to store the check code, not to store the data. From the perspective of the user, it cannot be accepted.

Therefore, one of the objectives of the present invention is to provide a flash memory device and a corresponding flash memory storage management method, which adopts an error correction encoding operation similar to a fault-tolerant disk array to reduce the occurrence rate of errors and the conventional mechanism. The number of check codes that need to be used, and the required check codes should be appropriately stored in the corresponding data page location, so that the required check can still be used when a write failure occurs, the character line is open, and the character line is shorted. Code to correct errors to some extent, which solves the above problem.

According to an embodiment of the invention, a flash memory device is disclosed. The flash memory device includes a flash memory module and a flash memory controller. The flash memory module includes a plurality of single-level unit data blocks and at least one multi-level unit data block. The flash memory The controller has multiple channels respectively connected to the flash memory module. The flash memory controller classifies a piece of data to be written into a plurality of groups of data, and the flash memory controller performs single-level unit data writing. Entering and performing an error correction encoding operation similar to a fault-tolerant disk array generates a corresponding check code to write the data of the complex group and the corresponding check code to a plurality of single-level unit data blocks; when the complex number is completed When writing single-level unit data blocks, the flash memory module performs internal copying to copy the data of the plural groups stored in the multiple single-level unit data blocks and the corresponding check code, according to the sequence of the data. Sequentially move and write to at least one multi-level cell data block.

According to an embodiment of the present invention, a flash memory storage management method is further disclosed. The method includes: providing a flash memory module, the flash memory module including a plurality of single-level unit data blocks and at least one multi-level unit data block; classifying a piece of data to be written into a plurality of numbers Group data; performing single-level unit data writing and performing an error correction encoding operation similar to a fault-tolerant disk array to generate a corresponding check code to write the data of the complex group and the corresponding check code to The plurality of single-level unit data blocks; when the writing of the plurality of single-level unit data blocks is completed, an internal copy is performed, the data of the plurality of groups stored in the plurality of single-level unit data blocks, and The corresponding check code is sequentially transferred and written to the at least one multi-level unit data block according to the sequence of the data.

Please refer to FIG. 1, which is a schematic diagram of a flash memory device 100 according to an embodiment of the present invention. The flash memory device 100 includes a flash memory module 105 and a flash memory controller 110. The flash memory module 105 is a flash memory module having a two-dimensional planar structure; however, this is not the case. limit. The flash memory module 105 includes multiple flash memory chips (not shown in FIG. 1). Each flash memory chip includes multiple single-level cell (SLC) data blocks. block) and multiple-lelve-cell blocks, each unit of a single-level unit data block can store 2 bits of data, and each unit of a multi-level unit data block can store 2 ^N For bit data, N is greater than or equal to 2 and is an integer. For example, a multi-level cell data block includes a MLC block (multi-level cell block), which can store 2 ^2- bit data, and a TLC block (triple-level). Cell block) can store 2 ³ yuan of data, QLC block (quad-level cell block) can store 2 ⁴ bits of data, and so on.

The flash memory controller 110 can be connected to the flash memory module 105 through a plurality of channels, so that different channels can be used to write data to different flash memory chips at the same time, increasing the writing efficiency. The controller 110 includes an error correction code encoding circuit 1101 and a parity check code buffer 1102. The error correction code encoding circuit 1101 is configured to encode data with an error correction code, for example, in the embodiment of the present case. Including Reed-Solomon codes (Reed-solomon codes) encoding operation and / or exclusive-OR (XOR) operation encoding operation to generate the corresponding check code, check code buffer 1102 is used The corresponding check code generated is temporarily stored, and the flash memory controller 110 uses a data management mechanism similar to a Redundant Array of Independent Disks (RAID) to write a piece of data to different Flash memory chip to reduce the error rate, and when writing data to the single-level unit data block, the check code of different encoding operations is also considered in the storage location of the single-level unit data block. It is located and stored in the TLC data block, so that when writing data to the single-level unit data block, data errors can be corrected and subsequent flash memory modules 105 are internally copied from the single-level unit area. It is also possible to correct data errors when copying and moving data to TLC data blocks.

In practice, in order to improve the efficiency of data writing and reduce the error rate, the flash memory module 105 includes multiple channels (the embodiment in this case is two channels, but not limited). When one channel executes a certain data page (Page) writing, another channel can be used to perform writing of another data page without waiting for the channel. Each channel has its own sequencer in the flash memory controller 110. ) And each contains multiple flash memory chips (the embodiment in this case is two chips, but not limited), so that one channel can simultaneously write different data pages to multiple flash memory chips without Need to wait for one of the chips. In addition, each flash memory chip can have a folded design with two different planes, so that a flash memory chip can use different data at the same time when writing data. Two data blocks on two planes are used to perform writing of different data pages without waiting for one of the data blocks. Therefore, a super block of the flash memory module 105 is composed of multiple data pages of multiple flash memory chips of multiple channels. The above-mentioned flash memory controller 110 writes data in units of super data blocks, and first writes data to a single-level unit data block in the flash memory module 105. The unit data block is buffered, and then the data is copied and moved from the single-level unit data blocks to the TLC data blocks. In addition, it should be noted that in other embodiments, each flash memory chip may not have a folding design, that is, a flash memory chip uses a data block to execute a data page when writing data. Write, other data pages need to wait for writing.

As far as the data writing process is concerned, a piece of data will be written into multiple single-level unit data blocks 1051A ~ 1051C by the flash memory controller 110, and then moved from these single-level unit data blocks 1051A ~ 1051C. To the multi-level unit data block 1052, for example, in this embodiment, the TLC unit is used as an example of the multi-level data block structure. The TLC unit can store ²³ bits of information, that is, three single-level unit data Block (hereinafter referred to as the SLC data block) data of 1051A ~ 1051C will be written to a TLC data block 1052. Based on this, considering the need to jointly write the SLC data blocks 1051A ~ 1051C and the TLC data area Block 1052 is written for error correction protection. The flash memory controller 110 classifies a piece of data into three groups of data. It should be noted that if it is a multi-layer data block based on the MLC unit for example, due to the MLC unit can store ²² bits of information, the flash memory controller 110 of the series will be classified as two groups of data, and if the department to QLC unit data block is a multi-layer architecture For example, because the QLC unit can be stored 2 ⁴ bits of information, so the flash memory controller 110 classifies the data into four groups of data; and so on. That is, when the unit of the multi-level cell data block 1052 can store 2 ^N bits of information, N is greater than or equal to 2 and is an integer, and the number of single-level cell data blocks will be designed as N SLC data blocks. The flash memory controller 110 classifies the data to be written into data of N groups to write to N SLC data blocks respectively.

In this embodiment, after the flash memory controller 110 classifies the data into three groups of data, it will then execute the first data write (SLC program) to write the data of the first group into the above. The first SLC data block 1051A and the corresponding correction code generated by the error correction code encoding circuit 1101 are written into the first SLC data block 1051A. This completes the writing operation of the SLC data block, and thereafter The flash memory controller 110 then executes a second data write (SLC program) to write the second group of data into the second SLC data block 1051B and generates a corresponding check using the error correction code encoding circuit 1101. The code is written to the second SLC data block 1051B, so that the second write operation of the SLC data block is completed, and the flash memory controller 110 then performs the third data write (SLC program) write the third group of data into the third SLC data block 1051C and generate a corresponding check code using the error correction code encoding circuit 1101 and write it into the third SLC data block 1051C. Third SLC Feed block write operation.

When the flash memory controller 110 executes a certain data write (SLC program) to write a certain group of data to a certain SLC data block, or after the data write, the flash memory controller 110 will Detect if there is an error, if there is an error in the data, such as a write fail (program fail), one word line open, and / or two word short (two word line) line short), the flash memory controller 110 will use the corresponding check code generated by the error correction code encoding circuit 1101 when the data is written to correct the above errors.

When the data of the aforementioned three groups are written to three SLC data blocks, when the data writing of 1051A ~ 1051C or a certain SLC data block is completed, the flash memory module 105 performs internal copying. Copy and move three groups of data or a group of data in some SLC data blocks 1051A ~ 1051C or one SLC data block and perform data writing (TLC program) to a TLC data area in the order of the data of the three groups Block 1052 (that is, the aforementioned super data block), the TLC data block 1052 is composed of data pages of word lines of different flash memory chips of different channels, for example, one character of the TLC data block 1052 A data page of the line includes an upper page, a middle page, and a lower page. The internal copy of the flash memory module 105 is, for example, an SLC data area in order. Multiple data pages on the Nth character line of the block are written to multiple upper data pages on one character line of the TLC data block 1052, and multiple data pages on the N + 1 character line of the SLC data block Data pages written to the same character line of TLC data block 1052 Multiple intermediate data pages of the SLC data block, and multiple data pages on the N + 2 character line of the SLC data block to multiple lower data pages on the same character line of the TLC data block 1052. After the data of all three groups are written to the TLC data block 1052, the writing operation of the super data block is completed.

It should be noted that in order to make the internal copy easy to implement, comply with the randomizer seed rule requirements of TLC data block 1052, and consider the error correction coding ability to reduce the error rate, the internal copy operation is only based on the data The data is moved to the upper, middle, and lower data page positions of the multiple character lines in the TLC data block 1052. The flash memory controller 110 writes data of different groups and correspondingly generates a check. When the code reaches these SLC data blocks 1051A ~ 1051C, according to the random number seed rule requirements of the TLC data block and the write storage location of the check code that considers the error correction code, the error corrects the error of the code encoding circuit 1101. The correction coding capability can correct errors caused by a write failure of the SLC data block, a broken one-character line, and / or a short-circuited two-character line when performing a write operation of the SLC data block, and can execute the super Correct the errors caused by the write failure of TLC data block 1052, the broken one-word line, and / or the short-circuited two-word line during the writing operation of the data block.

In addition, if the flash memory module 105 performs memory garbage collection, the flash memory controller 110 reads the data from the SLC data blocks 1051A ~ 1051C through external reading and re-reads the data. Perform error correction coding to perform data writing (SLC program), and / or read data from TLC data block 1052 and perform error correction coding again to perform data writing (SLC program). In addition, when writing data (SLC program) to an SLC data block and a sudden shutdown occurs, the flash memory controller 110 reads back data from the SLC data block and re-encodes and corrects the error correction. (SLC program) to another new SLC data block. In addition, if a TLC program is written to the TLC data block 1052 and a sudden shutdown occurs, the flash memory module 105 discards the data currently stored in the TLC data block 1052 and removes the data from the SLC. In blocks 1051A to 1051C, TLC data is written into the corresponding TLC data block 1052 again by internal copying.

Please refer to FIG. 2. FIG. 2 is a flash memory controller 110 shown in FIG. 1 of the first embodiment of the present invention to execute an SLC data write (SLC program) to write a group of data to the flash memory. A schematic diagram of performing an SLC data block write operation on one SLC data block in the module 105. The error correction code encoding circuit 1101 of the flash memory controller 110 performs a Reed Solomon (RS) encoding operation on the data using a similar fault-tolerant disk array to generate a corresponding check code. The checksum buffer 1102 is used to temporarily store the corresponding checksum generated.

The flash memory module 105 includes two channels, and includes two flash memory chips and two sets of blocks of each chip have two different planes. For writing efficiency, the flash memory controller 110 It writes data to two blocks of two flash memory chips in the flash memory module 105 through two channels. As shown in the embodiment in FIG. 2, an SLC data block includes, for example, 128 character lines (represented by WL0 to WL127, respectively). The SLC data block may be an SLC data block or a group of The composition of the SLC sub-data block varies depending on the definition of the SLC data block. For the convenience of description, the embodiment includes 128 character lines as the size of an SLC data block, where each character line includes For example, there are 8 data pages. Taking the first word line WL0 of the SLC data block as an example, the flash memory controller 110 writes the data pages P1 and P2 to the channel CH0 and the folding planes PLN0 and PLN1. Flash memory chip CE0, then the data page P3, P4 is written to another flash memory chip CE1 by the same channel CH0 and the folding planes PLN0, PLN1, and then by another channel CH1 and the folding planes PLN0, PLN1 The data pages P5 and P6 are written to the flash memory chip CE0, and then the data pages P7 and P8 are written to the flash memory chip CE1 through the channel CH1 and the folding planes PLN0 and PLN1. The rest can be deduced by analogy.

The flash memory controller 110 is to classify multiple M word lines WL0 to WL127 of a SLC data block in order into a group of each M word lines, where M is a positive integer greater than or equal to 2, for example, M Is 3, for example, the character lines WL0 ~ WL2 are the first group, the character lines WL3 ~ WL5 are the second group, the character lines WL6 ~ WL8 are the third group, and the character lines WL9 ~ WL11 are the fourth group ... The element lines WL120 ~ WL122 are the penultimate group, the character lines WL123 ~ WL125 are the penultimate group, and the last group of character lines are WL126, WL127, among which the characters of the first, third, fifth groups, etc. The lines are odd array character lines, and the second, fourth, sixth group, etc. character lines are even array character lines. The flash memory controller 110 writes data of one set of character lines at a time. (Including the data of the three character lines), using the error correction code encoding circuit 1101 to perform error correction encoding on the data of the group of character lines, and output the corresponding parity code of the corresponding part to The check code buffer 1102 stores a part of the check code temporarily.

The check code buffer 1102 stores the check code corresponding to the odd array character line data in a first buffer 1102A, and stores the check code corresponding to the odd array character line data in the temporary storage part of the check code. Part of the check code is stored in a second buffer 1102B. For example, when writing the data pages P1 to P24 of the character lines WL0 to WL2, the error correction code encoding circuit 1101 performs an error on the data pages P1 to P24. Correct the code, and output the corresponding check code to the check code buffer 1102, and temporarily store it in the first buffer 1102A; then write the data pages P1 to P24 of the word lines WL3 to WL5, The error correction code encoding circuit 1101 performs error correction encoding on the data pages P1 to P24, and outputs the corresponding check code generated to the check code buffer 1102, which is temporarily stored in the second buffer 1102B; When the data pages P25 to P48 of the character lines WL6 to WL8 are written, the error correction code encoding circuit 1101 performs error correction encoding on the data pages P25 to P48, and outputs the corresponding part of the check code to the check. The code buffer 1102 is temporarily stored in the first buffer 1102A; The data page writing and encoding operations are performed by analogy, etc .; when the data page of the character line WL120 ~ WL122 is written, the error correction code encoding circuit 1101 performs encoding on the data page of the character line WL120 ~ WL122, and The generated corresponding check code is output to the check code buffer 1102 and temporarily stored in the first buffer 1102A.

Next, when the flash memory controller 110 writes the last set of character lines (WL123 ~ WL125) of the even array character lines, in addition to executing the data writing (SLC program) and corresponding error correction coding, it also Read back some check codes of the data of all the even array character lines temporarily stored in the second buffer 1102B, and write all the check codes corresponding to the data of the even array character lines to the last even array of characters. The data page of the last character line WL125 of the meta line, such as the last 3 data pages (labeled 205), stores the Reed-Solomon check code corresponding to the data of the even array character line.

In addition, when writing the last character line WL127 of the last set of odd array character lines, the flash memory controller 110 will execute the SLC program and the corresponding error correction encoding, and the first Partial check codes of all the data of the odd array character lines temporarily stored in the buffer 1102A are read back, and all the check codes corresponding to the data of the odd array character lines are written to the last set of odd array character lines. The data page of the last character line WL127, such as the last 3 data pages (marked 210), stores the Reed-Solomon check code corresponding to the data of the odd array character line. This completes the writing of the SLC data block. Therefore, for the Reed-Solomon encoding operation, the check code corresponding to the data of the odd array character lines is stored in the last plurality of data pages of the last character line WL127 of the last set of odd array character lines. Position, and the check code corresponding to the data of the even array character line is stored in the position of the last plural data pages of the last character line WL125 of the last even array character line.

In addition, the error correction code encoding circuit 1101 in the embodiment shown in FIG. 2 performs a Reed-Solomon encoding operation, which can correct an error of a data page occurring at any three positions of the SLC data block. For example, The error correction code encoding circuit 1101 performs error correction encoding on the data of the three character lines of the character lines WL0 to WL2 and generates a corresponding partial check code. If three data pages of the same folding plane of the same chip of the same channel are used An error occurs, for example, the data pages P1, P9, and P17 are erroneous. The error correction code encoding circuit 1101 may use the corresponding partial check code generated to correct the errors of the three data pages.

If a program fail is detected during the writing of the SLC data block, for example, in terms of occurrence probability, for example, a data page P9 write failure is detected, the error correction code encoding circuit 1101 may Use the corresponding part of the check code to correct the error on the data page P9.

If it is detected that one word line open occurs during the writing of the SLC data block, such as a data page P9 error, the error correction code encoding circuit 1101 can use the corresponding part generated Check code to correct the error on the data page P9.

If it is detected that a two-word line short occurs during the writing of the SLC data block, for example, the data pages P9 and P17 are both wrong, the error correction code encoding circuit 1101 can use the generated phase The corresponding part of the check code corrects the errors on the data pages P9 and P17. If a short circuit between two character lines causes, for example, the data page P17 of the character line WL2 and the data page P1 of the character line WL3 to fail, the error correction code encoding circuit 1101 may use a partial check code of a set of character lines WL0 to WL2 And another part of the check code of the character lines WL3 to WL5 corrects the error of the data page P17 of the character line WL2 and the data page P1 of the character line WL3, respectively. If a short circuit between two character lines causes, for example, an error in the data pages P1 and P2 of the character line WL0, the error correction code encoding circuit 1101 may use a partial check code of a set of character lines WL0 to WL2 to respectively separate the character lines WL0. Correction of errors on the data pages P1, P2.

Therefore, regardless of a data page error caused by a write failure, a one-character line break, or a two-character line short while performing SLC data block write, the error correction code encoding circuit 1101 can correct the errors accordingly. 'S profile page.

Please refer to FIG. 3. FIG. 3 is a schematic diagram of writing data into a TLC data block 1052 by an internal copy of one SLC data block in the flash memory module 105. As shown in Figure 3, a group of three character line data in an SLC data block is written to a character line in the TLC data block 1052, correspondingly forming the least significant bit of the data page of one of the character lines. The data of the LSB, the middle significant bit CSB, and the most significant MSB, for example, the character line data WL0 ~ WL2 of the SLC data block are written to the TLC data block 1052, which is the lowest of the character line WL0 of the TLC data block 1052. Data of significant bit LSB, intermediate significant bit CSB, and most significant bit MSB; the character line data WL3 ~ WL5 of the SLC data block are written to the TLC data block 1052 as the word line WL1 of the TLC data block 1052 The data of the least significant bit LSB, the middle significant bit CSB, and the most significant bit MSB; the character line data WL6 ~ WL8 of the SLC data block is written to the TLC data block 1052 as the character line WL2 of the TLC data block 1052 The data of the least significant bit LSB, the middle significant bit CSB, and the most significant bit MSB; that is, the internal copy of the flash memory module 105 moves and writes the data of the SLC data block in the order of the character line Fill in the character line of the TLC data block.

Please refer to FIG. 4. FIG. 4 shows the flash memory controller 110 shown in FIG. 1 of the first embodiment of the present invention writing data of three groups to a plurality of SLCs in the flash memory module 105. Schematic diagram of data block 1051A ~ 1051C and transferring data into TLC data block by internal copy to form a super data block. Due to the error correction code encoding circuit 1101, each time the SLC data block is written, the data is classified into two groups of odd array character lines and even array character lines, and the corresponding generated check code is stored in the odd The last 3 data pages of the last character line of the array character line and the last 3 data pages of the last character line of the even array character line. Therefore, when writing the TLC data block, As shown in Figure 4, the corresponding check code of the odd array character line of the data of the first group is stored in the last three data pages (labeled 401A) of the middle significant bit CSB of the character line WL42 of the superblock. ), And the corresponding check code of the even array character line of the data of the first group is stored in the last three data pages (labeled 401B) of the most significant MSB of the character line WL41 of the super block; The corresponding check code of the odd array character line of the data of the second group is stored in the last three data pages (labeled 402A) of the least significant bit LSB of the character line WL85 of the superblock, and the second The corresponding check code of the even array character line of the data of each group is stored in the super block The last three data pages of the most significant MSB of the zigzag line WL84 (labeled 402B); the corresponding check codes for the odd array word lines of the third group of data are stored in the characters of the superblock The last three data pages (labeled 403A) of the MSB of the most significant bit of line WL127, and the corresponding check code of the even array character line of the third group of data is stored in the character line WL127 of the superblock. The last three data pages of the LSB of the least significant bit (labeled 403B).

If a short circuit between the two character lines is detected, for example, an error occurs on the two data pages (as indicated by the frame line 404) of the character lines WL0, WL1 of the super block, the flash memory module 105 can use the character line WL42 The check code 401A stored on the last three data pages of the middle significant bit CSB is used to correct the error of the data page of the character line WL0, and the data stored on the last three data pages of the MSB of the character line WL41 are used. The check code 401B corrects the data page error of the character line WL1.

Similarly, if a short circuit between two character lines is detected and an error occurs in the two data pages (for example, indicated by a frame line 405) of the character lines WL43 and WL44 of the super block, the flash memory module 105 can use the word The check code 402A stored on the least significant bit LSB of the last three data pages of the meta line WL85 corrects the least significant bit LSB, the middle significant bit CSB error, and the character of one of the data pages of the word line WL43 indicated by 405. The error of the MSB of the data page of line WL44 is incorrect, and the check code 402B stored on the middle significant bit CSB of the last three data pages of character line WL84 is used to correct the character line WL43 marked by 405. The error of the most significant bit MSB of the data page and the error of the least significant bit LSB and the middle significant bit CSB of the data page of word line WL44.

Similarly, if a short circuit between two character lines is detected and an error occurs in the two data pages (for example, indicated by a frame line 406) of the character lines WL125 and WL126 of the TLC data block, the flash memory module 105 may Use the check code 403A stored on the most significant MSB of the last three data pages of the character line WL127 to correct the middle significant CSB, most significant MSB error, and word of the data line WL125 marked one data page. The error of the MSB of the most significant bit of the data page of the line WL126 and the check code 403B stored on the least significant bit LSB of the last three data pages of the character line WL127 are used to correct the character line WL125 of the 406 mark. The error of the least significant bit LSB of the data page, and the error of the middle significant bit CSB and the most significant bit MSB of the data line WL126 of a data page indicated by 406.

If an error occurs in any data page of any character line in the super block (ie, any three consecutive data pages in error), a flash memory module is detected if a character line is disconnected or a write failure occurs 105 can use the corresponding stored check code to correct the error of any three consecutive sub-data pages.

In other words, the flash memory controller 110 writes three groups of data to multiple SLC data blocks 1051A ~ 1051C in the flash memory module 105. The storage location management design, When the flash memory module 105 copies the data from multiple SLC data blocks 1051A ~ 1051C to the TLC data block through internal copy to form a super data block, if a word line break is detected, Errors such as short circuit or write failure of the two character lines can be corrected by the check codes stored in multiple SLC data blocks 1051A to 1051C.

Furthermore, please refer to FIG. 5. FIG. 5 is a flash memory controller 110 shown in FIG. 1 of the second embodiment of the present invention performing a data write (SLC program) to write data of a group to the flash memory. The schematic diagram of the SLC data block in the memory module 105 to complete a write operation of the SLC data block. The error correction code encoding circuit 1101 of the flash memory controller 110 performs an encoding operation similar to the mutual exclusion or operation of the fault-tolerant disk array on the data to generate a corresponding check code, and the check code buffer 1102 It is used to temporarily store the corresponding check code generated. In addition, the mutually exclusive OR operation of the error correction code encoding circuit 1101 includes three different encoding engines to perform mutually exclusive OR operations on different character line data of the SLC data block; detailed operation contents are described below.

The flash memory module 105 includes two channels and includes two flash memory chips. For writing efficiency, the flash memory controller 110 writes data to the flash memory through two channels. The two flash memory chips in the module 105 program the data pages of one SLC data block into different flash memory chips, and one write operation of the SLC data block of the flash memory controller 110 The written data includes 128 character lines (represented by WL0 to WL127 respectively), and each character line includes 8 data pages. For example, taking the character line WL0 as an example, the error correction code encoding circuit 1101 uses a channel. CH0, PLN0, and PLN1 write data pages P1 and P2 to the flash memory chip CE0, and then write data pages P3 and P4 to another flash memory chip CE1 through the same channel CH0, PLN0, and PLN1, and then The data pages P5 and P6 are written into the flash memory chip CE0 by the other channels CH1, PLN0, and PLN1, and then the data pages P7 and P8 are written into the flash memory chip CE1 through the channels CH1, PLN0, and PLN1.

The error correction code encoding circuit 1101 is to classify multiple M word lines WL0 to WL127 of an SLC data block in order into a group of M word lines, where M is a positive integer greater than or equal to 2, and M is, for example, 3. For example, the character lines WL0 ~ WL2 are the first group, the character lines WL3 ~ WL5 are the second group, the character lines WL6 ~ WL8 are the third group, and the character lines WL9 ~ WL11 are the fourth group ..., characters Lines WL120 to WL122 are the penultimate group, character lines WL123 to WL125 are the penultimate group, and the last group of character lines are WL126, WL127, of which the first, third, fifth, etc. character lines Are odd array character lines, and the second, fourth, sixth group, etc. character lines are even array character lines. The flash memory controller 110 writes data of one set of character lines at a time ( Including the data of the three character lines), is the use of error correction code encoding circuit 1101 to perform mutually exclusive OR operation on the data of the group of character line error correction encoding, and the corresponding parity code (partial parity) code) is output to the check code buffer 1102 to temporarily store a part of the check code.

Each time the error correction code encoding circuit 1101 writes data to a set of three different character lines, it uses three different encoding engines to perform mutually exclusive or operation encoding on the written data, and generates the corresponding Part of the check code is output to the check code buffer 1102 to temporarily store the part of the check code, and the check code buffer 1102 corresponds to the character line data of the odd array when temporarily storing the part of the check code. A part of the check code is stored in a first buffer, and a part of the check code corresponding to the character line data of the even array is stored in a second buffer.

For example, the error correction code encoding circuit 1101 includes a first encoding engine, a second encoding engine, and a third encoding engine. When the data pages P1 to P24 of the character lines WL0 to WL2 are written, the first encoding engine is sequentially used. Perform a mutually exclusive OR operation on the data pages P1 ~ P8 of the character line WL0 to generate a first partial check code, and use a second encoding engine to perform a mutually exclusive OR operation on the data pages P9 ~ P16 of the character line WL1 to generate a first A two-part check code and a third encoding engine are used to perform a mutually exclusive OR operation on the data pages P17 to P24 of the word line WL2 to generate a third part check code, and output the generated part check codes separately To the check code buffer 1102, temporarily stored in the first buffer; then the error correction code encoding circuit 1101 writes the data pages P1 to P24 of the character lines WL3 to WL5, and sequentially uses the first encoding engine for the character line WL3 The data pages P1 ~ P8 on the data page perform a mutually exclusive OR operation to generate another first part check code, and the second encoding engine is used to perform a mutually exclusive OR operation on the data page P9 ~ P16 of the character line WL4 to generate another second part calibration. Check code and use the third encoding engine for word line WL5 The data pages P17 ~ P24 on the data pages perform mutual exclusion or operation to generate another third part check code, and output the generated part check codes to the check code buffer 1102, respectively, and temporarily store them in the second buffer. .

Subsequent data page writing and encoding operations are performed by analogy, that is, for the data of the first character line, the data of the second character line, and the third word of a set of odd array character lines The data of the meta lines and the data of the first character line, the data of the second character line, and the data of the third character line of a set of even array of character lines are respectively executed different times of mutual exclusion or Operation to generate the corresponding check code. In order to write the corresponding check codes in the appropriate storage location of the SLC data block, the error correction code encoding circuit 1101 writes the data pages of the last 6 word lines WL122 to WL127, corresponding to these. The check code is written on the last data page of the last 6 character lines WL122 ~ WL127 (as shown by the rectangular diagonal line box in Figure 5). For example, when writing the data page of character line WL122, the word Element line WL122 is the third character line of a set of odd array character lines. The error correction code encoding circuit 1101 is written in the last data page of character line WL122. The check code corresponding to the data of the character line (that is, all the third part check codes generated by the third encoding engine in the odd array character line), and when writing the data page of the character line WL123 The character line WL123 is the first character line of the last group of even array character lines. The error correction code encoding circuit 1101 is written in all the even array character lines in the last data page of the character line WL123. The check code corresponding to the data of all the first character lines (that is, All the first part check codes generated by the first encoding engine), and when writing the data page of the character line WL124, the character line WL124 is the second character line of the last group of even array character lines, The error correction code encoding circuit 1101 writes the check code corresponding to the data of all the second character lines in all even array character lines in the last data page of character line WL124 (that is, even array characters All the second part check codes generated by the second encoding engine in the line), and when writing to the data page of the character line WL125, the character line WL125 is the third word of the last set of even array character lines Element line, error correction code encoding circuit 1101 writes the check code corresponding to the data of all the third character lines in all even array character lines in the last data page of character line WL125 (that is, even numbers) All the third part check codes generated by the third encoding engine in the group of character lines), and when writing the data page of the character line WL126, the character line WL126 is the first of the last set of odd array character lines One character line, the error correction code encoding circuit 1101 is the last one of the character line WL126 The check code corresponding to the data of all the first character lines in all odd array character lines is written in the material page (that is, all the first part of the check code generated by the first encoding engine in the odd array character lines ), And when writing the data page of the character line WL127, the character line WL127 is the second character line of the last set of odd array character lines, and the error correction code encoding circuit 1101 is at the end of the character line WL127 A data page writes the check code corresponding to the data of all the second character lines in all odd array character lines (that is, all the second parts in the odd array character lines generated by the second encoding engine) Check code). This completes the writing of the SLC data block.

That is to say, when the flash memory controller 110 writes a group of data to an SLC data block, the flash memory controller 110 sequentially all the character lines of the SLC data block every M words The metaline is classified as a set of character lines to generate the character lines of the odd array of the complex array and the character lines of the even array of the complex array, and each character line of the odd array and each of the set of even array. One character line, which performs different M exclusive or OR encoding operations, to generate M partial check codes for each character line of the odd array and M for each character line of the even array. M partial check codes, write and store M partial check codes for each character line of the odd array of the complex array on the last data page of the last M word lines of the odd array of odd lines of the complex array Write and store the M partial check codes of each character line of the complex array even array on the last data page of the last M character lines of the complex array even character line. In the above embodiment, M is 3, but this is not a limitation of this case.

The error correction code encoding circuit 1101 in the embodiment shown in FIG. 5 performs a mutex or arithmetic encoding operation, which can correct a data page error that occurs at a position on a character line of an SLC data block. For example, If a write failure is detected during the writing of the SLC data block, for example, a write failure of the data page P9 of the word line WL1 is detected, the error correction code encoding circuit 1101 may use the second encoding engine to The corresponding partial check code generated when processing the character line WL1 of the first group of character lines and other correct data pages P10 ~ P16 of the same character line WL1, and the data page P9 of the character line WL1 is corrected. error.

If it is detected that a character line disconnection occurs during the writing of the SLC data block, for example, the data page P9 of the character line WL1 is incorrect, the error correction code encoding circuit 1101 may also use the second encoding engine to process The corresponding partial check code generated by the character line WL1 of a group of character lines and other correct data pages P10 ~ P16 of the same character line WL1, and the error of the data page P9 of the character line WL1 is corrected.

If it is detected that a short of two character lines occurs during the writing of the SLC data block, for example, the data page P9 of the character line WL1 and the P17 of the character line WL2 are both wrong. The error correction code encoding circuit 1101 can be used. The corresponding partial check code generated by the second encoding engine when processing the character line WL1 of the first group of character lines and other correct data pages P10 to P16 of the same character line WL1, and correcting the character line WL1 The error of the data page P9, and the corresponding partial check code generated by the third encoding engine when processing the character line WL2 of the first group of character lines, and other correct data pages P18 of the same character line WL2 ~ P24, Correct the error of the data page P17 of the character line WL2. If the data page P17 of the character line WL2 and the data page P1 of the character line WL3 are in error, the error correction code encoding circuit 1101 can use the third encoding engine to process the character line WL2 of the first group of character lines. The corresponding partial check code and other correct data pages P18 ~ P24 of the same character line WL2 are generated, errors of the data page P17 of the character line WL2 are corrected, and the first encoding engine is used to process the second set of characters The corresponding part of the check code generated by the character line WL3 of the line and other correct data pages P2 to P8 of the same character line WL3, and the error of the data page P1 of the character line WL3 is corrected. Therefore, regardless of a data page error caused by a write failure, a one-character line break, or a two-character line short while performing SLC data block write, the error correction code encoding circuit 1101 can correct the errors accordingly. 'S profile page. The operation of the flash memory module 105 writing data into the TLC data block through the internal copy of the SLC data block is the same as the content of FIG. 3 described above, and will not be described again.

Please refer to FIG. 6. FIG. 6 is a diagram of the flash memory controller 110 shown in FIG. 1 of the second embodiment of the present invention writing data of three groups to a plurality of SLCs in the flash memory module 105. Schematic diagram of data blocks 1051A ~ 1051C and transferring the data of these SLC data blocks 1051A ~ 1051C to TLC data block 1052 by internal copying to form a super block. The error correction code encoding circuit 1101 classifies data into odd array character lines and even array character lines each time the SLC data block is written, and stores the corresponding generated check codes in all odd array words. The last 3 data lines of the last 3 character lines in the meta line and the last 3 data lines of the last 3 character lines of all even array character lines, as shown in Figure 6, execute the TLC data block When writing, according to the order of data writing, the corresponding check code of the character line data in the first group, as indicated by 605A, is the last one of the character line WL40 written and stored in the TLC data block 1052. The MSB of the data page, the LSB of the last data page of the character line WL41, and the LSB of the last data page of the character line WL42 and the middle significant bit CSB, among which the SLC data in the first group The parity code of the odd array character line of the block is stored in the most significant bit MSB of the last data page of character line WL40 and the least significant bit LSB and middle significant bit CSB of the last data page of character line WL42. , And the even array of character lines of the SLC data block in the first group Check code stored in the word line WL41 of the last profile page (including the least significant bit LSB, CSB middle significant bit and the most significant bit MSB).

The corresponding check code of the character line data in the second group, as indicated by 605B, is written and stored in the last data page of the last data page of the character line WL83 in the TLC data block 1052 and the highest significant bit MSB, the least significant bit LSB of the last data page of character line WL84 and the last data page of character line WL85, where the odd array character line data in the SLC data block in the second group All third part check codes generated by the third encoding engine are stored in the middle significant bit CSB of the last data page of the word line WL83 of the TLC data block 1052, and all are generated by the first encoding engine. The first part of the check code is stored in the MSB of the last data page of the word line WL84 of the TLC data block 1052. All the second part of the check code generated by the second encoding engine is stored in the TLC data. The least significant bit LSB of the last data page of the character line WL85 in block 1052, and for the even array of character line data in the SLC data block in the second group, all the Part of the check code is stored in the TLC data area The MSB of the most significant bit of the last data page of the word line WL83 of 1052, all the second part check codes generated by the second encoding engine are stored in the last page of the word line WL84 of the TLC data block 1052 The least significant bit LSB of the data page, all the third part check codes generated by the third encoding engine are stored in the middle significant bit CSB of the last data page of the word line WL84 of the TLC data block 1052.

The corresponding check code of the character line data of the third group, as indicated by 605C, is the last data page (including the least significant bit LSB) written and stored in the TLC data block 1052 of the character line WL126, 127 , The middle significant bit (CSB) and the most significant bit (MSB)). For the third group of odd-line character line data in the SLC data block, all the third part check codes generated by the third encoding engine are stored in The least significant bit LSB of the last data page of the character line WL126 of the TLC data block 1052. All the first part of the check code generated by the first encoding engine are stored in the character line WL127 of the TLC data block 1052. The middle significant bit CSB of the last data page. All the second part check codes generated by the second encoding engine are stored in the MSB of the last data page of the word line WL127 of the TLC data block 1052. For the even array of character line data in the SLC data block in the third group, all the first part check codes generated by the first encoding engine are stored at the end of the character line WL126 in the TLC data block 1052 CSB in the middle of a data page All the second part check codes generated by the second encoding engine are stored in the MSB of the last data page of the last data page of the word line WL126 in the TLC data block 1052, and all are generated by the third encoding engine. The third part of the check code is the least significant bit LSB of the last data page of the word line WL127 stored in the TLC data block 1052.

Therefore, when the flash memory module 105 moves and writes data from the SLC data blocks 1051A to 1051C to the TLC data block 1052 through an internal copy operation, if a short circuit between the two word lines is detected, for example, the TLC data area An error occurred on the two data pages of the character line WL0 and WL1 of block 1052 (as indicated by the frame line 610). The flash memory module 105 can use the last data stored in the character line WL42 of the TLC data block 1052. The first part check code of the middle significant bit CSB of the page and the data of the least significant bit LSB of the other data pages of the word line WL0. Correct the data of the least significant bit LSB of the data page of the word line WL0 marked by 610. The second part of the MSB of the most significant bit MSB of the last data page of the word line WL42 in the TLC data block 1052 and the data of the middle significant bit CSB of the other data pages of the word line WL0 are corrected to 610. The data of the middle significant bit CSB of the data page of the marked character line WL0, and the third part of the check code using the most significant MSB of the last data page of the word line WL40 stored in TLC data block 1052 And the other word line WL0 The MSB data of the data page is used to correct the MSB data of the data page of the character line WL0 marked by 610. Similarly, the flash memory module 105 can use the first part of the LSB check code of the least significant bit LSB of the last data page of the word line WL41 stored in the TLC data block 1052 and other data pages of the word line WL1. The data of the least significant bit of LSB is used to correct the data of the least significant bit of LSB of the data page of the character line WL1 marked by 610, using the middle of the last data page of the character line WL41 of the word line 1052 of TLC The second part check code of the significant bit CSB and the data of the middle significant bit CSB of the other data pages of the word line WL1, to correct the data of the middle significant bit CSB of the data page of the word line WL1 marked 610, and use The third part check code of the most significant MSB of the last data page of the word line WL41 in the TLC data block 1052 and the data of the most significant MSB of the other data pages of the word line WL1 are corrected to 610. Data of the MSB of the data page of the marked character line WL1.

Similarly, if the two-character line is short-circuited and the error occurs on the continuous data page of any two consecutive character lines in the superblock (for example, the error position indicated by 615, 620), the flash memory module 105 can use the corresponding check code stored in the last data page of the last 6 character lines of an SLC data block in each group to correct the error. In addition, if a word line break or write failure is detected and an error occurs on any data page of any word line in the TLC data block 1052 (that is, all three valid bits of the same data page are wrong or Different consecutive significant bits of two different data pages are in error), then the flash memory module 105 can use the corresponding stored check code to correct the error of any three consecutive significant bits.

In other words, the flash memory controller 110 writes three groups of data to the multiple SLC data blocks 1051A ~ 1051C in the flash memory module 105. The storage location management design is designed to When the memory module 105 copies the data from multiple SLC data blocks 1051A ~ 1051C to the TLC data block by internal copying, if one word line is disconnected, two word lines are short-circuited or written Failure errors can be corrected by the check codes stored in multiple SLC data blocks 1051A ~ 1051C.

Furthermore, the above-mentioned embodiments in this case are also applicable to the MLC data block or QLC data block structure. When used in the MLC data block, the above three groups of data are changed to data classified into two groups. For encoding operations that perform mutual exclusion or operations, use two encoding engines instead. The other conditions are the same as those used in the TLC data block. Therefore, if used in the QLC data block, the above three Group data is classified into four groups of data. For encoding operations that perform mutual exclusion or operations, use four encoding engines to implement the other conditions. The other conditions are the same as those used in the TLC data block. The structure of other data blocks is the same.

In terms of the cost of data storage (overhead), if two channels are used to write two memory chips, and each memory chip has a folded flat design so that two blocks can be written simultaneously, one SLC data is used. As for the data writing of the block, the 128 character lines have a total of 8 * 128 data pages, and only 6 data pages need to be used to store the corresponding check code. The cost percentage is less than 1% (6 / ( 128 * 8)), that is, for writing SLC data blocks and writing TLC data blocks, you only need to use less than 1% of the data space as the corresponding error correction check code. Data space The use efficiency is extremely high. And if 4 channels are used to write 4 memory chips, and each memory chip has a folded flat design so that 2 blocks can be written at the same time, in terms of the data writing of an SLC data block, 128 Each character line has 4 * 4 * 2 * 128 data pages, and only 6 data pages need to be used to store the corresponding check code. The cost percentage will be lower, about 0.15% (6 / (128 * 4 * 4 * 2)), that is, for writing SLC data blocks and writing TLC data blocks, you only need to use about 0.15% of the data space as the corresponding error correction check code. , More efficient use of data space. The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the scope of patent application of the present invention shall fall within the scope of the present invention.

100‧‧‧Flash memory device

105‧‧‧Flash Memory Module

110‧‧‧Flash Memory Controller

205, 210, 401A, 401B, 402A, 402B, 403A, 403B, 605A, 605B, 605C‧‧‧ Check code storage location

Data pages for 404, 405, 406, 610, 615, 620‧‧‧TLC data blocks

1051A, 1051B, 1051C‧‧‧SLC data blocks

1052‧‧‧TLC data block

1101‧‧‧Error correction code encoding circuit

1102‧‧‧Check code buffer

1102A, 1102B‧‧‧Buffer zone

FIG. 1 is a schematic diagram of a flash memory device according to an embodiment of the present invention. FIG. 2 is a diagram of the flash memory controller shown in FIG. 1 of the first embodiment of the present invention performing SLC data writing to write a certain group of data to an SLC data block in the flash memory module for execution. Schematic diagram of an SLC data block write operation. FIG. 3 is a schematic diagram of writing data into a TLC data block by an internal copy of an SLC data block in a flash memory module. FIG. 4 is a diagram showing a flash memory controller shown in FIG. 1 of the first embodiment of the present invention, which writes data of three groups to a plurality of SLC data blocks in the flash memory module and internally copies the data. Schematic diagram of moving to the TLC data block to form a super block. Fig. 5 is a flash memory controller shown in Fig. 1 of the second embodiment of the present invention performing SLC data writing to write data of a group to the SLC data block in the flash memory module to complete once Schematic diagram of SLC data block write operation. FIG. 6 is a diagram of the flash memory controller shown in FIG. 1 of the second embodiment of the present invention, which writes data of three groups to a plurality of SLC data blocks in the flash memory module and copies the data by internal copying. The data transfer of some SLC data blocks is written into the TLC data blocks to form a super block diagram.

Claims (13)

A flash memory device includes: a flash memory module including a plurality of first data blocks and at least one second data block; and a flash memory controller having a plurality of channels respectively connected To the flash memory module, the flash memory controller first classifies a piece of data to be written into a plurality of groups of data, and the flash memory controller separately performs single-level unit data writing (SLC program ) And an error correction encoding operation similar to the mutual exclusion or operation of a fault-tolerant disk array generates a corresponding check code to write the data of the complex group and the corresponding check code to the plurality of first A data block, wherein one unit of the plurality of first data blocks stores one bit of data; after the writing of the plurality of first data blocks is completed, the flash memory module executes an internal Internal copy, transferring the data of the plural group stored in the plural first data blocks and the corresponding check code to the at least one second data block, wherein the at least one second Capital A storage unit in the block at least two data bits. According to the flash memory device described in item 1 of the scope of patent application, wherein the at least one second data block is a TLC data block and stores three bits of data, the flash memory controller The data to be written is classified into three groups of data to be written into three SLC data blocks respectively. The flash memory device described in item 1 of the scope of patent application, wherein the plurality of first data blocks are a plurality of SLC data blocks, and when the flash memory controller writes a group of data to an SLC data region At the time of the block, the flash memory controller classifies all the word lines of the SLC data block into a group of word lines in order every M word lines in order to generate a complex array of odd arrays. The character lines and the character lines of the complex and even arrays, and each M line of each set of odd arrays and each of the character lines of a set of even arrays are coded separately for M times of mutually exclusive operations. To generate M partial check codes for each character line of the odd array and M partial check codes for each character line of the even array, write and store each of the odd array of the complex array The M partial check codes of the character line are written on the last data page of the last M character lines in the odd array character line of the complex array, and the M of each character line of the even array of the complex array is written and stored. Partial check code is the last one of the last M character lines in the complex and even array character lines Material page. The flash memory device according to item 1 of the scope of the patent application, wherein when the garbage collection is performed, the flash memory controller reads the plurality of first data blocks from the outside. The data is re-encoded and written, or the at least one second data block is read from the outside and re-encoded and written. The flash memory device according to item 1 of the scope of patent application, wherein when writing data to the at least one second data block and a sudden shutdown occurs, the flash memory controller abandons the at least one second The data stored in the data block is internally copied, and the written data is moved from the plurality of first data blocks to the at least one second data block. The flash memory device according to item 1 of the scope of patent application, wherein when writing data to the first data blocks, the flash memory controller is based on one of the at least one second data block The randomizer seed rule writes data to the plural first data blocks. A flash memory storage management method is used for a flash memory module. The flash memory module includes a plurality of first data blocks and at least one second data block. The method includes: Classifying a piece of data to be written into a plurality of pieces of data; performing a single-level unit data write and performing a mutually exclusive or operation similar to a fault-tolerant disk array, respectively; an error correction encoding operation generates a corresponding check code, Write the data of the plurality of groups and the corresponding check code to the plurality of first data blocks, wherein a unit in the plurality of first data blocks stores one bit of data; make the flash The memory module performs an internal copy, and writes the data of the plurality of groups stored in the plurality of first data blocks and the corresponding check code to the at least one second data block, where the at least one first A unit in the two data blocks stores at least two bits of information. The flash memory storage management method described in item 7 of the scope of the patent application, wherein the at least one second data block is a TLC data block, storing three bits of data, and writing the The step of classifying the data into the data of the plurality of groups includes: classifying the data to be written into data of three groups to write to the three SLC data blocks respectively. The flash memory storage management method described in item 7 of the scope of the patent application, wherein the plurality of first data blocks are a plurality of SLC data blocks, and the flash memory storage management method further includes: when writing When a group of data is in an SLC data block, the flash memory controller classifies all the character lines of the SLC data block into a group of character lines in order every M character lines in order to generate a complex number Groups of character lines of odd arrays and character lines of even arrays of complex arrays; each M character line of a set of odd arrays and each character line of a set of even arrays are executed for M times of exclusive exclusions or operations, respectively Encoding operation, generating M partial check codes for each character line of the odd array and M partial check codes for each character line of the even array; and writing and storing the complex array odd The M partial check code of each character line of the array is written in the last data page of the last M character lines in the odd array character line of the complex array, and each word of the even array of the complex array is written and stored The M partial check codes of the meta line are the most Finally, a data page of the M word lines. According to the flash memory storage management method described in item 7 of the scope of the patent application, it further includes: when the memory garbage is collected, the data of the plurality of first data blocks is read from the outside and re-encoded And write, or read the at least one second data block from the outside and re-encode and write. The flash memory storage management method described in item 7 of the scope of patent application, further comprising: when writing data to the at least one second data block and a sudden shutdown occurs, abandon the at least one second data area Blocks the stored data, and executes the internal copy to move the written data from the plurality of first data blocks to the at least one second data block. The flash memory storage management method described in item 7 of the scope of patent application, further comprising: when writing data to the first data blocks, according to one of the at least one second data block The seed number rule writes data to the plural first data blocks. A flash memory controller includes: a plurality of channels respectively connected to a flash memory module, the flash memory module including a plurality of first data blocks and at least one second data block; and An error correction code encoding circuit; wherein the flash memory controller first classifies a piece of data to be written into a plurality of groups of data, performs single-level unit data writing, and uses the error correction code encoding circuit to execute a An error correction encoding operation similar to the mutual exclusion or operation of the fault-tolerant disk array generates a corresponding check code to write the data of the plural group and the corresponding check code to the plurality of first data blocks. Wherein one unit of the plurality of first data blocks stores one bit of data; after the writing of the plurality of first data blocks is completed, the flash memory controller causes the flash memory module to An internal copy is performed, and the data of the plural group stored in the plural first data blocks and the corresponding check code are moved and written to the at least one second data block, where the at least one Two data blocks in a storage unit of at least two bits of information.