TWI658466B - Memory device and method for test reading and writing thereof - Google Patents

Abstract

A memory device and a method for testing read and write. The precharge voltage control circuit generates a first precharge voltage and a second precharge voltage according to a precharge reference voltage. The sense amplifier circuit is coupled between the bit line and the complementary bit line to sense data of the memory cell coupled to the bit line, and is coupled to the precharge voltage control circuit so that the bit line is complementary to the bit line. The bit line receives the first precharge voltage and the second precharge voltage, respectively. In the precharge operation, the voltage levels of the first precharge voltage and the second precharge voltage are the same. The test write after the precharge operation The voltage levels of the first precharge voltage and the second precharge voltage provided by the precharge voltage control circuit to the bit line and the complementary bit line are different between the input sensing period and the test read sensing period.

Description

Memory device and test reading and writing method thereof

The present disclosure relates to a semiconductor memory technology, and more particularly, to a memory device capable of reading and writing all sensing circuits on a selected character line at a time in a parallel test mode and a test read / write method thereof. .

A general semiconductor memory element, such as a dynamic random access memory (DRAM), has a sense amplifier, which is connected to the bit line of the memory cell array, and can access data from the selected memory cell and amplify the data.

In the prior art, when a memory device is to be tested, for example, in a parallel test mode, multiple amplifiers for normal reading and writing are selected at one time, but it is not possible to select more than one data line at a time. It is one of the topics that we want to solve at present how to select multiple sense amplifiers on a character line to perform a parallel test mode in a cycle.

The present disclosure relates to a memory device and a method for testing read / write. These memory devices and methods can select a plurality of sense amplifiers on a character line in a cycle to perform a parallel test mode.

The disclosure provides a memory device including a pre-charge voltage control circuit and a sense amplifier circuit. The precharge voltage control circuit generates a first precharge voltage and a second precharge voltage according to a precharge reference voltage. The sense amplifier circuit is coupled between the bit line and the complementary bit line to sense data of the memory cell coupled to the bit line, and is coupled to the precharge voltage control circuit so that the bit line is complementary to the bit line. The bit line receives the first precharge voltage and the second precharge voltage, respectively. In the precharge operation, the voltage levels of the first precharge voltage and the second precharge voltage are the same. The test write after the precharge operation The voltage levels of the first precharge voltage and the second precharge voltage provided by the precharge voltage control circuit to the bit line and the complementary bit line are different between the input sensing period and the test read sensing period.

The disclosure provides a test read and write method for a memory device, which is used to perform a test write operation and a test read operation on a memory unit. The test read and write method includes: generating a first precharge voltage and a second voltage according to a precharge reference voltage. Precharge voltage; the bit line and the complementary bit line receive the first precharge voltage and the second precharge voltage, respectively, wherein in the precharge operation, the voltage levels of the first precharge voltage and the second precharge voltage Similarly, during the test write sensing period and the test read sensing period after the precharge operation, the precharge voltage control circuit provides the first precharge voltage and the second precharge voltage of the bit line and the complementary bit line to the The voltage levels are different.

In order to make the above-mentioned features and advantages of the present disclosure more comprehensible, embodiments are described below in detail with reference to the accompanying drawings.

Please refer to FIG. 1, which illustrates a schematic diagram of a memory device according to an embodiment of the present disclosure. The memory device 100 includes a word line WL, a bit line BLT, a complementary bit line BLN, a memory cell MC, a sense amplifier circuit 110, and a control and test circuit 120. The control and test circuit 120 is coupled to the sense amplifier circuit 110 to provide a plurality of control signals.

The memory cell MC includes, for example, a memory capacitor for storing a data potential, and a metal oxide semiconductor transistor (MOSFET) (not shown) as a switch. One end is coupled to the capacitor, the second end is coupled to the bit line BLT, and its gate terminal is coupled to the word line WL. Here, the plurality of memory cells MC are arranged in an array in a direction of a plurality of word lines WL, a plurality of bit lines BLT, and a plurality of complementary bit lines BLN to form a memory array 130. The word line signals WLn and WLm shown in FIG. 1 represent signals on different word lines WL.

The sensing amplifying circuit 110 is coupled to a pair of bit lines, that is, the bit line BLT and the complementary bit line BLN, to sense data of the memory cell MC. Therefore, a test write operation or test can be performed on the memory cell MC. Read operation.

The sense amplifier circuit 110 receives a first precharge voltage HFVT, a second precharge voltage HFVN, a first precharge enable signal BLP1 and a second precharge enable signal BLP2 from the control and test circuit 120. The sense amplifier circuit 110 determines whether to allow the bit line BLT and the complementary bit line BLN to receive the first precharge voltage HFVT and the second precharge, respectively, according to the first precharge enable signal BLP1 and the second precharge enable signal BLP2. Voltage HFVN. In the precharge operation, the voltage levels of the first precharge voltage HFVT and the second precharge voltage HFVN are the same. Therefore, the bit line BLT and the complementary bit line BLN have the same voltage level. However, During the test write sensing period and the test read sensing period after the precharge operation, the voltage levels of the first precharge voltage HFVT and the second precharge voltage HFVN provided by the control and test circuit 120 will be different, and the first A precharge enable signal BLP1 is not the same at the time point of switching the voltage level during the test write sensing period and the test read sensing period, so it is different from a general memory device. During the sensing process, the bit line BLT The voltage difference between the complementary bit line BLN and the complementary bit line BLN is mainly affected by the data released by the memory cell MC. The voltage difference between the bit line BLT and the complementary bit line BLN in this embodiment will be equal to the first precharge voltage HFVT. And between the second precharge voltage HFVN The voltage difference is related. The following examples will provide a more detailed explanation.

The sense amplifier circuit 110 includes a first switch T1, a second switch T2, a third switch T3, and a sensing circuit SA. Here, the first switch T1, the second switch T2, and the third switch T3 use an n-channel transistor as an example. But it is not limited to this. The first terminal (drain) of the first switch T1 receives the first precharge voltage HFVT, the second terminal (source) is coupled to the bit line BLT, and its gate terminal receives the first precharge enable signal BLP1 to determine whether Continuity. The first terminal (drain) of the second switch T2 receives the second precharge voltage HFVN, the second terminal (source) is coupled to the complementary bit line BLN, and its gate terminal also receives the first precharge enable signal BLP1 to Decide whether to conduct. The third switch T3 is coupled between the bit line BLT and the complementary bit line BLN, and its gate terminal receives the second precharge enable signal BLP2.

The sensing circuit SA is coupled between the bit line BLT and the complementary bit line BLN to amplify the bit line BLT according to the p-channel control voltage SAP and the n-channel control voltage SAN received from the control and test circuit 120. The voltage difference from the complementary bit line BLN. In this embodiment, the sensing circuit SA is a CMOS inverter including two MOS transistors Q1 and Q2 and a CMOS inverter including two MOS transistors Q3 and Q4 connected as a positive feedback circuit. Way to implement.

The first terminals (source here) of the transistors Q1 and Q3 of the sensing circuit SA are coupled to a first intermediate node N1. The first intermediate node N1 receives the p-channel control voltage SAP, and the first terminals of the transistors Q2 and Q4 The two terminals (here, the source) are coupled to a second intermediate node N2, which receives the n-channel control voltage SAN. The other ends of the transistors Q1 and Q2 of the sensing circuit SA (here, the drain electrodes) and the gates of the transistors Q3 and Q4 are coupled to the bit line BLT. The other ends of the transistors Q3 and Q4 (here, the drain electrodes) ) And the gates of the transistors Q1 and Q2 are coupled to the complementary bit line BLN, so the voltage level of the bit line BLT and the complementary bit line BLN can be affected by the p-channel control voltage SAP and the n-channel control voltage SAN. Pulled up or down to indicate a logical "1" or a logical "0".

FIG. 2 is a schematic diagram of an array structure of a memory device according to an embodiment of the disclosure. The embodiment of FIG. 2 is applicable to the memory device 100 of FIG. 1. Please refer to FIG. 2, the memory array 130 is composed of a memory cell MC at a junction of a plurality of word lines WL and a plurality of bit lines BLT, an X decoder block (XDEC) 140 and a Y decoder block ( YDEC) 150 is coupled to the memory array 130 and is used to select which memory cell MC to access data. The memory array 130 is coupled to the sense amplifier block 160. The sense amplifier block 160 is coupled to the control and test circuit 120. The sense amplifier block 160 includes a plurality of the above-mentioned sense amplifier circuits 110. The control and test circuit 120 and For the configuration relationship between the sense amplifier circuits 110 of the sense amplifier block 160, please refer to the disclosure in FIG. 1 described above.

FIG. 3 is a block diagram of a control and test circuit according to an embodiment of the disclosure. Referring to FIG. 3, the control and test circuit 120 includes a sensing control circuit 200 and a test read and write circuit 300 disposed beside the sensing control circuit 200. Both the sensing control circuit 200 and the test read and write circuit 300 are coupled to the sensing amplifier circuit 110 and provide a first precharge enable signal BLP1, a second precharge enable signal BLP2, a p-channel control voltage SAP, and an n-channel. The control voltage SAN, the first precharge voltage HFVT, and the second precharge voltage HFVN. In the test mode, the test read and write circuit 300 generates a test result TFAIL according to a comparison result between one of the first precharge voltage HFVT and the second precharge voltage HFVN and the test reference voltage TMREF to determine whether there is memory Unit MC failed. The following embodiments will explain in detail the mechanism of determining whether the memory unit MC has failed.

FIG. 4 is a schematic circuit diagram of a sensing control circuit according to an embodiment of the disclosure. Please refer to FIG. 4. In this embodiment, the sensing control circuit 200 includes a precharge enable control circuit 210 and a sensed amplified voltage control circuit 220. The precharge enable control circuit 210 is formed by, for example, inverters INV21 to INV26 and an inverse AND gate NA21.

Specifically, the input terminal of the inverter INV21 receives a precharge enable signal BLPE1, and the precharge enable signal BLPE1 is used to determine when to start precharging the bit BLT and the complementary bit line BLN, and the output terminal is coupled inversely. One input terminal of the gate NA21, and the other input terminal of the gate NA21 receive a column address signal X12B13B. The column address signal X12B13B is used to select which word line WL to act, and the output terminal is coupled to the inversion An input terminal of the inverter INV22, the inverter INV22 is connected in series with the inverter INV23, and the inverter INV23 outputs a first precharge enable signal BLP1. The inverter INV24, the inverter INV25 and the inverter INV26 are sequentially connected in series. The inverter INV24 receives the column address signal X12B13B, and the inverter INV26 outputs a second precharge enable signal BLP2.

Therefore, the precharge enable control circuit 210 is coupled to the sense amplifier circuit 110, and generates a first precharge enable signal BLP1 and a second precharge enable signal BLP2 according to the precharge enable signal BLPE1 and the column address signal X12B13B to provide Gives a sense amplifier circuit 110. When performing a test write operation and a test read operation on the memory cell MC, the precharge enable control circuit 210 may control the logic level of the first precharge enable signal BLP1 to switch the voltage level and the logic level of the second precharge enable signal BLP2. The bit is different from the first precharge enable signal BLP1, and after the test write operation and the test read operation are completed, the precharge enable control circuit 210 switches the voltage level of the second precharge enable signal BLP2 to restore and The logic level of the first precharge enable signal BLP1 is the same.

In addition, the sense amplifier voltage control circuit 220 is composed of inverters INV27 to INV29, inverter gates NA22 and NA23, and switches Q21 to Q25. The switches Q21 to Q25 described above are implemented by using a transistor to convert The voltage levels of the SAP output node NP and the SAN output node NN are switched between the precharge reference voltage HFV, the power supply voltage VDD, and the ground voltage VSS, respectively. The SAP output node NP and the SAN output node NN can output the p-channel control voltage SAP and the n-channel control voltage SAN.

Specifically, the NAND gate NA22 and the NAND gate NA23 receive the column address signal X12B13B, and the other input ends thereof respectively receive the sensing enable signals SE2 and SE1, the NAND gate NA22 and the inverter INV27, and the inverter INV28. In series, the switch Q21 is controlled by the output signal of the inverter INV28, and the first end thereof receives the power supply voltage VDD, and the second end is coupled to the SAP output node NP to pull up the p-channel control voltage SAP to the power supply voltage. VDD.

The inverse gate NA23 is connected in series with the inverter INV29. The switch Q22 is controlled by the output signal of the inverter INV29, and its first terminal is coupled to the SAN output node NN, and its second terminal is coupled to the ground voltage VSS to connect n The channel control voltage SAN is pulled down to the ground voltage VSS.

The switches Q23, Q24, and Q25 are all controlled by the second precharge enable signal BLP2. The first ends of the switches Q24 and Q25 receive a precharge reference voltage HFV. The precharge reference voltage HFV is lower than the power supply voltage VDD. Generally In other words, the voltage value of the precharge reference voltage HFV is substantially half of the power supply voltage VDD. The second terminal of the switch Q24 is coupled to the first terminal of the switch Q23, the second terminal of the switch Q25 is coupled to the SAP output node NP, and the second terminal of the switch Q23 is coupled to the SAN output node NN. Switches Q23 to Q25 are used to enable the second precharge enable signal BLP2 (for example, switches Q23 to Q25 use an n-channel transistor as an example here, so the second precharge enable signal BLP2 is enabled The period is a high level state) The voltage levels of the p-channel control voltage SAP and the n-channel control voltage SAN are restored to the precharged reference voltage HFV.

FIG. 5 is a circuit diagram of a test read and write circuit according to an embodiment of the disclosure. Referring to FIG. 5, the test read and write circuit 300 includes a pre-charge voltage control circuit 310 and a test comparison circuit 320. The pre-charge voltage control circuit 310 is coupled to the test comparison circuit 320 and the sense amplifier circuit 110. For example, the precharge voltage control circuit 310 includes inverters INV31 to INV33, inverter gates NA31 to NA33, inverter gates NO31 and NO32, switches Q31 to Q36, and transmission gates TG31 to TG34. The test comparison circuit 320 includes a comparator 312, inverters INV34 and INV35, inverse gates NA34 and NA35, invertor gates NO33 and switches Q37-Q39. In this embodiment, the switches Q31 to Q39 and the transmission gates TG31 to TG34 are implemented as CMOS transistors, but are not limited thereto.

In this embodiment, the test comparison circuit 320 further includes a latch circuit 314, but it is not necessary. In another embodiment, the test comparison circuit 320 may not include the latch circuit 314.

Specifically, the reverse gate NA31 of the precharge voltage control circuit 310 receives the column address signal X12B13B and the test enable signal TEST. The output terminal of the reverse gate NA31 is coupled to the inverter INV31, the transmission gate TG31, and the transmission gate TG32. The n-channel gate, the output terminal of the inverter INV31 is coupled to the p-channel gate of the transmission gate TG31 and the transmission gate TG32, and one end of the transmission gate TG31 and the transmission gate TG32 receives the precharge reference voltage HFV, and the other ends thereof are respectively coupled To the HFVT output node NHT and the HFVN output node NHN, the HFVT output node NHT and the HFVN output node NHN provide the first precharge voltage HFVT and the second precharge voltage HFVN to the sense amplifier circuit 110, respectively. Here, the transmission gate TG31 and the transmission gate TG32 are simultaneously turned on or turned off at the same time, and when turned on, the HFVT output node NHT and the HFVN output node NHN simultaneously receive the precharge reference voltage HFV.

The inverter INV32 receives the test data signal TDA, and its output terminal is coupled to the p-channel gate of the transmission gate TG33, the n-channel gate of the transmission gate TG34, the input terminal of the inverter INV33 and one of the input terminals of the OR gate NO31. . The output terminal of the inverter INV33 is coupled to one of the input terminals of the n-channel gate of the transmission gate TG33, the p-channel gate of the transmission gate TG34 and the reverse OR gate NO32. One end of the transmission gate TG33 and the transmission gate TG34 are respectively coupled to the HFVT output node NHT and the HFVN output node NHN, and the other end thereof is commonly coupled to the inverting input terminal of the comparator 312 of the test comparison circuit 320, and is used to connect the first One of the charging voltage HFVT and the second pre-charging voltage HFVN is supplied to the comparator 312.

Reverse gate NA32 receives the column address signal X12B13B and the test data line precharge signal TPIO. Its output controls whether switch Q35 and switch Q36 are conducting, and the first ends of switches Q35 and Q36 receive the power supply voltage VDD. Two terminals are coupled to the HFVN output node NHN, and the second terminal of the switch Q36 is coupled to the HFVT output node NHT. Therefore, during the enabling period of the test data line precharge signal TPIO (here, for example, a high level state), the voltage values of the first precharge voltage HFVT and the second precharge voltage HFVN are pulled up to the power supply voltage VDD.

The NAND gate NA33 receives the column address signal X12B13B and the test write enable signal TWE, and its output terminal is coupled to the other input terminal of the NOR gate NO31 and the NOR gate NO32. The output of the NOR gate NO31 controls whether the switch Q31 and the switch Q34 are conductive, and the output of the NOR gate NO32 controls whether the switch Q32 and the switch Q33 are conductive. The first terminal of the switch Q31 receives the voltage power source VDD, and the second terminal thereof is coupled. The first terminal of the switch Q32 is connected to the HFVT output node NHT, and the second terminal of the switch Q32 is coupled to the ground voltage VSS. Therefore, the voltage level of the first precharge voltage HFVT can be changed to the ground voltage VSS or the voltage source VDD minus the switch Q31. The first terminal of the switch Q33 receives the voltage power source VDD, the second terminal of the switch Q33 is coupled to the first terminal of the switch Q34 and the HFVN output node NHN, and the second terminal of the switch Q34 is coupled to the ground voltage VSS, Therefore, the voltage level of the second precharge voltage HFVN can be changed to a voltage obtained by subtracting the threshold voltage of the switch Q33 from the ground voltage VSS or the voltage power source VDD.

Therefore, the precharge voltage control circuit 310 generates the first precharge voltage HFVT and the second precharge voltage HFVN according to the precharge reference voltage HFV, and further receives a test write enable signal TWE and a test data signal TDA to make the first precharge The voltage HFVT and the second precharge voltage HFVN may be a power voltage VDD, a voltage obtained by subtracting a threshold voltage of the transistor from the voltage power VDD, a ground voltage VSS, or a precharge reference voltage HFV.

Specifically, the inverse gate NA34 of the test comparison circuit 320 receives the column address signal X12B13B and the test data enable signal TDE, and outputs it to the inverter INV34. The output terminal of the inverter INV34 is coupled to the input of the inverter INV35. And an input terminal of the inverting gate NA35, and an output terminal of the inverter INV35 is coupled to one of the input terminals of the inverting gate NO33. The non-inverting input terminal of the comparator 312 receives the test reference voltage TMREF. The inverting input terminal receives one of the first precharge voltage HFVT and the second precharge voltage HFVN from the transmission gate TG33 or the transmission gate TG34. The output terminal is coupled to the other input terminal of the inverting gate NA35 and the inverting gate NO33. Here, the test reference voltage TMREF is a preset fixed voltage value, and its voltage value will be greater than a half of the power supply voltage VDD or higher than the precharge reference voltage HFV, and less than the power supply voltage VDD. For example, the test reference voltage TMREF can be three quarters of the supply voltage VDD.

The switch Q37 is controlled by the output result of the inverse gate NA35. A first terminal thereof is coupled to the power supply voltage VDD, and a second terminal thereof is coupled to the test node NT. The test node NT outputs a test result TFAIL. The switch Q38 is controlled by the output of the reverse OR gate NO33. A first terminal thereof is coupled to the test node NT, and a second terminal thereof is coupled to the ground voltage VSS. Therefore, the voltage level of the test result TFAIL can be changed to the power supply voltage VDD or the ground voltage VSS by the output result of the comparator 312.

In addition, the first end of the switch Q39 is also coupled to the test node NT, and the second end of the switch Q39 is coupled to the ground voltage VSS and is controlled by the test data line precharge signal TPIO to enable the precharge signal TPIO on the test data line. During the test, the voltage level of the test result TFAIL is pulled down to the ground voltage VSS. The latch circuit 314 is also coupled to the test node NT to latch the voltage level of the test result TFAIL.

In brief, the test comparison circuit 320 compares one of the first precharge voltage HFVT and the second precharge voltage HFVN and the test reference voltage TMREF to generate a test result TFAIL to determine whether there is a memory cell MC failure. When one of the precharge voltage HFVT and the second precharge voltage HFVN is greater than the test reference voltage TMREF, the test result TFAIL is substantially equal to one of the power supply voltage VDD and the ground voltage VSS, for example, to indicate the data sense of the memory cell MC. The test is successful, and when both the first precharge voltage HFVT and the second precharge voltage HFVN are less than the test reference voltage TMREF, the test result TFAIL is, for example, substantially equal to the other of the power supply voltage VDD and the ground voltage VSS to indicate the memory cell MC's data sensing failed. The following embodiments will further describe the implementation of the read-write test and the determination of whether the memory unit MC fails.

Next, please refer to FIG. 6 to FIG. 8. FIG. 6 to FIG. 8 respectively show waveform diagrams of test write operations of logic “0” and logic “1” of the memory device according to an embodiment of the present disclosure. The operations in FIGS. 6 to 8 can be applied to the embodiments in FIGS. 1 to 5. In the test write operation, taking any memory cell MC as an example, FIG. 6 shows the word line signal WLn, the test write enable signal TWE, and the sense enable signals SE1 and SE2 on the corresponding word line WL. Operation waveform diagrams of the first precharge enable signal BLP1 and the second precharge enable signal BLP2. Figure 7 shows the test write operation when the written data is logic "0". The first precharge voltage HFVT, the second precharge voltage HFVN, the p-channel control voltage SAP, the n-channel control voltage SAN, the bit line BLT and Operation waveform diagram of the voltage level of the complementary bit line BLN. It is particularly noted that the thin straight line segments shown in FIG. 7 and FIG. 8 without labels are used to represent the waveform action in FIG. 6. The labeling is no longer to avoid clutter of the screen. Those with ordinary knowledge in the art can know these by matching with FIG. 6. The meaning represented by thin straight line segments.

First with Figures 1 to 5, and referring to Figures 6 and 7, the first precharge voltage HFVT and the second precharge voltage HFVN are maintained at the precharge reference because the transmission gate TG31 and the transmission gate TG32 are turned on before testing. The voltage value of the voltage HFV. In the test write operation, especially during the test write sensing period tW, the voltage value of one of the first precharge voltage HFVT and the second precharge voltage HFVN is lower than the power supply voltage VDD but higher than the precharge reference. The voltage HFV, and the voltage value of the other voltage is lower than the precharge reference voltage HFV, for example, substantially equal to the ground voltage VSS.

First, taking the data representing logic "0" as an example, the test data signal TDA is set to a low level state, and at this time, the word line signal WLn and the test write enable signal TWE are The voltage is in a high level state. Therefore, the switches Q31 and Q34 will be turned off, and the switches Q32 and Q33 will be turned on. Here, the switches Q31 to Q34 are all based on n-channel transistors as an example, but they are not limited to this. The voltage of the first precharge voltage HFVT provided by the charging voltage control circuit 310 is pulled down to the ground voltage VSS, and the second precharge voltage HFVN is pulled up to the power supply voltage VDD minus the threshold voltage VTN of the n-channel transistor to obtain The magnitude of the voltage. It should be noted that the voltage value of the power supply voltage VDD will be greater than the sum of the voltage values of the precharge reference voltage HFV and the threshold voltage VTN.

Next, the precharge enable control circuit 210 switches the first precharge enable signal BLP1 from the original low level state to the high level state, but the second precharge enable signal BLP2 maintains the low level state so that the first The switch T1 and the second switch T2 are turned on, and the third switch T3 is turned off, and the bit line BLT and the complementary bit line BLN can receive the first precharge voltage HFVT and the second precharge voltage HFVN, respectively.

In particular, in this embodiment, when the test write operation is performed on the memory cell MC, and before the first precharge enable signal BLP1 is switched to the enabled state, that is, the first switch T1 and the second switch T2 Before being turned on, the voltage levels of the first precharge voltage HFVT and the second precharge voltage HFVN are not the same.

Next, the sense amplifier voltage control circuit 220 switches the p-channel control voltage SAP and the n-channel control voltage SAN from the precharge reference voltage HFV to the power supply voltage VDD and the ground voltage VSS, respectively. The voltage levels of the p-channel control voltage SAP and the n-channel control voltage SAN were originally maintained below the power supply voltage VDD, which is the same as the pre-charge reference voltage HFV. During the enable period of the sensing enable signals SE1 and SE2, the OFF Q21 and OFF Q22 are turned on, and the p-channel control voltage SAP and the n-channel control voltage SAN are switched to the power supply voltage VDD and the ground voltage VSS, respectively, to amplify the voltage difference between the bit line BLT and the complementary bit line BLN. Therefore, during the test write sensing period tW, the voltage level of the bit line BLT is substantially equal to the ground voltage VSS, and the voltage level of the complementary bit line BLN is the power supply voltage VDD, so that the memory cell MC stores the display logic "0" data.

Next, referring to FIGS. 1 to 5 with reference to FIGS. 6 and 8, FIG. 8 shows a test write operation when the write data is logic “1”, the first precharge voltage HFVT, the second precharge voltage HFVN, and the p channel. The operation waveforms of the control voltage SAP and the n-channel control voltage SAN. In the test write operation, taking the data representing the logic "1" to the memory cell MC as an example, the test data signal TDA is set to a high level state, and during the test write sensing period tW, the precharge The voltage of the first precharge voltage HFVT output by the voltage control circuit 310 is pulled up to the power supply voltage VDD minus the threshold voltage VTN of the n-channel transistor, and the voltage of the second precharge voltage HFVN The level is pulled down to the ground voltage VSS. For detailed implementation, those with ordinary knowledge in the art can obtain sufficient teaching and suggestions from the above embodiments and general knowledge, and will not be repeated here.

FIG. 9 to FIG. 11 are waveform diagrams of a test read operation of a memory device according to an embodiment of the disclosure. The operations in FIG. 9 to FIG. 11 can be applied to the embodiments in FIG. 1 to FIG. 8. Please refer to FIGS. 1 to 5 and refer to FIGS. 9 to 11. In the test read operation, taking any memory cell MC as an example, FIG. 9 shows the word line signal WLn, the sensing enable signals SE1 and SE2, and the test. The operation waveforms of the data line precharge signal TPIO, the test data enable signal TDE, the first precharge enable signal BLP1 and the second precharge enable signal BLP2. FIG. 10 and FIG. 11 respectively show the first precharge voltage HFVT, the second precharge voltage HFVN, the p-channel control voltage SAP, the n-channel control voltage SAN, Operation waveform diagrams of the voltage levels of the bit line BLT and the complementary bit line BLN. In particular, the thin straight line segments shown in Figs. 10 and 11 without labels are used to represent the waveform action in Fig. 9 and are no longer labeled to avoid cluttering the screen. Those skilled in the art can know these by matching with Fig. 9 The meaning represented by thin straight line segments.

Referring to FIG. 9 and FIG. 10 first, before the first precharge voltage HFVT and the second precharge voltage HFVN are tested, the transmission gate TG31 and the transmission gate TG32 are turned on and maintained at the precharge reference voltage HFV.

When a test read operation is performed on the memory cell MC, taking the data of the memory cell MC indicating a logic “0” as an example, the state of the word line signal WLn is at a high level, and before the test read sensing period tR , The data line precharge operation is performed first, that is, during the enable period of the test data line precharge signal TPIO, the switches Q35, Q36 and Q39 are turned on, so the first precharge voltage HFVT and the second precharge voltage HFVN are first The pull-up is substantially equal to the power supply voltage VDD, and the test node NT substantially receives the ground voltage VSS. Here, the switches Q35 and Q36 use p-channel transistors, and the switch Q39 uses n-channel transistors as examples.

After the data line precharge operation is finished, the test data line precharge signal TPIO is disabled (for example, a low level state), and the sensing enable signals SE1 and SE2 are changed to enable, so the p-channel control voltage SAP The n-channel control voltage SAN is switched from the precharge reference voltage HFV to the power supply voltage VDD and the ground voltage VSS, respectively.

Then, the first precharge enable signal BLP1 is switched from the original low level state to the high level state, and the second precharge enable signal BLP2 is maintained in the low level state. The first precharge enable signal BLP1 switched to a high level state will make the first switch T1 and the second switch T2 conductive. If the data of the memory cells MC on the same word line WL are successfully sensed, During the test read sensing period tR, the voltage levels of the first precharge voltage HFVT and the second precharge voltage HFVN are different, and the voltage level of one of the first precharge voltage HFVT and the second precharge voltage HFVN is maintained. At the power supply voltage VDD, the other voltage level is pulled down to be substantially equal to the ground voltage VSS. In the embodiment of FIG. 9, the second precharge voltage HFVN is maintained at the power supply voltage VDD and the first precharge voltage is maintained. HFVT is pulled down to ground voltage VSS as an example.

It is specifically noted that the time points at which the first precharge enable signal BLP1 is switched from the low level state to the high level state during the test write operation and the test read operation are different. Specifically, the first precharge The time when the enable signal BLP1 switches the voltage level during the test write operation is earlier than the time when the test read operation is performed. In the test write operation, the first precharge enable signal BLP1 is switched to a high level state earlier than the sensing enable signals SE1 and SE2. However, in the test read operation, the first precharge enable signal BLP1 is later than The sensing enable signals SE1 and SE2 are switched to a high level state.

Next, the comparator 312 receives one of the test reference voltage TMREF and the first precharge voltage HFVT and the second precharge voltage HFVN, for example, the voltage level is higher. Therefore, in this embodiment, the comparator 312 receives the test The reference voltage TMREF and the second precharge voltage HFVN, wherein the voltage value of the test reference voltage TMREF is preset to three-quarters of the power supply voltage VDD, and the second precharge voltage HFVN is substantially equal to the power supply voltage VDD at this moment. During the test read sensing period tR, since the second precharge voltage HFVN is greater than the test reference voltage TMREF, the test result TFAIL is set to a low voltage level, for example, substantially equal to the ground voltage VSS to represent the same word line WL The data on the memory cell MC were successfully sensed.

Please refer to FIG. 9 and FIG. 11, if the data sensing failure of the memory cells MC on the same word line WL occurs, the first precharge voltage HFVT and the second precharge voltage HFVN are originally at a high level. A signal, after the first precharge enable signal BLP1 is switched to a high level state so that the first switch T1 and the second switch T2 are turned on, the voltage value thereof is pulled down by the ground voltage VSS, and thus is smaller than the original voltage level.

In this embodiment, the second precharge voltage HFVN is originally at a high level, and the voltage value is substantially equal to the power supply voltage VDD, and the voltage value of the first precharge voltage HFVT is substantially equal to the ground voltage VSS. During the test read sensing period tR, after the first switch T1 and the second switch T2 are turned on, the first precharge voltage HFVT is still equal to the ground voltage VSS, but the second precharge voltage HFVN is pulled down to nearly half the power supply voltage. The magnitude of VDD, specifically, the voltage of the second pre-charging voltage HFVN will be reduced to the power source voltage VDD minus the threshold voltage VTN of the n-channel transistor. In one embodiment, the power source voltage VDD is 1.5 The threshold voltage VTN of the V, n-channel transistor is 0.7V, so the voltage after the second precharge voltage HFVN drops is close to a half of the power supply voltage VDD.

Next, the comparator 312 receives the test reference voltage TMREF and the second precharge voltage HFVN for comparison. The voltage value of the test reference voltage TMREF is preset to three-quarters of the power supply voltage VDD, and the voltage value of the second precharge voltage HFVN at this moment. The magnitude of the power supply voltage VDD, which is close to one-half, is smaller than the test reference voltage TMREF. Therefore, the test result TFAIL is set to change to a high voltage level. For example, the power supply voltage VDD is substantially equal to the power supply voltage VDD. Has a status of sensing failure.

In the embodiments of FIGS. 9 to 11, when the test read operation is performed on the memory cell MC, during the test read sensing period tR, one of the first precharge voltage HFVT and the second precharge voltage HFVN The voltage value is not greater than the power supply voltage VDD but higher than the precharge reference voltage HFV, and the other voltage value is lower than the precharge reference voltage HFV, for example, equal to the ground voltage VSS.

In another embodiment, the first precharge voltage HFVT may be in a high level state, and the comparator 312 receives the test reference voltage TMREF and the first precharge voltage HFVT for comparison. In a detailed implementation, the art has a general The knowledgeable person can obtain sufficient teaching from the above description and general knowledge, and will not repeat them here.

Please refer to FIG. 12, which illustrates an operation waveform diagram of a memory device writing logic “0” to all memory cells according to another embodiment of the present disclosure. This embodiment can be applied to the memory device 100 in the embodiment shown in FIG. 1 to FIG. 11. In the embodiment shown in FIG. 12, when the memory device 100 is powered on or reset (RESET), the memory device 100 will be within the extended writing period T, for example, less than 200 microseconds to 300 microseconds. In the embodiment of FIG. 12, the extended writing period T is approximately 300 microseconds as an example, a writing operation is performed on all the word lines WL in the memory device 100 and all connected sense amplifier circuits 110, and The ellipsis in FIG. 12 indicates this. That is, the memory device 100 of this embodiment can write data logic “0” to the memory cells MC on all the word lines WL in a short time. Regarding the implementation of the action waveform of FIG. 12, those having ordinary knowledge in the art can obtain sufficient suggestions and teachings from the embodiments of FIGS. 6 to 8, which will not be repeated here.

In summary, the present disclosure provides a memory device including a pre-charge voltage control circuit and a sense amplifier circuit. The precharge voltage control circuit generates a first precharge voltage and a second precharge voltage according to a precharge reference voltage. The sense amplifier circuit is coupled between the bit line and the complementary bit line to sense data of the memory cell coupled to the bit line, and is coupled to the precharge voltage control circuit so that the bit line is complementary to the bit line. The bit line receives the first precharge voltage and the second precharge voltage, respectively. In the precharge operation, the voltage levels of the first precharge voltage and the second precharge voltage are the same. The test write after the precharge operation The voltage levels of the first precharge voltage and the second precharge voltage provided by the precharge voltage control circuit to the bit line and the complementary bit line are different between the input sensing period and the test read sensing period. In this way, a plurality of sense amplifiers on a character line can be selected in a cycle to perform a parallel test mode.

Although the present disclosure has been disclosed as above by way of example, it is not intended to limit the present disclosure. Any person with ordinary knowledge in the technical field should make some changes and modifications without departing from the spirit and scope of the present disclosure. The scope of protection of this disclosure shall be determined by the scope of the attached patent application.

100‧‧‧Memory circuit

110‧‧‧sensing amplifier circuit

120‧‧‧Control and test circuit

130‧‧‧Memory Array

140‧‧‧X decoder block

150‧‧‧Y decoder block

160‧‧‧Sense amplifier block

200‧‧‧sensing control circuit

210‧‧‧Pre-charge enable control circuit

220‧‧‧sense amplified voltage control circuit

300‧‧‧Test read and write circuit

310‧‧‧Pre-charge voltage control circuit

312‧‧‧ Comparator

314‧‧‧Latch circuit

320‧‧‧Test comparison circuit

BLT‧‧‧Bit Line

BLN‧‧‧Complementary bit line

BLPE1‧‧‧Precharge enable signal

BLP1‧‧‧First precharge enable signal

BLP2‧‧‧Second precharge enable signal

HFV‧‧‧Precharge reference voltage

HFVT‧‧‧First precharge voltage

HFVN‧‧‧Second precharge voltage

INV‧‧‧ Inverter

MC‧‧‧Memory Unit

N1‧‧‧First intermediate node

N2‧‧‧Second intermediate node

NP‧‧‧SAP output node

NN‧‧‧SAN output node

NHT‧‧‧HFVT output node

NHN‧‧‧HFVN output node

NT‧‧‧test node

NA21 ~ NA23, NA31 ~ NA35‧‧‧Reverse gate

NO31 ~ NO33‧‧‧Reverse OR gate

Q1, Q2, Q3, Q4‧‧‧ transistor

Q21 ~ Q25, Q1 ~ Q39‧‧‧Switch

SA‧‧‧sensing circuit

SE1, SE2‧‧‧Sensor enable signal

SAP‧‧‧p channel control voltage

SAN‧‧‧n channel control voltage

T‧‧‧Extended Write Cycle

T1‧‧‧First switch

T2‧‧‧Second switch

T3‧‧‧Third switch

TG31 ~ TG34‧‧‧Transmission gate

TFAIL‧‧‧Test results

TWE‧‧‧Test write enable signal

TDA‧‧‧Test data signal

TDE‧‧‧Test data enable signal

TEST‧‧‧test enable signal

TPIO‧‧‧Test data line precharge signal

tR‧‧‧ During test read sensing

tW‧‧‧Test write sensing period

TMREF‧‧‧Test reference voltage

VDD‧‧‧ supply voltage

VSS‧‧‧ ground voltage

VTN‧‧‧ threshold voltage of transistor

WL‧‧‧Character Line

WLn, WLm‧‧‧Word line signal

X12B13B‧‧‧column address signal

FIG. 1 is a schematic diagram of a memory device according to an embodiment of the disclosure. FIG. 2 is a schematic diagram of an array structure of a memory device according to an embodiment of the disclosure. FIG. 3 is a block diagram of a control and test circuit according to an embodiment of the disclosure. FIG. 4 is a schematic circuit diagram of a sensing control circuit according to an embodiment of the disclosure. FIG. 5 is a circuit diagram of a test read and write circuit according to an embodiment of the disclosure. FIGS. 6 to 8 are waveform diagrams of test write operations of logic “0” and logic “1” of the memory device according to an embodiment of the disclosure. FIG. 9 to FIG. 11 are waveform diagrams of a test read operation of a memory device according to an embodiment of the disclosure. FIG. 12 is an operation waveform diagram of a memory device writing logic “0” to all memory cells according to another embodiment of the disclosure.

Claims (14)

A memory device includes: a precharge voltage control circuit that generates a first precharge voltage and a second precharge voltage according to a precharge reference voltage; and a sense amplifier circuit, which is coupled between a bit line and a complementary bit line. Sensing the data of the memory unit coupled to the bit line, and the sensing amplifier circuit is coupled to the precharge voltage control circuit, so that the bit line and the complementary bit line are respectively received The first pre-charging voltage and the second pre-charging voltage, wherein in the pre-charging operation, the voltage levels of the first pre-charging voltage and the second pre-charging voltage are the same, and in the pre-charging During the test write sensing period and the test read sensing period after the operation, the precharge voltage control circuit provides the first precharge voltage and the first precharge voltage of the bit line and the complementary bit line to the bit line and the complementary bit line. The voltage levels of the two precharge voltages are different; and a test comparison circuit is coupled to the precharge voltage control circuit to compare one of the first precharge voltage and the second precharge voltage and a test reference. Voltage to produce a test result, where when the first When one of the precharge voltage and the second precharge voltage is greater than the test reference voltage, the test result indicates that the data of the memory unit is successfully sensed, and when the first precharge voltage and the When the second precharge voltage is less than the test reference voltage, the test result indicates that data sensing of the memory unit has failed. The memory device according to item 1 of the patent application scope, wherein the sensing amplifier circuit includes: a first switch, a first end of which receives the first precharge voltage, and a second end of which is coupled to the bit line And is controlled by a first precharge enable signal; a second switch, a first end of which receives the second precharge voltage, a second end of which is coupled to the complementary bit line and is controlled by the first A precharge enable signal; a third switch coupled between the bit line and the complementary bit line, which is controlled by a second precharge enable signal; and a sensing circuit, which is coupled to all The bit line and the complementary bit line are used to amplify the voltage difference between the bit line and the complementary bit line. The memory device according to item 2 of the scope of patent application, further comprising: a precharge enable control circuit, coupled to the sensing amplifier circuit, for generating the first precharge enable signal according to a precharge enable signal And the second precharge enable signal, wherein when a test write operation and a test read operation are performed on the memory cell, the first precharge enable signal switches a voltage level and the second precharge The logic level of the charge enable signal is different from the first precharge enable signal, and the second precharge enable signal switches the voltage level after the test write operation and the test read operation are completed. To restore the same logic level as the first precharge enable signal. The memory device according to item 1 of the patent application range, wherein a voltage level of the test reference voltage is higher than the precharge reference voltage and less than a power supply voltage. The memory device according to item 4 of the scope of patent application, wherein when one of the first precharge voltage and the second precharge voltage is greater than the test reference voltage, the voltage value of the test result is substantially Is equal to one of the power supply voltage and the ground voltage, and when both the first precharge voltage and the second precharge voltage are less than the test reference voltage, the voltage value of the test result is substantially The other of the power supply voltage and the ground voltage. The memory device according to item 1 of the patent application scope, wherein during the test write sensing period, a voltage value of one of the first precharge voltage and the second precharge voltage is lower than a power source But the voltage is higher than the precharge reference voltage, and the voltage value of the other is lower than the precharge reference voltage. The memory device according to item 1 of the scope of patent application, wherein when the test read operation is performed on the memory unit, before the test read sensing period, the first precharge voltage and the The second precharge voltage is first pulled to be substantially equal to the power supply voltage. A test read and write method for a memory device is used to perform a test write operation and a test read operation on a memory unit. The test read and write method includes: generating a first precharge voltage and a second precharge voltage according to a precharge reference voltage. Charging voltage; causing the bit line and the complementary bit line to receive the first precharge voltage and the second precharge voltage, respectively, wherein in the precharge operation, the first precharge voltage and the second precharge voltage The voltage level of the precharge voltage is the same. During the test write sensing period and the test read sensing period after the precharge operation, the precharge voltage control circuit provides the bit line and the complementary bit. The voltage levels of the first precharge voltage and the second precharge voltage of the element wires are different; and comparing one of the first precharge voltage and the second precharge voltage and a test reference voltage to Generating a test result, wherein when one of the first precharge voltage and the second precharge voltage is greater than the test reference voltage, the test result indicates that the data sensing of the memory unit is successful, and When the first pre-charge Pressure and the second pre-charge voltage are less than the reference voltage test, the test result indicates the sensing of the data memory unit failure. The test read and write method according to item 8 of the scope of patent application, further comprising: controlling the first switch and the second switch by using a first precharge enable signal to determine whether the bit line and the complementary bit line are Receiving the first pre-charging voltage and the second pre-charging voltage, respectively; using a second pre-charging enable signal to control a third switch to determine whether to electrically connect the bit line and the complementary bit line; And using a sensing circuit to amplify the voltage difference between the bit line and the complementary bit line. The test reading and writing method according to item 9 of the scope of patent application, further comprising: generating the first precharge enable signal and the second precharge enable signal according to a precharge enable signal, wherein when the When the memory unit performs the test write operation and the test read operation, the first precharge enable signal switches a voltage level and the logic level of the second precharge enable signal and the first precharge enable signal are switched. A precharge enable signal is different, and after the test write operation and the test read operation are completed, the second precharge enable signal switches a voltage level to restore the same level as the first precharge enable The logic levels of the energy signals are the same. The test read-write method according to item 8 of the scope of the patent application, wherein a voltage level of the test reference voltage is higher than the precharge reference voltage and less than a power supply voltage. The test read-write method according to item 11 of the scope of patent application, wherein when one of the first precharge voltage and the second precharge voltage is greater than the test reference voltage, the voltage of the test result The value is substantially equal to one of the power supply voltage and the ground voltage, and when the first precharge voltage and the second precharge voltage are both less than the test reference voltage, the voltage value of the test result is substantially Is the other of the power supply voltage and the ground voltage. The test read-write method according to item 8 of the patent application scope, wherein in the test write sensing period, a voltage value of one of the first precharge voltage and the second precharge voltage is low At the power supply voltage but higher than the precharge reference voltage, and the voltage value of the other is lower than the precharge reference voltage. The test read-write method according to item 8 of the scope of patent application, wherein when the test read operation is performed on the memory unit, before the test read sensing period, the first precharge voltage and The second precharge voltage is first pulled to be substantially equal to the power supply voltage.