TWI657544B - Wafer level chip size packaging structure and manufacturing method thereof - Google Patents

Abstract

The present invention relates to the field of semiconductor device packaging technologies, and in particular, to a wafer level wafer size package structure and a preparation method thereof, which can be pre-cutted by a pre-cutting of the upper epoxy resin and cut to the lower protective film layer. Medium, but not cutting through the protective film layer, and then performing epoxy resin watering and subsequent processes, thereby forming a concave-convex structure on the bonding faces of the two different materials, and forming the concave-convex structure on the bonding faces of the two different materials to crack the product The risk of defects is reduced to a minimum, thereby improving product yield, quality and reliability.

Description

Wafer level wafer size package structure and preparation method thereof

The present invention relates to the field of semiconductor device packaging technologies, and in particular, to a wafer level wafer size package structure and a method for fabricating the same.

At present, wafer level chip size packaging (WLCSP) can form a flip chip based on wafer level molding, thereby forming a thinner body size package. The structure is such that it is widely used for packaging semiconductor components.

However, during the actual packaging process and subsequent reliability test, cracks often occur between the layers of the package structure, especially between the protective tape and the molding compound. Different materials are prone to minor cracks, which in turn makes it difficult for the package to support subsequent back-side treatment of the back of the chip or silicon, and outside the package. The water oxygen and the like may also invade the package through the above-mentioned cracks, thereby causing corrosion of components in the package, and finally reducing the packaging effect and the performance of the device.

In view of the above problems, the present invention describes a wafer level wafer size package structure, comprising: a die; a laminated protective film and a molding plastic layer, and the die is encapsulated in the protective film Between the film and the plastic layer; wherein the contact surface between the molding compound layer and the protective film is at least partially curved.

As a preferred embodiment, in the above wafer level wafer size package structure, a contact surface between the molding compound layer and the die is at least partially curved.

As a preferred embodiment, the wafer level wafer size package structure further includes: a connection structure electrically connected to the die through the molding plastic layer; wherein the connection structure is further protruded from the mold a plastic layer for electrically connecting the die to an external device.

As a preferred embodiment, the wafer level wafer size package structure includes a columnar metal and a solder pad, and the column metal is electrically connected to the die through the molding plastic layer, A solder pad is stacked on an upper surface of the columnar metal; wherein the die is electrically connected to the external device through the columnar metal and the pad in sequence.

In a preferred embodiment, the wafer level wafer size package structure, the die includes a semiconductor substrate and a passivation layer covering the upper surface of the semiconductor substrate; wherein the columnar metal sequentially penetrates the And molding a plastic layer and the passivation layer to a metal layer in the semiconductor substrate.

In a preferred embodiment, the wafer level wafer size package structure, the semiconductor substrate includes a substrate layer and a second metal layer covering the upper surface of the substrate layer; wherein the columnar metal is sequentially penetrated The dummy plastic layer and the passivation layer are connected to an upper surface of the second metal layer.

In a preferred embodiment, the wafer level wafer size package structure, the semiconductor substrate further includes a first metal layer, wherein the first metal layer is disposed under the substrate layer with respect to the second metal layer a surface; wherein the protective film and the molding compound layer wrap the exposed surface of the first metal layer.

As a preferred embodiment, the wafer level wafer size package structure, the contact surface between the molding compound layer and the first metal layer, and/or between the molding compound layer and the first substrate layer The contact surface and/or the contact surface between the molding compound layer and the second metal layer and/or the contact surface between the molding compound layer and the passivation layer are at least partially curved.

In a preferred embodiment, the wafer level wafer size package structure, the material of the first gold layer comprises at least one of titanium, nickel, and silver; and/or the material of the substrate layer is 矽; and / Or the material of the second metal layer is aluminum; and/or the columnar metal side material is copper.

As a preferred embodiment, in any of the above wafer level wafer size package structures, the curved surface is a curved surface.

The present application also provides a method for fabricating a wafer level wafer size package structure, comprising: preparing a semiconductor structure including a plurality of cells to be packaged; placing the semiconductor structure on a carrier; continuing to perform the semiconductor structure a first cutting process to form a first opening in the semiconductor structure between adjacent cells to be packaged, a bottom of the first opening being a curved shape; a film plastic layer is prepared to cover the exposed surface of the semiconductor structure and Filling the first opening; after removing the carrier, performing a second dicing process on the semiconductor structure through the first opening to form a plurality of the wafer-level wafer-sized package structures separated from each other; The first opening of the first cutting process has a larger diameter of the first opening formed on the semiconductor structure than a second opening formed by the second cutting process on the semiconductor structure.

As a preferred embodiment, in the above method for fabricating a wafer level wafer size package structure, a contact surface between the molding compound layer and the semiconductor structure is a curved surface at a bottom of the first opening.

As a preferred embodiment, in the above method for fabricating a wafer level wafer size package structure, the curved surface is a curved surface.

As a preferred embodiment, in the above method for fabricating a wafer level wafer size package structure, the step of preparing a semiconductor structure including a plurality of cells to be packaged comprises: preparing a die unit including the plurality of cells to be packaged based on the same substrate layer An array; a protective film is formed on the die unit to form the semiconductor structure.

As a preferred embodiment, the method for fabricating a wafer level wafer size package structure according to the same substrate layer, the step of preparing a die unit array including the plurality of cells to be packaged comprises: providing a substrate layer, and The substrate layer has a front surface and a back surface opposite to the front surface; a second metal layer, a passivation layer and a plurality of connection structures are formed over the front surface of the substrate layer, and the second metal layer covers the front side of the substrate layer a surface, the passivation layer partially covers a surface of the second metal layer, the connection structure is electrically connected to the second metal layer through the passivation layer; after the back surface of the substrate layer is thinned, sequentially prepared A first metal layer and a protective film cover the back surface of the substrate layer to form the die unit array; wherein each of the package units includes at least one of the connection structures.

As a preferred embodiment, the method for fabricating a wafer level wafer size package structure, the connection structure comprises a columnar metal and a pad, the method further comprising: preparing a second surface on the front surface of the substrate layer After the metal layer, a passivation layer is deposited to cover the surface of the second metal layer; a columnar metal is prepared to penetrate the passivation layer to the second metal layer, and the columnar connection structure is over the passivation layer; A pad is prepared over the columnar metal layer to form the connection structure.

As a preferred embodiment, the method for fabricating the wafer level wafer size package structure further includes: fixing the semiconductor structure on the carrier by using a double-sided tape; wherein the first metal layer is located at the Between the protective film and the substrate layer, the double-sided tape is located between the protective film and the carrier.

The package structure and the preparation method thereof provided in the present application have at least the following advantages or beneficial effects compared to the existing package structure and the preparation method thereof:

1) better electrical and thermal properties;

2) smaller size and weight;

3) forming a flip chip without lead frame, thereby greatly reducing the process cost;

4) A simpler preparation process;

5) Back-side treatment which can effectively support subsequent back-side of a chip or silicon, such as etching, metal preparation, etc. );

6) It can meet the requirements of ultra-thin wafer processing.

The invention is further illustrated by the following figures and specific examples, but is not to be construed as limiting.

Embodiment 1:

The first figure is a schematic diagram of a wafer level wafer size package structure (that is, a package structure formed by one package unit in a subsequent method embodiment) in the embodiment of the present invention, as shown in the first figure, in the embodiment A wafer level wafer size package structure includes:

a protective tape 11 and a bottom-up order on the protective film 11 (it is to be noted that the upper and lower directions in the present embodiment are corresponding to the drawings, in the actual structure The definition of the upper and lower directions may be set according to a specific structure, which should not be construed as limiting the technical solution itself. The first metal layer (such as the back metal) 12 and the substrate layer (such as 矽) are sequentially disposed. (Si) substrate) 13, a second metal layer (such as aluminum (Al) layer) 14 and a passivation layer (Passivation, abbreviated as PV) 15, and the above protective film 11 may have a convex portion at the intermediate portion and have a curved recess a structure in which a region of the protective film 11 adjacent to the wafer-level wafer-sized package structure is protruded from a region adjacent to an edge of the wafer-level wafer-sized package structure, and the first metal layer 12 is covered with a protective film. 11 the upper surface of the convex portion, and the substrate layer 13 covers the upper surface of the first metal layer 12, the second metal layer 14 covers the upper surface of the substrate layer 13, and the passivation layer 15 partially covers the second metal Upper surface; It should be noted that the above-mentioned film structure of the first metal layer 12, the substrate layer 13, the second metal layer 14, and the passivation layer 15 and their corresponding positional relationship are only an embodiment of a die. Depending on the structure of the packaged device, other film layers may be included in the die, or may be formed separately from other film layers.

At least one connection structure (not shown), and each connection structure includes a columnar metal (such as a copper pillar) 16 and a solder pad (Solder Bump) 18; in addition, the connection structure can pass through the above passivation The layer 15 is electrically connected to the second metal layer 14; for example, the columnar metal 16 penetrates the passivation layer 15 from the upper surface to the lower surface thereof, and the columnar metal 16 also protrudes from the upper surface of the passivation layer 15, the pad 18 It is then overlaid on the upper surface of the columnar metal 16 for subsequent connection of the device.

a molding compound 17 covering the sidewall of the columnar metal 16 and the upper surface of the passivation layer 15 and extending to cover the sidewall of the passivation layer 15, the sidewall of the second metal layer 14, and the sidewall of the substrate layer 13, The sidewall of the first metal layer 12 and the recessed region of the protective film 11 are provided with the first metal layer 12, the substrate layer 13, the second metal layer 14, and the passivation layer 15 together with the columnar metal 16 and the protective film 11 described above. package.

Wherein, the surface of the molding plastic layer (the material may be epoxy resin) 17 in contact with the protective film 11 is at least partially a curved surface, that is, the curved surface can increase the contact surface between the molding plastic layer 17 and the protective film 11, and further Preferably, the contact surface between the molding plastic layer 17 and the protective film 11 may be an arc surface recessed toward the central portion of the wafer level wafer size packaging structure as shown in the first figure. To further enhance the adhesion between the molded plastic layer 17 and the protective film 11.

Further, the contact surface between the first metal layer 12 and/or the substrate layer 13 and/or the second metal layer 14 and/or the passivation layer 15 and the molding compound layer 17 is not affected on the basis of the performance of the package structure. The surface may be at least partially disposed as a curved surface, such as an arcuate surface between the molding compound layer 17 and the protective film 11 as shown in the first figure, thereby enhancing the relationship between the plastic layer 17 and the film layer in contact therewith. Adhesion.

Preferably, the material of the first metal layer may be at least one of metals such as titanium (Ti), nickel (Ni), and silver (Ag).

The second figure is a top view of the structure shown in the first figure. As shown in the first figure and the second figure, the height A of the wafer level wafer size package structure in this embodiment ranges from 0.175 to 0.250 mm (better. The value is 0.175 mm, 0.200 mm or 0.250 mm, the length D ranges from 0.585 to 0.615 mm (preferably 0.585 mm, 0.600 mm or 0.615 mm, etc.), and the width E ranges from 0.285 to 0.315 mm ( Preferably, the connection structure (including the columnar metal 16 and the pad 18) is in the length D direction along the wafer level wafer size package structure (ie, The length D1 of the lateral direction shown in the second figure is in the range of 0.090 to 0.190 mm (preferably 0.090 mm, 0.140 mm or 0.190 mm, etc.), and the connection structure is in the width E of the wafer level wafer size package structure. The length E1 in the direction ranges from 0.190 to 0.290 mm (preferably 0.190 mm, 0.240 mm or 0.290 mm, etc.); the length of the distance D2 between adjacent connection structures in the same wafer level wafer size package structure The range is 0.210 to 0.310 mm (preferably 0.210 mm, 0.260 mm or 0.310 mm equivalent).

In the present embodiment, since the molding plastic layer 17 can have a larger contact surface with other film layers such as the protective film 11, the adhesion between the molding layers can be effectively improved, and the curved surface (for example, can be set) a concave-convex structure (such as a protrusion formed by the molding plastic layer 17 and a groove matching the protrusion and extending into the protective film 11 to form the curved surface) can further enhance the film layer between Adhesion, which can effectively reduce the probability of cracks between the layers during the back processing, storage and use of the wafer level wafer package structure, and finally effectively improve the packaging effect of the device and prepare the product. Performance, that is, the uneven structure on the bonding surface of two different materials, can minimize the risk of defects such as product cracking, thereby improving the yield, quality and reliability of the product; at the same time, the edge of the wafer-level wafer size package structure The recessed structure provided can further improve the conductivity and heat dissipation performance of the package structure.

Embodiment 2:

The method for preparing a wafer level wafer size package structure in this embodiment may include:

First, a semiconductor structure including a plurality of cells to be packaged can be prepared, and after the semiconductor structure is placed on a carrier, the first dicing process of the semiconductor structure is continued to form a semiconductor structure between adjacent package cells. Forming a first opening therein;

Next, preparing a film plastic layer covering the exposed surface of the semiconductor structure and filling the first opening, removing the carrier, and performing a second cutting process on the semiconductor structure through the first opening to separate the plurality of wafer level wafers formed by the package unit Size package structure;

Wherein, the diameter of the first opening formed on the semiconductor structure by the first dicing process is larger than the diameter of the second opening formed on the semiconductor structure by the second dicing process, so as to avoid the occurrence of film layers in the semiconductor structure during the dicing process; crack.

Preferably, in each wafer level wafer size package structure formed, the contact surface between the molding compound layer and the semiconductor structure is at least partially a curved surface; for example, in the bottom of the first opening, the molding plastic layer and the semiconductor The contact surface between the structures is a curved surface such as an arcuate surface for increasing the adhesion between the molding plastic layer and each of the film layers in the semiconductor structure, thereby effectively preventing the occurrence of defects such as the above-mentioned cracks.

Preferably, the cutting process can be performed by using a cutting blade having a larger diameter than the diameter of the cutting blade used in the second cutting process in the first cutting process, so that the subsequent second cutting process only cuts the portion located in the first opening. The bottom region is such that the portion of the curved surface of the wafer-level wafer-size package structure after the separation is cut, thereby avoiding the preparation of the wafer-level wafer-size package structure for subsequent processes such as back processing, storage, and use. Cracks are formed between the layers during the process, which can effectively improve the packaging effect of the device and the performance of the prepared product.

3 to 12 are schematic flow diagrams showing a method of fabricating a wafer level wafer size package structure in an embodiment of the present invention; as shown in the third to twelfth drawings, the wafer level is prepared in this embodiment. The method of the wafer size package structure can be used to prepare the wafer level wafer size package structure described in the first embodiment (ie, the structure shown in the first figure and the second figure). The method may specifically include:

First, it may be based on a substrate layer (such as a germanium (Si) substrate) having a front surface (ie, an upper surface shown in FIG. 3) and a back surface opposite to the front surface (ie, a lower surface shown in FIG. 3). A first metal layer (such as an aluminum (Al) layer) 22 is prepared by a process such as sputtering to serve as a conductive layer for electrical connection between subsequent pads, that is, the second metal layer 22 covers the front surface of the substrate layer 21 The above-mentioned substrate layer 21 is provided with a plurality of cell regions to be packaged (not shown in the figure, in this embodiment, the two columnar metals 24 and the interval between them are used as a package unit region, However, it should not be understood as a limitation of the technical solution, and a dicing area is disposed between adjacent package unit regions; after that, after preparing a passivation layer 23 to cover the upper surface of the second metal layer 22, Part of the passivation layer 23 is removed by an etching process to form a plurality of trenches in the remaining passivation layer 23 for exposing a portion of the upper surface of the second metal layer 22; subsequently, a plurality of columnar metals separated from each other are prepared based on the trenches. (such as copper pill (copper pill) Ar)) 24, that is, the columnar metal 24 fills the above-mentioned slit and contacts the upper surface of the second metal layer 22, and the columnar metal 24 is also protruded from the upper surface of the passivation layer 23, thereby forming The structure shown in the third figure.

Next, as shown in the fourth figure, based on the structure shown in the third figure, a solder bump 25 is prepared on the upper surface of each of the columnar metal 24, thereby making each pad 25 and The columnar metal 24 located thereunder together form a connection structure, and adjacent connection structures in the same package unit are electrically connected through the second metal layer 22.

Thereafter, based on the structure shown in the fourth figure, the back surface of the substrate layer 21 is subjected to a thinning process (the back surface of the substrate layer 21, which is illustrated in the fifth to twelfth drawings in the present embodiment, is reduced. After the thin surface formed on the lower surface, that is, after removing the substrate 21 under the broken line in the fourth figure, the structure shown in the fifth figure is formed; based on the structure shown in the fifth figure, for example, a first metal layer (ie, a back metal) 26 is formed on the back surface of the substrate layer 21 shown in FIG. 5 by vapor deposition or sputtering, thereby forming the structure shown in FIG. 6; A metal layer 26 may be a single layer or a multilayer structure, that is, the first metal layer 26 includes at least one of metals such as titanium (Ti), nickel (Ni), and silver (Ag), and the first metal layer 26 The thickness may be 8 to 10 μm (such as 8 μm, 9 μm or 10 μm, etc.).

Further, as shown in the seventh figure, based on the structure shown in FIG. 6, the wafer backside protective taping 27 can be further formed on the lower surface of the first metal layer 26, thereby forming the seventh figure. The semiconductor structure shown in the seventh embodiment is fixed to a dummy wafer 29 by a double side tape 28, thereby forming the structure shown in the eighth figure.

Then, a first cutting process (ie, a pre-cut process) may be used to perform a pre-cutting process on the film layer in the cutting zone, and the depth of the cutting may be set according to specific process requirements (but not in the up and down direction) The protective film 27) of the semiconductor structure shown in FIG. 7 is configured to form a first opening in the semiconductor structure, and the bottom of the first opening has a curved shape (such as an arc shape or the like); in this embodiment, the cutting is stopped. The partial protective film 27 is exemplified by sequentially cutting the passivation layer 23, the second metal layer 22, the substrate layer 21, and the first metal layer 26 into the protective film 27 along the upper surface of the passivation layer 23 in the dicing region. Further, a first opening 30 as shown in FIG. 9 is formed; wherein, the shape characteristic of the cutting blade itself is selected, and an arc shape having a certain radius of curvature can be formed at the bottom of the first opening 30 (ie, the dotted circle in the ninth figure) Circled area).

Further, a film molding compound 31 is filled in the first opening 30, and the film plastic layer 31 also fills a space formed between the columnar metals 24 between the adjacent connection structures, that is, the film plastic layer. 31 covering the sidewall of the columnar metal 24 and the upper surface of the passivation layer 23 and extending to cover the sidewall of the passivation layer 23, the sidewall of the second metal layer 22, the sidewall of the substrate layer 21, the sidewall of the first metal layer 26, and The recessed region of the protective film 27 (ie, the region at the bottom of the first opening 30), together with the above-described columnar metal 24 and protective film 27, the first metal layer 26, the substrate layer 21, the second metal layer 22, and the passivation layer 23 All are wrapped. In addition, the material of the protective film 27 may be different from the material of the film plastic layer 31.

Further, based on the structure shown in FIG. 10, the above-described carrier sheet 29 and the double-sided tape 28 are removed to form a structure as shown in the first figure, and the structure shown in FIG. 11 is oriented in the direction indicated by the arrow 32. Cutting a portion of the film plastic layer 31 above the first opening and the protective film 27 to the protective film 27 from the top and bottom in the cutting zone by using a second cutting process (Dicing) to pass different packaging unit regions Separating, thereby forming a wafer level wafer size package structure as shown in the first and second figures.

Wherein, since the curved groove is formed at the bottom of the first opening 30, the surface of the protective film 27 contacting the film plastic layer 31 is an arc-shaped contact surface, thereby effectively preventing the second cutting process. The crack generated between the protective film 27 and the film plastic layer 31; at the same time, since the diameter of the cutting blade used in the second cutting process is smaller than the diameter of the cutting blade used in the first cutting process, the final cutting separation can be formed. The above-mentioned curved contact surface can be retained in the wafer level wafer size package structure, thereby increasing the adhesion between the film layers, especially between the protective film 27 and the film plastic layer 31, to effectively reduce the prepared crystal. The probability of cracks generated between the film layers during back processing, storage, and use of the wafer-level package structure (in this embodiment, only the contact surface between the protective film 27 and the film plastic layer 31 is curved, and The film plastic layer 31 and other film layers such as the first metal layer 26, the substrate layer 21, and the like may also be disposed as curved contact faces to enhance the adhesion between the film layers, due to technical solutions. Like, so here it will not be described herein, but should not be construed as limiting the present disclosure).

It should be noted that the method for fabricating the wafer level wafer size package structure described in the second embodiment can be used to prepare the wafer level wafer size package structure described in the first embodiment above (of course, other processes can also be used. The method of fabricating the wafer level wafer size package structure described in the first embodiment above is as long as a bump structure capable of reducing the risk of cracking or the like is formed on the bonding surface of the two different materials in the wafer level wafer size package structure. Therefore, the same or similar technical features and corresponding limitations between the two embodiments can be used interchangeably.

In summary, the present invention discloses a wafer level wafer size package structure and a method for fabricating the same, which is performed by a semiconductor chip structure having a plurality of semiconductor structures to be packaged (ie, a second dicing process). Performing a pre-cutting process (ie, a first dicing process) in the dicing region of the structure to form an opening having a curved surface at the bottom in the semiconductor structure, and continuing to fill the plastic layer of the film through the opening, thereby being able to increase The contact area between the plastic layer of the film and the semiconductor structure is followed by a second cutting process having a smaller cutting radius (ie, the cutting radius is smaller than the first cutting radius) to separate the package unit regions into mutually independent wafer level wafer size package structures; During the second cutting process, the molding plastic layer and the semiconductor structure are always in contact connection and have a relatively large connection area, thereby effectively avoiding cracks between the film layers caused by the second cutting process, especially It can greatly reduce the probability of cracks between the protective film and the molding compound, which can be passed through the upper layer of epoxy. Before the grease (ie, the plastic layer) is poured, the wafer is pre-cut and cut into the underlying protective film layer, but the protective film layer is not cut through, and then the epoxy resin is poured and the subsequent process is performed. Two different material bonding faces form a concave-convex structure, which can minimize the risk of defects such as product cracking, thereby improving product yield, quality and reliability; and forming a wafer-level wafer size package structure Compared with the conventional process, the structure has a large contact area between the molding plastic layer and the semiconductor structure, thereby effectively preventing the subsequent processing, storage and use of the wafer level wafer package structure. The cracks generated between the layers can ultimately improve the packaging effect of the device and the performance of the prepared product.

A person skilled in the art should understand that variations may be implemented by those skilled in the art in combination with the prior art and the foregoing embodiments, and no further details are provided herein. Such variations do not affect the substance of the present invention and will not be described herein.

The preferred embodiments of the present invention have been described above. It is to be understood that the invention is not limited to the specific embodiments described above, and that the device and structure are not described in detail. Many variations and modifications of the technical solutions of the present invention can be made, or modified to equivalent variations, without departing from the spirit and scope of the invention. Therefore, any simple modifications, equivalent changes, and modifications of the above embodiments may be made without departing from the spirit and scope of the invention.

11‧‧‧Protective film

12‧‧‧First metal layer

13‧‧‧Backing layer

14‧‧‧Second metal layer

15‧‧‧ Passivation layer

16‧‧‧ Columnar metal

17‧‧‧Molded plastic layer

18‧‧‧ solder pads

21‧‧‧Backing layer

22‧‧‧Second metal layer

23‧‧‧ Passivation layer

24‧‧‧ Columnar metal

25‧‧‧ solder pads

26‧‧‧First metal layer

27‧‧‧Protective layer

28‧‧‧ double-sided adhesive layer

29‧‧‧ slides

30‧‧‧first opening

31‧‧‧Molded plastic layer

32‧‧‧ arrow

A‧‧‧ Height

D, D1, D2‧‧‧ length

E‧‧‧Width

E1‧‧‧ length

The first figure is a schematic view of a wafer level wafer size package structure in the embodiment of the present invention; the second figure is a top view of the structure shown in the first figure; and the third figure - the twelfth figure is a wafer level prepared in the embodiment of the present invention. Schematic diagram of the process structure of the method of wafer size packaging structure.

Claims (17)

A wafer level wafer size package structure, the improvement comprising: a die; a laminated protective film and a molding plastic layer, wherein the die is encapsulated between the protective film and the film plastic layer; The contact surface between the molding plastic layer and the protective film is at least partially curved; the protective film has a structure in which the convex portion of the intermediate portion has a curved recess, and the contact surface is a wafer-level wafer size. An arcuate surface in which the central portion of the package structure is recessed. The wafer level wafer size package structure of claim 1, wherein the contact surface between the molding compound layer and the die is at least partially curved. The wafer level wafer size package structure of claim 1, wherein the wafer level wafer size package structure further comprises: a connection structure electrically connected to the die through the molding plastic layer; wherein The connection structure also protrudes from the molding compound layer for electrically connecting the die to an external device. The wafer level wafer size package structure of claim 3, wherein the connection structure comprises a columnar metal and a bonding pad, and the columnar metal is electrically connected to the die through the molding plastic layer The solder pad is stacked on an upper surface of the columnar metal, and the die is electrically connected to the external device through the columnar metal and the pad in sequence. The wafer level wafer size package structure of claim 4, wherein the die comprises a semiconductor substrate and a passivation layer covering an upper surface of the semiconductor substrate, wherein the columnar metal is sequentially penetrated Depicting the plastic layer and the passivation layer into the semiconductor substrate Metal layer. The wafer level wafer size package structure of claim 5, wherein the semiconductor substrate comprises a substrate layer and a second metal layer covering the upper surface of the substrate layer, the columnar metal sequentially passing through The molding compound layer and the passivation layer are connected to an upper surface of the second metal layer. The wafer level wafer size package structure of claim 6, wherein the semiconductor substrate further comprises a first metal layer, wherein the first metal layer is disposed on the second metal layer relative to the second metal layer a lower surface of the substrate layer, the protective film and the molding compound layer wrap the exposed surface of the first metal layer. The wafer level wafer size package structure of claim 7, wherein the contact surface between the molding compound layer and the first metal layer and/or the molding compound layer and the first lining The contact surface between the bottom layers and/or the contact surface between the molding compound layer and the second metal layer and/or the contact surface between the molding compound layer and the passivation layer are at least partially curved. The wafer level wafer size package structure of claim 8, wherein the material of the first gold layer comprises at least one of titanium, nickel, and silver; and/or the material of the substrate layer is 矽And/or the material of the second metal layer is aluminum; and/or the columnar metal side material is copper. The wafer level wafer size package structure of claim 1, wherein the curved surface is a curved surface. A method for fabricating a wafer level wafer size package structure, comprising: preparing a semiconductor structure including a plurality of cells to be packaged; Placing the semiconductor structure on a carrier; continuing to perform a first dicing process on the semiconductor structure to form a first opening in the semiconductor structure between adjacent cells to be packaged, the first The bottom of the opening has a curved shape; a film plastic layer is prepared to cover the exposed surface of the semiconductor structure and fills the first opening; after the carrier is removed, the semiconductor structure is subjected to a second cutting process through the first opening Forming a plurality of the wafer level wafer size package structures separated from each other; wherein the first opening process has a larger diameter of the first opening formed on the semiconductor structure than the second cutting process A diameter of the second opening formed in the semiconductor structure. The method of fabricating a wafer level wafer size package structure according to claim 11, wherein a contact surface between the molding compound layer and the semiconductor structure is a curved surface at a bottom of the first opening. The method of fabricating a wafer level wafer size package structure according to claim 12, wherein the curved surface is a curved surface. The method of fabricating a wafer level wafer size package structure according to claim 11, wherein the step of preparing a semiconductor structure including a plurality of cells to be packaged comprises: preparing a plurality of cells to be packaged based on the same substrate layer a die unit array; a protective film is formed on the die unit to form the semiconductor structure. The method of fabricating a wafer level wafer size package structure according to claim 14, wherein the step of preparing the die unit array including the plurality of cells to be packaged based on the same substrate layer comprises: providing a substrate layer And the substrate layer has a front side and a back side opposite the front side; Preparing a second metal layer, a passivation layer and a plurality of connection structures over the front surface of the substrate layer, and the second metal layer covers a front surface of the substrate layer, the passivation layer partially covering the second metal a surface of the layer, the connection structure is electrically connected to the second metal layer through the passivation layer; after thinning the back surface of the substrate layer, sequentially preparing a first metal layer and a protective film covering the substrate layer On the back surface, to form the die unit array, each of the package units includes at least one of the connection structures. The method of fabricating a wafer level wafer size package structure according to claim 15, wherein the connection structure comprises a columnar metal and a pad, the method further comprising: on a front surface of the substrate layer After preparing the second metal layer, depositing a passivation layer covering the surface of the second metal layer; preparing a columnar metal penetrating the passivation layer to the second metal layer, and the columnar connection structure is in the passivation layer Forming a solder pad over the columnar metal layer to form the connection structure. The method for fabricating a wafer level wafer size package structure according to claim 15 , further comprising: fixing the semiconductor structure on the carrier by using a double-sided tape, the first metal layer being located Between the protective film and the substrate layer, the double-sided tape is located between the protective film and the carrier.