TWI656535B - Non-volatile memory writing method of system chip - Google Patents

Abstract

A method for writing non-volatile memory of a system chip includes: (a) inputting a write address signal to a write address judgment logic; (b) judging that the write address signal is a lower limit or an upper limit of a specific address range To generate a selection code signal; (c) input the selection code signal to a multiplexer; (d) input a random number signal generated by a random number generator to the multiplexer; and (f) input a random number Signal to non-volatile memory to write to a specific address range of the non-volatile memory.

Description

Method for writing non-volatile memory of system chip

The present invention relates to a system chip, and more particularly, to a method for preventing non-volatile memory of the system chip from being copied.

The non-volatile memory integrated in the System on Chip (SoC) can store programs or data. After a power failure, the program or data can still be stored in the non-volatile memory. After restarting the power, the system A single chip can still perform the same function based on what is stored in non-volatile memory.

Users can use the same type of system single chip to develop programs or data stored in non-volatile memory according to different needs. If the program or data stored in the non-volatile memory is obtained by others, others can use the same program or data to copy the system function chip with the same function, which is something the user is unwilling to happen.

At present, there are many methods for protecting, preventing the probing or reading of programs or data stored in non-volatile memory, which is limited to the physical protection of the system single chip itself. If the original source of the program or data is stolen, all existing Physical protection is ineffective. Other methods, such as adding a cryptographically protected design of a Physically Unclonable Function (PUF) to the chip (eg, Patent Bulletin No. I488477), require special processes (eg, Patent Bulletin No. I571906), or special designs (eg, Patent Publication No. 201734879).

In view of the shortcomings of the above-mentioned conventional techniques, the present invention provides a novel method for preventing non-volatile memory of a system chip from being copied to overcome the above shortcomings.

The invention proposes a method for forcibly restricting writing and only writing random numbers in a specific address range of non-volatile memory in a system single chip. Therefore, different system single chips will have physical differences due to the different data in the specific address range, forming an absolute physical obstacle that cannot be completely copied.

The writing method of the non-volatile memory is completed by the non-volatile memory controller of the present invention. The controller can be implemented by a logic circuit in a chip, and must be designed to be completely uncontrollable by a program. The controller can automatically detect whether the write address is within a specific address range. If it falls within the range, it automatically selects the output of the random number generator as the write data. If it falls outside the range, it can be compared with ordinary non-volatile The memory controller is the same, and the write data signal of the system bus is selected as the write data.

In the present invention, a relatively large specific address range of nonvolatile memory can be designed, and a random number generator with relatively good random number source characteristics is selected, so that the probability of data duplication within a specific address range can be Drop to negligible levels.

A method for writing non-volatile memory of a system chip includes (a) inputting a write address signal to a write address judgment logic; (b) judging the write address in the write address judgment logic The signal is the lower or upper bound of a specific address range to generate a selection code signal; (c) input the selection code signal to a switching device to control a selection terminal of the switching device; (d) input a random number to generate The random number write data signal generated by the controller to the selection end of the switching device; and (f) input the random number write data signal to the non-volatile memory to write a specific address range of the non-volatile memory .

According to another aspect of the present invention, the system chip includes a processing unit, a random number generator, a non-volatile memory control module, a non-volatile memory, and a bus controller.

According to an aspect of the present invention, the non-volatile memory control module is coupled to a non-volatile memory. Sex memory and random number generator.

In another aspect, the non-volatile memory control module includes a switching device, a write address judgment logic, and a non-volatile memory controller. The switching device includes at least one multiplexer, and the multiplexer includes an input terminal, an output terminal, and two selection terminals.

According to another aspect of the present invention, the writing data of the non-volatile memory control module in a specific address range cannot be controlled by the program.

Non-volatile memory includes flash memory, erasable programmable read-only memory (EPROM), electronically erasable programmable read-only memory (EEPROM), magnetic random access memory (MRAM), iron Electrical random access memory (FRAM), or other non-volatile memory that can be integrated on a silicon chip. The flash memory includes a single-layer memory cell NAND / NOR type flash memory, or a multi-layer memory cell NAND / NOR type flash memory.

These advantages and other advantages will make the reader understand the present invention clearly from the description of the following preferred embodiments and the scope of patent application.

10‧‧‧ Non-volatile memory device

100‧‧‧ processing unit

102‧‧‧ random number generator

104‧‧‧Non-volatile memory control module

106‧‧‧Non-volatile memory

108‧‧‧Bus Controller

110‧‧‧Bus

120‧‧‧Non-volatile memory controller

130‧‧‧write address judgment logic

140‧‧‧ Switching device

The detailed description of the present invention and the schematic diagrams of the embodiments described below should make the present invention more fully understood; however, it should be understood that this is only used as a reference for understanding the application of the present invention, rather than limiting the present invention to a specific implementation. Example.

The first diagram shows a functional block diagram of a non-volatile memory device according to an embodiment of the present invention; the second diagram shows a diagram of a non-volatile memory controller according to an embodiment of the present invention; the third diagram shows Non-volatile memory controller according to another embodiment of the present invention Function block diagram.

The present invention will be described in detail herein with regard to specific embodiments of the invention and their perspectives. Such descriptions are intended to explain the structure or flow of steps of the present invention, and are intended to be illustrative and not to limit the scope of patent application of the present invention. Therefore, in addition to the specific embodiments and preferred embodiments in the description, the present invention can be widely implemented in other different embodiments. The following describes the implementation of the present invention through specific specific examples. Those skilled in the art can easily understand the efficacy and advantages of the present invention through the content disclosed in this specification. In addition, the present invention can also be applied and implemented by other specific embodiments. The details described in this specification can also be applied based on different needs, and various modifications or changes can be made without departing from the spirit of the present invention.

The first figure shows a schematic diagram of a non-volatile memory device according to the present invention. In this embodiment, the non-volatile memory device 10 is a system chip, which includes a processing unit 100, a random number generator 102, a non-volatile memory control module 104, a non-volatile memory 106, and A bus controller 108. The non-volatile memory control module 104 is coupled to the non-volatile memory 106 and the random number generator 102. The non-volatile memory control module 104 may be implemented in a hardware type or a firmware type. For example, the non-volatile memory control module 104 is a logic circuit including a plurality of logic gates. The non-volatile memory control module 104 may perform data writing, reading, erasing, reforming, and / or other operations in the non-volatile memory 106 according to instructions issued by a host or the processing unit 100. . The processing unit 100, the random number generator 102, and the non-volatile memory control module 104 are combined by a bus 110 into a non-volatile memory device 10 capable of performing various signal processing.

The processing unit 100 is used to control the overall operation of the non-volatile memory control module 104. For example, the processing unit 100 may control the non-volatile memory control module 104 to execute the operation method of this embodiment, to restructure the non-volatile memory 106, or to write data into the non-volatile memory 106 In. For one embodiment, the non-volatile memory control module 104 maintains one or more logical to physical address information tables or address mapping tables to record data in non-volatile memory. The mapping relationship between the physical addresses in the body 106. Therefore, when the non-volatile memory 106 wants to access a certain logical address, the processing unit 100 can obtain the corresponding address according to the information table. Corresponding physical address, and access data at the physical address in the non-volatile memory 106.

For one embodiment, the non-volatile memory 106 includes one or more non-volatile memory modules, where the number of non-volatile memory modules depends on the application. For example, the non-volatile memory module has at least one physical block to store data written by the host or the processing unit 100. Each physical block has at least one page, wherein different pages belonging to the same physical block can be written independently, and all pages belonging to the same physical block can be erased simultaneously. For example, each physical block may be composed of 64, 128, 256, or any other number of pages. There are many types of non-volatile memory, including, for example, flash memory, EPROM, EEPROM, MRAM, FRAM, and other non-volatile memory that can be integrated on a silicon chip. The flash memory is, for example, a single-level cell (SLC) NAND-type flash memory, a multi-level memory cell (Multi-level cell: MLC) NAND-type flash memory, a triple-level memory cell (Triple Level Cell: TLC) NAND-type flash memory or other types of flash memory. Among them, each memory cell of the SLC NAND type flash memory can store 1 bit of data, each memory cell of the MLC NAND type flash memory can store 2 bits of data, and the TLC NAND type flash memory Each memory unit of the memory can store 3 bits of data. SLC NAND-type flash memory has lower power consumption and better battery life, while MLC NAND-type flash memory has higher power consumption and lower battery life.

For a multi-level memory cell and a three-level memory cell NAND flash memory, it has the characteristics of paired pages (Pair Page) and multiple pages in the same memory cell, that is, two pages in a memory cell. Or three pages of bit data. In addition, for the same physical block, these paired pages may be continuous or discontinuous, depending on different designs.

The random number generator 102 may be used to generate random numbers or random numbers. The random number generator 102 is coupled to the non-volatile memory control module 104, so that the operation of the system chip of the non-volatile memory 106 is implemented. That is, the non-volatile memory control module 104 executes: each time the non-volatile memory 106 is accessed, the non-volatile memory 106 is determined according to the random number generated by the random number generator 102. A program that writes to these specific address areas.

The non-volatile memory 106 has special control signals for writing or reading data. Timing, and the non-volatile memory 106 cannot be directly connected to the system bus 110, it needs to be controlled by the corresponding non-volatile memory control module 104, and the processing unit 100 can operate the non-volatile memory through the system bus 110 106. In the present invention, the writing method of the non-volatile memory 106 is performed by the non-volatile memory control module 104. For example, the non-volatile memory control module 104 may be implemented by a logic circuit in a system chip, and the non-volatile memory control module 104 must be designed to write data in a specific address range. It is completely beyond the control of the program.

The non-volatile memory control module 104 may designate a specific address of the non-volatile memory 106 to write a signal generated by the random number generator 102. That is, based on the non-volatile memory control module 104, the specific address range of the non-volatile memory 106 in the system single chip of the present invention will forcibly limit writing and can only write to the random number generator 102. random number. Based on different system single chips, there are physical differences (for example, different turn-on voltages of the memory cells) due to the different data in the specific address range, forming an absolute physical obstacle that cannot be completely copied. Therefore, the non-volatile memory 106 of the system chip of the present invention can be prevented from being completely copied by other system single chips.

In the present invention, the non-volatile memory control module 104 is coupled to the non-volatile memory 106 and the random number generator 102. The non-volatile memory control module 104 is connected to the output from the random number generator 102. As shown in the second figure, the non-volatile memory control module 104 of the present invention can feed four types of input signals, which are the address signal ADDR_BUS from the system bus 110 and the write data signal WDATA_BUS from the system bus 110. , The write control signal WE_BUS from the system bus 110, and the signal WDATA_RNG from the random number generator 102. For one embodiment, the control signals and timing of the address signal ADDR_BUS, the write data signal WDATA_BUS, the write control signal WE_BUS, and the random number signal WDATA_RNG are issued by the processing unit 100 and by the bus controller. 108 to control the arrangement. Since the non-volatile memory control module 104 is connected to the output from the random number generator 102, the input signals of the non-volatile memory control module 104 include the signal WDATA_RNG generated from the random number generator 102. That is, the input signals of the non-volatile memory control module 104 of the present invention include, in addition to the address signal ADDR_BUS, the write data signal WDATA_BUS, and the write control signal WE_BUS from the system bus 110, a random number generation The write data signal WDATA_RNG generated by the processor 102. In other words, in this embodiment, the structure of the non-volatile memory control module 104 must be designed so that The address signal ADDR_BUS, the write data signal WDATA_BUS, the write control signal WE_BUS, and the write data signal WDATA_RNG generated by the random number generator 102 are received by the system bus 110.

As shown in the second figure, among the control signals of the non-volatile memory control module 104, the address signal ADDR_BUS from the system bus 110 is directly mapped to the address signal ADDR_NVM of the non-volatile memory 106 from the system bus The write data signal WDATA_BUS of the bank 110 directly reflects the write data signal WDATA_NVM of the non-volatile memory 106, and the write control signal WDATA_WE from the system bus 110 will trigger the internal data of the non-volatile memory controller 120. The state machine generates a write control signal PROG_NVM for the entire set of non-volatile memory 106; In addition, by issuing instructions from the processing unit 100 and the control function of the non-volatile memory control module 104, a random selection can be selected The write data signal WDATA_RNG generated by the number generator 102 is written into a memory cell within a specific address range of the non-volatile memory 106.

As shown in the third figure, in this embodiment, the non-volatile memory control module 104 that can feed the system bus 100 signal and the random number generator 102 signal includes a type 3 system bus 100 input The signal is a general non-volatile memory controller 120, a write address judgment logic 130, and a switching device 140. The write address judging logic 130 can judge the address signal ADDR_BUS to be the lower bound (RANGE_LOW) or the upper bound (RANGE_HIGH) of the specific address range according to the input address signal ADDR_BUS from the system bus 110 to generate two selection codes, expressed as Digital signal 0 or 1. Both the lower bound (RANGE_LOW) and the upper bound (RANGE_HIGH) of the specific address range of the write address judgment logic 130 are constant. In one embodiment, the switching device 140 includes a plurality of input ports, a plurality of multiplexers 140 and a plurality of selection ends. Each multiplexer 140 includes an input end, an output end, and at least one selection end. In this embodiment, the multiplexer 140 has two selection terminals to select the write data signal WDATA_BUS or the write data signal WDATA_RNG as the write data signal WDATA_BUS of the non-volatile memory controller 120. Among the output signals of the general non-volatile memory controller 120, the address signal ADDR_BUS from the system bus 110 directly reflects the address signal ADDR_NVM of the non-volatile memory 106, and the written data from the system bus 110 The signal WDATA_BUS directly reflects the write data signal WDATA of the non-volatile memory 106 _NVM, and the write control signal WDATA_WE from the system bus 110 will trigger the internal state machine of the non-volatile memory controller 120 to generate the write control signal PROG_NVM of the entire non-volatile memory 106. However, in this embodiment, the write address judgment logic 130 and the multiplexer 140 are added to the structure of the non-volatile memory control module 104, and the random number generator 102 signal can be fed. The process of writing the data signal WDATA_NVM in the non-volatile memory 106 in the volatile memory control module 104 will be the same as the writing of the non-volatile memory 106 in the general non-volatile memory controller 120. The procedure for entering the data signal WDATA_NVM is different.

As shown in the third figure, in the non-volatile memory control module 104, the procedure of the write data signal WDATA_BUS of the system bus 110 includes: the write address signal ADDR_BUS of the system bus 110 is input to the write address judgment Logic 130; then, the write address judgment logic 130 judges that the address signal ADDR_BUS is the lower bound RANGE_LOW or the upper bound RANGE_HIGH of the specific address range according to the input write address signal ADDR_BUS, and generates a selection code signal, which is expressed as a digital signal 0 Or 1; after that, the selection code generated by the judgment result is input to the multiplexer 140 of the switching device, so as to control and determine that the multiplexer 140 selects to write the data signal, that is, one of the selection ends of the multiplexer 140 inputs the write Into the data signal. For example, when the selection code of the judgment result is 0, the multiplexer 140 selects the write data signal WDATA_BUS, and when the selection code of the judgment result is 1, the multiplexer 140 selects the write data signal WDATA_RNG as a non- The write data signal WDATA_BUS of the volatile memory controller 120.

From the above, the non-volatile memory controller 120 can automatically detect whether the address signal ADDR_BUS input of the system bus 110 is within a specific address range; if the write address falls within the range, the random number generator 102 is automatically selected The output write data signal WDATA_RNG is used as write data, and if the write address falls outside the range, it can be the same as the general non-volatile memory controller 120, and the write data signal WDATA_BUS of the system bus 110 is selected As written data.

In the present invention, the non-volatile memory 106 can be programmed to store the selection codes of each write address judgment logic 130. Based on the selection codes, the The selection terminal controls each multiplexer 140 to select a signal that is actually input to the non-volatile memory controller 120 as the write data signal WDATA_BUS of the non-volatile memory controller 120.

In the present invention, a relatively large specific address range of the non-volatile memory 106 can be designed, and a random number generator 102 with relatively good random number source characteristics is selected. Probability can drop to negligible levels.

The above description is a preferred embodiment of the present invention. Those skilled in the art should understand that it is used to explain the present invention and not to limit the scope of the patent rights claimed by the present invention. The scope of its patent protection shall depend on the scope of the attached patent application and its equivalent fields. Anyone skilled in this field can make changes or modifications without departing from the spirit or scope of this patent, which belong to the equivalent changes or designs made in the spirit disclosed by the present invention, and should be included in the scope of patent application described below. Inside.

Claims (10)

A method for writing non-volatile memory of a system chip includes: (a) inputting a write address signal to a write address judgment logic; (b) judging the write address in the write address judgment logic The signal is the lower or upper bound of a specific address range to generate a selection code signal; (c) input the selection code signal to a switching device to control the two selection ends of the switching device; (d) input a write data Signal to one of the two selection ends of the switching device, and input a random number generated by a random number generator to write a data signal to the other of the two selection ends of the switching device; and (e) based on the Select the logic level of the code signal, select the random number to write the data signal to the memory in the specific address range of the non-volatile memory, or select the write data signal to write to the corresponding non-volatile memory Memory for addresses outside that particular address range. The writing method of the non-volatile memory of the system chip according to claim 1, wherein the system chip includes a processing unit, the random number generator, a non-volatile memory control module, and the non-volatile memory And a bus controller. The writing method of the non-volatile memory of the system chip according to claim 2, wherein the non-volatile memory control module is coupled to the non-volatile memory and the random number generator. The method for writing non-volatile memory of a system chip according to claim 3, wherein the non-volatile memory control module includes the switching device, the write address judgment logic, and a non-volatile memory controller. The method for writing non-volatile memory of a system chip according to claim 4, wherein the switching device includes at least one multiplexer. The method for writing non-volatile memory of a system chip according to claim 5, wherein the multiplexer includes an input terminal, an output terminal, and two selection terminals. The writing method of the non-volatile memory of the system chip according to claim 1, wherein the writing data of a non-volatile memory control module in the specific address range cannot be controlled by the program. The writing method of the non-volatile memory of the system chip according to claim 1, wherein the lower bound and the upper bound of the specific address range are constant. The writing method of the non-volatile memory of the system chip according to claim 1, wherein the non-volatile memory includes a single-layer memory unit NAND / NOR type flash memory, or a multi-layer memory unit NAND / NOR type flash memory Memory. The writing method of the non-volatile memory of the system chip according to claim 1, wherein the non-volatile memory includes an erasable programmable read-only memory (EPROM), an electronic erasable programmable read-only memory Memory (EEPROM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), or other non-volatile memory that can be integrated on a silicon chip.