TWI655768B - Array substrate - Google Patents

Abstract

An array substrate has a display area and a circuit area. The array substrate includes a metal layer, a flat layer, a first protective layer, and a conductive layer. The flat layer is on the metal layer. The first protective layer is located on the flat layer. The first protective layer has an opening portion, the opening portion is located in the display area, and the opening portion exposes the flat layer without exposing the metal layer. The conductive layer is located on the first protective layer and is filled in the opening to cover the flat layer exposed by the opening.

Description

Array substrate

The present invention relates to an array substrate, and more particularly, to an array substrate capable of maintaining stable electrical properties in a display area.

A large number of semiconductor elements are mounted in the display panel, and these semiconductor elements are particularly present in the array substrate. During the manufacturing process of the display panel, the ambient atmosphere is often rich in moisture. Once there is too much moisture in the process environment, it is easy to adversely affect the electrical properties of these components. Therefore, how to maintain the stable electrical properties of the semiconductor elements in the array substrate has become one of the efforts of the industry.

The present invention relates to an array substrate having an opening portion. The planarization layer is exposed to the manufacturing environment only from this opening, and an appropriate amount of moisture can enter the planarization layer during the manufacturing process to improve the electrical properties of the semiconductor elements in the array substrate.

According to an aspect of the present invention, an array substrate is provided. The array substrate has a display area and a circuit area. The array substrate includes a metal layer, a flat layer, a first protective layer, and a conductive layer. The flat layer is on the metal layer. First protective layer The first protective layer is located on the flat layer, and the first protective layer has an opening portion, the opening portion is located in the display area, and the opening portion exposes the flat layer but not the metal layer. The conductive layer is located on the first protective layer and is filled in the opening to cover the flat layer exposed by the opening.

In order to have a better understanding of the above and other aspects of the present invention, the following specific examples are described in detail below in conjunction with the accompanying drawings:

1‧‧‧display panel

10, 20, 30, 40, 50‧‧‧ array substrates

100‧‧‧ substrate

110‧‧‧Gate

111, SLn, SLn + 1‧‧‧scan line

112, CH1, CH2‧‧‧ Channel layer

113, DLn, DLn + 1‧‧‧ data line

114‧‧‧Source

116, D1‧‧‧ Drain

120, 220, 320, 420, 520‧‧‧ flat layers

122, 222, 322, 422, 522‧‧‧ contact window openings

130, 230, 330, 430, 530‧‧‧ first protective layer

132, 232, 332, 432‧‧‧ central opening

134, 234, 334‧‧‧ opening

140‧‧‧ conductive layer

150, 250, 350‧‧‧Second protective layer

240, 342, 440, 540, PE‧‧‧ pixel electrodes

260‧‧‧Reflective layer

341‧‧‧Common electrode

532‧‧‧offset opening

GI‧‧‧Gate insulation

M1‧‧‧First metal material layer

M2‧‧‧Second metal material layer

P‧‧‧ sub pixel structure

PA‧‧‧Pixel Array

R1‧‧‧display area

R2‧‧‧Peripheral circuit area

R3‧‧‧Drive circuit area

RF‧‧‧ reflection area

T, T1, T2‧‧‧active components

TR‧‧‧ Penetration area

FIG. 1 is a top view of a display panel according to an embodiment of the present invention.

2A and 2B are cross-sectional views of an array substrate of a previous experiment.

Figures 3A and 3B show the electrical test curves of the active device in Figures 2A and 2B, respectively.

Fig. 4 is a sectional view taken along the line 4-4 'in Fig. 1.

FIG. 5A is a top view of an array substrate according to an embodiment of the present invention.

Fig. 5B is a cross-sectional view taken along line 5B-5B 'in Fig. 5A.

FIG. 6A is a top view of an array substrate according to another embodiment of the present invention.

Fig. 6B is a sectional view taken along line 6B-6B 'in Fig. 6A.

The present invention relates to an array substrate. In some embodiments, a first protective layer is located on a flat layer, and the flat layer is located on a metal layer. The first protective layer has an opening, and the opening is located in a display area of the array substrate, and This opening penetrates the first protective layer and extends to the flat layer. Next, a conductive layer is formed on the first protective layer and fills the opening to cover the flat layer exposed from the opening. Therefore, before the conductive layer is formed, an appropriate amount of water vapor can be diffused into the flat layer through the opening; and after the conductive layer is formed, excess water vapor can be blocked by the conductive layer to prevent further diffusion into the flat layer. The applicant has found that by controlling the amount of water and gas entering the flat layer, the electrical properties of the semiconductor elements in the array substrate can be improved.

The following is a detailed description of various embodiments. The present invention does not show all possible embodiments, and other implementation modes not provided in the present invention can also be applied. Moreover, the dimensional proportions in the drawings are not drawn according to the actual products. Therefore, the contents of the description and the drawings are only used to describe the embodiments, but not to limit the scope of protection of the present invention. In addition, some elements in the drawings in the embodiments are omitted to clearly show the technical features of the present invention. The following uses the same / similar symbols to indicate the same / similar elements or steps for explanation.

Please refer to FIG. 1, which is a top view of a display panel 1 according to an embodiment of the present invention. The display panel 1 includes an array substrate 10. The array substrate 10 has a display region R1 and a circuit region. The circuit region includes a peripheral circuit region R2 and a driving circuit region R3. The array substrate 10 includes a pixel array PA, and the pixel array PA is located in the display area R1. The pixel array PA includes a plurality of sub-pixel structures P, a plurality of data lines DLn, DLn + 1, ..., and a plurality of scan lines SLn, SLn + 1, .... Each sub-pixel structure P includes an active element T and a pixel electrode PE, and the active element T is electrically connected to a corresponding data line (such as DLn) and a corresponding scanning line (such as SLn).

The array substrate 1 includes a plurality of semiconductor elements. For example, in the pixel array PA, a plurality of active elements T are included. When manufacturing the array substrate 1, it often needs to be in a variety of different process environments. Some semiconductor elements in the array substrate 1 are particularly sensitive to water vapor. Once the process environment is filled with excessive water vapor, these semiconductor elements may adversely affect the electrical properties.

2A and 2B are cross-sectional views of the array substrates 40 and 50 of the previous experiment. Figures 3A and 3B show the electrical test curves of the active components T1 and T2 in Figures 2A and 2B, respectively.

2A and 2B, the array substrate 40 includes an active element T1, a flat layer 420, a first protective layer 430, and a pixel electrode 440. The array substrate 50 includes an active element T2, a flat layer 520, and a first protective layer 530. And pixel electrode 540.

In this example, the active element T1 and the active element T2 are oxide semiconductor transistors, and this type of transistor is often used in the display area. Since the oxide semiconductor transistor has a low leakage current, it can save the power consumption of the display panel when it is used under the operation of the screen update frequency is low. However, the oxide semiconductor transistor is easily affected by water vapor. Once the water vapor diffuses into the channel layers CH1 and CH2 made of the oxide semiconductor material, the electrical characteristics of the channel layers CH1 and CH2 will change.

In FIG. 2A, the first protective layer 430 has a central opening 432 formed in the center of the contact window opening 422, so that the pixel electrode 440 can extend into the contact window opening 422 and the central opening 432 and drain. The pole D1 is electrically connected. Here, the first protective layer 430 has a water blocking effect. However, before the pixel electrode 440 is formed through the configuration of the central opening 432, moisture in the process environment cannot diffuse into the channel layer CH1 through the flat layer 420. However, as shown in FIG. 3A, if the water vapor is prevented from diffusing into the channel layer CH1, the gate bias V _G will be shifted in a positive direction instead.

In FIG. 2B, the first protective layer 530 has an offset opening 532, which is offset from the center of the contact window opening 522, that is, the offset opening 532 partially overlaps the contact window opening 522, so The flat layer 520 may be exposed from the offset opening 532. Through the configuration of the offset opening 532, before the pixel electrode 540 is formed, part of the water vapor in the process environment will diffuse into the channel layer CH2 through the flat layer 520. As shown in FIG. 3B, the electrical stability of the active device T2 is improved. In other words, if an appropriate amount of water vapor can be diffused into the channel layer of the oxide semiconductor transistor, it will contribute to the improvement of electrical properties.

However, in the setup of FIG. 2B, the offset of the offset opening 532 from the center of the contact window opening 522 must be accurately controlled, that is, the mask used to form such an offset opening 532 must be able to accurately align . If the offset is too large, excessive water vapor is diffused to the channel layer CH2, instead, the gate bias voltage V _G is shifted to a negative direction. If the offset is too small, the water vapor diffused to the channel layer CH2 will not be enough to make up for the problem that the gate bias voltage V _G is forward biased.

In view of this, the applicant proposes another opening that is independent of the above-mentioned central opening 432 or offset opening 532, so that water vapor can enter the flat layer during the process, so that the amount of water vapor diffusion to the channel layer can be effectively controlled . In addition, the formation of such an opening portion is not affected by the topography of the flat layer, and it is also not affected by an excessive or small shift caused by the displacement of the photomask.

Please refer to FIG. 4, which is a cross-sectional view taken along line 4-4 'in FIG. The active element T is formed on the substrate 100. The active device T includes a gate 110, a channel layer 112, a source 114, and a drain 116. The gate electrode 110 is located between the substrate 100 and the channel layer 112, and a gate insulating layer GI is further disposed between the gate electrode 110 and the channel layer 112 to avoid direct conduction between the two. Furthermore, both the source 114 and the drain 116 are electrically connected to the channel layer 112. The above structural design of the active element T is described by taking a bottom gate structure as an example, but it is not intended to limit the present invention.

The materials of the gate electrode 110, the source electrode 114, and the drain electrode 116 may be conductive materials, such as various metals, conductive metal oxides, and organic conductive materials. The channel layer 112 is, for example, an oxide semiconductor layer. The material of the channel layer 112 is selected from the group consisting of Indium Zinc Oxide (IZO), Indium-Tin-Zinc Oxide (ITZO), and Indium Gallium Oxide. (IGO), Indium Gallium Zinc Oxide (IGZO), Indium Tungsten Oxide (IWO), Zinc Oxide (ZnO), Tin Oxide (SnO), Gallium-Zinc Oxide (GZO) ), Zinc tin oxide (Zinc-Tin Oxide, ZTO) and indium tin oxide (Indium-Tin Oxide, ITO).

The fabrication method of the gate 110, the channel layer 112, the source 114, and the drain 116 includes a film deposition step (such as chemical vapor deposition, physical vapor deposition, thin film coating, etc.), and a patterning step (such as a lithography etching step). , Laser etching step, or stripping step) or a combination of the above steps. For example, the gate electrode 110 may be made of a first metal material. The layer M1 is patterned through a lithographic etching step, and the source 114 and the drain electrode 116 can be patterned and formed from a second metal material layer M2 through a lithographic etching step.

Next, a flat layer 120 is formed on the substrate 100 to cover the active device T. The flat layer 120 has a contact window opening 122, and the contact window opening 122 exposes a part of the drain electrode 116.

After the contact window opening 122 is formed, a first protection layer 130 is then formed on the flat layer 120, wherein the first protection layer 130 further covers the sidewall of the contact window opening 122. The first protective layer 130 has a central opening 132, which is formed in the center of the contact window opening 122 to expose a part of the drain electrode 116 from the central opening 132. In addition, the first protection layer 130 further has an opening portion 134. The opening portion 134 exposes a partial area of the flat layer 120, but does not expose the remaining film layers, such as the gate 110, the channel layer 112, the source 114, and the drain 116. In other words, the opening portion 134 penetrates the first protective layer 130 and extends to the flat layer 120.

The material of the flat layer 120 may include an organic material, which easily absorbs moisture. The material of the first protective layer 130 may include an inorganic material, such as silicon nitride (SiNx). Since silicon nitride is a dense material, the first protective layer 130 has the ability to block water. Here, the flat layer 120 is only exposed to the process environment from the opening portion 134, and moisture in the process environment can enter the flat layer 120 through the opening portion 134. Therefore, an appropriate amount of water and gas can be diffused to the channel layer 112, and thus can contribute to the improvement of the electrical properties of the active device T.

In some embodiments, the size of the opening 134 10 micrometers (μm), and the size of the opening 134 is, for example, the length, width, or diameter of the opening 134. In some embodiments, a ratio of an area of the opening portion 134 to a total area of the first protective layer 130 10%, for example between 0.01% and 10%. In this way, it is possible to further ensure that an appropriate amount of water vapor is diffused into the channel layer 112.

Next, a pixel electrode PE is formed on the first protective layer 130, and the pixel electrode PE is electrically connected to the drain electrode 116 through the contact window opening 122 and the central opening 132. In addition, a conductive layer 140 may be formed on the first protective layer 130 and filled in the opening portion 134 to cover the flat layer 120 exposed by the opening portion 134.

Here, the water vapor transmission rate of the material of the conductive layer 140 10 ^-1 g / m ² -24hr to prevent excessive moisture from further entering the flat layer 120. In some embodiments, the material of the conductive layer 140 may be metal, opaque conductive material, transparent conductive material, or the like. The transparent conductive material may be a mixture of oxides of elements of Groups 2, 3 and 4 in the periodic table of the chemical elements, such as indium-tin oxide (ITO), indium zinc oxide (IZO), Aluminum-doped Zinc Oxide (AZO), Indium Gallium Oxide (IGO), Indium Gallium Zine Oxide (IGZO), Indium-Tin-Zinc Oxide (ITZO) ), Indium Gallium Tin Oxide (IGTO) and other materials. In some embodiments, the conductive layer 140 and the pixel electrode PE are patterned from the same film layer. In some embodiments, the conductive layer 140 is a pixel electrode PE.

In addition, the array substrate 10 may further include a second protection layer 150, which is located on the gate insulation layer GI and covers the channel layer 112. The material of the second protective layer 150 may include an inorganic material, for example, a material such as silicon oxide (SiOx), silicon oxynitride (SiOxNy), or the like. material. The second protective layer 150 has the ability to block part of the water vapor, and can be used for supplementing oxygen, thereby improving the electrical property of the active device T.

FIG. 5A is a top view of an array substrate 20 according to an embodiment of the present invention. Fig. 5B is a cross-sectional view taken along line 5B-5B 'in Fig. 5A. In this embodiment, the array substrate 20 can be applied to a transflective liquid crystal display (TR LCD).

The array substrate 20 of FIGS. 5A and 5B may have an opening portion 234 that functions similarly to the opening portion 134 described in FIG. 4. As shown in FIGS. 5A and 5B, the pixel array PA (labeled in FIG. 1) may include a transmission region TR and a reflection region RF. The scan lines 111 and the gate electrodes 110 may be formed by patterning the first metal material layer M1. The data line 113, the source 114, and the drain 116 may be formed by patterning the second metal material layer M2.

In this embodiment, the material of the flat layer 220, the first protective layer 230, the pixel electrode 240, and the second protective layer 250 may be similar to the flat layer 120, the first protective layer 130, the pixel electrode PE,第二 保护 层 150。 The second protective layer 150.

After the active device T is formed, a second protection layer 250 may be formed on the active device T and the gate insulating layer GI. Next, a flat layer 220 is formed on the second protective layer 250, and the thickness of the flat layer 220 in the reflection region RF is greater than the thickness of the flat layer 220 in the transmission region TR. In addition, in order to improve the display effect of the transflective liquid crystal display, a plurality of convex patterns may be formed on a partial surface of the flat layer 220 in the reflective region RF. In addition, the flat layer 220 has a contact window opening 222 which is located in the reflection area RF, and the contact window opening 222 exposes a partial surface of the second protective layer 250.

Next, a first protective layer 230 is formed on the flat layer 220, wherein the first protective layer 230 further covers the sidewall of the contact window opening 222. Then, a photomask is used to form a central opening 232 in the center of the contact window opening 222, so that the local drain electrode 116 is exposed from the central opening 232. At the same time, an opening portion 234 is formed in the penetration region TR. The opening portion 234 exposes a partial area of the flat layer 220, but does not expose the remaining film layers.

Here, the flat layer 220 is exposed to the process environment only from the opening portion 234, and moisture in the process environment can enter the flat layer 220 through the opening portion 234. Therefore, an appropriate amount of water and gas can be diffused to the channel layer 112, and thus can contribute to the improvement of the electrical properties of the active device T.

Next, a pixel electrode 240 is formed on the first protective layer 230, and the pixel electrode 240 is electrically connected to the drain electrode 116 through the contact window opening 222 and the central opening 232. In addition, the pixel electrode 240 is further filled in the opening portion 234 to cover the flat layer 220 exposed by the opening portion 234.

Then, a reflective layer 260 is formed on the pixel electrode 240 in the reflective area RF. The reflective layer 260 is located in the contact window opening 222 and the central opening 232 and is located on several raised patterns of the flat layer 220. As a result, the reflective layer 260 can reflect ambient light from the outside and improve light uniformity at various viewing angles.

FIG. 6A is a top view of an array substrate 30 according to another embodiment of the present invention. Fig. 6B is a sectional view taken along line 6B-6B 'in Fig. 6A.

The array substrate 30 of FIGS. 6A and 6B may have an opening portion 334 that functions similarly to the opening portion 134 described in FIG. 4. As shown in FIGS. 6A and 6B, the scan lines 111 and the gate electrodes 110 may be patterned by the first metal material layer M1. to make. The data line 113, the source 114, and the drain 116 may be formed by patterning the second metal material layer M2.

In this embodiment, the material of the flat layer 320, the first protective layer 330, the pixel electrode 342, and the second protective layer 350 may be similar to the flat layer 120, the first protective layer 130, the pixel electrode PE,第二 保护 层 150。 The second protective layer 150.

After the active device T is formed, a second protection layer 350 may be formed on the active device T and the gate insulating layer GI. Next, a flat layer 320 is formed on the second protective layer 350. The flat layer 320 has a contact window opening 322, and the contact window opening 322 exposes a partial surface of the second protective layer 350.

Next, a first protective layer 330 is formed on the flat layer 320, wherein the first protective layer 330 further covers the sidewall of the contact window opening 322. Then, a photomask is used to form a central opening 332 in the center of the contact window opening 322, so that the local drain electrode 116 is exposed from the central opening 332. At the same time, an opening portion 334 is further formed. The opening portion 334 exposes a partial area of the flat layer 320 but does not expose the remaining film layers.

Here, the flat layer 320 is only exposed to the process environment from the opening portion 334, and moisture in the process environment can enter the flat layer 320 through the opening portion 334. Therefore, an appropriate amount of water and gas can be diffused to the channel layer 112, and thus can contribute to the improvement of the electrical properties of the active device T.

Next, a pixel electrode 342 is formed on the first protective layer 330, and the pixel electrode 342 is electrically connected to the drain electrode 116 through the contact window opening 322 and the central opening 332. In addition, the pixel electrode 342 is further filled in the opening portion 334 to cover the flat layer 320 exposed by the opening portion 334.

In this embodiment, the pixel array PA (labeled in FIG. 1) may further include a common electrode 341, and the common electrode 341 is located between the flat layer 320 and the first protective layer 330. Here, the common electrode 341, the first protective layer 330, and the pixel electrode 342 may form a storage capacitor together.

In addition, in this embodiment, the opening portion 334 may at least partially overlap the data line 113, thereby preventing loss of the aperture ratio of each sub-pixel.

The array substrate provided by each of the above embodiments has another opening portion independent of the central opening. The flat layer is only exposed to the process environment from this opening portion. Therefore, water vapor can enter the flat layer during the process to improve the electrical properties of the semiconductor elements in the array substrate.

In summary, although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention pertains can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application.

Claims (11)

An array substrate has a display area and a circuit area. The array substrate includes: a metal layer; a flat layer on the metal layer; a first protective layer on the flat layer; the first protective layer has An opening portion, the opening portion is located in the display area, and the opening portion exposes the flat layer without exposing the metal layer; and a conductive layer is located on the first protective layer and filled in the opening portion to cover The flat layer is exposed from the opening. According to the array substrate of claim 1, the material of the flat layer includes an organic material, and the material of the first protective layer includes an inorganic material. The array substrate according to item 1 of the scope of patent application, wherein the water vapor transmission rate of the conductive layer is 10 ^-1 g / m ² -24hr. The array substrate according to item 1 of the scope of patent application, further includes: a pixel array located in the display area, wherein the pixel array includes: a data line and a scan line; an active element, which is electrically connected to the A data line and the scan line, the active element includes a gate, an oxide semiconductor layer, a source, and a drain, the oxide semiconductor layer is located above the gate, and the source and the drain are electrically Connected to the oxide semiconductor layer; and a pixel electrode on the first protective layer; wherein the flat layer has a contact window opening, the first protective layer covers a sidewall of the contact window opening, and the pixel electrode passes through The contact window opening is electrically connected to the drain electrode. The array substrate according to item 4 of the scope of patent application, wherein the conductive layer is the pixel electrode. The array substrate according to item 4 of the scope of patent application, further comprising a second protective layer, the second protective layer covering the oxide semiconductor layer. The array substrate according to item 4 of the scope of patent application, wherein the pixel array includes a penetration region and a reflection region, the opening portion is located in the penetration region, and the contact window opening is located in the reflection region. According to the array substrate described in item 4 of the patent application scope, the pixel array further includes a common electrode, the common electrode is located between the flat layer and the first protective layer. The array substrate according to item 4 of the scope of patent application, wherein the metal layer is formed by patterning a metal material layer, and the metal layer includes the data line, the source electrode, and the drain electrode. The array substrate according to item 9 of the scope of patent application, wherein the opening portion at least partially overlaps the data line. The array substrate according to item 1 of the scope of patent application, wherein a ratio of an area of the opening portion to a total area of the first protective layer 10%.