TWI653539B - Data storage device and methods for processing data in the data storage device - Google Patents

Abstract

A data storage device includes a memory device and a controller. The memory device includes a plurality of memory blocks. The memory block includes a plurality of single layer unit blocks and a plurality of multi-level unit blocks. The controller is coupled to the memory device. When the controller executes the program for writing the data stored in the single-layer unit block to one of the multi-level unit blocks, the controller determines whether the effective page count value corresponding to each single-layer unit block is greater than a critical value. And when a valid page count value corresponding to the plurality of single-layer unit blocks is greater than a threshold, the controller performs a first combining procedure to directly directly use the plurality of single-layer unit areas having a valid page count value greater than a critical value The data stored in the block is written to one or more of the multi-level cell blocks.

Description

Data storage device and data processing method of memory device

The present invention relates to a data processing method for a flash memory device, which can efficiently process data stored in a memory device to improve the performance of the memory device.

As the technology of data storage devices has grown rapidly in recent years, many data storage devices, such as SD/MMC, CF, MS and XD memory cards, solid state drives, embedded memory (embedded) Multi Media Card (abbreviated as eMMC) and Universal Flash Storage (UFS) have been widely used in a variety of applications. Therefore, effective access control has become an important issue on these data storage devices.

In order to improve the access performance of the data storage device, the present invention proposes a new data processing method that can efficiently process the data stored in the memory device to improve the performance of the memory device.

The invention provides a data storage device comprising a memory device and a controller. The memory device includes a plurality of memory blocks. The memory block includes a plurality of single layer unit blocks and a plurality of multi-level unit blocks. The controller is coupled to the memory device. When the controller executes to write the data stored in the single-layer unit block When entering one of the multi-level unit blocks, the controller determines whether one of the valid page count values corresponding to each single-layer unit block is greater than a critical value, and the effective page count value corresponding to the plurality of single-layer unit blocks When the threshold value is greater than the threshold value, the controller performs a first merging process for directly writing the data stored in the plurality of single-layer unit blocks having the effective page count value greater than the threshold value into one or more of the multi-level unit blocks.

The present invention further provides a data processing method for a memory device, which is applicable to a data storage device. The data storage device includes a memory device and a controller. The memory device includes a plurality of memory blocks, and the memory blocks include a plurality of single-layer unit blocks and a plurality of multi-level unit blocks, the method comprising: determining whether a valid page count value corresponding to each single-layer unit block is greater than a critical value; and when the plurality of single-layer unit blocks correspond to When the valid page count value is greater than the threshold value, a first merging process is executed to directly write data stored in the plurality of single-layer unit blocks having the effective page count value greater than the threshold value into one or more of the multi-level unit blocks. By.

100‧‧‧ data storage device

110A, 110B‧‧‧ controller

111‧‧‧Microprocessor

112, SRAM‧‧‧ static random access memory

113, ROM‧‧‧ read-only memory

114‧‧‧Encoder

115‧‧‧Disruptor

120‧‧‧ memory device

200‧‧‧ host device

210‧‧‧ interface

300A, 300B‧‧‧ electronic devices

1A is a block diagram showing an example of an electronic device according to an embodiment of the present invention.

1B is a block diagram showing an example of an electronic device according to another embodiment of the present invention.

2 is a schematic view showing a process queue according to an embodiment of the present invention.

Figure 3 is a diagram showing a memory device according to an embodiment of the present invention. Flow chart of data processing method.

Figure 4 is a flow chart showing a data processing method of a memory device according to another embodiment of the present invention.

In order to make the objects, features and advantages of the present invention more comprehensible, the specific embodiments of the invention are set forth in the accompanying drawings. The intention is to illustrate the spirit of the invention and not to limit the scope of the invention, it being understood that the following embodiments can be implemented by software, hardware, firmware, or any combination of the above.

1A is a block diagram showing an electronic device according to an embodiment of the present invention. The electronic device 300A may include a host device 200 and a data storage device 100. The electronic device 300A can be a mobile device, such as a smart phone, a smart watch, or a tablet, but is not limited thereto.

According to an embodiment of the present invention, the data storage device 100 may include a controller 110A and a memory device 120. The controller 110A can include at least a microprocessor 111, a static random access memory (SRAM) 112, a read only memory (ROM) 113, an encoder 114, and a scrambler 115. Memory device 120 can include one or more non-volatile memory, such as flash memory.

The host device 200 and the data storage device 100 can be connected to each other through a predetermined interface 210. For example, when the data storage device 100 conforms to the specification of Universal Flash Storage (UFS), the host device 200 and the data storage device 100 can be connected to each other through the UFS interface. For another example, when the data storage device 100 conforms to the embedded memory (embedded Multi Media) When the card is abbreviated as eMMC), the host device 200 and the data storage device 100 can be connected to each other through the MMC interface.

FIG. 1B is a block diagram showing an example of an electronic device 300B according to another embodiment of the present invention. In this embodiment, the SRAM 112 is disposed outside of the controller 110B and coupled to the controller 110B.

It is to be noted that, for simplicity of explanation, FIGS. 1A and 1B show only elements related to the present invention, and FIGS. 1A and 1B show only two of the various structures to which the present invention can be applied. However, the implementation of the present invention is not limited to the elements and architectures shown in Figures 1A and 1B.

According to an embodiment of the invention, the memory device 120 includes a plurality of memory blocks. The memory block can be further divided into a plurality of single level cells (SLC) blocks and a plurality of multiple level cells (MLCs). One bit of metadata is stored in each memory unit of the SLC block, and a plurality of bit data are stored in each memory unit of the MLC block. For example, in accordance with an embodiment of the present invention, two bits of metadata are stored in each memory unit of an MLC block. For example, according to another embodiment of the present invention, the multi-level cell block may be a three-level cell (Triple Level Cell, abbreviated as TLC) block, and three bit elements are stored in each memory cell of the TLC block.

Each memory block can include a plurality of pages, typically in flash memory, one page is the smallest block unit of a write job, and one block is the smallest block unit of an erase job. The size of a physical page is fixed, and the size of a logical page can be flexibly designed according to firmware programming requirements.

In general, in order to enable the programming of the MLC/TLC block to maintain a stable state, each program needs to write data of multiple pages (such as data of two or three physical pages) to the MLC/TLC block, so the memory The SLC block of the body device 120 can function as a cache memory or a buffer for temporarily storing data. When the usage rate of the SLC block reaches a certain level, the controller 110A/110B may decide to execute a predetermined program to write the data stored in the SLC block into the MLC/TLC block, so that the memory space of the SLC block is performed. Can be released and can be used again.

In the above predetermined procedure, the stored data of a plurality of SLC blocks is written into one or more MLC/TLC blocks. Taking the TLC block as an example, the controller collects or combines the data of the amount of data that can be stored in the three SLC blocks, and writes the collected or merged data into the TLC block.

However, sometimes the data stored in the SLC block may have been invalid. For example, when the information stored in some pages in the SLC block is duplicated with the data stored in other blocks, and the data of the page is not the latest stored data, the data of the page is determined to be invalid. The page will be treated as an invalid page (also known as an expired page). Therefore, in the data processing method proposed by the present invention, the number of invalid pages is further considered in the predetermined program for writing the data stored in the SLC block into the MLC/TLC block, so as to more efficiently process the memory device. Information.

According to an embodiment of the present invention, when the controller 110A/110B decides to execute the predetermined program, it is determined whether one of the effective page count values VP_Count corresponding to each single-layer unit block is greater than a threshold TH. For example, the controller 110A/110B may establish a first table in the SRAM 112 or the memory device 120 for recording a valid page count value VP_Count corresponding to each memory block, where the page for recording is used. The unit can be a logical page. Therefore, the maximum value of VP_Count is the number of logical pages included in a memory block, and the minimum value is 0. The controller 110A/110B can update the content of the first form after each write operation.

More specifically, it is assumed that the controller 110A/110B writes a material of a main page (Host page) to the memory block B, and one of the main pages can be set as a data block unit for one access operation. For example, when the size of a physical page is 16K bytes, the size of one main page can be set to 4K bytes. When the controller 110A/110B determines that the same home page has been written to the memory block A earlier, the controller 110A/110B decrements the effective page count value VP_Count corresponding to the memory block A by one, and The effective page count value VP_Count corresponding to the memory block B is incremented by one.

According to an embodiment of the present invention, the controller 110A/110B can create a second table in the SRAM 112 or the memory device 120 for recording which page of the memory block the data of a main page is stored in. Therefore, the controller 110A/110B can query whether the main page has been stored in other memory blocks by querying the second table.

When the effective page count value VP_Count corresponding to the plurality of single layer unit blocks is greater than the threshold TH, the controller 110A/110B decides to perform a first combining procedure for using the effective page count value VP_Count to be greater than the threshold TH The data stored in the single-level cell block is written into one or more multi-level cell blocks.

According to an embodiment of the invention, the first merge program is a direct merge program. Take the TLC block as an example, when at least three single-layer units When the valid page count value VP_Count corresponding to the block is greater than the threshold TH, the controller 110A/110B decides to execute the direct merge procedure. The controller 110A/110B may combine three SLC blocks having a valid page count value VP_Count greater than a threshold TH into a group. The controller 110A/110B sequentially reads the data stored in the SLC block in a group (that is, reads the data stored in the entire SLC block without considering whether there is an invalid page), and sequentially reads the data. The data is written to a TLC block. In general, a read action is accompanied by a write action. Since the data of the SLC block does not need to pass through the controller, but is directly written into the TLC block, the advantage of the direct merge program is that it is fast.

On the other hand, when the controller 110A/110B finds that the effective page count value VP_Count corresponding to any single layer unit block is not greater than the threshold TH, the controller 110A/110B decides to perform a second combining procedure. In the second combining procedure, the controller 110A/110B selects a plurality of SLC blocks having a valid page count value VP_Count not greater than the threshold TH from the SLC blocks that have not been processed, and the SLC area to be selected After the data stored in the valid pages in the block is merged, the data is written to one of the multi-level cell blocks.

According to an embodiment of the invention, the second merging program is an application of an On Buffer Program (abbreviated as OBP) merging program. Taking the TLC block as an example, when the controller 110A/110B finds that the effective page count value VP_Count corresponding to any one of the SLC blocks is not greater than the threshold TH, the controller 110A/110B decides to perform an OBP merge procedure for the SLC block.

More specifically, in the OBP combining procedure, when the controller 110A/110B determines that the data stored in a physical page of an SLC block (for example, a physical page of a 16K byte) is valid data, the controller 110A/110B Instead of sorting out the valid data, the valid data is stored in the original SLC block.

When the controller 110A/110B determines that the data stored in a physical page of an SLC block is not all valid data, the data of the valid page stored in the SLC block is read and temporarily stored in the buffer. The controller 110A/110B then continues to detect if the data stored in the remaining SLC blocks is not all valid data. If the data stored in the remaining SLC blocks is not all valid data, the data of the valid page stored in the SLC block is read and temporarily stored in the buffer. When a valid data of a physical page size is collected in the buffer (for example, 16K bytes), it is written into a temporary storage block (hereinafter referred to as an OBP block).

In one embodiment of the invention, the controller 110A/110B can create an OBP table within the SRAM 112 or the memory device 120. The OBP table is used to record which page of the block in which the data of each page of the destination TLC block is stored in the OBP merge process. For example, it may be in the original SLC block, or it may be in the OBP block.

Finally, after accumulating valid data that can be accommodated in a TLC block, the data is sequentially read to the controller 110A/110B one page at a time (for example, a physical page) according to the information recorded on the OBP table, and The page number queries the corresponding random seed, and after being scrambled by the scrambler 115 and encoded by the encoder 114, the processed data is stored in the corresponding page of the TLC block. In addition, a random seed is also stored in the spare region of each page. After the data is read, the data can be restored according to the random seed of the spare area.

Therefore, in an embodiment of the present invention, in the second merge procedure, when the controller 110A/110B determines a physical page of an SLC block When the stored data is not all valid data, the controller 110A/110B reads the data of the valid page of the SLC block and temporarily stores it in the buffer, and when the valid data of the physical page size is collected in the buffer ( For example, 16K bytes), and then write it into an OBP block. When the controller 110A/110B determines that the data stored in a physical page of an SLC block is valid data, the controller 110A/110B does not read out the valid data, but saves the valid data in the original SLC area. In the block. When the controller 110A/110B collects the amount of valid page data that can be written to one TLC block (ie, three SLC blocks, which may be the original SLC block or the OBP block, the sum of the two), it will be valid again. The data is written into a TLC block. Compared to the direct merge (i.e., the first merge procedure described above), the OBP merge (i.e., the second merge procedure described above) has the advantage of ensuring that the data within the TLC block is valid.

In the embodiment of the present invention, the controller 110A/110B elastically determines which method to store the data stored in the single-layer unit block into the multi-level unit block according to the effective page count value VP_Count of the memory block, such that In the memory block with more effective pages, you can enjoy the advantages of the direct merge program (that is, the program that can quickly complete data collection and writing), and the memory block with fewer effective pages can also be used by OBP. The merge process effectively reduces the number of invalid pages written to the multi-level cell block, making subsequent garbage collection procedures or other data processing programs for multi-level cell blocks more efficient.

The following paragraphs will describe various embodiments of the present application in more detail.

According to a first embodiment of the present invention, the controller 110A/110B may first sequentially arrange the SLC blocks to be programmed into a processing queue so that The SLC blocks are grouped in advance according to random seeds. For example, when the controller 110A/110B sequentially writes data into the SLC blocks 0, 1, 2, ..., the SLC blocks 0, 1, 2, ... can also be assigned different according to a predetermined order. Random seed. More specifically, it is assumed that three sets of random seeds are configured in the data storage device system, each group contains a plurality of random seeds, each random seed is used to disturb a physical page, and the random seeds of the three groups are different. For example, if an SLC block contains 10 physical pages, each set of random seeds may contain 10 different random seeds, and the 30 random seeds included in the three configured random seeds are also different. .

The controllers 110A/110B can sequentially assign the three sets of random seeds to the SLC block. For example, assigning a first set of random seeds to SLC blocks 0, 3, 6..., assigning a second set of random seeds to SLC blocks 1, 4, 7..., assigning a third set of random seeds to SLC blocks 2, 5, 8... and so on. It is to be noted that the above examples are only intended to clearly illustrate the concept of the invention, and the invention is not limited to the use of three different sets of random seeds. For example, a data storage device system can use more than three different sets of random seeds.

The scrambler 115 of the controller 110A/110B can scramble the data according to the random seed and then store it in the SLC block. In addition, a random seed is also stored in the spare region of each page. After the data is read, the data can be restored according to the random seed of the spare area.

Since the controllers 110A/110B know that the SLC blocks 0, 1, 2 use different random seeds, the SLC blocks 3, 4, 5 use different random seeds, so the controller 110A/110B can be as shown in FIG. The SLC blocks to be subjected to the predetermined program are sequentially discharged into a processing queue, wherein the processing of the queue records may be the SLC region. The block number, such as the number in the box in Figure 2. In this way, the three SLC blocks of each column in the processing queue can be classified into a group, and the SLC blocks in each group can ensure data scrambling according to different random seeds (ie, Each physical page in the group will be scrambled according to different random seeds).

After the SLC blocks are sequentially discharged into the processing queue, the controller 110A/110B can sequentially determine whether one of the effective page count values VP_Count corresponding to each single-layer unit block is greater than a threshold TH. Assume that, as shown in FIG. 2, the effective page count value VP_Count corresponding to the SLC blocks 3, 5, 7, 11, 13, 15 is not greater than the threshold TH (the VP_Count<=TH is indicated by a diagonal line in FIG. 2) Block), the effective page count value VP_Count corresponding to the remaining SLC blocks is greater than the threshold TH.

According to an embodiment of the present invention, after determining that the effective page count value VP_Count corresponding to the SLC blocks 0, 1, and 2 is greater than the threshold TH, the controller 110A/110B may decide to perform the SLC blocks 0, 1, and 2. The first merge procedure is used to directly write the SLC blocks 0, 1, 2 into a TLC block. This process can continue until the SLC block that the valid page count value VP_Count is not greater than the threshold TH is encountered.

Assuming that the effective page count value VP_Count corresponding to the SLC block 3 is not greater than the threshold TH, then when processing to the SLC block 3, the controller 110A/110B decides to perform a second merge procedure. In the second merge procedure, the controller 110A/110B determines whether the data stored in the physical pages of each SLC block is valid data. When the controller 110A/110B determines that the data stored in a physical page of an SLC block is not all valid data, the controller 110A/110B reads The data of the valid page of the SLC block is taken and temporarily stored in the buffer. When the controller 110A/110B determines that the data stored in a physical page of an SLC block is valid data, the controller 110A/110B does not read out the valid data, but saves the valid data in the original SLC area. In the block. When the controller 110A/110B collects the amount of valid page data that can be written to one TLC block (ie, three SLC blocks, which may be the original SLC block or the OBP block, the sum of the two), it will be valid again. The data is written into a TLC block.

After the second merge process is completed, the controller 110A/110B further reprocesses the queue contents, and removes the SLC blocks that have been processed (ie, all valid data are merged and written into the TLC block), and are identical. Group (same column) unprocessed SLC block is replenished. As indicated by the arrow in FIG. 2, when the SLC block 3 has been processed, the controller 110A/110B fills the SLC block number 6 into the vacant position in the first column of the second column of the processing queue to replace the SLC area. Block 3, when the SLC block 5 has been processed, the controller 110A/110B fills the SLC block number 8 into the third column of the second column of the processing queue to replace the SLC block 5, and so on. . In this way, it can be ensured that the three SLC blocks classified as a column of a group will be scrambled according to different random seeds (that is, each physical page in the group will be based on different random seeds). Data disruption).

Similarly, each time the controller 110A/110B completes the first merging process, the queue contents can be reprocessed in the same manner.

In addition, after the second merging process is completed, the controller 110A/110B can process other unprocessed SLC blocks in sequence according to the processing queue contents. The controller 110A/110B may continue to sequentially determine, according to the foregoing, whether a valid page count value VP_Count corresponding to each single-layer unit block is greater than a threshold TH, and root According to the judgment result, it is decided to execute the first combining procedure or the second combining procedure.

In the first embodiment of the present invention, the controller 110A/110B elastically determines which method to store the data stored in the single-layer unit block into the multi-level unit block according to the effective page count value VP_Count of the memory block. In this way, for a memory block with a large number of effective pages, the predetermined program can be quickly completed, and for a memory block with fewer effective pages, the second merge program can effectively reduce the invalidity of writing the multi-level unit block. The number of pages makes it more efficient to carry out subsequent garbage collection procedures or other data processing programs for multi-level cell blocks.

According to a second embodiment of the present invention, the controller 110A/110B may further establish a third table in the SRAM 112 or the memory device 120 for recording random seed related information configured by each SLC block. For example, it is recorded which group the random seed configured for each SLC block belongs to. When the controller 110A/110B decides to execute the predetermined program, the contents of the first table and the third table may be first checked, and a plurality of different random seeds are selected from the SLC blocks having the valid page count value VP_Count greater than the threshold TH ( For example, three) SLC blocks form a group, and the first combining procedure described above is performed. After the SLC block group (ie, the group formed by having a valid page count value VP_Count greater than the threshold TH and having multiple (eg, three) SLC blocks with different random seeds) is processed, the remaining portion is reused. The SLC block performs the second merge procedure described above.

In the second embodiment of the present invention, the controller 110A/110B preferentially processes the memory blocks with more valid pages in the first merge program, so that the memory space can be quickly released. After the memory block with more valid pages is processed, the memory block with fewer effective pages is processed, and the second merge program is used to effectively reduce writing. The number of invalid pages into the multi-level cell block makes the subsequent garbage collection program or other data processing program of the multi-level cell block more efficient.

According to a third embodiment of the present invention, when the controller 110A/110B decides to execute the predetermined program, it is also possible to preferentially judge whether or not a sudden power off has occurred. According to an embodiment of the present invention, when a sudden power failure occurs, the system performs a Sudden Power Off Recovery (SPOR) procedure to re-establish the connection of the form and the data block when the system is powered back on. Therefore, when the SPOR procedure is executed, the controller 110A/110B can set a flag to indicate that a sudden power failure has occurred. When the controller 110A/110B decides to execute the predetermined program, it can check whether the flag is set to determine whether a sudden power failure has occurred. If yes, the controller 110A/110B may not determine whether the effective page count value VP_Count corresponding to the single-layer unit block is greater than the critical value TH, but directly decides to execute the first time when the predetermined program is executed after the power failure occurs. Three merger procedures. The third merge procedure is also an application of the OBP merge program. In the third merging process, the controller 110A/110B temporarily stores the data stored in the valid page in the single-layer unit block in the buffer for data merging. When the controller 110A/110B collects a valid page data amount that can be filled with one multi-level cell block (taking TLC blocks as an example, that is, three SLC blocks), the controller 110A/110B configures different physical pages for each physical page. Random seed, and then the combined data is written into a multi-level cell block. After the predetermined program is completed, the controller 110A/110B can clear the above flag. In this way, the third merge procedure is selected when the first program is to be executed for the first time after a sudden power failure.

It should be noted that in other embodiments of the invention, the control The device 110A/110B can also be designed to count the number of occurrences of a sudden power failure, and when the number of occurrences of the sudden power failure is greater than a predetermined value, another flag is set to indicate that a sudden sudden power failure has occurred. Happening. When the controller 110A/110B decides to execute the predetermined program, it can first confirm whether the flag of the continuous sudden power failure is set. When it is found that the flag of continuous sudden power failure is set, it is directly decided to execute the third combining procedure to complete the predetermined procedure. The controller 110A/110B may clear the flag after the scheduled procedure is completed. In this way, the third merge procedure is selected when the first program is executed for the first time after a continuous sudden power failure.

In general, every time a sudden power failure occurs, the system uses a new single-layer unit block as the current cache memory. Therefore, sudden power failure or continuous power failure may result in a single-layer unit area. The block contains a large number of invalid pages. Therefore, in the third embodiment of the present invention, when the predetermined program is to be executed for the first time after a sudden power failure or a continuous sudden power failure, it may be set to preferentially execute the third combining procedure.

3 is a data processing method for a memory device according to an embodiment of the present invention, which is applicable to a data storage device. The data storage device may include a memory device and a controller, and the memory device may include a plurality of The memory block, and the memory block can be cut into a plurality of single-layer unit blocks and a plurality of multi-level unit blocks, and the single-layer unit block is used for temporarily storing data.

The flowchart shown in Fig. 3 covers the first, second and third embodiments of the present invention. First, the controller decides to execute a predetermined program (step S302) for writing the data stored in the single-layer unit block to the multi-level unit block to release the memory space of the single-layer unit block. Next, the controller determines whether the data storage device has suddenly powered off (step S304). If yes, the controller decides to execute the third And the program (step S306). If not, the controller further determines whether one of the effective page count values VP_Count corresponding to each single layer unit block is greater than a threshold TH (step S308). If so, the first merging process is performed on the single-layer unit block (step S310), and the controller directly writes the data stored in the plurality of single-layer unit blocks having VP_Count>TH into the multi-level unit block. If not, a second merging procedure is performed on the single layer unit block (step S312).

As described above, in the embodiment of the present invention, the controller 110A/110B elastically determines which method to store the data stored in the single-layer unit block into the multi-level unit block according to the effective page count value VP_Count of the memory block. In this way, for a memory block with a large number of effective pages, the advantage of a direct merge program (ie, a program that can quickly complete data collection and writing) can be enjoyed, and for a memory block with fewer valid pages, The process of OBP merge effectively reduces the number of invalid pages written to the multi-level cell block, making subsequent garbage collection procedures or other data processing programs for multi-level cell blocks more efficient. In addition, when the first program is to be executed for the first time after a sudden power failure or continuous power failure, the OBP merge is preferred to ensure that the data in the multi-level cell block is valid.

In addition to being applied to the above-described program for writing the data stored in the SLC block to one of the TLC blocks, according to a fourth embodiment of the present invention, in the process of programming the buffer, it may also be randomized. The configuration of the seed enables each physical page to perform data scrambling according to different random seeds, and the configuration can make the above-mentioned merge procedure more efficient. As described above, in order to maintain the stability of programming, the SLC block of the memory device 120 can function as a buffer (or cache memory) for temporarily storing data when the host device 200 wants to write data into the memory device 100. . Wait When the usage rate of the SLC block reaches a certain level, the controller 110A/110B can execute the predetermined procedure described above.

According to a fourth embodiment of the present invention, the controller 110A/110B may configure different sets of random seeds for different SLC blocks, wherein each set of random seeds respectively contains a predetermined number of random seeds, and each group contains random seeds. Not the same. For example, the controller 110A/110B may configure different sets of random seeds for different SLC blocks, and when the data is written, the scrambler 115 may perform data scrambling according to the corresponding random seed. Assuming that an SLC block contains 10 physical pages, each set of random seeds can contain 10 different random seeds, and the 30 random seeds included in the three sets of random seeds configured for the three SLC blocks are different.

More specifically, in one embodiment of the present invention, the controller 110A/110B may first use the first SLC block as a buffer. When the controller 110A/110B receives the data to be written into the memory device 120 from the host device 200, the scrambler 115 may perform data scrambling on the data according to a first set of random seeds, and the encoder 114 may disturb the data. The encoding is performed, and then the scrambled and encoded data is written into the first SLC block.

When the first SLC block is filled or the usage of the first SLC block reaches a certain level, the controller 110A/110B may reuse the second SLC block as a buffer. Similarly, when the controller 110A/110B receives the data to be written into the memory device 120 from the host device 200, the scrambler 115 may perform data scrambling on the data according to a second set of random seeds, and the encoder 114 may disturb the data. The data is encoded, and the data that has been scrambled and encoded is then written to the second SLC block.

When the second SLC block is filled or pending use of the second SLC block When the rate reaches a certain level, the controller 110A/110B can reuse the third SLC block as a buffer. Similarly, when the controller 110A/110B receives the data to be written into the memory device 120 from the host device 200, the scrambler 115 may perform data scrambling on the data according to a third set of random seeds, and the encoder 114 may disturb the data. The data is encoded, and the data that has been scrambled and encoded is then written to the third SLC block, and so on.

As described above, the first set of random seeds, the second set of random seeds, and the third set of random seeds respectively comprise a predetermined number of random seeds, and the first set of random seeds, the second set of random seeds, and the third set of random seeds are included Random seeds are not the same.

In addition, when the scrambler 115 performs data scrambling, the random seed used by each physical page is also stored in one of the spare regions of the physical page. After the data is read, the random region may be randomly selected. The seed restores the data. More specifically, when reading data, the controller 110A/110B reads the corresponding data from the memory device 120, decodes the data via the encoder 114, and stores it according to the spare area of the data via the scrambler 115. The corresponding random seed can obtain the original data after decoding the decoded data.

According to the fourth embodiment of the present invention, since different sets of random seeds have been configured for different SLC blocks in advance, data is used to perform data scrambling using different random seeds when writing data to different SLC blocks, and each physical page The configured random seeds are also different. Therefore, when the controller 110A/110B decides to perform a direct merge procedure for writing data stored in a plurality of SLC blocks into one multi-level unit block (ie, the above-mentioned When a merger program), you can directly The data stored in the plurality of SLC blocks is written into a multi-level cell block.

As described above, the controller 110A/110B sequentially reads data stored in a plurality of (for example, three) SLC blocks, and sequentially writes the read data into one TLC block. In general, a read action is accompanied by a write action. For example, the controller 110A/110B can sequentially read the first SLC block and directly write the read data into a TLC block, read the second SLC block and directly write the read data into the same block. The TLC block, and reading the third SLC block and directly writing the read data to the same TLC block.

According to an embodiment of the present invention, the SLC block may be divided into three groups as described above, each group may correspond to a set of random seeds, and different groups of SLC blocks are configured with different sets of random seeds. For example, the first group can include a first SLC block, a fourth SLC block, etc., and the controller 110A/110B can configure a first set of random seeds for the first group of SLC blocks. Likewise, the second group may include a second SLC block, a fifth SLC block, etc., and the controller 110A/110B may configure a second set of random seeds for the second group of SLC blocks, and third The group may include a third SLC block, a sixth SLC block, etc., and the controller 110A/110B may configure a third set of random seeds for the third group of SLC blocks. In an embodiment of the present invention, if three groups each have only two SLC blocks, the controller 110A/110B can initiate direct merge immediately after one of the SLC blocks included in each group is filled. program. Assuming that the three groups each contain more than three SLC blocks, the controller 110A/110B may initiate a direct merge procedure when the number of empty SLC blocks included in each group is below a predetermined value.

Since the data of the SLC block does not need to pass through the controller, but is directly written into the TLC block, the advantage of the direct merge program is that it is fast. In addition, by In the fourth embodiment of the present invention, the controllers 110A/110B have configured different sets of random seeds for different SLC blocks, and therefore, the random seeds configured by the first, second, and third SLC blocks are not The same is true, and the random seeds configured on the physical pages of the first, second, and third SLC blocks are also different, and the configuration process can make the foregoing merge procedure more efficient.

Figure 4 is a flow chart showing a data processing method of a memory device according to another embodiment of the present invention. First, different sets of random seeds are configured for different SLC blocks (step S402). For example, when N SLC blocks are set as buffers, the controller 110A/110B can configure N sets of different random seeds, so that the random seeds corresponding to the SLC blocks are different, and each SLC block The random seeds corresponding to each physical page are also different, where N is a positive integer.

Then, when the controller 110A/110B wants to write the data into the nth SLC block (where 0<n<N), the data is scrambled according to the nth random seed corresponding to the SLC block, and the data is After the scrambled data is encoded, the scrambled and encoded data is written into the corresponding SLC block (step S404).

Compared with the prior art, when the data of the SLC block is to be sorted into the TLC block, in order to ensure that the random seeds of each physical page are different, it is often necessary to read the data from the memory device 120 to the SRAM 112 first. And the controller again re-scrambles/encodes the random seed before it can be stored in the TLC block, thus reducing the performance of the data storage device. In the embodiment of the present invention, the above-mentioned merge procedure can be made more efficient by the configuration of the random seed, and it can be ensured that the data of each physical page in the TLC block after the merged procedure is based on different random seeds. disturb.

The term "coupled" in this specification refers to a variety of direct or indirect electrical connections. The present invention has been described above with reference to the preferred embodiments thereof, and is not intended to limit the scope of the present invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

Claims (10)

A data storage device comprising: a memory device comprising a plurality of memory blocks, wherein the memory blocks comprise a plurality of single layer unit blocks and a plurality of multi-level unit blocks, and the single layer unit blocks comprise at least a first single layer unit block, a second single layer unit block, and a third single layer unit block; and a controller coupled to the memory device and including a scrambler and an encoder; When the controller receives the first data to be written into the memory device from a host device, the scrambler performs data scrambling on the first data according to a first set of random seeds, and the encoder interferes with the first data. A data is encoded, and the controller writes the first data that is disturbed and encoded into the first single layer unit block; and when the controller receives the second data to be written into the memory device from the host device And the scrambler performs data scrambling on the second data according to a second set of random seeds, the encoder encodes the scrambled second data, and the controller will scramble and encode the first data. Data is written into the second single-layer unit block; when the controller receives the third data to be written to the memory device from the host device, the scrambler performs the third data according to a third set of random seeds. Data scrambling, the encoder encodes the third data that has been disturbed, and the controller writes the scrambled and encoded third data into the third single layer unit block, wherein the first single layer unit area The block, the second single layer unit block, and the third single layer unit block are used as buffers for temporary storage Data; and the controller further writes data stored in the first single layer unit block, the second single layer unit block, and the third single layer unit block to at least one of the plurality of unit unit blocks Wherein the first set of random seeds, the second set of random seeds are different from the third set of random seeds. The data storage device of claim 1, wherein the first set of random seeds, the second set of random seeds, and the third set of random seeds respectively comprise a predetermined number of random seeds, and the first set of random seeds The seed, the second set of random seeds, and the random seeds included in the third set of random seeds are all different. The data storage device of claim 1, wherein the data of each physical page of the first/second single layer unit block is written according to different random seeds in the first/second group of random seeds. Disturbed, and the scrambler stores the random seed used by each physical page in one of the physical regions of the physical page. The data storage device of claim 3, wherein when the first data is read, the controller reads the first data from the memory device, and the encoder decodes the first data. The scrambler performs data descrambling on the decoded first data according to the corresponding random seed stored in the spare area to obtain the descrambled and decoded first data. The data storage device of claim 1, wherein the controller determines to perform a direct merge procedure for writing the data stored in the single-layer unit block to one of the multi-level unit blocks. The controller reads sequentially The first single layer unit block, the second single layer unit block, and the data stored by the third single layer unit block, and sequentially read the read data into a multi-level unit block. A data processing method for a memory device is applicable to a data storage device, the data storage device comprising a memory device and a controller, the memory device comprising a plurality of memory blocks, wherein the memory blocks comprise a plurality of a layer unit block and a plurality of multi-level unit blocks, and the single-layer unit blocks include at least a first single-layer unit block, a second single-layer unit block, and a third single-layer unit block, the method The method includes: when the first data is written into the memory device, performing data scrambling on the first data according to a first set of random seeds, encoding the first data that is disturbed, and disturbing and encoding the first data. The first data is written into the first single layer unit block; when the second data is written into the memory device, the second data is scrambled according to a second set of random seeds, and the second data is disturbed Data is encoded, and the second data that is scrambled and encoded is written into the second single layer unit block; when the third data is written into the memory device, the third data is Performing data scrambling, encoding the disturbed third data, and writing the scrambled and encoded third data to the third single-layer unit block, wherein the first single-layer unit block, the first The second single-layer unit block and the third single-layer unit block are used as buffers for temporarily storing data; and are stored in the first single-layer unit block, the second single-layer unit block, and The data of the third single layer unit block is further written to at least one of the plurality of multi-level unit blocks, wherein the first set of random seeds and the second set of random seeds are different from the third set of random seeds. The method of claim 6, wherein the first set of random seeds, the second set of random seeds, and the third set of random seeds respectively comprise a predetermined number of random seeds, and the first set of random seeds, The second set of random seeds is different from the random seeds included in the third set of random seeds. The method of claim 6, wherein the data of each physical page written in the first/second single layer unit block is disturbed according to different random seeds in the first/second group of random seeds. And the random seed used to disturb each physical page is stored in one of the spare regions of the physical page. The method of claim 8, wherein when the first data is read, the method further comprises: reading the first data from the memory device; decoding the first data; The corresponding random seed stored in the spare area performs data descrambling on the decoded first data. The method of claim 6, further comprising: reading the first single layer unit block and directly writing the read data into a multi-level unit block; reading the second single layer unit area Block and directly write the read data to the multi-level cell block; The third single layer unit block is read and the read data is directly written into the multi-level unit block.