TWI651829B - Semiconductor structure - Google Patents

Abstract

The semiconductor structure includes a transistor. The transistor includes a semiconductor substrate, a first source/drain side doped region, a second source/drain side doped region, and a gate structure. The first source/drain side doped region includes a lower doped portion of the conductivity type opposite to the semiconductor substrate. The second source/drain side doping region includes a first doped portion extending downward from an upper surface of the semiconductor substrate. The second source/drain side doped region has a bottom PN junction between the semiconductor substrate and the semiconductor substrate. A bottom surface position of the lower doped portion is lower than the bottom PN junction. The doping concentration of the first doped portion is greater than the doping concentration of the same conductivity type of the lower doped portion. The gate structure is on the semiconductor substrate between the first source/drain side doped region and the second source/drain side doped region.

Description

Semiconductor structure

This invention relates to a semiconductor structure, and more particularly to a semiconductor structure having a transistor.

Electrostatic discharge (ESD) is a phenomenon of electrostatic charge transfer between different objects and electrostatic charge accumulation. The time of ESD is very short, only within a few nanoseconds. Very high currents are generated in ESD events, and current values are typically a few amps. Therefore, once an ESD event occurs, the integrated circuit in which the ESD protection component is not placed is usually damaged. For low-voltage operated contact pads, traditional MOS is used. For ESD protection components, MOSs with long drain-to-polysilicon gate distance (DCGS) provide sufficient ESD protection, but the long DCGS adds parasitic connections. The surface capacitor will reduce the operating speed, while the short DCGS MOS may not provide enough ESD protection. In addition, the high-voltage operation of the contact pad using the traditional high-voltage MOS as ESD protection component, its ESD protection is weak.

This invention relates to a semiconductor structure.

According to one aspect of the invention, a semiconductor structure is provided that includes a transistor. The transistor includes a semiconductor substrate, a first source/drain side doping a region, a second source/drain side doped region, and a gate structure. The first source/drain side doped region includes a lower doped portion of the conductivity type opposite to the semiconductor substrate. The second source/drain side doping region includes a first doped portion extending downward from an upper surface of the semiconductor substrate. The second source/drain side doped region has a bottom PN junction between the semiconductor substrate and the semiconductor substrate. A bottom surface position of the lower doped portion is lower than the bottom PN junction. The doping concentration of the first doped portion is greater than the doping concentration of the same conductivity type of the lower doped portion. The gate structure is on the semiconductor substrate between the first source/drain side doped region and the second source/drain side doped region.

In order to better understand the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings

102‧‧‧Semiconductor substrate

104, 204, 304, 504‧‧‧ first source/drain side doping region

106, 406, 506‧‧‧Second source/drain side doping

108‧‧‧ gate structure

109‧‧‧Isolation structure

110‧‧‧Undoped part

112‧‧‧Top surface of the semiconductor substrate

114‧‧‧First doping

214‧‧‧Second doping

116‧‧‧First doped part

118‧‧‧ bottom surface of the doped part

120‧‧‧ bottom PN junction

122A‧‧‧First side surface

122B‧‧‧Second side surface

Side surface of the upper doped portion of 122C, 122D‧‧

Side surfaces of the under-doped portions of 124A, 124B, 124C, 124D‧‧

126, 128, 654‧‧‧ conductive contact

Side surface of the 132A, 132B‧‧ ‧ gate structure

230‧‧‧ bottom surface of the upper doped portion

434‧‧‧Second doped part

536‧‧‧Contact pads

538‧‧‧Internal circuits

540‧‧‧ MOS semiconductor transistor

542‧‧‧resistance

544‧‧‧ nodes

546‧‧‧ Grounding terminal

648‧‧‧First resistance doping area

650‧‧‧second resistance doping zone

652A, 652B, 652C, 652D‧‧‧ side surface of the first resistance doped region

D1‧‧‧ source to bungee direction

D2‧‧ Direction

W1‧‧‧ width of the doped part

W2‧‧‧ width of the upper doped portion

W3‧‧‧ width of the doped part

Fig. 1 is a top view showing a MOS transistor according to a first embodiment.

2 is a cross-sectional view showing a MOS transistor according to the first embodiment.

Fig. 3 is a cross-sectional view showing a MOS transistor according to the first embodiment.

Fig. 4 is a cross-sectional view showing a MOS transistor according to the first embodiment.

Fig. 5 is a top view showing a MOS transistor according to a second embodiment.

Fig. 6 is a cross-sectional view showing a MOS transistor according to a second embodiment.

Fig. 7 is a top view showing a MOS transistor according to a third embodiment.

Figure 8 is a cross-sectional view showing a MOS transistor according to a third embodiment.

Figure 9 is a cross-sectional view showing a MOS transistor according to a third embodiment.

Fig. 10 is a top view showing a MOS transistor according to a fourth embodiment.

Figure 11 is a cross-sectional view showing a MOS transistor according to a fourth embodiment.

Figure 12 is a cross-sectional view showing a MOS transistor according to a fourth embodiment.

Figure 13 is a top view of a MOS transistor according to a fifth embodiment.

Figure 14 is a cross-sectional view showing a MOS transistor according to a fifth embodiment.

Fig. 15 is a top view showing a MOS transistor according to a sixth embodiment.

Figure 16 is a cross-sectional view showing a MOS transistor according to a sixth embodiment.

Figure 17 is a top view of a MOS transistor according to a seventh embodiment.

Figure 18 is a cross-sectional view showing a MOS transistor according to a seventh embodiment.

Fig. 19 is a top view showing a MOS transistor according to the eighth embodiment.

Figure 20 is a cross-sectional view showing a MOS transistor according to an eighth embodiment.

Figure 21 is a diagram showing the circuit of the semiconductor structure according to the ninth embodiment.

Fig. 22 shows the test results of the semiconductor structures of the examples and the comparative examples.

Fig. 23 is a top view showing the resistor according to the tenth embodiment.

Figure 24 is a cross-sectional view showing the resistor according to the tenth embodiment.

Fig. 25 is a top view showing the resistor according to the eleventh embodiment.

Figure 26 is a cross-sectional view showing the resistor according to the eleventh embodiment.

Figure 27 is a cross-sectional view showing the resistor according to the eleventh embodiment.

Fig. 28 is a top view showing the resistor according to the twelfth embodiment.

Fig. 29 shows the test results of the semiconductor structures of the examples and the comparative examples.

The following is explained by some embodiments. It should be noted that the disclosure does not show all possible embodiments, and other embodiments not disclosed in the disclosure may also be applied. Moreover, the size ratio on the schema is not based on actual products, etc. Scale drawing. Therefore, the description and illustration are for illustrative purposes only and are not intended to be limiting. In addition, the description in the embodiments, such as the detailed structure, the process steps, the material application, and the like, are for illustrative purposes only and are not intended to limit the scope of the disclosure. The details of the steps and the details of the embodiments may be varied and modified in accordance with the needs of the actual application process without departing from the spirit and scope of the disclosure. The same/similar symbols are used to describe the same/similar elements.

First embodiment

Referring to FIGS. 1 to 4, an N-type MOS transistor (NMOS) according to the first embodiment is illustrated. The first picture is a top view of a MOS transistor. Fig. 2 is a cross-sectional view taken along line AA of Fig. 1. Fig. 3 is a cross-sectional view taken along line BB of Fig. 1. Fig. 4 is a cross-sectional view taken along line ZZ of Fig. 1. The MOS transistor includes an N-type first source/drain side doping region 104 and an N-type second source/drain side doping region 106 formed in the P-type semiconductor substrate 102, and on the semiconductor substrate 102 Gate structure 108.

The first source/drain side doping region 104 includes a lower doped portion 110, and a first doping 114 formed doped from the upper surface 112 of the semiconductor substrate 102 and over the lower doped portion 110. The second source/drain side doping region 106 includes a first doped portion 116 doped from the upper surface 112 of the semiconductor substrate 102. In an embodiment, the (net) N-type dopant concentration of the lower doped portion 110 is less than the (net) N-type dopant concentration of the first dopant 114 and less than (net) of the first doped portion 116. N-type dopant concentration. In the figure, the symbol "N" can also indicate that the (net) N-type dopant concentration is less than The number "N+" indicates a region of the N-type dopant concentration. In one embodiment, for example, the first dopant 114 of the first source/drain side doping region 104 is used as a heavily doped region of the MOSFET, and the second source/drain side The first doped portion 116 of the doped region 106 serves as a source heavily doped region of the MOS transistor. In an embodiment, the lower doped portion 110 having a lower doping concentration than the first doped portion 116 is implanted at a deeper depth of the semiconductor substrate 102, thus the bottom surface 118 of the lower doped portion 110 (or with the semiconductor substrate 102) The intervening bottom PN junction) is tied lower than the bottom PN junction 120 formed between the first doped portion 116 and the semiconductor substrate 102.

For example, the first doping member 114 and the first doping portion 116 may be heavily doped regions formed simultaneously by the implantation process. The (net) N-type dopant concentration of the first dopant 114 may be equal to the (net) N-type dopant concentration of the first dopant portion 116. In an embodiment, the implantation process for forming the lower doped portion 110 may also dope impurities in the region of the first doping member 114. At this time, the (net) N-type dopant concentration of the first doping member 114 may be greater than The (net) N-type dopant concentration of the first doped portion 116. In an embodiment, for example, the doping profile of the first doping 114 can be defined by the gate structure 108 and the isolation structure 109. The isolation structure 109 is not limited to shallow trench isolation (STI) as shown, but other isolation elements such as field oxide (FOX) structures and the like can also be used.

In this example, the opposite first side surface 122A and second side surface 122B of the first doping member 114 exceed the opposite side surface 124A of the lower doped portion 110 in the source to drain direction D1. 124B, and the width W1 of the lower doped portion 110 is smaller than the width W2 of the first doping member 114. In addition, the opposite side surfaces 122C, 122D of the first doping member 114 are in contact with the source to the drain D1. The wrong direction D2 (for example, the long extension direction of the gate structure 108/the long extension direction of the source/the long extension direction of the drain) which is substantially orthogonal to the source-to-dip direction D1 is over the lower doped portion 110. Opposing side surfaces 124C, 124D. The conductive contact 126 and the conductive contact 128 can be electrically connected to the first doping member 114 and the first doping portion 116 above the lower doped portion 110, respectively. As shown in the top view of FIG. 1, the conductive contacts 126 are disposed within the outline of the lower doped portion 110. The gate structure 108 extends beyond the side surface 122C and the side surface 122D of the first doping 114 in the direction D2.

Second embodiment

Please refer to Figure 5 and Figure 6. 5 is a top view of the MOS transistor according to the second embodiment, and FIG. 6 is a cross-sectional view taken along line ZZ of FIG. 5. The difference between this example and the first embodiment is that the lower doped portion 110 of the first source/drain side doping region 104 exceeds the first doping member 114 in the direction D2. In other words, the opposite side surfaces 124C, 124D of the lower doped portion 110 are outside the opposite side surfaces 122C, 122D of the first doping 114. A cross-sectional view of the MOS transistor across the first dopant 114 (e.g., a cross-sectional view along line AA) can be similar to FIG.

Third embodiment

Please refer to Figures 7 to 9. Figure 7 shows a top view of the MOS transistor. Figure 8 is a cross-sectional view taken along line AA of Figure 7. Figure 9 is a cross-sectional view taken along line ZZ of Figure 7. Third embodiment and first The difference in the embodiment is that the lower doped portion 110 of the third embodiment has a smaller size than the doped portion 110 below the first embodiment. Further, as shown in the upper view of FIG. 7, the conductive contact 126 is disposed not only within the outline of the lower doped portion 110 but also in a region other than the lower doped portion 110. For example, the cross-sectional view of the MOS transistor of FIG. 7 along line BB can be similar to FIG.

Fourth embodiment

Please refer to Figures 10 to 12. Figure 10 shows a top view of the MOS transistor. Figure 11 is a cross-sectional view taken along line AA of Figure 10. Fig. 12 is a cross-sectional view taken along line ZZ of Fig. 10. The fourth embodiment differs from the first embodiment in that the lateral extent of the doped portion 110 under the fourth embodiment (i.e., the implantation range observed from the top view) is substantially the same as the first doping 114. For example, the width W3 of the lower doped portion 110 is substantially equal to the width W2 of the first doping 114. The side surfaces 124A, 124B, 124C, 124D of the lower doped portion 110 are substantially aligned with the first side surface 122A, the second side surface 122B, and the side surfaces 122C, 122D of the first doping 114, respectively. In the first to fourth embodiments, the first doping member 114 is an upper doped portion.

Fifth embodiment

Please refer to Figure 13 and Figure 14. Figure 13 is a top view of the MOS transistor. Figure 14 is a cross-sectional view taken along line AA of Figure 13. The difference between the fifth embodiment and the first embodiment is exemplified as follows. the first The source/drain side doping region 204 includes a lower doping portion 110, and a second doping member 214 formed over the lower doping portion 110 and doped from the upper surface 112 of the semiconductor substrate 102. In an embodiment, the (net) N-type dopant concentration of the second dopant 214 is less than the (net) N-type dopant concentration of the first dopant portion 116. In the fifth embodiment, the second doping member 214 is an upper doped portion.

In one embodiment, for example, the (net) N-type doping concentration of the lower doped portion 110 whose bottom surface 118 is lower than the bottom PN junction 120 is greater than the second doping 214 ( The net N-type dopant concentration is less than the (net) N-type dopant concentration of the first doped portion 116. In the figure, the symbol "N" may also indicate that the (net) N-type dopant concentration is smaller than the region where the N-type dopant concentration is represented by the symbol "N+", and the N-type dopant concentration is greater than the symbol "N-". Area. The disclosure is not limited thereto. In other embodiments, the lower doped portion 110 may have the same (net) N-type dopant concentration as the second dopant 214 or a lower concentration than the second dopant 214. Replacement of the heterozygous part.

In one embodiment, for example, the second doping 214 of the first source/drain side doping region 204 is electrically connected to the gate conductive contact 126 of the MOS transistor, and the second source/drain side The first doped portion 116 of the doped region 106 serves as a source heavily doped region of the MOS transistor. Both the second doping 214 and the first doped portion 116 extend downward from the upper surface 112 of the semiconductor substrate 102. In one embodiment, as shown in FIG. 14, the bottom surface 230 of the second doping member 214 has a depth position below the first doped portion 116. However, the disclosure is not limited thereto. In other embodiments, the bottom surface 230 of the second doping member 214 has a depth position at a bottom surface of the first doping portion 116. Above the face or at the same depth.

Sixth embodiment

Please refer to Figure 15 and Figure 16. Figure 15 is a top view of the MOS transistor. Figure 16 is a cross-sectional view taken along line AA of Figure 15. The difference between the sixth embodiment and the fifth embodiment is that the first source/drain side doping region 304 further includes the first doping member 114 formed in the second doping member 214. The features of the first doping 114 are similar to those of the first doping 114 described in the first embodiment. Thus, for example, the dopant concentration (indicated by the symbol "N") of the doped portion 110 in this example is greater than the second dopant 214 (represented by the symbol "N-"), and less than the first blend. The impurity portion 116 and the first dopant 114 (represented by the symbol "N+"). The structure of this example may include other different features than the fifth embodiment by including the first doping 114. In the sixth embodiment, the upper doped portion includes the first doping member 114 and the second doping member 214.

Seventh embodiment

Please refer to Figure 17 and Figure 18. Figure 17 is a top view of the MOS transistor. Figure 18 is a cross-sectional view taken along line AA of Figure 17. The difference between the seventh embodiment and the sixth embodiment further includes the second doping portion 434 in which the first doping portion 116 is formed in the second source/drain side doping region 406. The doping concentration (indicated by the symbol "N") of the doped portion 110 in this example is greater than the second doping portion 434 and the second doping member 214 (indicated by the symbol "N-"), and less than the first A doped portion 116 and a first doped member 114 (denoted by the symbol "N+"). In one embodiment, for example, the second doped portion 434 and the second doped member 214 may be formed simultaneously using the implant process and thus may have the same depth. In the seventh embodiment, the upper doped portion includes the first doping member 114 and the second doping member 214.

Eighth embodiment

Please refer to Figure 19 and Figure 20. Fig. 19 is a top view showing the MOS transistor. Figure 20 is a cross-sectional view taken along line AA of Figure 19. The difference between the eighth embodiment and the fifth embodiment further includes the second doping portion 434 in which the first doping portion 116 is formed in the second source/drain side doping region 406. The second doped portion 434 of this example is similar in features to the second doped portion 434 described in the seventh embodiment. Thus, for example, the dopant concentration (indicated by the symbol "N") of the doped portion 110 in this example is greater than the second dopant 214 and the second dopant portion 434 (represented by the symbol "N-") ) is smaller than the first doped portion 116 (indicated by the symbol "N+"). The structure of this example may include other different features than the fifth embodiment due to the inclusion of the second doped portion 434, and so on. In the eighth embodiment, the second doping member 214 is an upper doped portion.

The concept of the present disclosure can also be extended to other types of MOS transistors, such as P-type MOS transistors of opposite conductivity type.

The MOS transistor of the embodiment can be used to enhance the device properties of the semiconductor structure, for example, when applied to an ESD protection device for low voltage operation. The desired electrostatic discharge protection characteristics have a low parasitic junction capacitance or are applied to high voltage MOS transistors to enhance antistatic performance. The following is a description of some embodiments.

Ninth embodiment

Figure 21 illustrates a circuit of a semiconductor structure including an ESD protection device electrically connected between (external) contact pads 536 and (pre-protected) internal circuitry 538. The ESD protection device includes a MOS transistor 540 and a resistor 542. The resistor 542 is electrically connected between the contact pad 536 and the internal circuit 538. The first source/drain side doping region 504 of the MOS transistor 540 is electrically coupled to a node 544 between the resistor 542 and the contact pad 536. The second source/drain side doping region 506 of the MOS transistor 540 is electrically connected to the ground terminal 546.

In the embodiment, for example, the MOS transistor 540 of the electrostatic discharge protection device can use the first to fourth embodiments. Referring to the experimental results of FIG. 22, it is shown that the MOS transistor according to the embodiment is compared with the MOS semiconductor transistor in which the first source/drain side doping region does not have a lower doping portion in the comparative example. Since the first source/drain side doping region includes the doped portion 110 which is less doped than the first doping member 114, it has a larger depletion region width, so that it can have the same static electricity as the comparative example. The discharge protection characteristic, while having a smaller capacitance value (parasitic junction capacitance) at the same drain voltage, can result in a more efficient contact pad operation speed.

In other embodiments, the contact pads can be designed to increase operating speed and maintain desired electrostatic discharge protection. Some examples of the structure of the resistor 542 which can be used for the electrostatic discharge protection device are exemplified below.

Tenth embodiment

Please refer to Figure 23 and Figure 24. Figure 23 shows a top view of the resistor. Figure 24 is a cross-sectional view taken along line CC of the resistor of Figure 23. The resistor includes a P-type semiconductor substrate 102, an N-type first resistance doping region 648, and an N-type second resistance doping region 650. The second resistance doping region 650 is formed in the semiconductor substrate 102. The first resistance doping region 648 is formed in the second resistance doping region 650. In an embodiment, for example, the (net) N-type dopant concentration of the first resistive doping region 648 (indicated by the symbol "N+") is greater than the (net) N-type doping of the second resistive doping region 650. The mass concentration is indicated by the symbol "N"). In this example, the second resistive doping region 650 surrounds all of the side surfaces 652A-652D of the first resistive doping region 648. The conductive contact 654 is electrically connected to the first resistance doping region 648. For example, the conductive contact 654 can be electrically connected to the 汲 extreme conductive contact of the MOS transistor (eg, the conductive contact 126 shown in the first embodiment). In an embodiment, for example, the doping profile of the first dopant 114 can be defined by the isolation structure 109. The isolation structure 109 is not limited to shallow trench isolation (STI) as shown, but other isolation elements such as field oxide (FOX) structures and the like can also be used.

Eleventh embodiment

Please refer to Figures 25 to 27. Figure 25 shows a top view of the resistor. Figure 26 is a cross-sectional view taken along line CC of the resistor of Figure 25. Figure 27 is a cross-sectional view taken along line DD of the resistor of Figure 25. The difference between the eleventh embodiment and the tenth embodiment is that the lateral extension of the second resistance doping region 650 does not exceed all of the side surfaces 652A to 652D of the first resistance doping region 648.

Twelfth embodiment

Figure 28 shows a top view of the resistor. In this example, the cross-sectional view of the resistor along the CC line can be similar to that of Figure 24, and the cross-sectional view along the DD line can be similar to Figure 27. The difference between the twelfth embodiment and the tenth embodiment is that the lateral extension of the second resistance doping region 650 exceeds the opposite side surfaces 652A, 652B of the first resistance doping region 648, but does not exceed the first resistance doping Opposite side surfaces 652C, 652D of the miscellaneous region 648.

In some embodiments, the MOS semiconductor transistors of the fifth to eighth embodiments are used as high voltage MOS transistors. Referring to the test results shown in FIG. 29, the MOS transistor according to the embodiment is included in the first source/drain side doped region under the drain electrode as compared with the comparative example having no under-doped portion. The lower doped portion 110, which provides an additional current path, can avoid premature collapse between the (eg, N-type) drain and the adjacent opposite-conducting (eg, P-type) well region, and thus can be better Electrostatic discharge withstand capability. Furthermore, in some embodiments, for example, referring to the fifth embodiment described in FIGS. 13 and 14 or the eighth embodiment described in FIGS. 19 and 20, the upper doped portion has only N type The doping concentration is smaller than the second doping 214 of the first doping portion 116, and the conductive contact 126 is electrically connected to the second doping member 214, wherein the second doping member 214 is subjected to lower heat during electrostatic discharge. The stress, therefore, enables the device to have a high electrostatic discharge protection capability.

In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

Claims (9)

A semiconductor structure comprising a transistor, the transistor comprising: a semiconductor substrate; a first source/drain side doped region comprising a conductive type opposite to a lower doped portion of the semiconductor substrate, and further comprising an on-doped a dummy portion above the lower doped portion, the upper doped portion having a first side surface and a second side surface opposite to each other in a source-to-dial direction, the lower doped portion not exceeding The entire first side surface of the upper doped portion and the entire second side surface, the upper doped portion includes a first doping member above the lower doping portion; a second source/drain side doping The doped region includes a first doped portion extending downward from an upper surface of the semiconductor substrate and having a bottom PN junction with the semiconductor substrate, wherein a bottom surface of the lower doped portion is lower than The doping concentration of the first doped portion is greater than the doping concentration of the same conductive type of the lower doped portion, and the doping concentration of the first doping is greater than the first The doping concentration of the doped portion; and a gate structure, The semiconductor substrate between the first source / drain region and the second doped side source / drain region on the side of the doping. The semiconductor structure of claim 1, wherein the doping concentration of the first doping is greater than the doping concentration of the lower doping portion having the same conductivity type, the first doping The first doped portion having the same conductivity type has the same depth. The semiconductor structure of claim 1, wherein the electro-crystalline system is used as an N-type MOS transistor (NMOS) as an electrostatic discharge protection device. The semiconductor structure of claim 1, comprising an electrostatic discharge protection device, wherein the electrostatic discharge protection device comprises: the transistor; and a resistor electrically connected to the first source/drain side doping region . The semiconductor structure of claim 4, further comprising a contact pad electrically connected to a node between the resistor and the first source/drain side doping region, wherein the second source/drain The side doped regions are grounded. The semiconductor structure of claim 4, wherein the resistor comprises: a first resistive doping region; and a second resistive doping region adjacent to a lower surface of the first resistive doping region, and There is a PN junction between the semiconductor substrates, wherein the doping concentration of the first resistance doping region is greater than the doping concentration of the second resistance doping region having the same conductivity type. The semiconductor structure of claim 4, wherein the second resistance doping region does not extend beyond the first resistance doping region. The semiconductor structure of claim 1, further comprising a conductive contact, wherein the upper doped portion further comprises a second doping adjacent to the lower doped portion, the second doped portion Doping concentration is less than The doping concentration of the first doped portion of the same conductivity type is electrically connected to the second doping. The semiconductor structure of claim 1, wherein the upper doped portion further comprises: a second doping member adjacent to the lower doped portion, wherein the doping of the second doping member The concentration is less than the doping concentration of the first doped portion having the same conductivity type; wherein the first doping is formed in the second doping, the doping of the first doping The concentration is greater than the dopant concentration of the lower doped portion having the same conductivity type and greater than the dopant concentration of the second dopant.